btev trigger architecture vertex 2002, nov. 4-8 michael wang, fermilab (for the btev collaboration)
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BTeV Trigger Architecture
Vertex 2002, Nov. 4-8
Michael Wang, Fermilab
(for the BTeV collaboration)
Michael WangVertex 2002, BTeV trigger architecture
BTeV - a hadron collider B-physics experiment
BTeV at C0CDF
D0 pp
Tevatron
Fermi National Accelerator Laboratory
Michael WangVertex 2002, BTeV trigger architecture
BTeV detector in the C0 collision hall
Michael WangVertex 2002, BTeV trigger architecture
BTeV detector
MuonEM Cal
Straws &Si Strips
SM3 Magnet
RICH
30 StationPixel Detector
Michael WangVertex 2002, BTeV trigger architecture
Pixel detector half-station
Multichip module
Si pixel detector
50 m
400 m5 cm
1 cm
6 cm
10 cm
HDI flex circuitWire bonds
Sensor module
Readout module Bump bonds
Si pixel sensors
sensor module
5 FPIX ROC’s
128 rows x22 columns
14,080 pixels (128 rows x 110 cols)
380,160 pixelsper half-station
total of 23Million pixelsin the full pixel detector
Michael WangVertex 2002, BTeV trigger architecture
Simulated B event
Michael WangVertex 2002, BTeV trigger architecture
Simulated B event
Michael WangVertex 2002, BTeV trigger architecture
Primary interaction vertex
Michael WangVertex 2002, BTeV trigger architecture
Primary interaction vertex
Michael WangVertex 2002, BTeV trigger architecture
B decay vertex
Ds
K
KK
Bs
Michael WangVertex 2002, BTeV trigger architecture
L1 vertex trigger algorithm
1) Segment finding stage: Use pixel hits from 3 neighboring stations to find the beginning and ending segments of tracks. These segments are referred to as triplets
Two stage trigger algorithm:1. Segment finding2. Track/vertex finding
Michael WangVertex 2002, BTeV trigger architecture
1a) Segment finding stage: phase 1 Start with inner triplets close to the interaction region. An inner triplet represents the start of a track.
Segment finding: inner tripletes
Michael WangVertex 2002, BTeV trigger architecture
1b) Segment finding stage: phase 2 Next, find the outer triplets close to the boundaries of the pixel detector volume. An outer triplet represents the end of a track.
Segment finding: outer triplets
Michael WangVertex 2002, BTeV trigger architecture
2a) Track finding phase: Finally, match the inner triplets with the outer triplets to find complete tracks.
2b) Vertex finding phase:• Use reconstructed tracks to locate interaction vertices• Search for tracks detached from interaction vertices
Track/vertex finding
Michael WangVertex 2002, BTeV trigger architecture
Trigger decision
• Generate Level-1 accept if “detached” tracks in the same arm of the BTeV detector with:
2
2.0
6
25.02
b
b
pT
(GeV/c)2
cm
Execute Trigger
b
p p
B-meson
Michael WangVertex 2002, BTeV trigger architecture
GlobalLevel-1
ITCH
Information Transfer Control Hardware
GL1
Level-1 Buffers
12 x 24-port Fast Ethernet Switches
Level 2/3Processor Farm
Pixel Processors
FPGA Segment Finder
Track/Vertex Farm
Gigabit Ethernet Switch
Data Combiners +Optical Transmitters
OpticalReceivers
BTeV Detector
Front End Boards
8 Data Highways
Data Logger
Cross Connect Switch
BTeV trigger architecture
Michael WangVertex 2002, BTeV trigger architecture
Pixel data readout
Counting RoomCollision Hall
Pixelprocessor
Pixelprocessor
Pixelprocessor
FPGA tracker
to neighboring FPGAsegment tracker
to neighboring FPGAsegment tracker
Pixel stations
Optical links
Pixel processor
time-stamp expansion
time ordering
clustering algorithm
xy table lookup
FPIX2 Read-out chip
DCB
DCB
DCB
Data combiners
Row (7bits) Column (5bits) BCO (8bits) ADC (3bits)
sync (1bit)
Chip ID (13bits)
Michael WangVertex 2002, BTeV trigger architecture
Level 1 vertex trigger architecture
FPGA segment trackers
Merge
Trigger decision to Global Level 1
Switch: sort by crossing number
track/vertex farm(~2500 processors)
30 station pixel detector
Michael WangVertex 2002, BTeV trigger architecture
L1 trigger pre-prototype board
32-bit input32-bit output
FIFO
Buffer ManagerFPGA
CMC connectors
Michael WangVertex 2002, BTeV trigger architecture
L1 pre-prototype with DSP mezzanine cards
TI C6711
McBSP
McBSP
GL1/HPI FPGA
Hitachi H8SHitachi H8S
FPGA bootdevice
CF/LCDFPGA
ArcNetArcNet
Hitachi programming
Hitachi serial consoles
Michael WangVertex 2002, BTeV trigger architecture
L1 trigger pre-prototype test stand
PCI test adapter
TI DSP JTAGemulator
Xilinx programmingcable
Hitachi programming
ArcNet
serial console
Michael WangVertex 2002, BTeV trigger architecture
Level 2/3 trigger R&D
Processing nodes fromretired Fermilab farm
24-port fanout switch
High-density blade serverunder evaluation
Michael WangVertex 2002, BTeV trigger architecture
End
Michael WangVertex 2002, BTeV trigger architecture
Backup slides
Michael WangVertex 2002, BTeV trigger architecture
L1 vertex trigger efficiencies
Process Eff. (%) Monte Carlo
Minimum bias 1 BTeVGeant
Bs D+sK- 74 BTeVGeant
B0 D*+- 64 BTeVGeant
B0 00 56 BTeVGeant
B0 J/s 50 BTeVGeant
Bs J/*0 68 MCFast
B- D0- 70 MCFast
B- Ks- 27 MCFast
B0 2-body modes 63 MCFast
()