breakthrough technologies: from r&d to...

© 2005 ASM

Breakthrough Technologies: From R&D to Manufacturing

Ivo RaaijmakersCTO Front-end Operations and Director of R&D

Semicon West, San Francisco, July 18, 2007

Front-End Operations

© 2005 ASM July 18, 2007ASM Proprietary Information 2

ASM Front-end R&D InvestmentsThrough good Years and bad Years…

• Average R&D intensity over the five year period 2002-2006 is 19%, up from 16% in the previous five year period

• Industry averages are around 17% for 2002-2004 period, up from about 15% for the 1997-2001 five year period(1)

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Revenue Front-end

RD&E

(1) Semi White Paper, October 2005



ASM has created a powerful IP Portfolio

• Since 2002, 80 – 100 original inventions are filed per year• Best in class in terms of the number of issued patents per

invested R&D dollar

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© 2005 ASM July 18, 2007 4

ASM has created a powerful IP PortfolioNot only in Quantity but also in Quality

• ASM shares a position in the “top 10 patent companies” (as determined by IEEE Spectrum), all of whichare >10 times the size of ASM

• Many fundamentalpatents in important growth areas, includingAtomic Layer Deposition, epitaxy and plasma processing

• Large future revenuepotential in core and non-core markets

IEEE Spectrum, November 2006



Product Lines are the Gateways between ASM Technology and our Customers

Our Customers

Capacitor Products

PECVD Products

Epitaxy Products

Transistor Products

Vertical Furnace

RTPProducts

CorporateR&D

LP / RTCVD

AL / MOCVD

Epitaxy

Thermal Process

Plasma Process

A400/412

Levitor

Epsilon

Polygon/Pulsar

Eagle

Dragon

Proc

ess

Tech

nolo

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atfo

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Polygon, Epsilon, Levitor, Eagle, and Dragon are registered ASM owned trademarks. A400, A412, PEALD and ALCVD are our trademarks



Transistor Products (TP)Polygon® and Pulsar®

Our Customers

Capacitor Products

PECVD Products

Epitaxy Products

Transistor Products

Vertical Furnace

RTP Products

CorporateR&D

LP / RTCVD

AL / MOCVD

Epitaxy

Thermal Process

Plasma Process

A400/412

Levitor

Epsilon

Polygon/Pulsar

Eagle

Dragon

Proc

ess

Tech

nolo

gyPl

atfo

rms

Prod

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latfo

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Early Investments in ALCVD™ High-k Gate Stacks: 1999 - 2002

ASM Proprietary and Confidential Information

ASM International

© ASM International 2000 IJR 07/03/2007/1 ®

ASM Microchemistry

• Suntola invented Atomic Layer CVD (ALCVD), then called Atomic Layer Epitaxy (ALE); basic patents issued in 1977 - 1983.

• Microchemistry was founded in 1987. Location: Espoo(close to Helsinki)

• Microchemistry was acquired in July 1999 fromFortum and is now ASM Microchemistry

• Size: ≈ 50 people, of which 15 in R&D, 10 in engineering

• Installed base: ≈ 25 systems; mainly R&D and FPD• Good fit to ASM: CVD, next generation technology1999


ASM International

Copyright © ASM International N.V. 2000IJR 07/03/2007/21

®

C.M.Perkins et al., Semiconductor Research Corporation Fellowship Meeting, Austin, Sebtember 1999

ALCVD ZrO2/NH3/Cleaning Oxide/Si

• Nitridation improves Performance of the Gate Stack (Lower EOT, Lower Leakage)

• End-structure has 1.3 nm Interfacial Silicate/Oxynitirde (EOT 1.4 nm)

Copyright © ASM 2002 Single Wafer RTCVD /49

Confidential and Proprietary Information

FRONT-END OPERATIONS

Metal Gates: ALCVD WCN and TiN on ALCVD HfO2

2002

Acquisition of Microchemistry

First Atomically Engineered High-k

GatestacksFirst High-k/Metal

Gatestacks



ALCVD™ High-k Gatestacks: 45 nm Production Technology

Polygon® 8300300/200mm Cluster

Pulsar® 3000ALD Reactor

EmerALD™ 3000PEALD™ Reactor

High-k Dielectric

Metal Electrode



ALCVD™ High-k Gatestacks: 45 nm Production Technology

• Excellent repeatability, and consistently low particle adders assure high yield

• ASM’s Pulsar is the only reactor today with a reliable solid source for HfCl4 based ALCVD chemistries

0 500 1000 1500 2000 2500 3000 3500Wafers Processed

Thic

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on-u

nifo

rmity

or

Par

ticle

Add

ers

Thickness Repeatability

Uniformity Repeatability

Particle Adders



ALCVD™ High-k Gatestacks and Metal GatesReady for the Future

ALD HfO2 (2nm) +PEALD TiN (5nm)

5 nm

SiON

PEALD TiN

Swerts, ALD Conference (2006)

• Conformality for both dielectric and metal will be a requirement for 3D devices

• ALCVD is the only realistic option



Capacitor Products (CP)Stellar™

Our Customers

Capacitor Products

PECVD Products

Epitaxy Products

Transistor Products

Vertical Furnace RTPCorporate

R&D

LP / RTCVD

AL / MOCVD

Epitaxy

Thermal Process

Plasma Process

A400/412

Levitor

Epsilon

Polygon/Pulsar

Eagle

Dragon

Proc

ess

Tech

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Early Investments in PEALD™

2002 - 2004

Strictly for ASM Internal Use


Copyright © ASM International N.V. 2002 IJR 07/03/2007/24

®

Genitech, Inc.Daejon, South Korea

• Supplier of Plasma Enhanced ALD equipmentHigh quality films at lower temperatures & from a larger varietyof precursorsBarrier layers & certain dielectric films

• Superfill CVD™ processPreferential deposits inside small featuresSeed layers for copper electroplating

• Exclusive technology, marketing, license and OEM agreement

Genitech sells combined technology in KoreaASM sells combined technology everywhere else2002

Strictly for ASM Internal Use



®

Genitech PEALD Reactor


© 2005 ASM 07/13/2005ASM Proprietary Information 20

Polygon: PEALD for RF/AMSRF and Decoupling Capacitors

AHA MIM Capacitors

1.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-021.E-011.E+00

0 2 4 6 8 10 12 14

Capacitance Density (fF/um2)

Leak

age

Cur

rent

(A

/cm

2)

ALDPEALD

• Low temperature process for all BEOL insertions• Wide range of capacitance densities• Low leakage PEALD™ films (compared to ALD)2004

Acquisition of Genitech

Demonstrated advantagesof PEALD for some Applications



Stellar™ 3000: World’s first PEALD™

System. Introduced Dec 2006

• Advanced Plasma- Enhanced ALD (PEALD) for high-k capacitors

• Dielectrics• Metal electrodes

• Two parallel single wafer reactors• Choice of Lateral Flow or Showerhead

Flow designs in the same platform• High throughput and small foot

print• Designed for low CoO, high volume

manufacturing

Matching Network

inlet

Showerhead electrode

Heater Wafer

outlet

Matching Network

inlet

Showerhead electrode

Heater Wafer

outlet

inlet outlet

electrode

Heater

distrib

Matching Network

Plasma

inlet outlet

electrode

Heater

distrib

Matching Network

Plasma



Stellar™ 3000: Target Applications

• BEOL MIM Capacitors• RF MIM capacitors• Decoupling MIM capacitors• eDRAM

• High-k for LCD• High-k for CMOS Image Sensors• DRAM high-k dielectrics

MIM Capacitor eDRAM CIS

Al Al

AlM - Electrode

M - ElectrodeAl V

ia

Via

I - Dielectric

Al Al

AlM - Electrode

M - ElectrodeAl V

ia

Via

I - Dielectric

YearM

arke

t Siz

e

DRAM

Hi-k Gate

PEALD



Vertical Batch Furnace (VF)A400™ and A412™

Our Customers

Capacitor Products

PECVD Products

Epitaxy Products

Transistor Products


R&D

LP / RTCVD

AL / MOCVD

Epitaxy

Thermal Process

Plasma Process

A400/412

Levitor

Epsilon

Polygon/Pulsar

Eagle

Dragon

Proc

ess

Tech

nolo

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A412™: Productivity and InnovationAlmost Tripled VF Revenue in last 5 years

24 hrs

Waf

ers

Out

in o

ne D

ay

04/11 0:00 04/12 0:00

LogisticsWHR Load/Unload

Processing (2.5 hr)

Tube ATube B

Tube ATube B

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24 hrs

Waf

ers

Out

in o

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ay

04/11 0:00 04/12 0:00


Processing (2.5 hr)

Tube ATube B

Tube ATube B

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300

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600

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2100

04/11 0:00 04/12 0:00


Processing (2.5 hr)

Tube ATube B

Tube ATube B

150

300

900

600

1200

1500

1800

2100

Innovation• Furnaces are NOT old

technology• 2002-2005: addition of LT

processes• 2006-2010: addition of

ALCVD processes• Platform Roadmap (COO,

CT, performance,…)

AB

A412 Application Space

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Atmosheric Processes

Productivity• One A412 = upto 60 kwpm

(2.5 hr process, 90% available, 150 wafer boat)

• About 40% lower capexper m2 as competitors

• Dual boat/dual reactor system

• Large global installed base and support organization


© 2005 ASM July 18, 2007ASM and UoH Proprietary Information 17

Early Investments in New Chemistry Developments – Patents Issued


ASM International


®

XTEM of ALCVD ZrO2 on HSG

100% Step Coverage


ASM International


®

Mikko Ritala et al: ATOMIC LAYER DEPOSITION OF HIGH-k OXIDES, ECS 2000

ALCVD™ of SrTiO3Step Coverage

• 325 C Deposition Temperature

• Step Coverage close to 100%2000

20032006



A412™ Innovation: Improved High-k Capacitor Dielectric for DRAM

• Patented, thermally stable ALCVD chemistry and process

• Linear growth at 0.57 nm/cc:• 6 nm ZrO2 = 100 cycles

• Uniform deposition over batch• >95 % coverage in 1:40 AR trench• High t’put for low COO DRAM fabs

GPC

y = 0.57x + 5.8333

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# cycles

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knes

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Growth Per CycleTop

0.92% 1s; 62.1Å

Middle

0.95% 1s; 60.9Å

Bottom

1.36%1s;61.4Å

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A412™ Innovation: Silcore for Low Temp. Deposition of Thin Smooth Amorphous Silicon

• Possible Applications of thin smooth a-Si• Stacked gates for NVM• Quantum dot NVM• Hardmask for metal gate

Positive TOF-SIMS Imaging

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SiTi


Front-end Operations


®

New Technology RTCVDVery Smooth Si Layers on Oxide at 450C

2002

Single Wafer Feasibility

Batch Productivity

2007



Rapid Thermal Processing (RTP)Levitor®

Our Customers

Capacitor Products

PECVD Products

Epitaxy Products

Transistor Products

Vertical Furnace

RTPProducts

CorporateR&D

LP / RTCVD

AL / MOCVD

Epitaxy

Thermal Process

Plasma Process

A400/412

Levitor

Epsilon

Polygon/Pulsar

Eagle

Dragon

Proc

ess

Tech

nolo

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Levitor® in Production Today in DRAM and Logic Fabs

• Emissivity independent • Demonstrated yield advantages

• More uniform spike anneal: less variability in transistor parameters

• Better control and process window for NiSi anneals (FuSi, Source/ Drain)

• Mature system and processes• System availablity >90%



Advantages of Conductive Heating (Levitor®) over Radiative Heating (Lamps)

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5.48% 1σ 1.18% 1σ

Radiative heating180ºC/s

Conductive heatingLevitor ~ 300°C/s

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ΔT = 43°C ! ΔT < 1°C



Epitaxy Products Epsilon® 3x00 and 2x00

Our Customers

Capacitor Products

PECVD Products

Epitaxy Products

Transistor Products


R&D

LP / RTCVD

AL / MOCVD

Epitaxy

Thermal Process

Plasma Process

A400/412

Levitor

Epsilon

Polygon/Pulsar

Eagle

Dragon

Proc

ess

Tech

nolo

gyPl

atfo

rms

Prod

uct P

latfo

rms

Prod

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ines


© 2005 ASM July 18, 2007ASM and TI Proprietary Information 24

Early Investments in Selective Epitaxial Technologies


ASM International


®

ASMI Research and DevelopmentApplications driving ASM Technology - 2

• Shallow Junctions: scale S/D Junction Depth and Extrinsic Series Resistance

Elevated Source/Drain StructuresReduce Thermal Budget S/D activation, Spike Anneal

• HBT Transistors: increase Switching Speed with Low Cost, Manufacturing Worthy Processes

Mixed Deposition of SiGe, SiGe(C)Selective Epitaxial SiGe and SiGe(C)



®


SEG : Faceting and Geometry

2000


Copyright © ASM International n.v., July 07 - 14 - IJRASM

®

Elevated Source Drain and Silicide Contacts Selective Epitaxy

ESD Epi

SpacersGate

Courtesy of TI

2003Early work on Selective Epitaxy

Aimed at HBT’s and Elevated Source/Drain

Use of strain to enhance Transistor Performance


© 2005 ASM July 18, 2007Contains ASM Proprietary Information 25

20% SiGe Selective EpiIn Production Today at multiple Locations

• Mobility scaling increases Id,sat while not increasing dynamic power dissipation

• Parameters that affect strain and mobility:1. Recess depth2. Ge concentration for PMOS (C

for NMOS)3. Under etch, over fill, …

10-10

10-9

10-8

10-7

10-6

10-5

10-4

200 300 400 500 600 700

SiGe S/DReferenceI O

FF[A

/μm

] @ V

GS=0

.2V

ION

[μΑ/μm] @ VGS

=-0.8V

25%

1

Intel, IEDM 2003

22

2

,VC

LWI isatd μ=

2VfCP ii =

…and decreasing transistor power consumption



NMOS and PMOS Require different EpitaxialMaterials and Processes

• Epitaxial Stressors in Source/Drain• Selective SiGe for uniaxial compressive strain (pMOS)• Selective SiC for uniaxial tensile strain (nMOS)

• High levels of n-type & p-type in-situ doping

SiGeSiGe

CompressiveStrain

45nm SiC:P SiC:P

Tensile Strain



Improving NMOS Performance

Traditional ASM Patented Approach


© 2005 ASM July 18, 2007ASM and Soitec Proprietary Information 28

Early Investments in Epitaxial Technologies for Global Strain (sSOI) with Soitec

Front end Operations


®


Engineered SubstratesThe Ultimate Silicon Substrate

StrainedStrained Si on Si on insulatorinsulatorSiGeStrained Si

BOX

Si substrate

20% Ge bufferTDD = 1x105 cm-2



2006

www.soitec.com, accessed July 6, 2007

2003



PECVD Eagle® and Dragon®

Our Customers

Capacitor Products

PECVD Products

Epitaxy Products

Transistor Products


R&D

LP / RTCVD

AL / MOCVD

Epitaxy

Thermal Process

Plasma Process

A400/412

Levitor

Epsilon

Polygon/Pulsar

Eagle

Dragon

Proc

ess

Tech

nolo

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atfo

rms

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ASM’s Positioning on Low-k Scaling and New Materials Introduction


Copyright © ASM International n.v., July 07 - 20 - IJRASM

®

Third Generation InterconnectThree Generations of Aurora

0

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12

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DesorptionAdsorption

C: CVD SiOC

Pore Radius Distribution

6 A, 6 - 7% 8 - 9 A, ≈30% 8 A, 15 - 20%

Aurora 2.7 Aurora ULK Aurora ELK

• Suite of Aurora® based Materials:• 3 generations with k-values from 3.0 down to 2.5• Conservative position on k-value scaling• The low-k material with the best integration properties




®

ASM BEOL RoadmapMainstream Approach

Design

ProcessTechnology Materials

• Established Aurora dielectric technology, scalable to k ≈ 2

• ASM’s BEOL Metal Technology targeted for 65 nm and extendable to 45 and 32 nm

• Concurrent and evolutionary improvements on dielectric, barrier materials, with design optimization will bring us to 45/32nm

20032002



Three Generations of Aurora® Low-kHigh Volume Production

• And one more is qualified…• Effective k value reductions are achieved by a succession of

• Bulk k –value scaling from 3.0 to 2.5• Integration scheme improvements

1.00

1.50

2.00

2.50

3.00

3.50

4.00

1999

2001

2003

2005

2007

2009

2011

2013

2015

2017

2019

2021

Year Production Start

Effe

ctiv

e k-

Valu

e

ITRS 1999ITRS 2001ITRS 2003ITRS 2005ASM HVM Tool Availability



ASM Choice for 32 nm: Aurora® ULK LD

2

2.5

3

3.5

ASM AuroraULK

PorousLow-k

MorePorousLow-k?

Bul

k k-

valu

e af

ter

Inte

grat

ion

After IntegrationAs Deposited

• Material with a low “as deposited” k-value may be more susceptible to damage

• Pore sealing strategies usually increase k-value to a certain depth

• This will become especially important at small spacing

0102030405060708090

100

30 50 70 90 110Distance (nm)

Ato

mic

con

cent

ratio

n (a

.u.) O

C

SiC(N)

Low-k

C

O

ASM choice: Robust integrationLow damage duringEtch and cleans



Aurora® Low-k for DRAM

Al CuSiO Low-k

Low-k Ultra Low-kAl CuSiO Low-k

Low-k Ultra Low-kAl CuSiO Low-k

Low-k Ultra Low-k

ALCVD WNC, Rh, Ru; Superfill CVD CuHAR Contact

Low-k with low damage susceptibilityM1 Pitch

Eagle XP, Low cost chemistry and integration scheme

CostSolutionChallenge



Various Low-k PrecursorsCost and Thermal Stability

3MS

DMDMOS

OMCTS

TMCTS

StabilityHigher Lower

Prec

urso

r Cos

tLo

wH

igh

Best DRAM Low-k

Candidate



PECVD: Advanced Patterning with Nano-Carbon Polymer (NCP™) Hard-Mask

Roadmap:• Increasing aspect ratio of mask

needed• Increasing number of

applications• More 3D structures, HAR• Smaller feature sizes

Process Flow• NCP/ARC deposition• Resist coat and develop• Etch NCP hardmask• Etch Oxide• Strip remaining resist

and hardmask

J.M.Park, IEDM 2002

SiO2

NCP (300nm)

193 nm ARC

Resist (200nm)

ResistThickness (nm)

Hard MaskThickness (nm)

500100015002000

Device NodeProduction

Year

LithographyProcessComparison

LithographyTechnology

0.14 0.12 0.09 0.07 0.05 0.03

2001 2003 2005 2007 2009

Single Layer ResistBi Layer Resist

Hard Mask Resist (Carbon Film)

KrF 248nm ArF 193nm F2 or EPL, EUVL

100200

300400500 2500

ResistThickness (nm)

Hard MaskThickness (nm)

500100015002000

Device NodeProduction

Year

LithographyProcessComparison

LithographyTechnology

0.14 0.12 0.09 0.07 0.05 0.03

2001 2003 2005 2007 2009

Single Layer ResistBi Layer Resist

Hard Mask Resist (Carbon Film)

KrF 248nm ArF 193nm F2 or EPL, EUVL

100200

300400500 2500

Soft Rigid



NCP™ HardmaskMany Applications in Memory Devices

Metal Contact DRAM

Metal Contact Flash

Storage Node Poly

Bit Line

Bit Line Contact

Self-aligned Contact

Gate Electrode

Isolation

Metal 1

HT - NCP

LT - NCPTR - NCP

Legend



Corporate R&D

Our Customers

Capacitor Products

PECVD Products

Epitaxy Products

Transistor Products


R&D

LP / RTCVD

AL / MOCVD

Epitaxy

Thermal Process

Plasma Process

A400/412

Levitor

Epsilon

Polygon/Pulsar

Eagle

Dragon

Proc

ess

Tech

nolo

gyPl

atfo

rms

Prod

uct P

latfo

rms

Prod

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ines


© 2005 ASM July 18, 2007 38

The use of the 3rd Dimension will change the Industry

Improvements in speed, cost and

power consumption

3D Processor/Memory Stacking

Intel, ISS 2007; VLSI 2006(top), Samsung IEDM 2006 (Bottom)

3D in the Front-end of Line

Improvements in drive current and density

3D SystemIntegration

Improvements infunctionality

and formfactor



Summary and Conclusions (1 of 2)

• Transistor Products (Polygon® and Pulsar®)• High-k Production Technology. ASM has enabled the biggest

change in CMOS since 40 years with its Pulsar® ALCVD™ Reactor• Multiple metal gate options available to control VT• FinFET integration performed with IMEC

• Capacitor Products (Stellar™)• World’s first manufacturing worthy PEALD™ system• High-k dielectrics and metal electrodes for today’s and tomorrow’s

capacitor needs• PEALD™ reactors on two platforms for single film or integrated film

deposition• Vertical Furnace (A412™ and A400™)

• Many innovative new processes developed, continued interest to implement these in batch because of productivity

• HVM workhorse for all market segments: one system manages up to 60kwpm output!



Summary and Conclusions (2 of 2)

• RTP (Levitor®)• Superior throughput; Low COO RTP system• Unconditional temperature uniformity

• Epitaxy (Epsilon®)• PMOS strain engineering with selective Si:Ge in HVM at multiple

sites• NMOS strain engineering with selective Si:C in development with

multiple customers• Bi-axial strained sSOI in manufacturing at wafer supplier

• PECVD (Eagle® and Dragon®)• 3rd generation Aurora® low-k materials qualified for 45 and 32nm• Low damage susceptibility during Dual Damascene processing• Best, and lowest cost film for extending low-k to DRAM• Porous ELK (k<2.5) being investigated for integration• NCP™: Unique Nano Carbon Polymer hardmask for patterning

with (immersion) litho

breakthrough technologies: from r&d to...

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