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Hints on Meeting Project Constraints

• Clock Cycle Constraint (12 clocks)– More resources (multipliers, adders), less clocks

– Can be done with four parallel datapath approach (4 mults + 4 adders)

• Clock Frequency Constraint (25 Mhz )– Will need to pipeline multiplier 1-3 stages

– May need to put DFFs on some control outputs of the FSM

– For state encoding, Gray Code or One Hot encoding will produce faster FSM than Binary Counting order encoding.

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REG

REG

+REG

XDIN DOUT

State DFFs

Comb LogicInputs

NstatePstate

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REG

REG

+REG

XDIN DOUT

State DFFs

Comb LogicInputs

NstatePstate

Critical Path in dashed arrows

Clk2Q

Tpd of FSM Logic

Tpd of Mux, Mult. Mux, Reg Tsu

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REG

REG

+REG

XDIN DOUT

State DFFs

Comb LogicInputs

NstatePstate

FSM delay removed from datapath delay

DFFs

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Be Careful!

• When putting DFFs on control outputs, will delay control action by one clock

• This will affect your ASM chart!!• Do not have to put DFFs on all control outputs, just

the ones that are in the longest delay path.

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Original ASM Chart

Zero?

ld_cnt = 1

Addr_sel =1, zero_we = 1,cnt_en = 1

Cnt_eq?

Clr_Busy = 1Yes

No

NoYes

S0

S1

S2

Set_Busy = 1

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“ld_cnt” signal is now delayed via DFF

Zero?

Addr_sel =1, zero_we = 1,cnt_en = 1

Cnt_eq?

Clr_Busy = 1Yes

No

NoYes

S0

S1

S2

Set_Busy = 1ld_cnt = 1

Assertion moved to previous state

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How do I add DFFs to FSM outputs?

• In two process VHDL model, explicity add DFFs via separate signals

comblogic: process (zero, cnt_eq, pstate) begin -- default assignments ld_cnt <= '0'; ….. Etc….

stateff:process(clk) -- process has DFFs only begin if (reset = '1') then pstate <= S0; elsif (clk'event and clk='1') then pstate <= nstate; -- updated present state with next state ld_cnt_dly <= ld_cnt; -- DFF on ld_cnt line. Connect endif; -- ld_cnt_dly to counter end process stateff;

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How do I add DFFs to FSM outputs? (cont) begin state <= pstate; -- look at present state for debugging purposes stateff:process(clk) -- process has state transistions ONLY begin if (reset = '1') then pstate <= S0; elsif (clk'event and clk='1') then -- rising edge of clock

CASE pstate IS WHEN S0 => if (zero = '1') then ld_cnt <= 1; pstate <= S1; end if;

WHEN S1 => pstate <= S2; WHEN S2 => if (cnt_eq = '1') then pstate <= S0 ; end if; WHEN others => pstate <= S0; end case; end if; end process stateff; set_busy <= '1' when (pstate = S0 and zero = ‘1’) else '0'; addr_sel <= '1' when (pstate = S2) else '0'; zero_we <= '1' when (pstate = S2) else '0'; cnt_en <= '1' when (pstate = S2) else '0'; clr_busy <= '1' when (pstate = S2 and cnt_eq = '1') else '0'; end a;

In one process model, put ld_cnt inside of state process!

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Determining Longest Paths

• If your design does not meet the Clock frequency target of 25 Mhz, then need to determine the longest paths

• The “list paths” button will list longest paths.

List paths button.

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Longest register to register path will be the Clk2Q of first DFF to D input of 2nd DFF. Path is reported as:

‘1’.q - the ‘1’ is the component number on schematic.

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A Resource Limitation

• In Lab #7, the 16 coefficients were stored in a LPM_RAM_DQ that was configured as 16 x 9.

• In the project, cannot store the coefficients in one RAM. Would take 16 clock cycles to read all 16 coefficients, you only have 12 clocks.

• If use four datapaths, may want to split coefficients into four groups.

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A Resource Limitation (cont)

• Could use four LPM_RAM_DQs configured as 4x9.• However, a RAM_DQ uses an Embedded Array

Block (EAB). Only 6 EABs on the the Flex 10K20.• An EAB can be configured as 256 x8, 512 x 4, 1024

x 2, or 2048 x 1. Each 4x9 RAM would take two EABs, would need 8 EABs total! Not enough!– One solution would be to use three 4x9 RAM_DQs, then

make up another “psuedo” RAM_DQ using registers.

– Could store all coefficients in registers, but may run short of gates when implementing the maximum initiation rate solution.