boundary-scan driven vectorless testing on active components
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Boundary-Scan driven Vectorless Testing on Active Components. Steve Hird Loveland, CO. Purpose. Describe a methodology that extends Boundary-Scan driven Vectorless test to include active components. Outline. Review Existing technology used for connectors - PowerPoint PPT PresentationTRANSCRIPT
Boundary-Scan driven Vectorless Testing on Active Components
Steve Hird
Loveland, CO
BTW 2009 2
Purpose
Describe a methodology that extends
Boundary-Scan driven Vectorless test to
include active components.
BTW 2009 3
Outline
• Review Existing technology used for
connectors
• Examine the unique challenges of active
components
• Examine some target devices
• Conclusions
BTW 2009 4
• Combine Boundary-Scan drivers with
TestJet/VTEP sensors.
• Use Boundary-Scan drivers in place of In-
Circuit drivers for guarding and stimulus, but
retain capacitive pickup of signal.
Using Boundary-Scan for Test Stimulus in VTEP test.
BTW 2009 5
Using Boundary-Scan for Test Stimulus
What are the advantages of this ?
• Test pins whose signals are not accessible
• Can eliminate access (cheaper fixtures)
• Validates the investment in Boundary-Scan
BTW 2009 6
Picture from paper 11.2 ITC 2008.
Using Boundary-Scan for Test StimulusWhat are the advantages of this ?
Boundary-Scan interface
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What are the challenges with active components?• Silicon devices require accurate setup
information.
• Connectors require very little pin information
for test generation. Most of the information is
external and gathered from the node data.
All pins are considered either fixed or inputs.
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Required Setup Information
• Pin orientation: Input, Output, Bidirectional
• Disabling information (DUT): All bidirectional,
output and buffer pins require disabling
• Disabling all devices involved in test
(connected to DUT)
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Incomplete Disabling Problems
• Sequential logic creates variability in
response
• Signals may add or cancel from run to run
• Causes high standard deviation.
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Standard Deviation and Testability
• Cpk = (Mean-LL)/(3 x Std Dev)
• Cpk 1.5 = 99.865% Yield
• Cpk 1.0 = 93.3% Yield
0 5 10 15 20
Measured Value
Sigma = 1
Sigma = 2
BTW 2009 11
Experimental Results – Incomplete Disabling
Standard Deviation
0
5
10
15
20
25
30
35
40
45
50
Pin Number
Perc
en
t o
f S
ign
al
Full Disabled
IncompleteDisable
BTW 2009 12
Board Coverage
(pins)
Potential
Coverage
(pins)
Existing
Coverage
(pins)
Package Type
Brd1 11* 44 0 FBGA
Brd2 32 44 0 FBGA
Brd3 41 44 0 FBGA
Brd3 38 44 0 FBGA
Experimental ResultsSi Parts Evaluated – DDR2
* Coverage before resolving issues discussed on next two slides.
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Experimental Results – DDR2 FBGA
DDR2 FBGA Data
0
10
20
30
40
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46
Pin
Cap
acit
ance
(S
cale
d)
LowLimit
Mean
Open
BTW 2009 14
DDR2 FBGAs are Challenging but Testable
• Small part geometries and lead frame yield
small signal on Vtep Sensor plate
• Care must be taken to minimize on board
noise sources
BTW 2009 15
Board Coverage
(pins)
Potential
Coverage
(pins)
Number of
Devices
Package Type
Brd6 - SRAM 198 252 4 100 QFP
Brd6 -DRAM 82 96 2 86 TSOP
Brd6 - DRAM 18* 96 2 86 TSOP
Si Parts Evaluated – SRAM, DRAM
* Coverage before resolving issues discussed on next two slides.
BTW 2009 16
Experimental Results – DRAM QFP
DRAM 100 pin QFP Data
0
100
200
300400
500
600
700
800
1 4 7 10 13 16 19 22 25 28 31 34 37 40
Pin Number
Ca
pa
cit
an
ce
(S
ca
led
)
LowLimit
HighLimit
Mean
Open
BTW 2009 17
Results of Experiments
• Learnings– Noise from surrounding circuits should be
minimized for best results– Disable DUT and connected devices for
test stability and increased coverage– Lead frame geometry plays important role
(similar to any Vtep test)
BTW 2009 18
Conclusion
• Active components can be tested using Boundary-Scan driven Vectorless Test Technology
• Proper disabling is critical
• Eliminating on board noise sources will increase coverage
• Technique reduces need for access
BTW 2009 19
Thank You!