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A Low Voltage High Output Impedance Bulk Driven

Regulated Cascode Current Mirror

Naresh Lakkamraju Ashis Kumar Mal

Department of ECE Department of ECENational Institute of Technology National Institute of Technology

Durgapur, India-713209 Durgapur, India-713209mail2rajuvarma@gmail.com akmal@ece.nitdgp.ac.in

Abstract This work proposes the design of a new low voltage

high output impedance CMOS current mirror that offers

enhanced output voltage compliance using bulk-driven

technique. The input/output characteristics of the proposed

current mirror are discussed. Designed circuit is simulated in aproprietary 180 nm CMOS process, using Cadence Spectre

and BSIM3v3 models. Simulated results with 0.8 V power

supply and 50 A input current reveal that the proposed

implementation requires a minimum input and output voltages

of 0.4 V and 0.39 V respectively. It yields an increase of the

output impedance compared with that of existing bulk driven

current mirrors, thus offering a potential solution to mitigate

the effect of ultra-deep submicron CMOS transistors used in

sub 1-V current mirrors and current sources. Compared to

high output impedance gate driven regulated cascode current

mirror (GDRCCM), low voltage high output impedance body

driven regulated cascode current mirror (BDRCCM) supports

higher output voltage swing. Thus, the proposed design finds

wide acceptability in low voltage and low power CMOS analog

integrated circuits.

Keywords CMOS, Low Voltage, Low Power, Body Driven

Technique, Current Mirror.

I. INTRODUCTIONColossal advances in CMOS technology have made it

possible to design chips with high integration density, betterperformance, and lower power consumption. To attain theseobjectives, the feature size of the CMOS devices has facedaggressive scaling down to very small features anddimensions. However, the power supply voltage has not

been scaled down proportionally to the device dimensions

in ultra deep sub-micron technology. The fundamentallimitation of low voltage circuit design using the existingdesign methodology is that the power supply must beat least equal to the sum of the magnitude of the cascode

p-type and n-type threshold voltages. Thus, several possibletechniques, such as bulk-driven, sub-threshold, self-cascode, and floating-gate have been developed to constructhigh performance analog circuits under low power supplyvoltages.

The bulk-driven technique, which uses bulk terminal assignal input, is a promising method as it achievesenhanced performance without having to modify theexisting structure of MOSFET circuits [1]. This techniquemay remove the limitation of threshold voltage effectively

by controlling weak positive bias between bulk and sourceof transistors, thereby reducing the total supply voltage ofcircuits. Furthermore, it is completely compatible with thestandard CMOS process. Hence, the bulk-driven techniqueis attracting more and more attention as an importantmethod for low-voltage low-power design [2].

Current mirrors (CM) are essential and widely usedbuilding blocks in analog integrated circuits. They are usedto perform current amplification, biasing, active loading andlevel shifting. Hence, their efficient design improves theoverall performance of the system. The most important

parameters of current mirrors are accuracy, input/outputcompliances, input/output impedances, bandwidth, linearity,noise and sensitivity to changes in load impedance. Due totechnology down scaling and its intrinsic benefits, the trendin VLSI design is to reduce voltage supply. Hence, lowvoltage and low power circuit designs are in great demand.So, it is necessary to develop some new structures of CMunder low voltage low power conditions to meet designrequirements of low voltage CMOS analog integratedcircuits [3-5].

There have been some current mirror realizations usingbulk driven technique [6-8]. But the critical parameters suchas accuracy, input/output impedances, linearity andinput/output compliances of those current mirrors arelimited. To attain high output impedance and linearity anew low voltage high output impedance regulated cascodecurrent mirror is proposed. The rest of the paper isorganized as follows. Section II discusses basic structureand principle of operation of the proposed design.Section III explores analytical formulations to extract

parameters such as input/output impedances of the proposedcurrent mirror and comparison of those with some existingcurrent mirrors. Section IV presents the simulation resultsof both the proposed current mirror and its gate drivenequivalent performed in a proprietary 180 nm CMOS

process. On the basis of results analyzed, section Vconcludes the significance of the proposed design in variouslow voltage and low power analog integrated circuits.

II. LOW VOLTAGE HIGH OUTPUT IMPEDANCE BODYDRIVEN REGULATED CASCODE CURRENT MIRROR

The conceptual schematic of the PMOS version of proposed current mirror is shown in Fig. 1. Circuitconsisting of M1, M2, M3, and IB2 forms output side of the

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current mirror. The feedback amplifier in this case is realized by the commonsource amplifierconsisting ofM3

Fig. 1. Conceptual schematic of proposed circuit

and its current source IB2. The basic ideais to use a feedbackamplifier to keep the drain to source voltage across M2 asstable as possible irrespective of the output voltage. Theaddition of this amplifier ideally increases the outputimpedance by a factor equal to one plus the loop gain overthat which would occur for low voltage low power bodydriven cascode current mirror (BDCCM) [7]. The circuitconsisting of M4, M5, M6, IB1, and Iin operates almostidentical to a diode connected transistor, but is used insteadto guarantee that all transistor bias voltages are accuratelymatched to those of the output circuitrary. As a result, Iout

will very accurately match Iin.The gate voltages of all PMOS transistors are connected

to a fixed voltage VG (the lowest potential of circuits usuallyground) to form the conduction channel beneath the gate.Input signal is directly imported to the bulk terminals of M2and M5 whose source drain currents are built by controllingweak positive bias between bulk and source of transistors.Low voltage high output impedance PMOS BDRCCM mayeliminate the limitation of threshold voltage on the signal

pathway, thereby achieving a low input/output voltage drop.The minimum input and output voltage drops of low

voltage high output impedance BDRCCM may be describedas

(1)

(2)

The minimum input and output voltage drops of high output

impedance GDRCCM may be described as

(3)

(4)

And here

For the weak positive bias between bulk and source oftransistor, the input voltage drop of low voltage high outputimpedance BDRCCM is less than or equal to 0.4 V, whichis much lower than that of high output impedanceGDRCCM.

III. CIRCUIT ANALYSISAnalytical formulations to extract parameters of the

proposed current mirror are performed in the followingsubsections.

A. Output impedance analysisThe small signal equivalent circuit to derive the

analytical expression for output impedance is shown in

Fig. 2. In the following analysis, stand for the transconductance, the trnsconductance due to

body effect, the output impedance of the transistor, outputimpedance of IB1, and output impedance of IB2 respectively.

Usually, is approximately equal to 3 [7]. Thetransistors numbers are indicated as subscripts of these

parameters. All the derivations are listed as follows.

(5)

In the Eq. (5)

and (6)

(7)

(8)

In the Eq. (8)

(9)

And let (10)

Substituting Eq. (9) and Eq. (10) in Eq. (8) gives

(11)

Fig. 2. Small signal equivalent circuit for output impedance calculation

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The Eq. (11) further reduces to

(12)

Substituting Eq. (6) and Eq. (12) in Eq. (5) produces

(13)

Output impedance (

(14)

From Eq. (13)

(15)

Therefore Eq. (15) shows the overall output impedanceof the proposed current mirror which is higher than that oflow voltage low power BDCCM [7] by a factor equal to one

plus loop gain.

B.Input impedance analysisThe small signal equivalent circuit to derive the

analytical expression for input impedance is shown inFig. 3 and all the derivations are listed below.

(16)

In the Eq. (5)

(17)

(18)

(19)

In Eq. (19)

Let (20)

Substituting Eq. (20) in Eq. (19) gives

(21)

In Eq. (21)

(22)

Fig. 3. Small signal equivalent circuit for input impedance calculation

Therefore

(23)

(24)

By substituting Eq. (23) and Eq. (24) in Eq. (16) gives an

expression for.

From that expression, the input impedance can be defined as

(25)Therefore

(26)

The Eq. (26) shows the overall input impedance of the

proposed current mirror.To get a clear understanding of the low voltage high

output impedance BDRCCM characteristics, they arecompared with low voltage low power BDCCM [7] andhigh output impedance GDRCCM [9]. They are listed inTable I. As shown in Table I, the low voltage high output

impedance BDRCCM has high output impedance than thelow voltage low power BDCCM and lower input/outputvoltage drops than the high output impedance GDRCCM. In

the Table I the parameters are the loop gains of thehighoutput impedance GDRCCM. Thus, it can be seen thatlow voltage high output impedance BDRCCM has a good

performance no matter as current mirror or current source.

IV. SIMULATION RESULTS AND DISCUSSIONSThe above implemented proposed current mirror was

simulated along with its gate driven equivalent in 180 nmCMOS process using Cadence Spectre and BSIM3v3

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models. The power supply used to simulate the proposed current mirror is 0.8 V rather standard available

TABLE I. THE CHARACTERISTICS OF DIFFERENT PMOS CURRENT MIRRORS

Current

mirror

Output impedance Input impedanceOutputvoltage

drop

Inputvoltage

Drop

Low voltageHigh output

impedance

BDRCCM

Low voltage

Low powerBDCCM

High output

impedance

GDRCCM

power supply 1.8 V, which was used to simulate the gate

driven equivalent of the proposed current mirror.Fig. 4 shows the DC output characteristics of the low

voltage high output impedance BDRCCM with outputvoltage (Vout) swept from 0 to 0.8 V and input current (Iin)stepped from 45 A to 55 A in 5 steps. Fig. 5 shows the DCoutput characteristics of the high output impedanceGDRCCM with output voltage (Vout) swept from 0 to 1.8 Vand input current (Iin) stepped from 45 A to 55 A in 5steps.

From Fig .4 and Fig. 5, it is observed that the proposedcurrent mirror has a bit lower or approximately equal outputimpedance than its gate driven equivalent.

Fig. 6 and Fig. 7 shows the DC input characteristics oflow voltage high output impedance BDRCCM and highoutput impedance GDRCCM respectively with Iin sweptfrom 20 A to 55 A. Furthermore, it is observed that theproposed current mirror has much lower input voltage dropthan its gate driven equivalent to get same amount of outputcurrent.

Fig. 4. DC output characteristics of low voltage high output impedance

BDRCCM

Fig. 8 and Fig. 9 shows the DC current transfercharacteristics of low voltage high output impedanceBDRCCM and high output impedance GDRCCMrespectively with Iin swept from 35 A to 55 A. From thesefigures, a conclusion can be deduced that the proposedcurrent mirror has the similar current transfer characteristicsas high output impedance GDRCCM for higher ordercurrents.

Fig. 5. DC output characteristics of high output impedance GDRCCM

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Fig. 6. DC input characteristics of low voltage high output impedance

BDRCCM

Fig. 7. DC input characteristics of high output impedance GDRCCM

Fig. 8. DC current transfer characteristics of low voltage high output

impedance BDRCCM

Fig. 8. DC current transfer characteristics of high output impedance

GDRCCM

V. CONCLUSIONWith the aim of attaining a high output impedance and

enhanced input/output voltage compliances under bulk

driven technique, a low voltage high output impedanceBDRCCM is designed and simulated using a 180 nm CMOS process. The proposed design exhibits enhanced outputimpedance than low voltage low power BDCCM and aninput voltage drop of 0.4 V and an output voltage drop of0.39 V for 50 A input/output current. Aforesaid simulationresults quite well justify that these input/output voltage dropsare much lower than high output impedance GDRCCM.Therefore, the proposed low voltage high output impedanceBDRCCM would be suitable for various wide range of lowvoltage and low power analog applications.

ACKNOWLEDGMENT

The authors would like to express their gratitude to Dr.Debashis Datta, MCIT, Govt. of India, for extending theSMDP project at NIT Durgapur. The authors delightfullyacknowledge Prof. S. K. Dutta, ex-chair of SMDP-II, NITDurgapur, for helpful discussions and encouragement. Theyalso express their cordial thanks to Mr. Rishi Todani, Mr.Kanchan B. Maji and Mr. Om Prakash Hari for all kinds oftechnical and moral support.

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