black box consulting 2009 brochure

Authorised Training Provider

Authorised Digilent Distributor


Black Box Consulting2009 Products & Services Brochure


Authorised Digilent Distributor 2



Table of Contents .................................................................................................................................... 3

Recruitment Services .............................................................................................................................. 4

Consulting Services ................................................................................................................................. 5

Xilinx Training Courses ............................................................................................................................ 6

Academy I ........................................................................................................................................ 7

Academy II ....................................................................................................................................... 9

Academy III .................................................................................................................................... 11

DSP Implementation Techniques using Xilinx FPGAs .................................................................... 14

DSP Design Using System Generator ............................................................................................ 15

Embedded System Development .................................................................................................. 16

Advanced Features & Techniques of Embedded System Development ....................................... 17

Embedded System Software development .................................................................................. 18

Embedded Open-Source Linux Development ............................................................................... 19

Designing with Ethernet MAC Controllers .................................................................................... 20

Designing with Multi-Gigabit Serial I/O ........................................................................................ 21

Advanced VHDL ............................................................................................................................. 22

Fundamentals of CPLD Design ...................................................................................................... 23

Designing For Performance for CPLDs .......................................................................................... 24

Designing with Virtex-4 ................................................................................................................. 25

Designing with Virtex-5 ................................................................................................................. 26

Digilent Xilinx Demo Boards .................................................................................................................. 27

Pricing Guide ......................................................................................................................................... 29

Recruitment .................................................................................................................................. 29

Training ......................................................................................................................................... 29

Consulting ..................................................................................................................................... 29

Credit Packages ............................................................................................................................. 30

Terms & Conditions............................................................................................................................... 31

Contact Details / About Us .................................................................................................................... 33

Table of Contents



Black Box Consulting can offer you a complete recruitment package which can include training.

When you recruit with us we can offer you:

• A partnership where we will work with you to understand your business

• Expertise allowing us to understand the requirements of employees at a technical level

• FPGA training to ensure new employees start with the knowledge and skills needed to

contribute to your business from day one

In a technical environment, where knowledge relates to time to market, it’s important to ensure you

recruit engineers with sound technical ability and promise, as well as the ability to form a team with

strong morale and work ethic for tangible results. How do you do this?

At Black Box consulting we:

• Take a firm brief of the role and thoroughly understand it

• Assist with Job Descriptions, salary expectations, writing and placement of adverts

• Provide advice, assist in writing, and conduct technical assessments for further screening

• Create a candidate sourcing strategy from local and overseas markets if applicable

• Work closely with Universities to source talented and fresh Engineers

• Control the entire recruitment process from sourcing, reviewing and filtering applications, to

short listing, interviewing and providing reports

• Carry out reference checking and optional background and Psychometric testing

• Provide you with professional recruitment advice throughout the entire process at a

personnel and engineering level

• Follow up with new employees during those more difficult first six months, and can act as a

neutral entity for employee reviews

Recruitment can be an underestimated and ongoing concern for many companies. The process can

take a considerable amount of time and resources through out, let alone if it needs to be repeated.

Our aim is to reduce the resources and time required from your company and at the same time

delivery exceptional value and quality candidates from your recruitment campaigns.

Roles recruited in the past:

Engineering Management Sales Marketing

Electronic Engineers General Manager Sales Manager Technical Marketing

Electrical Engineers State Managers Account Managers Brand Managers

Project Managers Product Managers Sales Engineers Marketing Analysts

Our services can also be broken down into modules to integrate into your existing HR practices.

Recruitment Services



At Xilinx, as a Strategic Applications Engineer, Peter Boxall spent his time supporting his assigned

customers’ designs. Xilinx also offer a ‘Titanium Support Service’ to assign customers a dedicated

Engineer for short term assistance for anything from achieving timing closure to troubleshooting

designs. During his time at Xilinx, this is something Peter did frequently, and was also the first

Engineer at Xilinx to be assigned to this service in 1999.

Many customer issues come down to Timing Closure, including properly constraining designs and

ensuring synchronous design techniques are used to avoid those unexplained and intermittent

issues. Other times it can simply be to improve design utilisation, frequency or reduce runtimes.

Black Box Consulting offers consultative services of this manner to help you build faster:

• Design Implementation Support

o Xilinx interface

o Flow support

o Troubleshooting errors

o Floorplanning/PlanAhead

o Run Times

• Timing Closure and consistency

o Assistance with fully constraining your design and ensuring all paths are covered and

not over constrained

o Design and implementation techniques and flow support to ensure you’re using the

best synthesis and implementation options to get the best performance.

o PlanAhead flows to achieve timing and run time needs

There are lots of tricks and techniques we can use to help get you over the line. We encourage

knowledge transfer so you also learn along the way.

• Troubleshooting

o Design not working, or intermittently? Common reasons include asynchronous

design or incomplete timing constraints. Let us bring fresh eyes to the table.

• Open Days

o Common for companies with multiple design groups or large teams. Have us onsite

in a meeting room from time to time, where engineers can come and ask questions,

fill in knowledge gaps, discuss implementation issues and ask advice.

We provide consulting services both on and offsite, or a mixture of both.

At this time, Black Box Consulting specialise their efforts on FPGA design support services and not

full design house services. However, small design examples, modular assistance, and design

conversions are within our scope. We do work closely with a small alliance of Design House

companies in Australia. Please contact us for further details for such recommendations.

Consulting Services



There are a number of ways we can provide Training to you:

• Onsite Training. Starting from groups of only 3 people up to 12, arrange private, dedicated

and tailored training at your own offices without having to wait for public schedules

• Public Training. Low cost training for individual engineers.

• Online – Live Instructor Led Training. Attend training from the comfort of your home or

office, break a 5 day course into smaller blocks, reduce travel and accommodation costs and

still have live training with real time presentations and questions. During labs you can share

your PC applications (such as ISE) with the presenter, or even log in to one of our remote

Training PCs located right next to the presenter. Using WebEx Training software it’s as good

as having a presenter in the room with you.

Academy I

Using the Xilinx Integrated Software Environment (ISE)

Fundamentals of FPGA Design

Comprehensive Introduction to VHDL

Academy II

FPGA Design Tips & Techniques

Designing for Performance

Academy III

Advanced FPGA Design

Chipscope Pro Use and Debug Guide

Designing with PlanAhead

DSP courses

DSP Implementation Techniques using Xilinx FPGAs

DSP Design Using System Generator

Embedded Courses

Embedded System Development

Advanced Features & Techniques of Embedded System Development

Embedded Systems Software Development

Embedded Open-source Linux Development

Connectivity Courses

Designing with Ethernet MAC Controllers

Designing with Multi-Gigabit Serial I/O

Other Courses

Advanced VHDL

Fundamentals of CPLD Design & Designing for Performance for CPLDs

Designing with Virtex-4

Designing with Virtex-5

Xilinx Training Courses

Version 10.1i rev2 Course Specification

7

© 2008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Xilinx Academy I

www.blackboxconsulting.com.au

Xilinx Academy I Description: The Academy I course consists of 3 packaged courses including:

• ISE Design Entry (1 Day) • Fundamentals of FPGA Design (1 Day) • Comprehensive Introduction to VHDL (3 days)

Promotion: Save $60 per day and receive a free Digilent Nexys2 Demo Board worth $180. Purchase all 5 days at AU$2700 + GST. Further discounts are available with our credit packages Individual Days are AU $600 + GST

ISE Design Entry In this course you will learn about project structure, process windows, various ISE® software design flows, and Xilinx Synthesis Technology (XST). You will examine XST synthesis and use the XST constraints file in the Project Navigator GUI. You will learn about the Engineering Capture System (ECS) , the State Diagram Editor and Simulator tools.

After completing this comprehensive training, you will have the necessary skills to:

� Create a new Project Navigator project in the ISE software

� List the design flows available in the ISE software

� Access and modify XST synthesis options

� Create a schematic design by using the ECS schematic entry tool

� Create a symbolic state machine using the State Diagram Editor

� Create testbenches and simulate a design using the TestBench Wizard and the ISE Simulator

Course Outline

� Course Agenda

� Projects in the Project Navigator

� Lab 1: Projects in the Project Navigator

� HDL Synthesis and XST

� Lab 2: XST Synthesis Options

� ECS: Engineering Capture System

� Lab 3: ECS

� State Diagram Editor

� ISE Simulator

� Lab 4: ISE Simulator and the State Diagram Editor

� Additional Features

� Summary

Lab Descriptions

� Lab 1: Projects in the Project Navigator – Gain comprehensive hands-on experience with the HDL flow in the ISE software.

Create a new project, add source files, synthesize a design, and use the error navigation feature.

� Lab 2: Synthesis Options – Modify XST synthesis properties, read synthesis reports to compare the synthesis results, and use the snapshot utility.

� Lab 3: ECS – Perform the basic tasks of the schematic editor, such as adding symbols, connecting symbols with wires, naming wires and buses, adding I/O markers, and using the Xilinx CORE Generator™ tool with ECS.

� Lab 4: ISE Simulator and the State Diagram Editor – Perform the simulation and verification process of the design cycle. Demonstrate how these tools are incorporated into the ISE tools.

Fundamentals of FPGA Design Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices and understand the subtleties of the Xilinx design flow. This course covers ISE 10.1 features, such as the Architecture Wizard and the Floorplan Editor. Other topics include design planning, implementation options, and global timing constraints.

Three recorded E-Learning Modules are available for this course: www.xilinx.com/education and click the Recorded e-Learning link. After completing this comprehensive training, you will have the necessary skills to:

� Use the Xilinx Project Navigator to implement and simulate an FPGA design

� Read reports and determine whether your design goals were met

� Use the Architecture Wizard to create DCM instantiations

� Use the Floorplan Editor and PinAhead to make good pin assignments

� Use the Xilinx Constraints Editor to enter global timing constraints

� Locate and modify the implementation options

Course Outline

� Course Agenda

� Xilinx Tool Flow

� Lab 1: Xilinx Tool Flow

� Reading Reports

� Lab 2: Architecture Wizard and Floorplan Editor/PACE

Who Should Attend? – Designers who wish to gain a well rounded knowledge of the ISE 10.1 design tools Recommended

� Basic FPGA Architecture knowledge Software Tools

� Xilinx ISE Foundation™ 10.1 Design Tools

Who Should Attend? – Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs Prerequisites

� Basic FPGA Architecture RELs: Slice and I/O Resources, Memory and Clocking Resources, Architecture Wizard and Floorplan Editor

� Digital design experience Recommended

� Basic HDL Coding Techniques REL* (parts 1 and 2)

� Spartan-3 FPGA HDL Coding Techniques REL* (parts 1 and 2)

� Virtex-5 FPGA HDL Coding Techniques REL* (parts 1 and 2) Software Tools

� Xilinx ISE Foundation™ 10.1 software with the ISE Simulator

Version 10.1i rev2 Course Specification

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Xilinx Academy I


� Lab 3: Pre-Assigning I/O Pins Using PinAhead

� Global Timing Constraints

� Lab 4: Global Timing Constraints

� Implementation Options

� Lab 5: Implementation Options

� Synchronous Design Techniques

� Course Summary

Lab Descriptions

� Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the Architecture Wizard and the Floorplan Editor or PACE in the design process. Implement a design by using default software options. The design will be simulated and downloaded to a Spartan®-3E FPGA 1600 demo board.

� Lab 2: Architecture Wizard and Floorplan Editor/PACE – Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use the Floorplan Editor to assign pin locations and implement the design.

� Lab 3: Pre-Assigning I/O Pins Using PinAhead – This lab introduces the basics of making good I/O pin assignments with PinAhead. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow I/O banking rules.

� Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for timing constraints.

� Lab 5: Implementation Options – Adjust process properties and I/O configuration options to improve the design performance.

Comprehensive Introduction to VHDL This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing Register Transfer Level (RTL) and behavioral source code. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts and advanced coding techniques that will increase your overall VHDL proficiency

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this

course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. After completing this comprehensive training, you will have the necessary skills to:

� Write RTL VHDL code for synthesis

� Write VHDL testbenches for simulation

� Create Finite State Machines (FSMs) by using VHDL

� Target and optimize Xilinx FPGAs by using VHDL

� Create RAM and ROM data structures

� Use VHDL scalar and composite data types

� Run a simulation by using VITAL libraries

� Use the VHDL textio package during simulation

� Create and manage designs within the ISE design environment

Course Outline

Day 1 � Course Agenda

� Hardware Modeling Overview

� VHDL Language Concepts

� Lab 1: Building Hierarchy

� Introduction to Testbenches

� Lab 2: VHDL Simulation and RTL Verification

� Signals and Data Types

� VHDL Operators and Expressions

� Lab 3: Memory

Day 2 � Concurrent and Sequential Statements

� Lab 4: Clock Divider and Address Counter

� Controlled Operation Statements

� Lab 5: n-bit Binary Counter and RTL Verification

� VITAL: VHDL Initiative toward ASIC Libraries

� Lab 6: Timing Simulation

� Behavioral to RTL Coding

Day 3 � Finite State Machines

� Lab 7: Finite State Machines

� Targeting Xilinx FPGAs

� Lab 8: Implement and Download

� Functions and Procedures

� Advanced Process Statements

� Lab 9: Text I/O

Lab Description The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits. The labs culminate in a functional calculator that you will verify in simulation.

Register Today Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand. For more information, such as our range of courses, current schedules, and other services including consulting and recruitment/training packages, please use one of the contact methods below: Black Box Consulting PO Box 1147 Stafford City QLD 4053 Tel: + 61 7 3137 0905 www.blackboxconsulting.com.au

Who Should Attend? – Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs Prerequisites

� Basic digital design knowledge Software Tools

� Xilinx ISE® Foundation™ software 10.1 with the ISE Simulator

V10.1i Rev1 Course Specification

9


Xilinx Academy II www.xilinx.com


Xilinx Academy II Description: The Academy II course consists of 2 packaged courses including:

• Design Tips & Techniques for Low Cost (2 days) • Designing For Performance (2 days)

Promotion: Save $50 per day. Attend the full Academy II at AU$2200 + GST. Further discounts available with credit packages Individual days are AU $600 + GST.

Design Tips & Techniques This course appeals to engineers who have an interest in good design techniques, to produce compact design (for lower coast) with additional discussion on Logic Levels for Timing. The course and exercises cover several different design techniques, which will be interesting and challenging for any digital designer regardless of the final application.


� Describe the features of the Spartan-II(E) and Spartan-3 devices

� Accurately estimate design size to aid in predicting product costs

� Apply design techniques that result in low-cost implementations

� Explore creative ways to use the FPGA memory resources to reduce design costs

Course Outline � Refresh: What is an FPGA?

� Spartan and Virtex Family

� CLBs, Slices and BRAM

� Multiplexers

� Flip-Flop Controls

� Synchronous Timing vs. Asynchronous Timing

� Digital Clock Managers

� Number Representation

� Dedicated Carry Logic

� Counters

� Wired Carry Gates

� Block MemoryDistributed RAM

� FIFO

� Dual Port Memory

� State Machines

� DSP48 Blocks

� Design Challenges

Exercises

� Exploring the Slice

� LUT Functions

� Logic Levels

� Dedicated Multiplexers

� Flip Flop Controls

� Performance by Design

� Clocks

� Counters

� Fractional Number Formats

� Adders

� Wired Carry Gates

� Aspect Ratios

� Replacing Logic with Block RAM

� Distributed RAM

� Essence of FIFO

� Delay

� State Machines

� DSP48

� Optional Design Challenges

Designing for Performance Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

Note that one of the prerequisites of Designing for Performance is the completion of the HDL coding style modules listed below (or attend the much more comprehensive Intro to VHDL course). Go to www.xilinx.com/education and click the Recorded e-Learning link to view these recorded modules.

Level – Fundamental - Intermediate Prerequisites

� An understanding of digital design and the concept of an FPGA

� Basic – Intermediate VHDL skills Supported Devices Note: software is only required to run optional exercises

� Spartan™- 3E/A/AN/DSP

� Virtex-4, Virtex-5

Level – Intermediate Prerequisites

� Fundamentals of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor

� Intermediate HDL knowledge (VHDL or Verilog)

� Solid digital design background

� Basic HDL Coding Techniques REL (parts 1 and 2)

� Spartan-3 FPGA HDL Coding Techniques REL (parts 1 and 2)

� Virtex-5 FPGA HDL Coding Techniques REL (parts 1 and 2) Software Tools

� ISE Foundation™ software 10.1 with the ISE Simulator

� ChipScope™ Pro software


10


Xilinx Academy II www.xilinx.com



� Describe a flow for obtaining timing closure

� Describe architectural features of the Virtex-5 FPGA

� Describe the features of the Digital Clock Manager (DCM) and Phase-Locked Loop (PLL) and how they can be used to improve performance

� Increase performance by duplicating registers and pipelining

� Describe different synthesis options and how they can improve performance

� Create and integrate cores into your design flow by using the CORE Generator™ software system

� Run behavioral simulation on an FPGA design that contains cores

� Pinpoint design bottlenecks by using the Timing Analyzer reports

� Apply advanced timing constraints to meet your performance goals

� Use advanced implementation options to increase design performance

Course Outline

Day 1

� Review of Fundamentals of FPGA Design

� Designing with Virtex-5 FPGA Resources

� CORE Generator Software System

� Lab 1: CORE Generator Software System

� Designing Clock Resources

� Lab 2: Designing Clock Resources

� FPGA Design Techniques

� Synthesis Techniques

� Lab 3: Synthesis Techniques

Day 2

� Achieving Timing Closure

� Lab 4: Review of Global Timing Constraints

� Timing Groups and OFFSET Constraints

� Path-Specific Timing Constraints

� Lab 5: Achieving Timing Closure

� Advanced Implementation Options

� Lab 6: Designing for Performance

� Power Estimation (Optional)

� Lab 7: FPGA Editor Demo (Optional)

� ChipScope Pro Software (Optional)

� Lab 8: ChipScope Pro Software (Optional)

Lab Descriptions � Lab 1: CORE Generator Software System – Create a core,

instantiate the core into VHDL or Verilog source code, and run behavioral simulation.

� Lab 2: Designing Clock Resources – Use the Clocking Wizard to configure DCMs and global clock buffer resources.

� Lab 3: Synthesis Techniques – Experiment with different synthesis options and view the results. Versions of this lab are available for Synplicity Synplify Pro, Precision RTL, and Xilinx XST software.

� Lab 4: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.

� Lab 5: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to meet performance goals.

� Lab 6: Designing for Performance – Improve performance and maximize results solely with implementation options.

� Lab 7: FPGA Editor Demo – Use the FPGA Editor to view a design and add a probe to an internal net.

� Lab 8: ChipScope Pro Software – Add an internal logic analyzer to a design to perform real-time debugging.

Register Today Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand. For more information, such as our range of courses, current schedules, and other services including consulting and recruitment/training packages, please use one of the contact methods below: Black Box Consulting PO Box 1147 Stafford City QLD 4053 Tel: + 61 7 3137 0905 Fax: +61 7 39015586



11


Xilinx Academy III


Xilinx Academy III Description: The Academy III course consists of 3 packaged courses including:

• Advanced FPGA Implementation (2 days) • Chipscope Pro Debug & Verification (1 day) • Designing with PlanAhead ( 2 days)

Promotion: Save $80 per day. Attend this 5 day Academy III at AU$2600 + GST. Further discounts available with credit packages Individual days are AU $600 + GST

Advanced FPGA Implementation This course tackles the most sophisticated aspects of the ISE® 10.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day course and cover the Xilinx Synthesis Technology (XST) tools. This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 10.1 tools and the Virtex®-5 and Spartan®-3E FPGAs.


� Implement designs via the Tcl command line

� Create and edit timing constraints in the UCF file

� Identify the I/O timing constraints and design modifications required for source-synchronous and system-synchronous interfaces

� Preserve design results by using SmartGuide™ technology or partitions

� Use the Floorplan Editor or Pinout and Area Constraints Editor (PACE) to create area constraints

� Change signals of interest in the ChipScope™ Pro tool for board-level debugging using the FPGA Editor

Course Outline � Introduction

� Lab 1: Achieving Timing Closure and Review of Global Timing Constraints

� Tcl Scripting

� Lab 2: Tcl Scripting

� UCF Editing

� Lab 3: UCF Editing

� Advanced I/O Timing

� Lab 4: Advanced I/O Timing

� SmartCompile™ Technology Design Preservation Techniques

� Lab 5: SmartCompile Technology

� Floorplanning an Effective Layout

� Lab 6: Floorplanning

� FPGA Editor: Viewing and Editing a Routed Design

� Lab 7: Advanced FPGA Editor

Lab Descriptions Note: Labs will be based on Xilinx ISE 10.1 software.

� Lab 1: Achieving Timing Closure and Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.

� Lab 2: Tcl Scripting – Write ISE tool control commands in a Tcl script file to implement the design. Then modify program switches to obtain the greatest possible performance from the design.

� Lab 3: UCF – Write constraints directly into a UCF file to guide the performance results of implementation.

� Lab 4: Advanced I/O Timing – Compose timing constraints for an I/O interface. Analyze the timing failures and determine changes to correct the timing issues. Modify the design to fix timing failures.

� Lab 5: SmartCompile Technology – Utilize SmartGuide technology and partitions to preserve the timing results from one iteration to the next.

� Lab 6: Floorplanning – Implement a design by using floorplanned constraints to enhance the timing results over a design without floorplanning.

� Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.

Chipscope Pro Debug & Verification As FPGA designs become increasingly more complex, designers are searching to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for debug and verification. This one-day course will show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.

Level – Advanced Prerequisites

� Fundamentals of FPGA Design

� Designing for Performance

� Intermediate knowledge of Verilog or VHDL is strongly recommended

� At least six months’ design experience with Xilinx tools and FPGAs

Software Tools

� Xilinx ISE Foundation™ 10.1 software with the ISE Simulator

� ChipScope™ Pro software


� FPGA design experience or completion of the Xilinx Fundamentals of FPGA Design course

� ChipScope Pro Software REL strongly recommended (www.xilinx.com/support/training/rel/chipscopepro-rel.htm)

Software Tools

� ISE™ 9.2i software

� ChipScope Pro 9.2i software

� ChipScope Pro Serial I/O Toolkit 9.2i*

� Agilent Logic Analyzer Application Software*


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Xilinx Academy III



� Maximize ChipScope Pro tool core performance

� Minimize negative timing impacts on a design

� Use techniques that enhance and extend the capabilities of the ChipScope Pro tools

� Enable and identify the advantages of remote debugging

� Analyze, set up, and debug high-speed serial I/O designs*

� Use the Agilent solutions to overcome storage issues and perform a system-level debug*

Course Outline � Agenda and Introduction

� Lab: Adding the ILA Core to an Existing Design and/or Adding the ILA and VIO Cores for Remote Monitoring and Control

� Timing Implications

� Demo: Minimizing ILA Core Impact with the PlanAhead Software

� Tips and Tricks

� Lab: Tips and Tricks

� Remote Debug

� Lab: Enabling Remote Debug*

� High-Speed Serial I/O Debug and Verification (Optional*)

� Lab: High-Speed Serial I/O Debug and Verification (Optional*)

� Agilent Solutions for Storage Qualification and System-Level Debug (Optional*)

� Lab: Inserting the Agilent ATC2 Measurement Core and Viewing Internal Activity with the FPGA Dynamic Probe (Optional*)

� Lab: Performing System-Level Debug with the Agilent FPGA Dynamic Probe (Optional*)

* Please check with your ATP to confirm whether this content is included with your specific class.

Lab Descriptions

� Adding the ILA Core to an Existing Design – You will use the Core Inserter tool flow for adding the ChipScope Pro tool ILA cores into a design to rapidly locate and solve a simple logic problem.

� Adding the ILA and VIO Cores for Remote Monitoring and Control – You will instantiate ICON, ILA, and VIO cores into a VHDL or Verilog design and practice monitoring signals of interest and externally driving select control signals.

� Tips and Tricks – This lab demonstrates the flexibility of the ChipScope Pro tool solution as you explore data qualification, cross-clock domain analysis, and oversampling techniques.

� Enabling Remote Debug* –This lab demonstrates how the ChipScope Pro tools can be used across a network. You will connect to another team’s board, download your bitstream, and remotely monitor the other team’s board on your machine.

� High-Speed Serial I/O Debug and Verification* – You will use the Xilinx ChipScope Pro Serial I/O Toolkit for the RocketIO™ transceivers in the Virtex™-5 FPGA. You will generate the ChipScope Pro tool IBERT design for the Virtex-5 XC5VLX50T device and customize it for the ML505 board. You will then connect two GTPs on the ML505 board and use the ChipScope Pro Analyzer tool to control the GTP parameters and monitor the effects.

� Inserting the Agilent ATC2 Measurement Core and Viewing Internal Activity with the FPGA Dynamic Probe* – You will leverage external memory resources by using the Agilent ATC2 Core, FPGA Dynamic Probe, and Virtual Logic Analyzer to address storage demands.

� Performing System-Level Debug with the Agilent FPGA Dynamic Probe* – You will see how the Agilent solution is used to reduce the time required to validate and determine the root cause of problems in FPGA-based systems.

Designing With PlanAhead Learn to increase design performance and achieve repeatable results by using the PlanAhead™ software tool. Topics include: a product overview, synthesis and project tips, design analysis, creating a floorplan, improving performance, experimenting with implementation options, incremental methodology, block-based IP design, and I/O pin assignment.

Note: The hands-on labs provided within this course are identical to the tutorials that are packaged with the PlanAhead tool. This course is supplemented with instructor-led presentations and demos.


� List the main features and benefits of the PlanAhead tool

� Import designs into the PlanAhead tool project environment

� Assign optimal I/O pin locations

� Import HDL sources and elaborate and analyze an RTL netlist

� Analyze design statistics, connectivity, timing, and placement results

� Run the Design Rule Checker (DRC) and Weighted Average Simultaneous Switching Output (WASSO) analysis

� Partition and floorplan designs

� Run ExploreAhead to try multiple implementation strategies

� Import and analyze the implementation results to improve the floorplan

� Floorplan to improve performance and consistency

� Use block-based design and create reusable IP


� Fundamentals of FPGA Design or equivalent knowledge of the FPGA architecture and the Xilinx ISE® software flow

� Designing for Performance recommended Software Tools

� Xilinx ISE® Foundation™ 10.1 software

� PlanAhead software 10.1


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Xilinx Academy III


Course Outline

Day 1 � Course Overview

� Lab 1: Getting Started with the PlanAhead Tool

� I/O Pin Planning

� Lab 2: Assigning I/O Pins

� Design Analysis and Exploration

� Lab 3: Design Analysis and Exploration

� Design Partitioning and Top-Level Floorplanning

� Lab 4: Design Partitioning and Top-Level Floorplanning

Day 2 � Implementing a Floorplanned Design

� Lab 5: Implementation

� Floorplanning Techniques

� Lab 6: Floorplanning

� Tuning a Floorplan for Performance

� Lab 7: Floorplan Tuning

� Block-Based Design and IP Reuse

� Lab 8: Block-Based Design and IP Reuse

� Floorplanning Strategies

� Course Summary

Lab Descriptions Note: All labs within this course are also available as self-guided tutorials, which are packaged with the PlanAhead tool.

� Lab 1: Getting Started with the PlanAhead Tool – Illustrates the steps you take to import a synthesized design into the PlanAhead tool so that you can begin floorplanning. Also introduces the PlanAhead tool environment and views.

� Lab 2: Assigning I/O Pins – Introduces the PinAhead environment for performing I/O pin assignment. You will create a project, import and export I/O ports lists, create I/O ports and interfaces, and make pin assignments.

� Lab 3: Design Analysis and Exploration – Introduces the analysis features of the PlanAhead tool that enable early detection of potential design issues, alternate device selection, initial floorplanning direction, and post-implementation exploration.

� Lab 4: Design Partitioning – Introduces the concept of floorplanning. By using automated partitioning tools, you will create a top-level floorplan and experiment with sizing and shaping Pblocks based on resources assigned to them.

� Lab 5: Implementation – Introduces the integration of the ISE software implementation tools with the PlanAhead tool. Also introduces the ExploreAhead tool for queuing multiple ISE software runs with varying strategies.

� Lab 6: Floorplanning – Describes how to analyze implementation results and to use that information to generate a floorplan aimed at increasing design performance.

� Lab 7: Floorplan Tuning – Introduces techniques to help close on timing targets consistently.

� Lab 8: Block-Based Design and IP Reuse – Describes the steps to implement a block-based methodology that includes the creation and reuse of an IP module.

Register Today Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand. For more information, such as our range of courses, current schedules, and other services including consulting and recruitment/training packages, please use one of the contact methods below: Black Box Consulting PO Box 1147 Stafford City QLD 4053 Tel: + 61 7 3137 0905 Fax: +61 7 39015586


DSP20000-7-ILT (v1.0) Course Specification

14


DSP Implementation

Techniques for Xilinx FPGAs


Course Description This course shows you how to take advantage of the features available in the Xilinx FPGA architecture, including the Virtex™-4 FPGA, and describes how DSP algorithms can be implemented efficiently. The techniques also demonstrate which decisions at the system level have the greatest impact on the implementation process and product costs.


� Describe how DSP algorithms can be implemented efficiently by using Xilinx FPGA technology

� Identify the capabilities and features of the various Xilinx FPGA families to implement efficient DSP algorithms

� Establish methods for the accurate estimation of silicon area consumption and cost

� Evaluate which algorithms are best suited for FPGA implementation and identify which algorithms are less desirable

� Assess how system-level decisions impact hardware implementation and how hardware implementation can enhance results at the system level

Course Outline Day 1 � On the Same Wavelength

� Basic terminology and acronyms used in DSP design

� Sample rates and bit widths used in DSP applications

� DSP building blocks and processing requirements

� Some Bits About Numbers

� Numbering formats, range, and precision

� Mathematical operations using a variety of formats

� Tuning the Receiver

� Structure and Resources of Xilinx Devices

� Estimating DSP building block sizes

Day 2 � Tuning the Receiver (continued)

� Implementing the multiplication function

� Bit-width impact on system-level decisions

� Memories are Made of This

� Block versus distributed memory

� SRL16E and the delay function

� Memory aspect ratios and their manipulation

� Selective Filters

� FIR filter specifications and implementation

� Selecting a technique for a given specification

� Effects of halfband and interpolated filters

Day 3 � One Filter Does Not Make a System

� Options to be considered with multiple channels

� Interpolation and decimation � Rate changing and its effect on FIR filter choice

� Filtering algorithms that exploit device architecture

� Importance of connectivity versus isolated functions

� Do Not Block the Datapath

� Numeric controlled oscillators and mixers

� Strategies for FFT implementation

� Achieving bandwidth requirements of the FFT

� Using the FPGA as an efficient co-processor 3

Course Exercises � MAC Rates and Memory Requirements

� Constructing a 128-Tap FIR Filter

� Fractional Number Formats

� Twos Complement Arithmetic

� Summation by Addition Tree

� Summation by Addition Chain

� Full Adder: How Many Slices?

� Summation Structure Sizes

� Serial Summation Structure

� 8-Bit by 12-Bit Multiplier

� KCM Multipliers

� Distributed RAM for FIFO

� Size Estimates for Delay Structures

� Using the SRL16E as a FIFO

� Creating Larger RAM Structures

� Selecting a MAC FIR Technique

� Parallel FIR Filter Size

� Symmetry, Interpolation, and Phases

� Decimation Filter

� “fs/4” Mixing and Decimation

� Designing a Numeric Controlled Oscillator (NCO)

� FFT: Benchmarks and Transform Time

� Collection Time = Processing Time

� 128-Point FFT in 1.28 µs

Register Today Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand . For more information, such as our range of courses, current schedules, and other services including consulting and recruitment/training packages, please use one of the contact methods below: Black Box Consulting PO Box 1147 Stafford City QLD 4053 Tel: + 61 7 3137 0905 Fax: +61 7 39015586 [email protected] www.blackboxconsulting.com.au

Level – Advanced Course Duration – 3 days Price – $2000 + GST Course Part Number – DSP20000-7-ILT Who Should Attend? – Engineers and designers who have an interest in developing products that use digital signal processing Prerequisites A fundamental understanding of digital signal processing theory, including an understanding of the following principles:

� Sample rates

� Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters

� Oscillators and mixers

� Fast Fourier Transform (FFT) algorithm

DSP11000-10-ILT (v1.0) Course Specification

15


DSP Design Using System Generator


Course Description This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware co-simulation verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification using the Xilinx FPGA capabilities.


� Describe the System Generator design flow for implementing DSP functions

� Identify Xilinx FPGA capabilities and how to implement a design from algorithm concept to hardware simulation

� List various low-level and high-level functional blocks available in System Generator

� Identify the high-level blocks available for FIR and FFT designs

� Design a multiple-clock-based System Generator system

� Embed two System Generator designs into a larger design

Course Outline Day 1 � Introduction to System Generator

� Simulink Software Basics

� Lab 1: Using the Simulink Software

� Basic Xilinx Design Capture

� Lab 2: Getting Started with Xilinx System Generator

� Signal Routing

� Lab 3: Signal Routing

� Implementing System Control

� Lab 4: Implementing System Control

Day 2 � Multi-Rate Systems

� Lab 5: Designing a MAC-Based FIR

� Filter Design

� Lab 6: Designing a FIR Filter Using the FIR Compiler Block

� Xilinx System Generator, Project Navigator, and Platform Studio Integration

� Lab 7: System Generator and Project Navigator Integration

� Lab 8: System Generator, Project Navigator, and Platform Studio Integration

Lab Descriptions � Lab 1: Using the Simulink Software – Learn how to use the

toolbox blocks in the Simulink software and design a system. Understand the effect sampling rate.

� Lab 2: Getting Started with Xilinx System Generator – Illustrates a DSP48-based (ML505 board) design. Perform hardware co-simulation verification targeting an ML505 board.

� Lab 3: Signal Routing – Design padding and unpadding logic by using signal routing blocks.

� Lab 4: Implementing System Control – Design an address generator circuit by using blocks and Mcode.

� Lab 5: Designing a MAC-Based FIR – Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware co-simulation by using an ML505 board.

� Lab 6: Designing a FIR Filter Using the FIR Compiler Block – Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity. Verify the design through hardware co-simulation by using the ML505 board.

� Lab 7: System Generator and Project Navigator Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.

� Lab 8: System Generator, Project Navigator, and Platform Studio Integration – Learn how to embed two System Generator designs into a larger design and how VHDL created by System Generator can be incorporated into the simulation model of the overall system.


Level – Intermediate Course Duration – 2 days Price – AU$1400 + GST Who Should Attend? – System engineers, system designers, logic designers, and experienced hardware engineers who are implementing DSP algorithms using the MathWorks MATLAB® and Simulink® software and want to use Xilinx System Generator for DSP design Prerequisites

� Experience with the MATLAB and Simulink software

� Basic understanding of sampling theory Software Tools

� Xilinx ISE® Foundation™ 10.1 software with the ISE Simulator

� System Generator for DSP 10.1

� Platform Studio and Embedded Development Kit (EDK) 10.1

� MATLAB with Simulink software R2007a or R2007b

EMBD21000-7-ILT (v2.0) Course Specification

16


Embedded Systems Development


Course Description Xilinx FPGAs provide a new level of system design capabilities through soft MicroBlaze™ processors, hard PowerPC® processors, and silicon-efficient architectural resources. This course brings experienced FPGA designers up to speed on developing embedded systems using the Embedded Development Kit (EDK). The features and capabilities of the Xilinx MicroBlaze soft processor and the PowerPC 440 processor are also included in the lectures and labs. The hands-on labs provide experience with the development, debugging, and simulation of an embedded system.


� Describe the various tools that encompass the Xilinx Embedded Development Kit (EDK)

� Rapidly architect an embedded system containing a MicroBlaze or IBM PowerPC processor and Xilinx-supplied CoreConnect bus architecture IP by using the Base System Builder (BSB)

� Utilize the Eclipse-based Software Development Kit (SDK) to develop software applications and debug software

� Create and integrate your own IP into the EDK environment

Course Outline

Day 1 � EDK Overview

� Base System Builder

� Lab 1: Hardware Construction with the Base System Builder

� Software Development Using SDK

� Lab 2: Software, Implementation, and Download

� System Buses

� Hardware Design

� Hardware Design Using EDK

� Lab 3: Adding IP to a Hardware Design

Day 2

� Adding Your Own IP to the Embedded System

� Lab 4: Adding Custom IP to an Embedded System

� Software Debugging

� Linker Script Generator

� Lab 5: Software Debugging

� System Simulation

� Lab 6: Performing System Simulation

Lab Descriptions Both the MicroBlaze and PowerPC 440 processors are supported in the labs. All labs target the ML507 board.

� Lab 1: Hardware Construction with the Base System Builder – Create an XPS project by using the Base System Builder to develop a basic hardware system and generate a series of netlists for the embedded design.

� Lab 2: Software, Implementation, and Download – Complete the processes begun in Lab 1 by building the software libraries and applications, generating a bitstream file, merging the application into the bitstream, and downloading to the ML507 board.

� Lab 3: Adding IP to a Hardware Design – Learn to add IP from the many choices in the IP library. Use the GUI to add a general-purpose I/O module and access internal block RAM directly from the MHS file.

� Lab 4: Adding Custom IP to an Embedded System – Add custom IP to your design by using the Create and Import Peripheral wizard.

� Lab 5: Software Debugging – Run the Software Development Kit (SDK) to produce a debug perspective, set breakpoints, and debug the application.

� Lab 6: Performing System Simulation – Use ISIM to perform behavioral simulation of the completed design.

Register Today Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand . For more information, such as our range of courses, current schedules, and other services including consulting and recruitment/training packages, please use one of the contact methods below: Black Box Consulting PO Box 1147 Stafford City QLD 4053 Tel: + 61 7 3137 0905 Fax: +61 7 39015586 [email protected]

Level / Duration – Intermediate / 2 days Price – AU$1400 + GST Who Should Attend? – Engineers who are interested in developing embedded systems with the Xilinx MicroBlaze soft processor or IBM PowerPC 440 core using the Embedded Development Kit and a Xilinx FPGA Prerequisites

� FPGA design experience

� Completion of the Fundamentals of FPGA Design course or equivalent knowledge of Xilinx ISE® implementation tools

� Basic understanding of C programming

� Some HDL modeling experience Software Tools

� Xilinx ISE® Foundation™ design tools 10.1 with the ISE Simulator

� Embedded Development Kit 10.1 with the Software Development Kit (SDK)

� Mentor Graphics ModelSim


17


Advanced Features and Techniques of Embedded Systems Development


Course Description Advanced Features and Techniques of Embedded Systems Development provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Embedded Development Kit (EDK). This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system.

This course builds on the skills gained in the Embedded Systems Development course. Labs provide hands-on experience with the development, verification, debugging, and simulation of an embedded system. Some labs use the ML507 demo board in which designs are downloaded and verified.


� Assemble an advanced embedded system

� Identify the steps involved in integrating a memory controller into an embedded system using the PowerPC® 440 microprocessor

� Apply advanced debugging techniques including the use of the ChipScope™ Pro software and Bus Functional Model (BFM) simulation

� Design a flash memory-based system and boot load from an off-chip flash memory

� Take advantage of the various Virtex®-5 FPGA and PowerPC processor 440 features, including the crossbar and multi-port memory controller

� Integrate an interrupt controller and interrupt handler into your embedded design

Course Outline

Day 1 � Embedded Systems Development Review

� Lab 1: Building a Complete Embedded System

� External Memory Controllers and File Systems

� Lab 2: External Memory Controllers and File Systems

� Debugging Using the ChipScope Pro Analyzer

� Lab 3: Debugging Using the ChipScope Pro Analyzer

� Bus Functional Model Simulation

Day 2 � Interrupts

� Interfacing an Embedded System with FPGA Fabric

� Lab 4: Interfacing an Embedded System to the FPGA Fabric

� PowerPC 440 Processor Crossbar

� Multi-Port Memory Controller

� Boot Loader

� Lab 5: Boot Loading from Flash Memory

Lab Descriptions � Lab 1: Building a Complete Embedded System – Develop

hardware that incorporates IP cores to interface to push buttons, switches, LEDs, an LCD display, and serial communication. Develop an application that interacts with switches, push buttons, an LCD display, and serial communication. Generate and download a bitstream onto the ML507 demo board.

� Lab 2: External Memory Controllers and File Systems – Design a system that includes a DDR2 IP core attached to the memory controller interface port. Develop an application that performs file-related tasks on external memory.

� Lab 3: Debugging Using the ChipScope Pro Analyzer – Perform simultaneous hardware and software debugging on stack-related errors with the ChipScope™ Pro Analyzer, SDK Debug perspective, and XMD.

� Lab 4: Interfacing an Embedded System to FPGA Fabric – Move data between an embedded system and FPGA fabric via an FSL and a dual-port block RAM. Implement an interrupt controller and an interrupt handler.

� Lab 5: Boot Loading from Flash Memory – Develop an application that is stored in flash memory, load it through a boot loader program, and execute the software from external memory.


Level / Duration – Advanced / 2 days Price – AU$1400 + GST Who Should Attend? – FPGA design engineers, system architects, and system engineers who are interested in Xilinx embedded systems development flow Prerequisites

� Experience in C programming

� Embedded Systems Development course or experience with embedded systems design and Xilinx EDK tools

� Some HDL modeling experience

� Basic microprocessor experience and understanding of PowerPC®-processor and MicroBlaze™-processor systems

Software Tools

� Xilinx ISE® Foundation™ design tools 10.1 with the ISE Simulator

� Embedded Development Kit 10.1 with the Software Development Kit (SDK)


18


Embedded Systems

Software Development


Course Description This two-day course introduces you to software design and development for Xilinx embedded processor systems. You will learn the basic tool use and concepts required for the software phase of the design cycle, after the hardware design is completed.

Topics are comprehensive, covering the design and implementation of the software platform for resource access and management. Major topics include device driver development and user application debugging and integration. Practical implementation tips and best practices are also provided throughout to enable you to make good design decisions and keep your design cycles to a minimum. You will have enough practical information to get started developing the software platform for a Xilinx embedded system based on a PowerPC® 440 or MicroBlaze™ processor.

While this course includes many of the topics presented in the Embedded Systems Development & Advanced Features & Techniques of Embedded Systems Development courses, the focus is on software development concepts & practices rather than hardware development. Hardware design concepts and procedures are not covered.


� Implement an effective software design for a Xilinx embedded system using the Xilinx tools

� Write a basic user application using the Xilinx Software Development Kit (SDK) and run it on the embedded system.

� Use Xilinx debugger tools to troubleshoot user applications

� Apply software techniques to improve operability

� Reduce embedded software development time

Course Outline Day 1 � Course Agenda

� Processors, Peripherals, and Tools

� Software Platform Development

� Software Development Using XPS

� Lab 1: Basic System Implementation

� Writing Code in the Xilinx Environment

� Software Development Using SDK

� Lab 2: Application Development

� Address Management

� Interrupts

� Lab 3: Software Interrupts

Day 2 � Software Platform Download and Boot

� Application Debugging

� Lab 4: Debugging

� Application Profiling

� Lab 5: SDK Profiling

� Writing a Custom Device Driver

� Project Management with the Xilinx Design Tools

� Lab 6: Writing a Device Driver

Lab Descriptions � Lab 1: Basic System Implementation – Construct the hardware

and software platforms used for the course labs. Begin with Base System Builder to create the hardware design. Specify a basic software platform and add a software application to the system.

� Lab 2: Application Development – Create a simple software application project from provided source files for a software loop-based stopwatch. Research hardware & software documentation to complete the application; then download it to hardware.

� Lab 3: Software Interrupts – Replace a software timing loop with an interrupt-driven timer. Add the timer software and write an interrupt handler for the timer. Configure the FPGA, download, and test the application.

� Lab 4: Debugging – Set up the SDK debug perspective and the previous lab’s stopwatch application for debugging, setting breakpoints, calculating latency, and stepping through the program’s operation.

� Lab 5: SDK Profiling – Profile a program, interpret profile reports, then enable cache and rewrite code for optimal performance.

� Lab 6: Writing a Device Driver – Create the skeleton driver framework, add an LCD device driver, create the BSP, and verify proper device driver operation via a download to hardware test.


Level / Duration – Basic / 2 days Price – AU$1400 + GST Who Should Attend? Software and hardware design engineers interested in system design and implementation, platform software support, and software application development and debugging. This course is not for the hardware-only embedded designer. Prerequisites

� C or C++ programming experience, including general debugging techniques

� Conceptual understanding of embedded processing systems including device drivers, interrupt routines writing / modifying scripts, user applications, and boot loader operation

Software Tools

� Xilinx ISE® Design Suite 10.1

� Embedded Development Kit 10.1


19


Embedded Open-Source Linux

Development


Course Description This intermediate-level, two-day course provides embedded systems developers with experience in creating an embedded open-source Linux operating system on a Xilinx development board. The course offers students hands-on experience from building the environment to booting the system using a basic, single-processor System on Chip (SoC) design with Linux 2.6 from the Xilinx kernel tree.

This course introduces embedded Linux components, use of open-source components, environment configurations, network components, and debugging/profiling options for embedded Linux platforms. The primary focus is on embedded Linux development in conjunction with the Xilinx tool flow.

After completing this basic training, you will have the necessary skills to: � Build a Linux development environment from pretested tool

components � Identify the basic concepts of an embedded Linux operating

system � Configure a Xilinx FPGA for a Linux operating system � Determine scheduling requirements for an embedded Linux

operating system and apply them to the FPGA configuration � Analyze system requirements for interprocess communication and

configure the FPGA � Determine system requirements for memory management � Develop and add Linux device drivers to the system

Course Outline Day 1 � Course Agenda and Introduction

� Building the Environment

� Lab 1: Building the Environment

� Basic Linux System

� Lab 2: Basic Linux System

Day 2 � Booting and Debugging

� Lab 3: Boot Loader

� Peripherals and Drivers

� Lab 4: Peripherals and Drivers

� Embedded Linux Memory Manager

� Processes, Scheduling, and Timing

Lab Descriptions � Lab 1: Building the Environment – On a virtual machine

environment, download and build a Linux development system that integrates Xilinx tools and open-source components. Includes the use of build scripts.

� Lab 2: Basic Linux System – Configure the kernel; build the kernel without a root file system; download and start the kernel with xmd; try basic debugging techniques; build a minimal rootfs; rebuild Linux with a minimal rootfs; and boot Linux and login.

� Lab 3: Boot Loader – Analyze the starting point of the kernel; analyze the boot messages; add the first-stage boot loader; add U-Boot; boot Linux with U-Boot; and boot Linux with an NFS rootfs.

� Lab 4: Peripherals and Drivers – Program a Hello World kernel module; compile external kernel modules; and create a simple gpio driver.

Register Today Black Box Consulting delivers public and private courses in locations throughout Australia and New Zealand . For more information, such as our range of courses, current schedules, and other services including consulting and recruitment/training packages, please use one of the contact methods below: Black Box Consulting PO Box 1147 Stafford City QLD 4053 Tel: + 61 7 3137 0905 Fax: +61 7 39015586 [email protected]


Level / Duration – Intermediate / 2 days Price – AU$1400 + GST Who Should Attend? – Embedded software developers interested in customizing an open-source Linux kernel for a Xilinx embedded processor system Prerequisites

� Experience in C or C++ programming

� Basic understanding of VHDL or Verilog design

� Basic microprocessor design experience and understanding of MicroBlaze™ or PowerPC® processor architecture

� Knowledge of operating system architecture

� Experience using a Linux command-line shell for common file operations

Software Tools

� Xilinx ISE® Foundation™ design tools 10.1

� Embedded Development Kit 10.1

EMAC23000-82-ILT (v1.0) Course Specification

20


Designing with Ethernet MAC

Controllers


Course Description Become acquainted with the various solutions that Xilinx offers for Ethernet connectivity. Learn the basics of the Ethernet standard, protocol, and OSI model while applying Xilinx solutions via hands-on laboratory exercises. Perform simulation to understand fundamental principles and obtain the knowledge to assess hardware design considerations and software development requirements.


� Identify Ethernet basics

� Utilize various Ethernet cores, used either in standalone mode or as a peripheral in a processor-based design

� Determine the appropriate core to use

� Develop software to drive the core and achieve desired functionality

� Integrate hard and soft IP into the Embedded Development Kit (EDK)

Course Outline Day 1 � Ethernet Basics

� Network Protocols, Ethernet Interfaces, and Hardware

� Lab 1: Analyzing Ethernet Frames

� Physical Layer

� LocalLink Interface

� Lab 2: VLAN and Jumbo Frames

� Xilinx EMAC Solutions

Day 2 � Lab 3: Implementation

� EMAC and EMAC Lite

� Lab 4: EMAC Peripheral in Loopback Mode

� GEMAC

� TEMAC

� Lab 5: TEMAC in Loopback Mode

� 10GE MAC

� Lab 6: Analyzing 10GE MAC Frames

Lab Descriptions � Lab 1: Analyzing Ethernet Frames – Understand components of

Ethernet frames and how the packets flow. Analyze various packets and observe how the core reacts to MAC address changes.

� Lab 2: VLAN and Jumbo Frames – Modify the configuration register to enable and observe the effects of VLAN and jumbo frames. Understand statistics vectors.

� Lab 3: Implementation – Use CORE Generator™ software to generate a gigabit Ethernet core and then proceed with the implementation flow.

� Lab 4: EMAC Peripheral in Loopback Mode – Use the EDK to instantiate and connect the OPB EMAC peripheral to the OPB bus. Develop software to place the core in loopback mode.

� Lab 5: TEMAC in Loopback Mode – Use the EDK to instantiate a hard TEMAC and soft PLB TEMAC wrapper. Configure cores in scatter gather DMA mode. Use three programs to test the hardware in polled, simple DMA, and scatter/gather DMA modes after placing the hardware in loopback mode.

� Lab 6: Analyzing 10GE MAC Frames – Use the ModelSim simulator to perform functional simulation. Analyze various frames from XGMII and the client interface point of view.


Level – Intermediate Course Duration – 2 days Price – AU$1200 + GST Course Part Number – EMAC23000-82-ILT Who Should Attend? – Engineers who would like to come up to speed on utilizing Xilinx Ethernet connectivity solutions (soft cores and hard IP) Prerequisites

� Fundamentals of FPGA Design course

� C programming knowledge recommended

� Experience with Xilinx ISE™ and Embedded Development Kit (EDK) software tools

Software Tools

� Xilinx ISE 8.2i

� Mentor Graphics ModelSim PE 6.0

� EDK 8.2

RIO22000-10-ILT (v1.0) Course Specification

21

© 2009 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

Designing with

Multi-Gigabit Serial I/O


Course Description Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Virtex®-5 LXT, SXT, FXT, or TXT FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as CRC, 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.


� Describe and utilize the ports and attributes of the RocketIO multi-gigabit transceiver in the Virtex-5 FPGA

� Effectively utilize the following features of the GTP/GTX:

� 8B/10B and other encoding/decoding, comma detection, CRC, clock correction, and channel bonding

� Pre-emphasis and linear equalization

� Use the GTP/GTX Transceiver Wizard to instantiate GTP and GTX primitives in a design

� Access appropriate reference material for board design issues involving the power supply, oscillators, and trace design

Course Outline

Day 1 � Virtex-5 Family Overview

� GTP Overview

� GTP Clocking and Resets

� 8B/10B Encoder and Decoder

� Lab 1: 8B/10B Disparity and Bypass

� Commas and Deserializer Alignment

� Lab 2: Commas and Data Alignment

� RX Elastic Buffer and Clock Correction

Day 2 � Lab 3: Clock Correction

� Channel Bonding

� Lab 4: Channel Bonding

� Cyclical Redundancy Check

� Lab 5: Cyclical Redundancy Check

� GTP Wizard Overview

� Implementing and Simulating a RocketIO Transceiver Design

� Lab 6: Synthesis and Implementation

� Physical Media Attachments

Day 3 � GTP Board Design

� Differences Between the GTX and GTP Transceivers

� 64B/66B Encoding and the Gearbox

� Lab 7: 64B/66B GTX Transceiver

� RocketIO Transceiver Test and Debugging

� Lab 8: ChipScope Pro Serial I/O Toolkit and IBERT

� RocketIO Transceiver Application Examples

Lab Descriptions � Lab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder

and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.

� Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.

� Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.

� Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.

� Lab 5: Cyclical Redundancy Check – Create design modules that include the dedicated CRC blocks in the Virtex-5 FPGA.

� Lab 6: Synthesis and Implementation – Use the GTP Wizard to configure RocketIO transceiver primitives. Instantiate the resulting component in a design, synthesize and implement the design.

� Lab 7: 64B/66B GTX Transceiver – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results.

� Lab 8: ChipScope Pro Serial I/O Toolkit and IBERT – Use the ChipScope Pro Serial I/O Toolkit to verify a GTP link.


Level – Intermediate Course Duration – 3 days Price – AU$1800 + GST Prerequisites

� Verilog or VHDL experience (or the Introduction to Verilog or the Introduction to VHDL course)

� Familiarity with synchronous logic design

� Basic knowledge of Virtex-5 FPGA architecture and Xilinx implementation tools is helpful

� Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

Software Tools

� Xilinx ISE® Foundation™ & ChipScope™ Pro software 10.1

� Mentor Graphics ModelSim simulator

LANG21000-8-ILT (v1.0) Course Specification

22


Advanced VHDL


Course Description Increase your VHDL proficiency by learning advanced techniques that will help you write more robust and reusable code. This comprehensive course is targeted toward designers who already have some experience with VHDL. The course highlights modeling, testbenches, RTL/synthesizable design, and techniques aimed at creating parameterizable and reusable designs. The majority of class time is spent in challenging hands-on labs as compared to lecture modules.


� Write efficient and reusable RTL, testbenches, and packages

� Create self-testing testbenches

� Create realistic models

� Use the Text IO capabilities of the VHDL language

� Store data dynamically

� Create parameterized designs

Course Outline Day 1 � Course Introduction

� Modeling and Simulation I: Subprograms and Attributes

� Modeling and Simulation II: Access Types and Blocks

� Lab 1: Modeling

� Testbench Stimulus

� Lab 2: Model Testbench

� Utilizing Text IO

� Lab 3: Text IO Testbench

Day 2

� RTL Design and Xilinx

� Design Reuse and Parameterized Design

� Lab 4: RTL and Scalable Design

� Finite State Machines

� Lab 5: FSM and Scalable Design

� Simulation Issues Specific to Xilinx

� Lab 6: Xilinx and Scalable Design

� Course Review

Lab Descriptions

� Lab 1: Modeling – Write a hardware model utilizing generics, subprograms, generate statements, and access data types.

� Lab 2: Model Testbench – Write a self-testing testbench and simulate model.

� Lab 3: Text IO Testbench – Utilize VHDL Text IO operations in a self-testing testbench.

� Lab 4: RTL and Scalable Design – Write a reusable and scalable design block by utilizing synchronous design techniques.

� Lab 5: FSM and Scalable Design – Write a Finite State Machine (FSM) by utilizing FSM techniques for a high-performance FSM.

� Lab 6: Xilinx and Scalable Design – Optimize the design for Xilinx implementation. Simulate and implement the optimized design.


Level – Advanced Course Duration – 2 days Price – AU$1400 + GST Course Part Number – LANG21000-8-ILT Who Should Attend? – VHDL users with introductory to intermediate knowledge of VHDL Prerequisites

� Introduction to VHDL course or equivalent knowledge of modeling, simulation, and RTL coding

� At least 6 months of coding experience beyond an introductory course

Software Tools

� Xilinx ISE™ 8.1i

� Mentor Graphics ModelSim PE 6.0c

CPLD13000-9-ILT (v1.0) Course Specification

23


Fundamentals of CPLD Design


Course Description This comprehensive course provides you with an introduction to designing with Xilinx CPLDs by using the ISE™ series software tools. You will learn the basics of ISE software flow and how to interpret CPLD reports for optimum performance designs. This course covers ISE features such as the Constraints Editor and PACE. Other topics include design planning, implementation options, and global timing constraints. You will ultimately configure a CPLD demo board by using Xilinx configuration software.

After completing this comprehensive training, you will have the necessary skills to: � Describe what products Xilinx offers and where the

CoolRunner-II CPLD fits into this offering � Identify the basic architectural resources of the

CoolRunner-II CPLD � Describe the CPLD tool flow: Design entry, synthesis,

implementation, and programming � Specify global timing constraints and pin assignments � Access and implement basic and advanced CPLD

software options via the ISE software

Course Outline

� Course Agenda � Introduction to Xilinx Products � CoolRunner-II CPLD Architecture � CPLD Software Flow � Lab 1: Xilinx CPLD Tool Flow

� Reading CPLD Reports � Global Constraints � Lab 2: Constraints for CPLDs

� CPLD Software Options � Lab 3: CPLD Implementation Options

Lab Descriptions � Lab 1: Xilinx CPLD Tool Flow – Create a new project in

the Project Navigator of the ISE software. Implement a design by using default software options and configure the CoolRunner-II CPLD demo board with iMPACT, the Xilinx In-System Programming (ISP) software.

� Lab 2: Constraints for CPLDs – Use constraints to specify

clock frequencies, pin locations, and I/O standards for the CPLD demo board project. Fit the design and analyze the Timing and Fitter Reports to confirm performance and I/O placement.

� Lab 3: CPLD Implementation Options – Implement the

design with default software options and evaluate the design performance versus design requirements. Apply a global timing constraint for PERIOD to the design. Change the software options and add I/O constraints to meet the design’s timing goals.


Level – Fundamental Course Duration – 1 day Price – AU$550 + GST (both CPLD Courses $850 + GST)

Course Part Number – CPLD13000-9-ILT Who Should Attend? – Digital designers who have working knowledge of basic HDL (VHDL or Verilog) and who are new to Xilinx CPLDs, ISE software, or both Prerequisites

� Basic HDL knowledge (VHDL or Verilog) � Digital design experience Software Tools

� Xilinx ISE 9.1i Recommended Hardware Demo Board � Coolrunner™-II Starter Kit (part number HW-CRII-SK-G)

CPLD23000-9-ILT (v1.0) Course Specification

24


Designing for Performance for CPLD


Course Description Designing for Performance for CPLDs is an intermediate-level course that provides a comprehensive overview of the CPLD software flow. By applying the techniques presented in this course, you will be able to enhance design performance and make the best possible use of Xilinx CPLD architectures. This course uses the ISE™ 9.1 software, including the Constraints Editor and Timing Analyzer. Other topics include understanding the CPLD logic engine, estimating power, and

fitting difficult designs.

After completing this comprehensive training, you will have the necessary skills to: � Apply techniques to fit more logic into a device

� Describe the CoolRunner™-II CPLD timing model and how it

can be used to analyze design performance

� Describe the advanced capabilities of the CoolRunner-II CPLD

architecture

� Estimate the power consumption of a CPLD design

Course Outline � Course Agenda � Review of Fundamentals of CPLD Design � XST for CPLDs � Advanced Fitting � Handling No-Fit Situations � Lab 1: Fitting

� CPLD Timing � Lab 2: CPLD Timing

� CPLD Logic Engine � Coding Techniques � CPLD Best Design Practices � Power Estimation

Lab Descriptions � Lab 1: Fitting – Apply the knowledge and techniques

learned in the previous modules to fit designs into smaller devices.

� Lab 2: CPLD Timing – Analyze the timing of a design and

create testbenches that can be simulated to verify the behavior of the design.


Level – Intermediate Course Duration – 1 day Price – AU$550 + GST (both CPLD Courses $850 + GST) Course Part Number – CPLD23000-9-ILT Who Should Attend? – Digital designers who have working knowledge of basic HDL (VHDL or Verilog) and who have some experience designing with Xilinx CPLDs. Alternatively, those who have recently attended Fundamentals of CPLD Design. Prerequisites

� Basic HDL knowledge (VHDL or Verilog)

� Digital design knowledge and Xilinx CPLD experience

� Fundamentals of CPLD Design course or equivalent knowledge of CPLD architecture; Xilinx implementation software flow and options; global constraints, the Constraints Editor; and reading fitting and timing reports

� Some experience with the software tool flow and global

timing constraints Software Tools

� Xilinx ISE 9.1i

V4-23000-8-ILT (v1.0) Course Specification

25


Designing with the Virtex-4 Family


Course Description Interested in learning how to utilize Virtex™-4 FPGA architectural resources effectively? This course focuses on understanding and utilizing several of the new and enhanced resources found in our newest device. Topics covered include an overview of the Virtex-4 FPGA; the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD); global and regional clocking techniques; memory and FIFO; and source-synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught in this course.


� Describe the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD) functionality of the Virtex-4 FPGA

� Describe the global and regional clock resources of the Virtex-4 FPGA

� Describe the ILOGIC and OLOGIC blocks

� Describe the ISERDES and OSERDES blocks

� Describe the block RAM features in the Virtex-4 FPGA

� Describe the new FIFO-dedicated resources

� Specify the features of the DSP48 block

� Describe what’s new in the configuration of the Virtex-4 FPGA

Course Outline

Day 1 � Introduction

� Product Overview

� DCM Clock Management

� PMCD Clock Management

� Lab 1: DCM Clocking

� Clock Networks

� Lab 2: Clocking Resources

Day 2 � Day Two Overview

� I/O and Source-Synchronous Resources

� Lab 3: Utilizing Source-Synchronous I/O Resources

� Block RAM Memory Resources

� FIFO16 Memory Resources

� Lab 4: Utilizing Block RAM and FIFO16

� XtremeDSP™ Technology Slice

� Lab 5: Utilizing XtremeDSP Technology Resources

� Configuration

� Day Two Review

Lab Descriptions � Lab 1: DCM Clocking – Designing a clock management scheme

with DCMs and PMCDs.

� Lab 2: Clocking Resources – Utilizing global and regional clock networks.

� Lab 3: Utilizing Source-Synchronous I/O Resources – Creating a source-synchronous design interface for a network application.

� Lab 4: Utilizing Block RAM and FIFO16 – Utilizing new block RAM features and FIFO16-dedicated resources.

� Lab 5: Utilizing XtremeDSP Technology Resources – Utilizing the DSP48 block.


Level – Intermediate Course Duration – 2 days Price – AU$1000 + GST Course Part Number – V4-23000-8-ILT Who Should Attend? – Experienced Xilinx users or those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. Students should have a solid understanding of Virtex-II, Virtex-II Pro, and Virtex-II ProX FPGA architectures, the ISE™ software, timing constraints, and timing closure techniques. Prerequisites


� Designing for Performance course

� Understanding of the Virtex-II, Virtex-II Pro, Virtex-II Pro X FPGA architecture

� Intermediate knowledge of VHDL or Verilog Software Tools

� Xilinx ISE 8.1i

� Xilinx XST

V4-23000-8-ILT (v1.0) Course Specification

26


Designing with the Virtex-5 Family


Course Description Interested in learning how to effectively utilize Virtex®-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.

Topics covered include a Virtex-5 FPGA overview, the new CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources. The resources available in the LXT and SXT platforms (EMAC, the PCI Express® architecture, and GTP transceivers) are also discussed. In addition, you will learn about the resources included in the FXT platform (GTX transceivers and the PowerPC® processor). A combination of modules and labs allow for practical hands-on application of the principles taught. After completing this comprehensive training, you will have the necessary skills to:

� Describe the 6-input LUT of the Virtex-5 FPGA

� Specify the CLB arrangement in the Virtex-5 FPGA

� Define the block RAM resources of the Virtex-5 FPGA

� Differentiate the arithmetic logic resources of the DSP48E slice in the Virtex-5 FPGA

� Identify the clocking resources of the Virtex-5 FPGA

� Describe the new features of the Virtex-5 LXT, SXT, and FXT FPGA platforms

Course Outline � Introduction

� Virtex-5 FPGA Overview

� CLB Resources

� Clocking Resources

� Lab 1: Clocking Resources

� I/O Resources

� Memory Resources

� XtremeDSP Solution Resources

� Lab 2: DSP48E Resources

� Virtex-5 LXT, SXT, and FXT FPGA Overview

� Lab 3: (Optional) DSP48E Resources

Lab Descriptions The labs will provide practical hands-on application of the principles taught throughout the course. Lab 1: Clocking Resources – In this lab, you will use the Architecture Wizard to create a PLL core for instantiation in your design. You will then simulate and verify the PLL core.

Lab 2: DSP48E Resources – In this lab, you will create a MACC and a loadable MACC by using the XtremeDSP™ solution (DSP48E) resource through the CORE Generator™ software. You will then compare the OPMODEs chosen by the CORE Generator software with the expected values.

Lab 3: DSP48E Resources – The DSP48E resource in the Virtex-5 FPGA can also be utilized to create non-DSP functions in order to save slice resources. In this optional lab, you will create a multiplexer by using the XtremeDSP solution (DSP48E) resource through primitive instantiation. You will then simulate the resources to verify functionality.


Level – Intermediate Course Duration – 1 day Price – AU$500 + GST Course Part Number – V5-21000-10-ILT Who Should Attend? – For those who have taken the Fundamentals of FPGA Design and Designing for Performance courses. A comprehensive knowledge of the Virtex-4 family architecture is also required. This material should be considered a Virtex-5 FPGA update course from the Virtex-4 FPGA family. Prerequisites


� Designing for Performance course

� Designing with the Virtex-4 Family course or comprehensive knowledge of the Virtex-4 FPGA

Software Tool

� Xilinx ISE® Foundation™ 10.1 software



27

Black Box Consulting distribute Digilent FPGA Demonstration boards throughout Australia and New

Zealand. What’s more, you can purchase one of the below boards at Academic prices when you

attend one of our training courses.

The Nexys-2 is a powerful digital system

design platform built around a Xilinx Spartan

3E FPGA. With 16Mbytes of fast SDRAM and

16Mbytes of Flash ROM, the Nexys-2 is ideally

suited to embedded processors like Xilinx's 32-

bit RISC Microblaze™. The on-board high-

speed USB2 port, together with a collection of

I/O devices, data ports, and expansion

connectors, allow a wide range of designs to

be completed without the need for any

additional components.

Academic = US$99 Commercial = $US129

+ US$15 postage & Handling

An ideal circuit design platform for anyone

who wants to learn about FPGAs and digital

circuit design. It combines the advanced

features of Xilinx's Spartan-3E FPGA with

straightforward power supply and I/O circuits,

making it the perfect platform for introductory

designs ranging from simple logic circuits to

complex digital systems.

Ships with a USB programming cable which

also supplies power.

Academic = US$59 Commercial = $US79

+ US$15 postage & Handling

Digilent Xilinx Demo Boards



28

For more details on these Digilent boards, other accessories and downloads please visit their website

at www.digilentinc.com. We are a fully recognised distributor for Australia and New Zealand.

Features a 500K gate Spartan 3E FPGA with a

32 bit RISC processor and DDR interfaces.

The board also features a Xilinx Platform

Flash, USB and JTAG parallel programming

interfaces with numerous FPGA configuration

options via the onboard Intel StrataFlash and

ST Microelectronics Serial Flash. Ships with a

power supply and USB programming cable

Compatible with the MicroBlaze Embedded

Development Kit (EDK) and PicoBlaze

Price = US$145 + US$15 postage & Handling

OpenSparc T1 open-source microprocessor.

Based on the Xilinx XUPV5-LX110T, a versatile

general purpose development board

powered by the Virtex®-5 FPGA, this kit brings

the throughput of OpenSPARC Chip Multi-

Threading to an FPGA.

Kit Includes a XUPV5-LX110T board, 1GB

Compact Flash card, 256 MB SODIMM

module, SATA cable, USB programming

cable, DVI to VGA adapter, 6A power supply

Commercial = US$1999 Academic = US$750!

+ US$15 P & H



29

All pricing unless otherwise stated are in Australian dollars and exclude GST at 10%. Please contact

us for terms and conditions for our products, services, and pricing.

Recruitment

Generic recruitment companies tend to charge 15 – 23%. See where we sit below.... and we throw

in up to $3000 of free training. Get real industry knowledge at sensible prices.

Full recruitment/training package including 5 Training Credits (equal to 5 days training)

• 15% of 1st year’s Salary Package, minimum $7500

Just Recruitment:

• 13% of 1st year’s Salary Package, no minimum

Contract roles:

• 13% of hourly wage

We charge $3000 up front as a retainer, with the final instalment due on placement. This covers our

advertising costs and time involved in the process. Please note if for any reason you had to cancel

the process before we present a candidate to you, $1500 is refunded to you in Credits.

Training

Pricing below is for Pay-As-You-Go training. See our Annual Credit Package section for packages

which can provide further discounts from $400 per day and for smaller group sizes from 3 people

For Public and online training, there are no minimum attendance requirements. All computer

equipment is provided, as are workbooks, and lunch and refreshments for public courses.

Embedded, DSP and Advanced VHDL courses: $700 per day, per person

All other courses are $600 per day per person. We further discount attendance of Full Academy

courses, details of which can be found on the course summary pages.

Minimum course size for onsite training is 5ppl capital cities except Perth, 6ppl for Perth and NZ for

our Academy Courses, and 6ppl capital cities except Perth, 7ppl Perth and NZ for other courses.

Consulting

Short term consulting is $150 per hour plus travel and accommodation expenses if applicable.

Please see our Credit packages for discounted fees.

Onsite consulting have minimum book times depending on location.

Pricing Guide



30

Credit Packages

Many companies are committed to ongoing training and support for their Engineers. This ultimately

leads to a higher level of innovation within a company, faster time to market, and of course, higher

median knowledge and retention rates.

Black Box Consulting has a discounted and flexible solution via an annual credit scheme to meet

these needs. You may purchase credit packs annually which can be used in many ways:

• Onsite training From as little as 3 Engineers per day depending on location

o Consistent training for smaller groups resulting in better learning experience

o Training can fit in with project schedules on a group by group basis

o Training can be divided over time. Ie Academy can be staggered instead of over a

block of 5 days, easing the burden on Engineers work load

o No need to achieve large groups. Run three courses for four engineers at the same

rate as one course for twelve, but achieve more 1-2-1 presenter time.

• Public Training courses in ANZ

o For niche courses with or training of 1 or 2 engineers,

• Online Training

o Less travel and expenses for small groups and faster scheduling times

• Consulting

o On or Off site Support

o Xilinx Champion – Use Black Box consulting to liaise with Xilinx on support questions

Credit Values are:

• Onsite, Public, Online Academy Training, per person, per day = 1 credit

• Consulting = Billed at 0.25 credit/hr offsite, 0.3 credit/hr onsite

For onsite work, you reimburse our travel and accommodation costs. This allows us to be onsite as

frequently, for shorter durations and for smaller groups, while keeping public, online, and offsite

consulting at a cheaper rate. Credits expire 12 months after purchase, but can be extended into a

new Annual Credit Purchase. See out Terms and Conditions for Further details.

Credits

Rack Rate @

$600/Credit Now

New Rate

/ Credit Saving

10 6000 5000 500 17%

20 12000 9700 485 19%

25 15000 11875 475 21%

30 18000 13950 465 23%

40 24000 18200 455 24%

50 30000 22250 445 26%

60 36000 26100 435 28%

70 42000 30100 425 29%

80 48000 33600 420 30%

90 54000 37350 415 31%

100 60000 41000 410 32%

125 75000 50625 405 33%

150 90000 60000 400 33%



31

Training & Consulting Credit Packages:

• We have a minimum billing requirement when using our services.

o 1 hour minimum billing time for offsite consulting

o 2 days / 16 hours, minimum billing for onsite consulting

• For all onsite Academy courses

o 2 days minimum onsite

o 1 credit = 1 days training for one engineer

o Minimum of 3 attendees billed per day for onsite training in Sydney, Melbourne, Adelaide, Brisbane, and Canberra

o Minimum of 4 attendees billed per day for onsite training in Perth and New Zealand

• For Embedded, DSP and Advanced VHDL courses

o 2 days minimum onsite

o $700 per day per person. Credits can be used for payment at a rate determined by your discounted credit rate



o You will not be liable for presenter expenses

• For Annual Training Packages, you are responsible for paying Travel and Accommodation expenses for any onsite work. We will bill

you accordingly and give copies of receipts when requested. Credits may be used to pay for expenses. A ‘Fair Play’ policy applies; we

fly at the cheapest economy rate available as long as it doesn’t leave us waiting for hours in an airport unless it’s the only flight out.

Accommodation costs maximum $135 is passed on per night unless no other accommodation venues in your area can be found at a

reasonable rate. For car hire we hire the cheapest vehicle from a reputable hire company. We do not pass on any food or sundry

expenses, only flight, car and accommodation costs.

• With Onsite training you are responsible for providing a suitable venue, Computer and environment and food and refreshments. We

have up to 5 Training Laptops available for no charge other than freight to and from your premises.

• The Credits within our packages expire 12 months after date of invoice. We do allow them to be used for consulting or training

courses up to 3 months after this date as long as they are assigned within the 12 month period. You may also roll credits across into a

new package with a new 12 month expiry as long as it accounts for no more than a third of the original or new package. I.e. you

purchase a 2009 agreement for 100 credits; you can roll 33 of these into a new 2010 package as long as the new package contains 66

more credits. You now have 100 Credits expiring 12 months after the 2010 invoice.

• Credits can only be used to purchase training or consulting services.

• All courses we offer direct except our Embedded, DSP and Advanced VHDL courses use a rate of 1 credit per person per day. Credits

can still be used towards these other courses at a rate determined by your cost per credit. We cannot discount these courses due to

the additional consultant and set up fee’s required.

• Public and online course have no minimum requirements. Laptops are provided, as is lunch and refreshments for public courses.

Pay As You Go Training & Consulting:

• We have a minimum billing requirement when using our consulting services.

o 1 hour minimum billing time for offsite consulting

o 2 days / 16 hours, minimum billing for onsite consulting

o Customer pays any Travel and Accommodation expenses

• For all onsite Academy courses

o You are not responsible for expenses



o 2 days or 10 Trained Students days minimum

Terms & Conditions



32

• For onsite Embedded, DSP and Advanced VHDL courses

o $700 per day per person. Credits



o You will not be liable for presenter expenses

• With Onsite training you are responsible for providing a suitable venue, computer environment and food and refreshments. We have

up to 5 Training Laptops available for no charge other than freight to and from your premises


Recruitment

• Fees are 15% of 1st year’s Salary Package which includes 5 Credits for Training or consulting use, which are valid for 12 months after

1st invoice and attract a minimum total campaign fee of $7500. Recruitment with no Training Credits is at 13% of salary package, no

minimum fee. All prices exclude GST. Fees are payable after successful placement of candidate deemed to be when any contracts are

signed by both parties or 1 week before any start date given. Salary Package is defined as Base Salary + Super + Car Allowance +

Guaranteed Bonuses.

• Fees do not cover advertising fees beyond the initial online advertising cost in either Australia or New Zealand. Nor do they cover

costs relating to travel, food and accommodation if the company wishes us to be present for face to face interviews. These will be

passed on at cost value.

• We have a 3 month placement guarantee covering any reason that employment is terminated from either side. This guarantee

covers our time and efforts in recruiting a replacement and does not cover actual costs such as re-advertisements, travel, food,

accommodation or other incurred costs. There are no guarantees for contract positions.

• Any candidate passed to you from Black Box Consulting remains our candidate and a fee equal to our standard recruitment fee’s will

be invoiced to you should you employ the candidate within a 12 month period of you receiving their details or pass details on to

other parties who subsequently employ this person. Any candidate details must be considered confidential and must not be shown

to 3rd

parties other than those within the company appointing the role.

• For contractors you, the employer is responsible to cover the contractor for all relevant insurances applicable to their location.

• On employing a contractor you agree to pay the hourly rate to Black Box Consulting on an ongoing basis which we bill monthly. If

applicable, after 12 months of employment our rate drops to 9% and zero after 24 months.

• Black Box Consulting will not be held fully or partially responsible for actions taken or any losses to your company which arise from

the placed candidates or contractors in any way or form.

General

• All invoices are payable within 30 days of invoice date or before commencement of training course, whichever is sooner

• All prices, expenses and otherwise quotes excluding GST unless otherwise mentioned

• For a positive training experience we limit our public and onsite class size to 12 people; however the average class size is 5 people.


• We reserve the right to update our terms and conditions at any time. Our current terms and conditions can be found on our website

Cancelations

• For up to 28 days before schedule date a full re-imbursement is made. A full credit is given up to 14 days prior. For less than 14 days

you are liable for our minimum onsite costs or the invoice amount, whichever is smallest. For onsite work, you will also be charged

any travel, accommodation, freight, setup, and workbook costs the cancellation may have incurred, regardless of notice.



33

Contact Address:

Black Box Consulting

PO BOX 1147

Stafford City

QLD 4053

Tel: +61 7 3137 0905

Email: [email protected]

Web: www.blackboxconsulting.com.au

Managing Director: Peter Boxall

Email: [email protected]

About:

Black Box Consulting is a privately owned company by Peter Boxall. Peter was previously employed by Xilinx for 7yrs from

1997 to 2004 in the UK as a Senior Strategic Applications Engineer and Product Specialist. Peter supported global accounts

through their entire project cycle from concept to production using Xilinx products which included design and

implementation support, training, and Xilinx 'Titanium' support both on and off site, as well as supporting Xilinx Sales and

Marketing teams.

After moving to Australia in 2004 on a sabbatical break for 18 months, Peter provided technical recruitment services with

Carroll Consulting Group in the areas of Technical Sales, Marketing, and Engineering. Peter grew a strong client base who

appreciated how his technical ability assisted in the recruitment process.

In early 2006, Peter established Black Box Consulting and became the sole Authorised Training Provider for Xilinx education

courses in Australia and New Zealand, providing expert training courses using the same high-quality training materials

developed by Xilinx.

Recognising the need for faster design cycles, as well as offering Xilinx training courses, Black Box Consulting also offer on

or off site consulting to support Xilinx FPGA projects. Black Box Consulting use technical experts in their field, drawn from

right across the industry. To us, it’s not only technical know-how which sets us apart, it’s the ability to teach and transfer

skills in order to best enable a company and its employees to increase their skills base, reduce their design cycle, and

become cost effective, now, and for the future.

Black Box Consulting also offers Australia wide recruitment services. With a strong association with Carroll Consulting

Group, a member of NPA who are a worldwide recruitment association with over 80 recruitment companies in Australia

alone. With this alliance, we can offer a solution to all your recruitment needs, while using our technical expertise for more

technical assignments.

In 2008 Black Box Consulting also became the Authorised distributor for Digilent, a manufacturer of Xilinx Demonstration

Boards, predominately in the Training and Education sector.

In 2009 Black Box Consulting was the first Xilinx Authorised Training Provider in the world to offer live, real-time instructor

led Xilinx training courses online.

CONTACT DETAILS / ABOUT

black box consulting 2009 brochure

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