bist / test-decompressor design using combinational test spectrum
DESCRIPTION
BIST / Test-Decompressor Design using Combinational Test Spectrum. Nitin Yogi Vishwani D. Agrawal Auburn University, Dept. of Elec. & Comp. Eng. Auburn, AL 36849, U.S.A. 13th IEEE / VSI VLSI Design and Test Symposium Bangalore, India. Outline. Problem Definition Proposed Design Method - PowerPoint PPT PresentationTRANSCRIPT
July 10, 2009 13th VLSI Design and Test Symposium 1
BIST / Test-Decompressor Design using Combinational Test Spectrum
Nitin YogiVishwani D. Agrawal
Auburn University, Dept. of Elec. & Comp. Eng.Auburn, AL 36849, U.S.A.
13th IEEE / VSI VLSI Design and Test Symposium Bangalore, India
July 10, 2009 13th VLSI Design and Test Symposium 2
Outline
Problem Definition Proposed Design Method
Spectral Analysis BIST Architecture
Results Results without reseeding Results with reseeding
Conclusion
July 10, 2009 13th VLSI Design and Test Symposium 3
Problem Definition
To design a Test Pattern Generator (TPG) for Built-In Self Test (BIST) of combinational circuits achieving the following goals:
Given a set of pre-generated test vectors, replicate their effects in hardware
Low area overhead
Low test application times
July 10, 2009 13th VLSI Design and Test Symposium 4
Proposed Design Methodology
Determine prominent spectral
components by spectral analysis
Preprocess test vectors
Pre-generated test vectors
BIST implementation
Step 1 Step 2
Spectral properties
BIST TPG gate-level
netlist
July 10, 2009 13th VLSI Design and Test Symposium 5
Walsh Functions and Hadamard Matrix
H(3) =
• Walsh functions: a complete orthogonal set of basis functions that can represent any arbitrary bit-stream.
• Walsh functions form the rows of a Hadamard matrix.
Example of Hadamard matrix of order 3
1 1 1 1 1 1 1 11 -1 1 -1 1 -1 1 -11 1 -1 -1 1 1 -1 -11 -1 -1 1 1 -1 -1 11 1 1 1 -1 -1 -1 -11 -1 1 -1 -1 1 -1 11 1 -1 -1 -1 -1 1 11 -1 -1 1 -1 1 1 -1
w0
w1
w2
w3
w4
w5
w6
w7
Wal
sh f
unct
ions
(or
der
3)
time
July 10, 2009 13th VLSI Design and Test Symposium 6
Test Vectors and Bit-streams
Circuit Under Test (CUT)
Inpu
t 1
Inpu
t 2
Inpu
t 3
Inpu
t 4
Inpu
t 5
Inpu
t J
Vector 1 →Vector 2 →Vector 3 →Vector 4 →Vector 5 →
Vector K →
OutputsT
ime
A binary bit-stream
to be spectrally analyzed
1 1 0 1 0 . . 10 0 1 0 1 . . 11 0 0 1 1 . . 01 1 0 0 0 . . 10 0 1 1 0 . . 0. . . . . . . .. . . . . . . .1 0 1 1 1 . . 0
July 10, 2009 13th VLSI Design and Test Symposium 7
Spectrum: Input 1 of circuit s5378
Spectrum of ATPG bit-stream applied to input 1 of circuit s5378
0
50
100
150
200
250
1 21 41 61 81 101 121 141 161 181 201 221 241
Spectral Coefficients
Mag
nitu
de
Theoretical random noise
level (16)
July 10, 2009 13th VLSI Design and Test Symposium 8
Spectrum: Input 9 of circuit s5378
Spectrum of ATPG bit-stream applied to input 9 of circuit s5378
0
50
100
150
200
250
1 21 41 61 81 101 121 141 161 181 201 221 241
Spectral Coefficients
Mag
nitu
de
Theoretical random noise
level (16)
July 10, 2009 13th VLSI Design and Test Symposium 9
Effect of Noise
Noise inserted in ATPG vectors, generated for a sample of faults (RTL faults), for s5378 circuit, using increasing spectral threshold (ST) values (i.e., increasing noise)
226 ATPG vectors for1602 RTL faults
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
3100 3150 3200 3250 3300 3350 3400
Freq
uenc
y
Number of gate-level stuck-at faults detected
Effect of noise (500 samples)
ST = 0
ST = 1
ST = 5
ST = 9
Gate-level faults detected by 226 ATPG vectors
More faults detected than
original vectors
July 10, 2009 13th VLSI Design and Test Symposium 10
To CUT
BIST Architecture
Weighted pseudo-random pattern
generator
Spectral component synthesizer
Input 1
Input 2
Input 3
Hadamard Components
2
3
1
1
1
To CUTRandomizer
Hadamard wave
generator
System clock
BISTclock
Weighted pseudo-random
bit-streams
N-bit counter with XOR gates
SC1
SC2
SC3
Weighted random
bit-stream (W=0.5)
Weighted random
bit-stream (W=0.5)
Proportion:
SC1 = 0.5 SC2 = 0.5 Proportion:
SC1 = 0.25 SC2 = 0.25SC3 = 0.5
Cellular Automata Register with
AND-OR gates
System clock
BIST clock
Weighted random bit-stream (W = 0.25)
Bit-stream of spectral component
Noise inserted
bit-stream
July 10, 2009 13th VLSI Design and Test Symposium 11
3-bit down counter;N flip-flopsFor H(N)
Hadamard Wave Generator
FF1
FF2
Logic ‘1’
FF3
W0
W1
W2
W3
W 4
W5
W6
W7
LSB
MSB
CLK
C. K. Yuen, “New Walsh-Function Generator,” Electronics Letters, vol. 7, p. 605, 1971.
July 10, 2009 13th VLSI Design and Test Symposium 12
Generation of Weighted Random Bit-streams
Cellular Automata Register
M Flip-flops
P1=0.5
P1=0.5P1=0.25
P1=0.5
P1=0.625
P1=0.5
P1=0.5
P1=0.5
P1=0.5
P1=0.75P1=0.875 P1=0.9375
Circuit No. of PINo. of Flip-flops
Hadamard wave gen. (N) CA register (M)
c7552 207 6 24
s15850 (comb.) 600 7 28
July 10, 2009 13th VLSI Design and Test Symposium 13
Spectral BIST Results and Area Overhead
CircuitRandom vectors
Weighted Random vectors
Spectral BIST
ATPG Coverage
(No. of vecs)
c7552 97.41% 97.86% 99.81% 100% (247)
s15850(combinational)
96.81% 97.41% 98.77% 100% (530)
Test coverage results without reseeding (64000 vectors)
CircuitNo. of
gates in circuit
Spectral BIST PRPG
No. of gates
% Area overhead
No. of gates
% Area overhead
c7552 3513 976 27.78 830 23.63
s15850 (combinational)
9772 2672 27.34 2400 24.56
Area overhead comparison
July 10, 2009 13th VLSI Design and Test Symposium 14
Test Coverage vs Number of Vectors
c7552
93
94
95
96
97
98
99
100
0 10000 20000 30000 40000 50000 60000
Test vectors
Test
cove
rage
SpectralBIST
WeightedRandom
Random
July 10, 2009 13th VLSI Design and Test Symposium 15
Test Coverage vs Number of Vectors
s15850
86
88
90
92
94
96
98
100
0 10000 20000 30000 40000 50000 60000
Test vectors
Test
cov
erag
e
SpectralBIST
WeightedRandom
Random
July 10, 2009 13th VLSI Design and Test Symposium 16
Reseeding of Spectral TPG
To CUT
Data from external tester
Serial scan interface
Par
alle
l int
erfa
ce
Spectral BIST / Decompressor
Flip
-flo
ps
BIST / Decompressor
Logic
Mode of operation Function
External Tester Mode (ETM) One-seed-per-test vector operation
Hybrid BIST Mode (HBM) Used to generate test vectors and reseed flip-flops periodically
July 10, 2009 13th VLSI Design and Test Symposium 17
Spectral TPG Results with Reseeding
Mode of test applicationNo. of vecs./ seeds
No. of inputs
Test data
volume (bits)
No. of tester cycles
No. of system clock cycles
Test time (us)†
Conventional (parallel) 247 207 51129 247 0 2
Conventional (serial) 247 1 51129 51129 0 511
Spectral BIST
ETM (parallel) 197 30 5910 197 0 2
ETM (serial) 197 1 5910 5910 0 59
HBM (parallel) 33 30 990 33 8034 8
HBM (serial) 33 1 990 990 8034 18
Comparison of test data volume and test time for c7552
† assuming tester clock period Ttester=10ns and on-chip system clock period Tclk=1ns
July 10, 2009 13th VLSI Design and Test Symposium 18
Spectral TPG Results with Reseeding
Mode of test applicationNo. of vecs./ seeds
No. of inputs
Test data
volume (bits)
No. of tester cycles
No. of system clock cycles
Test time (us)†
Conventional (parallel) 530 600 318000 530 0 5
Conventional (serial) 530 1 318000 318000 0 3180
Spectral BIST
ETM (parallel) 455 35 15925 455 0 5
ETM (serial) 455 1 15925 15925 0 159
HBM (parallel) 134 35 4690 134 20129 21
HBM (serial) 134 1 4690 4690 20129 67
Comparison of test data volume and test time for s15850 (combinational)
† assuming tester clock period Ttester=10ns and on-chip system clock period Tclk=1ns
July 10, 2009 13th VLSI Design and Test Symposium 19
Conclusion
Proposed a TPG design methodology for combinational circuits using spectral techniques. Also proposed a reshuffling algorithm to enhance spectral
components. Designed TPG exhibits the following:
Higher test coverage than random and weighted random vectors for equal number of test vectors.
Encouraging test data compression capabilities up to 95%. An order of magnitude reduction in test application time.
Issues to address: Slightly high area overhead
Overhead might reduce by: Implementation on larger circuits Optimum selection of spectral components by reshuffling algorithm
Increase in test time for parallel HBM Optimum seeds and intervals for reseeding can reduce the test time.
July 10, 2009 13th VLSI Design and Test Symposium 20
Thank you.
Questions please?
July 10, 2009 13th VLSI Design and Test Symposium 21
Pre-processing of Test VectorsReshuffling Algorithm:
Input Data and Parameters:NI: No of inputsNV: No. of vectorsV(1:NV,1:NI): Test vector Set of dimensions NV x NI
hd: Dimension of Hadamard matrixH: Hadamard transform matrix of dimension 2hd x 2hd
Procedure:Vector set V appended with redundant vectors to make weighting of bit-streams of all inputs = 0.5
for i=1 to NI
Perform spectral analysis on bit-stream of input i: S = V(:,i) x H;Pick the prominent spectral component Sp(i) from SRearrange vector set V such that maximum bits in the
bit-streams of inputs 1 to i match with the picked prominent spectral components Sp(1 to i) respectively.
end