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Biennial Report 2002/03

Solid-State Electronics Department Prof.Dr.rer.nat. F.J.Tegude

Universität Duisburg-Essen Fakultät für Ingenieurwissenschaften

Institut für Technologien der Informationstechnik

Halbleitertechnik/Halbleitertechnologie

Lotharstrasse 55 / ZHO D-47057 Duisburg

Germany

Tel.: ++49 (0)203 379 3392 (Secr.) Fax: ++49 (0)203 379 3400 email: [email protected] www: http://www.zho.uni-duisburg.de

Editors: Dr.-Ing. Werner Prost Dr.-Ing. Wolfgang Brockerhoff

Halbleitertechnik/Halbleitertechnologie

Biennial Report 2002/03 - Solid-State Electronics Department

Table of Contents 1 Preface ........................................................................................................................................ 1

2 Members and Guests of the Department ................................................................................... 3

3 Teaching Activities..................................................................................................................... 5 3.1 Lectures and Laboratory Exercises ............................................................................................ 5 3.2 Student Reports and Diploma Thesis ......................................................................................... 8 3.3 Doctor Thesis.............................................................................................................................. 9 3.4 Seminar on Semiconductor Electronics.................................................................................... 10

4 Research Activities .................................................................................................................. 15 4.1 Epitaxial Growth and Materials ........................................................................................... 15

4.1.1 Calculation and Design of MOVPE Input Parameters M. Haase................................................................................................................ 16

4.1.2 Automated Evaluation of Growth Programs for MOVPE AIX-200 T. Reimann, M. Haase ........................................................................................... 19

4.1.3 Nitrogen Carrier Gas for the Growth of GaAsSb/InP DHBT S. Neumann, I. Regolin, M. Haase, A. Osinski ..................................................... 23

4.1.4 Growth and Characterization of pnp InAlAs/InGaAs HBTs S. Neumann, A. Osinski ........................................................................................ 26

4.1.5 Ordering of InxGa1-xAsyP1-y Depending on Composition and Growth Temperature

S. Neumann, J. Spieler , Robert Blache, M. Haase................................................ 29

4.1.6 MOVPE Growth of (dis-)ordered InGaAsP PIN-FET Diodes for Optical Fibre Applications

S. Neumann, J. Spieler , Robert Blache1), M. Haase............................................. 33

4.1.7 LP-MOVPE Growth of InGaAs/InP Superlattice on Si Substrate S. Neumann, A. Bakin ........................................................................................... 37

4.1.8 Growth and Characterization of III-V Device Layers on Si Substrates A. Che Mofor, V. Khorenko.................................................................................. 40

4.1.9 Application of Reflectance Spectroscopy in Molecular Beam Epitaxy for in-situ Surface Characterization

A. Che Mofor, V. Khorenko.................................................................................. 44 4.2 Device and Circuit Processing .............................................................................................. 49

4.2.1 Investigation of the Gate-Recess Processing Parameters of Heterojunction Field Effect Transistors

J. Degenhardt, A. Poloczek ................................................................................... 50

4.2.2 Statistical Exaltation of DC Transistor Parameters J. Degenhardt, G.Grah, A. Osinski ........................................................................ 54


4.2.3 Current Gain Increase in Self-Aligned InGaAs/InP Heterostructure Bipolar Transistor Using SiNx Passivation

Z. Jin, F. Otten, T. Reimann, S. Neumann ............................................................ 57

4.2.4 Effects of (NH4)2S Passivation on the Performance of Graded-Base InGaAs/InP HBTs

Z. Jin, S. Neumann, W. Prost ................................................................................ 60

4.2.5 Sulfur and Low-Temperature SiNx Passivation of InGaAs/InP Heterostructure Bipolar Transistors

Z. Jin, S. Neumann, W. Prost ................................................................................ 64

4.2.6 DC Characterization of a GaAsSb Heterojunction Bipolar Transistor Based on InP Ingo Regolin, Stefan Neumann ............................................................................. 67

4.2.7 Comparison between InP/InGaAs- and InP/GaAsSb-DHBT J. Driesen, S. Topaloglu......................................................................................... 71

4.2.8 On the Improvements of HBT Performance Provided by Lateral and Vertical Optimisation

J. Driesen ............................................................................................................... 74

4.2.9 HBTs with Directly Contacted Emitters S. Topaloglu, J. Driesen......................................................................................... 78

4.2.10 Different Approaches for Integrating HBTs and EAMs T. Reimann, S. Neumann, M. Schneider, M. Haase.............................................. 81

4.2.11 HBT-EAM with InGaAlAs Base T. Reimann, S. Neumann, M. Schneider, M. Haase.............................................. 85

4.2.12 A 2.5 Gbit/s Operation InP Based RTD/HBT MOBILE S.O. Kim1, H.van Husen, W.Prost, P. Glösekötter, K.F. Goser ............................ 89

4.2.13 Influence of Layer Structure on the IV Characteristic of Si/SiGe Interband Tunnelling Diodes

E. Khorenko, M. Stoffel, O.G. Schmidt ................................................................ 91 4.3 Device and Circuit Simulation, Measurement and Modeling .......................................... 95

4.3.1 Physical Simulation of Transmission Line Measurements with TCAD S. Deragopian, B. Schlothmann............................................................................. 96

4.3.2 Simulation of n-GaAs/N-AlGaAs Heterojunction B. Schlothmann ..................................................................................................... 99

4.3.3 Simulation of Heterostructure Bipolar Transistors with Various Collector- Constructions and their Influence on the High Frequency Behaviour

Lars Schneider, Björn Schlothmann.................................................................... 102

4.3.4 Current Transport Mechanisms of InP Based Double Heterojunction Bipolar Transistors with Different Base Structures

Z. Jin, S. Neumann, W. Prost .............................................................................. 105


4.3.5 Experimental Set-Up for CV Measurement R. Schlangen, M. Haase, W. Prost....................................................................... 108

4.3.6 Development of a DC Test System G. Grah ................................................................................................................ 111

4.3.7 Development of a Calibration Technique for On-Wafer Optoelectronic S-Parameter Measurements

A. Matiss, W. Brockerhoff, M. Agethen, D. Cheskis......................................... 114

4.3.8 Implementation of the Cadence Design Framework for Use with III-V Technologies J. Driesen ............................................................................................................. 117

4.3.9 Evaluation of a Small Signal Model for Si/SiGe Interband Tunneling Diodes M. Tekloth, S. Ehrich .......................................................................................... 121

4.3.10 A Combined Large-Signal and Small-Signal Model for InP Based Single HBT S. Ehrich .............................................................................................................. 124

4.3.11 Scaling of Intrinsic Small-Signal Elements with Respect to the Emitter Area of Single HBT Based on InP

S. Ehrich .............................................................................................................. 127

4.3.12 Large-Signal Model for the HBT-EAM in PSpice S. Mahmud, T. Reimann...................................................................................... 131

4.3.13 Design of 1:16 Time Division Demultiplexer for 16 Gb/s J. Degenhardt, G.Grah, A. Osinski ...................................................................... 135

4.3.14 Development and Simulation of Digital Circuits for Measurement Applications Based on HBT Technology

M. Brysch, J. Driesen .......................................................................................... 139

4.3.15 Developement of a D-FF as Part of a Demultiplexer J. Degenhardt, G. Grah U. Doerk ....................................................................... 143

4.3.16 Development of an Optoelectronic Preamplifier Based on HBT Technology R.Bednorz, G.Janssen, J. Driesen, W. Brockerhoff............................................. 146

4.3.17 Re-Design of a 40GHz Broadband Amplifier Based on HBT Technology R. Bednorz, G. Janssen, W. Brockerhoff............................................................. 149

4.3.18 Development of a Low Noise Optoelectronical Front-End Amplifier Based on HEMT/HBT Layers

A. Matiss, G. Janssen, W. Brockerhoff ............................................................... 153

4.3.19 Design and Fabrication of a MOBILE-Gate with an Optical Input S. Mahmud,E. Khorenko, W. Prost ..................................................................... 157


4.4 Nanoelectronics..................................................................................................................... 161

4.4.1 Formation of Zero-Dimensional Nanostructures by Epitaxial Overgrowth of Gas Phase Generated Indium Nanoparticles

V. Khorenko, K.Nanda, E.Kruis.......................................................................... 162

4.4.2 Electrical Characterization of Laterally Structured Nanocrystal Films F. Otten, F.E. Kruis, H. Fißan.............................................................................. 165

4.4.3 Potential Measurements with Electrostatic Scanning Probe Microscopy Q.T.Do, W.Prost, F.Otten .................................................................................... 167

4.4.4 3-Dimensional Self-Assembly of Nanoparticles on Microcrystal Surfaces: an SFM/SEM Study

V. Khorenko, M. Barth, T. Do, D. Cunningham, J.-L. Martinez-Albertos, B. Moore ............................................................................................................................. 168

4.4.5 Microelectronic Patterning Technics for K2SO4/Au Nanocrystals M. Barth, Q. T. Do............................................................................................... 172

4.4.6 A Nanoparticle Coated Nanocrystal Gate for an InP Based Heterostructure Field Effect Transistor

Q.T. Do, R. Geitmann, K.Katzer, J.-L. Martinez-Albertos, B. Moore ............... 175 4.5 Conference Contributions....................................................................................................... 178 4.6 Publications ........................................................................................................................... 183 4.7 Research Projects ................................................................................................................... 187

4.8. Other Activities ...................................................................................................................... 189

5 Guide to the Solid-State Electronics Department .................................................................. 192

Biennial Report 2002/03 - Solid-State Electronics Department 1

1 Preface

Since January 1st 2003 the Solid State Electronics Department (Fachgebiet Halbleitertechnik/ Halbleitertechnologie) is member of the new University of Duisburg-Essen which was formed by merging the formerly separated Universities of Duisburg and Essen, respectively. This merger yields a broader and more complete spectrum of research and teaching, giving our new university a stronger position in the long run, though the new structure still has to be established within the research, teaching and administration organization.

This report is thicker than previous ones because it covers our activities of 2002 and 2003. Teaching is getting increasingly international, and our curricula have attracted Bachelor and Master students from all over the world. In general, due to increasing numbers of beginners also for German students, and because of excellent equipment and careful supervision we enjoy an increasing number of students interested in preparing student and diploma thesis in our department.

Research activities with respect to established devices, like HFETs and SHBTs, are more and more concentrating on circuit applications for high speed digital and analog circuits, demanding improved yield and reproducibility, even for RTDs. Nevertheless, growth and process development of GaAsSb based DHBTs, like passivation and contact optimisation still are challenging tasks.

On the other hand increasing effort has been put on nanomaterials and -structures, and silicon based technologies like III-V-growth on silicon substrates and Si/SiGe-RTDs. After decreasing funding of pure III-V-research worldwide, we think these activities could open up new application oriented research areas and cost efficient processing opportunities.

Finally, I want to thank friends and partners everywhere for their support and cooperation, and last, but not least, all students and members of the Solid State Electronics Department for their efforts and contributions.

Duisburg, April 2004

Prof. Dr. rer. nat. F.-J. Tegude

2 Biennial Report 2002/03 - Solid-State Electronics Department

2


2 Members and Guests of the Department

379- office email

head of the department

Prof. Dr.rer.nat. Franz-Josef Tegude - 3391 LT 207 [email protected]

secretary

Dagmar Birke - 3392 LT 206 [email protected]

Prof. Dr.rer.nat. Franz-Josef Tegude - 3391 LT 207 [email protected]

scientific staff

Dr.-Ing. Wolfgang Brockerhoff (AOR) - 2989 LT 205 [email protected]

Dipl.-Phys. Jan Degenhardt - 3877 LT 104 [email protected]

Dipl.-Phys. Quoc Thai Do since 01/03 - 3393 LT 106 [email protected]

Dipl.-Ing. Jörn Driesen since 09/02 - 2491 LT 218 [email protected]

Dipl.-Ing. Silja Ehrich - 3881 LT 204 [email protected]

Dipl.-Ing. Georg Grah - 3878 LT 105 [email protected]

Dr. Zhi Jin 05/02 - 02/04

Dr.-rer.nat. Victor Khorenko - 3877 LT 104 [email protected]

M.Sc. Evgenia Khorenko - 3877 LT 104 [email protected]

Dipl.-Ing. Andreas Matiss since 10/03 - 4605 LT 203 [email protected]

Dipl.-Phys. Stefan Neumann - 3879 LT 106 [email protected]

Dipl.-Ing. Frank Otten until 07/02

Dr.-Ing. Werner Prost - 4607 LT 205 [email protected]

Dipl.-Phys. Thorsten Reimann until 02/03

M.Sc. Serkan Topaloglu since 01/03 - 2492 LT 218 [email protected]

Dipl.-Phys. Holger van Husen until 12/02

technical staff

Udo Doerk - 3395 LT 202 [email protected]

Dipl.-Ing. Ralf Geitmann - 4604 LT 202 [email protected]

Dipl.-Ing. Matthias Haase until 04/03

Dipl.-Ing. Wolfgang Molls - 4603 LT 201 [email protected]

Andrea Osinski - 4600 LT 104 [email protected]

Ing. (grad.) Reimund Tilders - 3396 LT 201 [email protected]

Claudia Schmidt - 4095 LT 106 [email protected]

Jana Bödige - 4618 LT 106 bö[email protected]

4 Biennial Report 2002/03- Solid-State Electronics Department

students Ouafa El Alami until 09/02 Johannes Henze

Gurujai Bagepalli until 02/02 Stefan Herschbach until 06/03

Matthias Barth Giuseppe Landi until 12/02

Karsten Bettray until 12/02 Andreas Matiss until 03/03

Rafael Bednorz until 12/02 Augustine Che Mofor

Stefan Bonsels Artur Poloczek until 06/03

Ralph Chemali until 02/03 Christoph Prusinski

Adam Chwalczyk until 12/02 Ingo Regolin until 09/03

Serge Deragopian Lars Schneider

Quoc Thai Do until 06/02 Rudolf Schlangen until 09/03

Jörg Finzel until 02/02 Thorsten Scholz

Thomas Fischle Michael Tekloth

Urs Heidemann Conny Walzebug until 12/02

guests

Prof. Dr. Robert Weigel Universität Erlangen-Nürnberg Lehrstuhl für Technische Elektronik, Germany

Dr. Emilio Gini ETH Zürich Center for Micro- and Nanosciences, Switzerland

Dr. Günther Tränkle Ferdinand-Braun Institut für Hochfrequenztechnik Berlin, Germany

Dr. Michael Feiginov TU Darmstadt Institut für Hochfrequenztechnik, Germany

Prof. Waho Sophia University Tokyo, Japan

Dr. G.Klimeck Jet Propulsion Laboratory, California Institute of Technology, USA

Prof. S.Watkins Simon Fraser University Burnaby, Canada

K.Hirche TESAT Backnang, Germany


3 Teaching Activities

3.1 Lectures and Laboratory Exercises

Schedule

International Studies in Engineering (ISE)

Lectures and exercises diploma course

B.Sc. M.Sc

Solid-State Electronics 1 Festkörperelektronik 1 3rd sem.

Solid-State Electronics 2 Festkörperelektronik 2

4th sem.

Introduction to Solid-State Electronics Einführung in die Festkörperelektronik

4th sem.

Technical Electronics 1 Technische Elektronik 1

5th sem.

Basic Electronic Devices Grundlagen Elektronischer Bauelemente

3rd / 5th

sem.

Technical Electronics 2 Technische Elektronik 2

6th sem.

Basic Electronic Circuits Grundlagen Elektronischer Schaltungen

2nd sem.

Semiconductor Microelectronics Technology 1/ III-V Technologies and Components 1/ Halbleitertechnologie 1

optional

Laboratory exercises

Communication Electronics Praktikum Technische Elektronik

7th sem.

Introduction to Operational Amplifiers Praktikum Operationsverstärker

6th/8th sem.

(optional) optional

Semiconductor Technology Praktikum Halbleitertechnologie/ Halbleitertechnologie 2

8th sem. (optional)

optional

Basic Electronic Devices Praktikum Grundlagen Elektronischer Bauelemente

3rd / 5th

sem.

Basic Electronic Circuits Praktikum Grundlagen Elektronischer Schaltungen

2nd sem.

Seminars and Colloquia

Seminar on Semiconductor Electronics Probleme der modernen Halbleiterphysik

Seminar on Epitaxial Problems


6

Lectures and Exercises:

Introduction to Solid-State Electronics / Solid-State Electronics 1,2 (Einführung in die Festkörperelektronik) / (Festkörperelektronik 1,2)

These courses start with an introduction to the basics of Quantum physics. Based on Schroedinger's equation and Heisenberg's uncertainty relations a comprehensive understanding of semiconductor band structure is achieved. The first part (Introduction to Solid-State Electronics) also includes carrier statistics and ends up with a discussion of current continuity and Poisson's equation. In the second part of this lecture the basic building blocks of electronic devices, i.e. semiconductor-metal contact, MIS system, pn junction and heterostructures, are treated for subsequent courses on field effect and bipolar electronics.

Basic Electronic Devices (Technische Elektronik 1)

MOS-Capacitors, charge coupled devices and Field-Effect Transistors both, on Silicon and III/V material, are treated during the first part of the course. The fundamentals as well as the DC characteristics of MOSFET, MESFET, JFET, and Heterostructure FET (HFET) are derived and analysed in detail.

Additionally, bipolar devices - pn-diodes, npn- and pnp-transistors as well as tunnel- and zener-diodes - are considered. Based on the dc characterisitics simple small-signal equivalent circuits are derived.

Basic Electronic Circuits (Technische Elektronik 2)

This course covers the basic methods to calculate complex electronic circuits using the devices treated within the "Basic Electronic Devices". Various device models with respect to circuit design and circuit simulation using commercial circuit simulation tools are discussed. Numerous analog (e.g. operational amplifiers) and digital applications are included.

Semiconductor Microelectronics Technology 1,2 (Halbleitertechnologie 1,2)

The semiconductor microelectronics technology lectures are devoted to III/V-semiconductor heterostructures for high speed electronic devices. The process steps from crystal growth to circuit fabrication are discussed. The first semester is focused on heterostructure material issues. Modern growth techniques like molecular beam epitaxy (MBE) and metal-organic vapour-phase epitaxy (MOVPE) are discussed in terms atomic layer control of thickness, composition, and doping. High Resolution X-ray diffraction, photoluminescence, and ellipsometry are explained for non-destructive material assessment in the mono-layer scale. The second semester is devoted to microelectronic fabrication techniques for high speed (f ≥100 GHz) devices and circuits. The lateral and vertical processing of epitaxial films, insulating layers, and metallizations are presented for high performance monolithic high speed analog and digital integrated circuits.


Laboratory exercises

Communication Electronics, Basic Electronic Devices, Basic Electronic Circuits (Praktikum Technische Elektronik)

Within the laboratory exercises students apply their theoretical knowledge based on the lectures "Basic Electronic Devices" and "Basic Electronic Circuits". The capacitance-voltage characteristics of schottky diodes are measured and evaluated. The dc and small signal parameters of bipolar transistors as well as the switching behaviour is experimentally investigated. The course also covers the analysis of the dynamical performance of digital circuits. Additionally, numerical simulations and synthesis of basic electronic circuits are carried out on a UNIX system.

Introduction to Operational Amplifiers (Praktikum Operationsverstärker)

The aim of this course is the understanding of the basic principles and the characteristics of operational amplifiers (OpAmps). The laboratory exercises demonstrate their applicability in electronic circuits enabling the students to an independent design and understanding of complex circuits. Starting with the measurement and interpretation of the most important characteristic parameters of OpAmps, circuits like adders and multipliers, amplifiers and active filters are intensively calculated and investigated. Oscillators and generators are designed and measured.

Seminars and Colloquia

Seminar on Semiconductor Electronics (Probleme der modernen Halbleiterphysik)

Within this seminar actual topics of the semiconductor electronics are discussed. Students, but also members of the department, report about their own work.

Seminar on Epitaxial Problems

Problems of the epitaxial growth of semiconductor structures are analysed, results are interpreted and future trends are discussed.

Colloquium on Optoelectronics Recent developments and problems in the Optoelectronics/Photonics field and neighboured topics are presented by invited experts from all over the world.


3.2 Student Reports and Diploma Thesis

(Studien-/Diplomarbeiten)

Student reports

MATISS, ANDREAS

Development of a calibration technique for on-wafer optoelectronic s-parameter measurements April 2002

BEDNORZ, RAFAEL

Entwurf eines optoelektronischen Eingangsverstärkers auf Basis eines HBT-Schichtsystems September 2002

MAHMUD, SALIM

Anpassen eines Großsignalmodells für HBT-EAMs unter PSPICE September 2002

MOFOR, AUGUSTINE MOFOR

Anwendung der Reflexionsspektrometrie in der Molekularstrahlepitaxie zur in-situ Oberflächen-charakterisierung January 2003

SCHLANGEN, RUDOLF

CV-Charakterisierung oberflächenmodifizierter MIS-Dioden January 2003

REGOLIN, INGO

Gleichspannungscharakterisierung von InP/GaAsSb Heterobipolartransistoren February 2003

DERAGOPIAN, SERGE

Physikalische Simulation von Transmission-Line-Messungen mit TCAD February 2003

POLOCZEK, ARTUR

Untersuchung der Prozessparameter bei Gate-Prozess an Heterostrukturfeldeffekttransistoren February 2003

BONSELS, STEFAN

Kontaktoptimierung an hoch p-dotierten GaAsSb Schichten July 2003

BARTH, MATTHIAS

Test mikroelektronischer Strukturierungstechniken für K2SO2/Au Nanobausteine September 2003


BRYSCH, MICHAEL

Entwurf und Simulation von digitalen Schaltungen mit HBT zur Anwendung in der Messtechnik August 2003

SCHNEIDER, LARS

Simulation von HBT mit verschiedenen Kollektorausführungen und deren Auswirkung auf das Hochfrequenzverhalten October 2003

HERSCHBACH, STEFAN

2GHz , 5W Mikrowellen-Leistungsverstärker für Funkanwendungen mit SMD Bauelementen – Entwurf und Optimierung October 2003

Diploma thesis

MAHMUD, SALIM

Entwurf und Herstellung eines MOBILE-Gatters mit optischem Eingang April 2003

MATISS, ANDREAS

Entwurf eines rauscharmen optoelektronischen Eingangsverstärkers auf Basis eines HEMT/ HBT Schichtsystems August 2003

BEDNORZ, RAFAEL

Re-Design eines 40GHz Breitbandverstärkers auf Basis eines HBT-Schichtsystems November 2003

3.3 Doctor Thesis

VELLING, PETER

Zur Metallorganischen Gasphasenepitaxie (MOVPE) mittels nicht gasförmiger Quellen für elektronische Heterostrukturbauelemente basierend auf III/V Halbleitern January 2002


3.4 Seminar on Semiconductor Electronics

17.01.2002 S. NEUMANN, REPORT ON 'Schichtherstellung von HBT mittels MOVPE' - Stand der Arbeiten

24.01.2002 W.PROST, REPORT ON:

'16th Workshop of the DGKK 'Epitaxie von III/V Halbleitern" (2001), Berlin, Germany, 06.12.01 - 07.12.01'

TH. REIMANN, REPORT ON: '11th European Heterostructure Technology Workshop (HETECH 2001), Padova, Italy, 28.10.01 - 30.10.01'

23.05.2002 A. MATISS, REPORT ON THE STUDENT THESIS: 'Entwicklung einer On-Wafer Kalibrationstechnik für optoelektronische S-Parameter Messungen'

20.06.2002 W. PROST, REPORT ON: '26th Workshop on Compound Semiconductor Devices and Circuits ( WOCSDICE 2002), Chernogolovka, Russia, 21.05.02-25.05.02, Chernogolovka, Russia, 21.05.02 - 25.05.02'

04.07.2002 W. BROCKERHOFF, B. SCHLOTHMANN, REPORT ON: '13th Workshop on Physical Simulation of Semiconductor Devices ( PSSD), Ilkley, West Yorkshire, U.K., 25.03.02-26.03.02'

F.J.TEGUDE, REPORT ON: '14th Int. Conf. on InP and Related Materials ( IPRM 2002), Stockholm, Schweden, 12.05.02-16.05.02'

S. EHRICH, REPORT ON: 'Int. Conference on Microelectronic Test Structures ( IEEE), Cork, Ireland, 08.04.02 - 11.04.02'

04.07.2002 S. EHRICH, REPORT ON: 'HF-Charakterisierung und Modellierung von InP basierenden Bauelementen'

11.07.2002 B. SCHLOTHMANN, REPORT ON: 'Expert Evaluation & Control of Compound Semiconductor Materials & Technologies ( EXMATEC 2002), Budapest, Hungary, 26.05.02-29.05.02'

B.SCHLOTHMANN, REPORT ON: 'Simulation von InP basierenden HBT'

18.07.2002 F. OTTEN, REPORT ON: 'Nano 7', Malmö, Schweden, 27.-28.06.02

J. DEGENHARDT, H.-G. GRAH, BERICHT ÜBER DEN STAND DER ARBEITEN 'Entwicklung digitaler Schaltungen auf InP'


25.07.2002 Z. JIN, REPORT ON: 'Chemical Vapor Deposition (CVD) and Reactive Ion Etching (RIE): experiences and outlook'

31.10.2002 R.BEDNORZ, REPORT ON THE STUDENT THESIS: 'Entwurf eines optoelektronischen Eingangsverstärkers auf Basis eines HBT-Schichtsystems'

07.11.2002 MAHMUD, REPORT ON THE STUDENT THESIS: 'Anpassen eines Großsignalmodells für HBT-EAMs unter PSPICE'

14.11.2002 F.J. TEGUDE, REPORT ON: "European Microwave Conference (EUMC)", Mailand, 23.-26.09.02

21.11.2002 W. PROST, REPORT ON: '9th Int. Conf. on Electronics, Circuits and Systems ( ICECS 2002), Dubrovnik, Kroatien, 15.09.02-18.09.02, Dubrovnik, Kroatien

W. PROST, REPORT ON: '4th Int. Conference on Advanced Semiconductor Devices and Microsystems (ASDAM 2002), Smolenice, Slowakei, 13.10.02-16.10.02, Smolenice, Slowakei

16.01.2003 W. MERTIN, V. KHORENKO, REPORT ON THE PROJECT: "ESCHER: Self-assembled building blocks for nanocomputers"

13.02.2003 G. GRAH, J. DEGENHARDT, REPORT ON THE PROJECT: "SUPER-ADC: A/D-converter in superconductor-semiconductor hybrid tech-nology"

24.04.2003 A.MOFOR, REPORT ON THE STUDENT THESIS: 'Anwendung der Reflexionsspektrometrie in der Molekularstrahlepitaxie zur in-situ Oberflächencharakterisierung'

R. SCHLANGEN, REPORT ON THE STUDENT THESIS: 'CV-Charakterisierung oberflächenmodifizierter MIS-Dioden'

22.05.2003 I. REGOLIN, REPORT ON THE STUDENT THESIS: 'Gleichspannungscharakterisierung von InP/GaAsSb Heterobipolartransistoren'

A. POLOCZEK, REPORT ON THE STUDENT THESIS: 'Untersuchung der Prozessparameter bei Gate-Prozess an Heterostruktur-feldeffekttransistoren'

05.06.2003 S. DERAGOPIAN, REPORT ON THE STUDENT THESIS: 'Physikalische Simulation von Transmission-Line-Messungen mit TCAD'

S.MAHMUD, REPORT ON THE DIPLOMA THESIS: 'Entwurf und Herstellung eines MOBILE-Gatters mit optischem Eingang'


03.07.2003 V. KHORENKO, REPORT ON: '20th Anniversary Europ. Materials Research Society Spring Meeting ( E-MRS 2003), Strasbourg, France, 10.06.03-13.06.03, Strasbourg, France'

11.07.2003 J.DRIESEN, REPORT ON: Stand der Parameterextraktion für die HBT-Modellbildung

17.07.2003 F.-J. TEGUDE, S.NEUMANN, REPORT ON: 'Int. Conf. on InP and Related Materials ( IEEE), Santa Barbara, CA, USA, 12.05.03-16.05.03, Santa Barbara, CA, USA

W.PROST, REPORT ON: 'Device Research Conference ( DRC 2003), Salt Lake City, Utah, USA, 23.06.2003-25.06.2003, Salt Lake City, Utah, USA

W. PROST, REPORT ON: '10th Eurp. Workshop on Metalorganic Vapour Phase Epitaxy ( EW MOVPE X), Leece, Italy, 08.06.03-11.06.03, Leece, Italy

24.07.2003 S.TOPALOGLU, J.DRIESEN, REPORT ON THE PROJECT: InP-Elektronik für +80 Gbit/s

23.10.2003 M. BARTH, REPORT ON THE STUDENT THESIS: 'Test mikroelektronischer Strukturierungstechniken für K2SO2/Au Nano-bausteine'

A. MATISS, REPORT ON THE DIPLOMA THESIS: 'Entwurf eines rauscharmen optoelektronischen Eingangsverstärkers auf Basis eines HEMT/HBT Schichtsystems'

06.11.2003 M. BRYSCH, REPORT ON THE STUDENT THESIS: 'Entwurf und Simulation von digitalen Schaltungen mit HBT zur Anwendung in der Messtechnik'

13.11.2003 S. BONSELS, REPORT ON THE STUDENT THESIS: 'Kontaktoptimierung an hoch p-dotierten GaAsSb Schichten'

L. SCHNEIDER, REPORT ON THE STUDENT THESIS: 'Simulation von HBT mit verschiedenen Kollektorausführungen und deren Auswirkung auf das Hochfrequenzverhalten'


27.11.2003 S.EHRICH, REPORT ON: '14th Workshop on Modelling and Simulation of Electron Devices ( MSED), Barcelona, Spain, 16.10.2003-17.10.2003, Barcelona, Spain, 16.10.2003- 17.10.2003'

Z.JIN, REPORT ON: 'EUMC/GAAS/Wireless ( Europ. Microwave Week 2003), München, FRG, 06.10.2003-10.10.2003

04.12.2003 R.BEDNORZ, REPORT ON THE DIPLOMA THESIS: 'Re-Design eines 40GHz Breitbandverstärkers auf Basis eines HBT-Schichtsystems'

S.HERSCHBACH, , REPORT ON THE STUDENT THESIS: '2GHz , 5W Mikrowellen-Leistungsverstärker für Funkanwendungen mit SMD Bauelementen – Entwurf und Optimierung'

16.12.2003, B.SCHLOTHMANN, REPORT ON THE PROJECT 'Simulation von InP basierenden Heterostruktur-Bipolartransistoren'


4 Research Activities

4.1 Materials, Growth and Characterization


4.1.1 Calculation and Design of MOVPE Input Parameters

Technician: M. Haase

Introduction

Growth run programs for Metal Organic Vapour Phase Epitaxy (MOVPE) have to control in each time step typically about 100 parameters. Even if the readability of the recipes was simplified by introducing a syntax (cf. 4.1.2) the controllable technical parameters remained not explicitly related to physical parameters describing the gas mixture situation at the entrance of the reactor. This problem was soon realized during the emergence of MOVPE technology 20 years ago and was first addressed in our group by the work of M. Heuken and F. Scheffer at the end of the 80s [1]. Here I present the state of our understanding of the physical situation at the entrance of the reactor as it has been established after a couple of years and define reasonable parameters, with which the grown crystal and its properties can be controlled.

Established expressions for the gas flows

A gas line configuration, as it is shown in Fig. 1a, a typical MO-line (MO: MetalOrganic), leads to the following expression for the effective MO-flux into the reactor FMO,reac in sccm/min:

totMOMOreacMO FconcF ,, ∗= [sccm/min].g (1)

FMO, the input carrier gas flow into the MO-bubbler, is expanded inside the bubbler by the vaporization and MO-source gas enrichment process up to the value FMO,tot :

)1/(, MOMOtotMO concFF −= [sccm/min]. (2)

By bubbling a concentration concMO is established, which is defined as

MOlinesatMO ppconc ,/= . (3)

The pressure in the bubbler is controlled by the pressure controller to the value pline,MO. It is convenient to use the following expression for the saturation vapour pressure psat of the MO source material:

)760/25,1013(10 )( ∗= − TBAsatp [mbar]. (4)

The parameters A an B are listed for most of the interesting materials in the technical literature (typically giving values in units of torr). The equation itself is the integrated Clausius-Clapeyron equation, and thus hold only for not too high temperature differences to measured values. On the other side for doping situations another line configuration, as can be seen in Fig. 1b, is useful, and the expression for the flux is as follows:

)/( ,,, dilutetotdopMOinjecttotdopMOdopMOreacdopMO FFFFconcF +∗∗= −−−− [sccm/min]. (5)

Here the “MO”-subscript is replaced by “MO-dop”. Eqs. 2 and 5 can be interpreted in the following way: The reactor flow Freac of a MO-material is the product of two concentration and the inject flow:


injectlineMOreacMO FconcconcF ∗∗=, [sccm/min]. (6)

where concMO is defined by Eq. (3) and concline is the concentration behind the line node depicted in Fig.1 of materials A and B using

)/()/( ,,,, dilutetotMOtotMOMOlineBAAAline FFFconcFFFconc +==+= . (7)

Finject’ which is the part of gas behind the line node, which comes into the reactor, is for the MO-line-system the total amount of flow out of the line node FMO,tot + Fdilute (see Eq. (2)).

Fig. 1 Typical realization of a a) MO-line system and b) a MO-dop-line system in the gas cabinet of an Aixtron MOVPE system

The inject-MFC’s see mixtures of gases, but they themselves are calibrated with the carrier gas. So there is a decalibration, because the measured flow is proportional to cp, the heat capacitance at constant pressure, of the gas. It is in this way possible to use the concentration information to calculate the decalibration error [2].

Defined characteristic parameters

With this information you can define some calculable parameters, most of them have shown to be important because of their physical and technological significance:

V/III-ratio defined as:

∑∑= reacIIIreacV FFIIIV ,, // . (8)

V-materials are e.g. arsine, phosphine, or antimone. III-materials are e.g. aluminium, gallium, or indium. This ratio gives hints about the crystalline quality of the grown layer and in some cases about the doping concentration.

IV/III-ratios are defined as (here for the case of carbon):

∑= reacIIIreacCC FFIIIIV ,, // . (9)


This ratio has the form of a concentration and so with it the doping concentration can be controlled. Often the realized doping values are proportional to their IV/III-ratio. For Zn-, Si- or S-doping there can be defined similar expressions.

III/III- or V/V-ratios (which are input concentrations) are defined as (e.g. for IIIGa/III and VAs/V):

∑= reacIIIreacGaGa FFIIIIII ,, // (10)

∑= reacVreacAsAs FFVV ,, // . (11)

With this concentration ratios the concentration x and/or y of the grown ternary and quaternary compounds, e.g. InxGa1-xAsyP1-y; can be controlled.

Other parameters

In the same way the gas flow into the reactor can be summed up to give the gas velocity and to control the growth rate and other parameters. If you use both H2 and N2 as carrier gases, then the hydrogen concentration H2/(H2 + N2) becomes important (because it has also to be maintained) and can be used for technological optimizations [3]. One can easily find other representations of the gas flows, e.g. the partial pressures at the reactor entrance. In the case of special purposes also other meaningful parameters can be defined. So in the case of delta doping it is obvious that a V/IV- or V/II-ratio makes sense [4].

Conclusion

By analyzing and calculating the different flows into the reactor it is possible to extract out of the recipe important process parameters, which allow the versatile control of a MOVPE epilayer structure. An implemantation of these concepts was done recently by Thorsten Reimann (see this Annual Report). Using these parameters is an important step in a paradigm shift towards the use of more significant process data in the control of MOVPE growth processes. But it can only be established by transfering the state of the art technical knowledge of a MOVPE system to a carefully to be maintained database. Then the growth process can be completely automized, so that an operator needs not to know the details of it. It is my opinion, that this step is necessary, because it can lead to a much better documentation of growth processes together with a much better understanding how to control the quality of even complicated epilayer structures. A mature technology must be free of physically meaningless technical details.

References: [1] Frank Scheffer, „Metallorganische Gasphasenepitaxie (MOVPE) für Varaktordioden in monolithisch

integrierten Mikrowellenoszillatoren“, Diplomarbeit, Universität Duisburg, 1989.

[2] In Kim, Kushant Uppal, Won-Jin Choi, and P. Daniel Dapkus; "Composition control of InGaAsP in metalorganic chemical vapor deposition using tertiarybutylphosphine and tertiarybutylarsine“, J. Cryst. Growth, Vol. 193, 1998, pp. 293.

[3] D. Keiper; "Effect of carrier gas and group-V precursor on the doping efficiency of SiH4 for InP and In0.54Ga0.46As/InP in LP-MOVPE“, J. Cryst. Growth, Vol. 233, 2001, pp. 121.

[4] G. Li and C. Jagadish; "Recent progress in δ-doping of III-V semiconductors grown by metal organic vapour phase epitaxy“, Sol. State Electron., Vol. 41, 1997, pp. 1207.


4.1.2 Automated Evaluation of Growth Programs for MOVPE AIX-200

Scientist: T. Reimann Technician: M. Haase

Introduction

Epitaxial growth programs for a MOVPE-system are quite complex and difficult to read. For each grown layer exists a separate command, where the corresponding gas flows and pressures are defined. Unfortunately the actual source gas flow into the reactor and therefore the V/III-ratio is not given directly in the growth program, but defined implicitly. Additionally in complex programs there is a probability that typing errors come in and the growth of the wafer goes wrong. In most cases the result of the error will be a scattering wafer surface. However more subtle errors are possible like when doping was omitted only after device processing and electrical measurement the malfunctionality appears. Even then it is not clear where the problems resides: in epitaxy or in the device technology. Hence there is the wish for extracting all relevant epitaxial growth parameters directly out of the growth program. Simulatenously the syntax of the program is verified. In our research group a computer program emerged (called epi2dat) which parses and evaluates the growth programs for the MOVPE AIX-200. It is intended not only for helping epitaxy people but also for process engineers in tracking down epitaxial/technology problems.

read MOVPE configurationdefine source materials

parse next command inEPI-program

actualize gas variables

calculate effective flows

print state (e.g. HTML)

Fig. 1 Flow diagram of the MOVPE extraction program epi2dat.

Program implementation

The program was written in the language C++ for the gcc-compiler and can be used under MS-Windows and Linux. It accepts a complete directory of growth programs and converts the output to HTML, which can be read by any browser having network access to the files. A basic flow diagram of the program is shown in Fig. 1. After start a configuration file is read which defines what source materials are available and what are its properties. Thereafter all necessary variables are generated


to fully define the state of the MOVPE-system, like fluxes of the mass-flow-controllers, the pressure controllers and the state of the valves. Fig. 2 shows two samples from the configuration file describing e.g. the source name and its partial pressure. This file contains also wanted keywords to define several categories, under which the growth programs should be listed. After initialization each command of the growth program is parsed and stored into the state variables of the system. With all given values it is straightforward to calculate the effective gas flows into the recipient.

# name type sym v partp m_mol line run src push pressTMIn_1 liq In 3 2.31 159.9 off off 10 50 200

# name type sym v partp m_mol line run1 run2 src dil inj1 inj2 pressCBr4_1 liq2 C 4 1.22 331.6 off off off 10 50 5 20 1200

Fig. 2 Sample fragment of the configuration file. The name of the sources, symbols, partial pressures, molecular masses and others can be defined easily.

The formulas used for the calculations are listed in the report from M. Haase in this annual report. Then the values are converted to HTML and stored in a newly generated file. The program epi2dat can be executed by a command line like "epi2dat -inputfile -outputfile" to convert a single file. With "epi2dat -inputdir /dir" a complete directory is converted.

Fig. 3 Output of epi2dat in HTML-format. On the left the user is able to select growth programs which contain a keyword. On right the parsed and evaluated data is shown. Several views are possible. Here the tiny-view is given.


Sample outputs

If a complete directory of growth programs was processed, the browser window can look like Fig. 3. The left bar shows the predefined keywords. After pressing a keyword all growth programs containing that keyword will be listed to the left (see Fig. 4). It is also possible to use materials as a keyword (e.g. InAlAs:C). On the right of Fig. 3 the tiny-view of a sample program is given. It lists the layers to be grown and gives a basic overview of the most important parameters. Already at this point most errors possible should be identified. At the right top is a navigation bar enabling access to other more detailed views. At the very top resides a line which splits two independent browser windows. By dragging the line down two growth programs can be view and compared.

Fig. 4 On the left bar all epi-layers which contain the keyword HBT are listed. On the right the short-view is given. All commands which will grow a layer onto the substrate are listed beside its actual parameters like temperature, effective source flows and V/III-ratios.

In Fig. 4 the short-view is visible. Here more specific values are listed. All calculated source flows are printed and grouped together in accordance to their chemical group. For each group the total source flow is determined and the ratios V/III and IV/III are given, which are visualized by a graphic bar. Additionally the total flow through the reactor is calculated. Between the different epitaxial layers the total flow should be kept constant. The ratio Frun/Ftot gives the amount of source carrier gas (here H2) to the total gas flow (here N2 plus H2).

There is also a long-view available. In this case intermediate commands in the growth program are printed like growth pauses and temperature ramps. Fig. 5 shows the table-view where all relevant


parameters are listed. The data can be selected and copied into an external calculation program e.g. MS-Excel.

The quantity-view lists an approximation for the usage of source material in gram. The amount, which is directed to the vent gas line, is printed as percentage. A look to this results should help in saving valuable source material.

Fig. 5 Here the table-view is shown. It lists all relevant data in a compact format.

Conclusions

An extraction tool for MOVPE AIX-200 growth programs was developed. After parsing the original program all defined states can be extracted and converted into a more readable form like effective source flows and V/III-ratios. This simplifies program generation and helps to minimize errors. As an outlook one can imagine that the same could be done the opposite way, i.e. creating a tool for generating the growth programs themselves by choosing the wanted layers and thicknesses out of a material data base.


4.1.3 Nitrogen Carrier Gas for the Growth of GaAsSb/InP DHBT

Scientist: S. Neumann Technical Assistant: M. Haase, A. Osinski

Introduction

The GaAs0.51Sb0.49:C base layer in InP double heterojunction transistor (DHBT) has recently demonstrated ultra high speed combined with high breakdown voltage and very high current density [1]. The success of this approach is attributed to the type-II transition at the GaAsSb/InP base collector heterointerface [2] enabling a wide band gap InP collector without any current blocking effect. However, the growth of GaAsxSb1-x lattice matched to InP is possible far away from thermal equilibrium, only. In addition, the limited growth temperatures required for high p-type doping and the etching effect of the carbon sources like CBr4 or CCl4 resulted in substantial efforts in order to control sticking coefficients of As and Sb and the limited decomposition of the Ga source. It is well known from previous studies using the InGaAs:C base layer that nitrogen carrier gas instead of hydrogen may relax the growth difficulties while enabling higher growth temperatures for the same C-doping density [3]. In this work the use of nitrogen carrier gas for the GaAsSb:C base layer and the GaAsSb/InP DHBT is investigated.

Experimental Setup

The experiments were done on semi insulating, exactly oriented (001) InP:Fe substrate in a AIX 200 reactor with RF heating. Purified nitrogen is used as carrier gas except for source take-up. A reactor pressure of ptot= 50 mbar and a total flow of Qtot= 3.4 slm were adjusted. We used a non gaseous source configuration with TBAs/TBP/TMSb as group V sources, DitBuSi/CBr4 as group IV doping sources and the metal-organic sources TMIn/TEGa. For the determination of the antimon (Sb) concentration in the partial highly strained GaAsSb layers and for the non destructive characterisation of the HBT layers high resolution x-ray diffractometry (HRXRD) was used. Hall measurements were performed using standard van der Pauw method.

Experimental Results

In the presence of nitrogen carrier gas the solid Sb incorporation is studied in detail. The growth temperature is fixed at Tg = 550°C for high p-type doping and the gas phase is fixed to V/V = 1. In Fig. 1a the solid Sb incorporation in GaAsxSb1-x is plotted versus the V/III ratio. It can be seen that under excess group-III (V/III<1) the Sb incorporation saturates while under excess group-V (V/III>1) the Sb incorporation decrease. This effect is related to a preferable As-Ga bond which is evident under Ga-shortage, only. Using hydrogen carrier gas enhances the Ga source decomposition and results in a higher V/III ratio for this effect.


a) b)

Fig 1 a) Antimony incorporation as a function of the V/III ratio at 550°C at a fixed V/V ratio of 1.

b) Dependence of Sb incorporation of the grown layer for various CBr4 flows. The growth temperature was fixed at 550°C.(symbols: measured data; solid line: fitting)

For p-type doping CBr4 is used and a linear increase of dopant density with CBr4/Ga ratio (IV/III) up to p= 6.3 x 1019 cm-3 is observed. The CBr4 reduces the Ga concentration at the growth front which results, in agreement with Fig. 1b, in a reduction of Sb incorporation. Based on this results the growth of p-GaAsSb single layers (Fig. 2) and final DHBT layers is performed using nitrogen carrier gas.

010

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p-GaAs0.43Sb0.57 InP99.2Sb0.8

Fig. 2 Measured and simulated high resolution x-ray curve for the (004) reflex of a 65 nm thick p-GaAsSb layer.

HRXRD measurement (Fig. 2) show excellent crystal quality. Attributed to the run to run memory effect up to 8% Sb was build in the first InP buffer layer. First non optimised DHBT devices we

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X. G. XuAPL, 74 (7) 1999

M. J. CherngJ. of Electr. Mater.13 (5) 1984

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realized with a p-type doping level of p= 6 x 1019 cm-3 (cf. Fig. 3). High frequency analysis on a 1x5 µm2 device shows a current gain cut-off frequency fT= 95 GHz and a maximum oscillation frequency fMAX= 60 GHz.

Fig. 3 Common emitter output characteristic for an InP/GaAsSb/InP DHBT.

In summary the MOVPE process for GaAsSb/InP DHBT is elaborated using nitrogen carrier gas. We observe excellent material quality of single layers and first DC and HF measurements of realized DHBTs confirm this approach.

Acknowledgement

Thanks to Eric Majoor from Akzo Nobel for helpfully discussions and the cooperation concerning the TMSb source.

References: [1] C. R. Bolognesi, M. W. Dvorak, N. Matine, O. J. Pitts, S. Watkins ; Jpn. J. Appl. Phys, Vol. 41, 2002.

[2] R. Bhat, W-P. Hong, C. Caneau, M. A. Koza, C-K. Nguyen, S. Goswami ; Appl. Phys. Lett, Vol. 68 (7), 1996.

[3] D.Keiper, P.Velling, W.Prost, M.Agethen, F.J.Tegude, G.Landgren, Jpn.J.Appl. Phys. vol. 39, 2000.

[4] M. J. Cherng, R. M. Cohen, G. B. Stringfellow; J. of Electronic. Materials, Vol. 13, No. 5, 1984.

[5] X.G. Xu, J. Hu, S.P. Watkins, Appl. Phys. Lett., Vol. 74, No. 7, 1999.

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4.1.4 Growth and Characterization of pnp InAlAs/InGaAs HBTs

Scientist: S. Neumann Technician: A. Osinski

Introduction

InP-based heterobipolar transistors (HBTs) are widly used for high speed application. Especially npn-HBTs shows excellent high speed performance [1] with record cut-off frequency (fT) and maximum frequency of oscillation (fmax) up to 300 GHz. Only few effort were done to investigate pnp-HBT. This is due to the slower hole than electron transport characteristic. InP-based pnp HBT research has been concentrated on HBTs with InAlAs as emitter and Zn as p-type dopant. The best InAlAs/InGaAs pnp HBT achieved up to fT = 20 GHz and fmax= 30 GHz [2]. The use of both, npn and pnp HBTs, enables a complementary circuit design with make the design easier and save space. In this work we present the first InAlAs/InGaAs pnp-HBT we realized on our department. Due to the low diffusivity CBr4 was used as p-type doping source. Carbon is preferred as an alternative p-dopant over Zn and Be.

Experimental Setup

The experiments were done on (001)±0.5° orientated s.i. InP:Fe epi-ready substrates in an AIX200-system with rf-heating at 50 mbar reactor pressure using N2 carrier gas and a total gas flow of Qtot= 3.4 slm. The ngs-configuration based on TBAs/TBP/TMAs as group V, CBr4 as group IV doping source and the metal organic sources TMIn and TMAl. An in-situ annealing sequence with TMAs at T > 600 °C for H-radical free arsenic stabilization was used to activate the carbon atoms by reducing the hydrogen passivation. The group-V to group-III ratios (V/III) and also the group-IV to group-III ratios (IV/III) were calculated from the ratio of the partial pressures of the involved precursors by the assumption of 100% source efficiency. The doping behaviour from InAlAs:C with carbon was investigated intensely [3]. A linear cabon incorporation with IV/III ratio was found in the investigated rang from p=1.1017 cm-3 up to p=1.1020 cm-3. The p-type doping level of the p+-InAlAs:C layers was determined at room temperature by van der Pauw Hall measurements. Ohmic contacts were made using alloyed Indium junctions. The quality of the layer structures was proven by high-resolution X-ray (HRXRD) measurements in the vicinity of the 004- and 002 -reflection in a coupled ϖ-2Θ-mode using a double monochromator set-up.


In fig. 1, the HBT layer parameters are given which were determined by simulation of the recorded reflection curves of the (004) and the (002) reflex using the optimiser software. The as-grown HBT layer sequence is used for the X-ray simulations and only small variations of about +/-10% in composition and thickness of each layer around the intended values are chosen as simulation parameters. The excellent agreement of the measured and simulated rocking curve for the 004- and 002- reflex enables the determination of the compostion and thickness


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Fig. 1 Measurement and Simulation of the (004) and (002) x-ray curve. The simulation for both reflections were done with the same layer stack.

Figure 2 shows the Equilibrium energy-band diagram of fabricated pnp-HBT by using InAlAs as emitter a high barrier for the Electrons

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Fig.2 Equilibrium energy-band diagram of fabricated pnp-HBT

Figure 3 shows the common emitter output characteristics. Only a small current gain of ß=2.3 can be achieved. Further, the sample shows an ideal output characteristic with a high breakdown and a small early voltage.


-10 -8 -6 -4 -2 0-2.5

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A]

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Fig.3 Common emitter I-V characteristic for the fabricated pnp-HBT with a 3 x 15 µm2 emitter finger

The on-wafer S-parameter measurements were performed using an HP8510C network analyzer in the frequency range from 45 MHz to 40 GHz. The non-deembedded cutoff frequency (fT) of 6 GHz and maximum oscillation frequency (fMax) of 3.5 GHz are measured at VCE of 4.0 V and JC =8x104 A/cm2.

Conclusion

InAlAs/InGaAs pnp-HBT structures are grown by LP-MOVPE using a non-gaseous-source configuration with nitrogen carrier gas. The present results demonstrate the applicability of the ngs-configuation for the growth of highly homogeneously pnp HBTs. Using HRXRD measurement and simulation the layer parameters can be determined. The current gain and the S-parameter measurements shown that further work is necessary to improve the HBT characteristics. A simple way is to reduce the base doping level. This will be improve directly the current gain and the high frequency performance [2].

References [1] P.A. Housten; “High-frequency heterojunction bipolar transistor device design and technology”,

Electronics & Communication Engineering Journal, IEE (2002).

[2] D. Cui, S. S. H. Hsu, D. Pavlidis; “DC and High Frequency Characterization of Metalorganic Chemical Vapor Deposition (MOCVD) Grown InP/InGaAs PNP Heterojunction Bipolat Transistoren”, Jpn. J. Appl. Phys., Vol. 41 (2002) pp. 1143-1149.

[3] S.Neumann, W.Prost, F.J.Tegude; “Growth of Carbon doped LP-MOVPE InAlAs using non gaseous sources”, J. Chrystal Growth 248 (2003) 130-133.


4.1.5 Ordering of InxGa1-xAsyP1-y Depending on Composition and Growth Temperature

Scientist: S. Neumann, J. Spieler1) Student: Robert Blache1)

Technical Assistant: M. Haase

1): Technische Physik I, G. H. Döhler, University Erlangen-Nürnberg

Introduction

The quaternary material InxGa1-xAsyP1-y shows under certain growth conditions the formation of a natural superlattice in [111]B direction, corresponding to a CuPtB strucure [1,2]. It is formed by alternating gallium, indium and arsenic, phosphorous rich layers along the [11-1] and [1-11] direction We have investigated the spontaneous self ordering in dependence of growth temperature and substrate tilt using the Franz-Keldysh effect. The specific requirement to get ordering is a low growth temperature (Tg = 550°C – 600°C). Using the standard hydrides as group-V sources this temperature would be far below the diffusion controlled growth regime and results in unstable growth conditions. Therefore, we used liquid group-V precursors (TBAs, TBP) instead of the conventional sources AsH3 and PH3. Especially the better thermal decomposition of TBP compared to PH3 is a key component to realise a constant phosphorous content y during growth, enabling thick In1-xGaxAsyP1-y layers. This way the exploitation of the ordering effect of thick and lattice matched In1-xGaxAsyP1-y layers is feasible for various wavelengths including 1.3 µm and 1.55 µm.

Experimental Setup

The growth was done on (001)±0.5°, (001) 2°A and (001) 2°B orientated s.i. InP:Fe epi-ready substrates in an AIX200-system with rf heating at 50 mbar reactor pressure using N2 carrier gas and a total gas flow of Qtot= 3.4 slm. The ngs-configuration is based on TBAs/TBP as group-V, TMIn/ TEGa. A growth temperature range of 550°C < Tg < 625°C are investigated. The given group-V to group-III and V/V ratios are calculated from the ratio of the partial pressures of the involved precursors by the assumption of 100% source efficiency. The input V/III ratio was typically between 20-30.

The composition and the quality of the material is evaluated by HRXRD measurements near the (0 0 4)-reflection in a coupled ω-2Θ-mode using a double monochromator set-up. Further with the formation of ordered structures a additional reflection can be observed, wich are forbidden in zinc-blende crystals [3]. The band gap and the layer quality is characterized by photoluminescence. An iterative method is used to extract the quaternary layer composition [4]. Room-temperature electroabsorption measurements based on the Franz-Keldysh effect are used to measure the valence-band splitting as parameter for the degree of ordering while the ordering related band-gap reduction remains quantitatively uncertain. The measuring method is described in detail in [5]. In this paper we used the extracted values according [4] for the composition without consideration of the band gap reduction.


Growth

The precise control of the group III- and the group V-ratio is necessary to achieve lattice matched material with the desired composition. 300 nm thick In1-xGaxAsyP1-y layers were grown with different composition at various growth temperatures.

Fig. 1 Experimental data of used phosphorus to arsenic partial pressure versus growth temperature to achieve lattice matched InGaAsP for 1.3 µm and 1.5 µm application

Figure 1 shows the used V/V ratio in the gas phase versus growth temperature to achieve lattice matched material for optical fibre application. The exponential trend in V/V ratio with decreasing growth temperature indicate the kinetically controlled growth mode. This is caused by the less complete decomposition of TBP compared to TBAs. An influence of the group V/V- and V/III-ratios on the group III incorporation was not observed.

Fig. 2 Dependence III/III [In/Ga] to V/V [P/As] ratios in gas phase to observe lattice matched InGaAsP on InP and dependence on solid layer composition at Tg=575°C.

In Figure 2 the used III/III [In/Ga] and V/V [P/As] partial pressure ratios are shown to achieve lattice matched In1-xGaxAsyP1-y for different composition at Tg=575°C. Again here an exponential correlation is observable. The fitting of the experimental data enabling the simple adjustment to a

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∆a/a< 3000 ppm

Tg=575°C


new composition for a fixed growth temperature. For the x-ray and FKE measurements we grown 500 nm and 700 nm thick In1-xGaxAsyP1-y layers with different composition at various substrate temperatures.

Results and Discussion

The asymmetric ½ (115) x-ray reflection can be used to observe the ordering structure [3]. Because of the superlattice dimension on an atomic scale and antiphase boundaries only a weak peak with a broad FWHM can be observed.

Fig. 3 Experimental x-ray diffraction curve of the monolayer superlattice in the vicinity of the ½ (115) reflection.

Figure 3 shows the ½ (115) ordering reflection of In0.75Ga0.25As0.5P0.5 lattice matched on InP. This recordered reflection curve is the first observation of this additional peak of quaternary InGaAsP on InP substrate.

Fig. 4 Temperature dependence valence band splitting for exact, 2°A and 2°B oriented substrates.

The ordering effect influence the band structure. This leading to a band gap reduction and to a splitting of the light and heavy hole states in the valence band. The splitting energy EVBS correlated

38.5 39.0 39.5 40.0 40.5 41.030

40

50

60

80

100

200

log

Inte

nsity

[cou

nts/

s]

2Θ [degree]

550 575 600 625

0

5

10

15

20

25

30

EV

BS [m

eV]

Tgrow

substrate tilt 0° = [001] 2° = [111]

A

2° = [111]B

In0.75Ga0.25As0.5P0.5

λ ≅ 1300nm

550 575 600

0

5

10

15

20

∆E

VB

S [m

eV]

Tgrow

substrate tilt 0° = [001] 2° = [111]

A

2° = [111]B

In0.6Ga0.4As0.75P0.25

λ ≅ 1300nm


to the degree of ordering. Electro absorption measurements are very appropriate method to investigate direct optical transitions and to determine the valence band splitting energy.

For various compositions, growth temperature and substrate tilt the valence band splitting energy VBS is evaluated (Fig. 4). The highest degree of ordering is observed at a growth temperature of

Tg= 575°C. With decreasing or increasing growth temperature the splitting energy ∆EVBS decreases. The splitting energy can enhanced by using tilted substrate with the maximum observed at 2° against [111]B direction. Surprisingly, a high degree of ordering is observed at 1.55 µm and the highest degree is obtained at 1.3 µm. The valence band splitting energy is even higher than found in the ternary material InGaAs on InP and InGaP on GaAs. This observation indicates a strong additional contribution of group-V ordering in the In1-xGaxAsyP1-y layers.

Conclusions

With low pressure MOVPE and non gaseous source configuration high quality In1-xGaxAsyP1-y layers were grown with different composition at low growth temperatures. The use of TBP is a key component to grow layers of high quality at growth temperatures below 600°C. In agreement with previous studies the highest degree of ordering is achieved on (100) substrates tilted by 2° against (111)B. The splitting energy of In1-xGaxAsyP1-y is comparable or even higher than in group-III ordered GaInP/InGaAs indicating a strong additional contribution of group-V ordering.

References [1] W.E. Plano, D.W. Nam, J.S. Major, Jr., K.C. Hsieh, N. Holonyak Jr; “Column III and V ordering in

InGaAsP and GaAsP grown on GaAs by metalorganic chemical vapor deposition”; Appl. Phys. Lett., Vol. 53, No. 25, pp. 2537-2539, December 1988.

[2] Knauer, G. Oelgart, A. Oster, S. Gramlich, F. Bugge, M. Weyers; “Ordering in InxGa1-xAsyP1-y grown on GaAs by metalorganic vapour-phase epitaxy”, J. Crystal Growth, vol. 195, pp. 694-699, 1998.

[3] Q. Liu, H. Lakner, F. Scheffer, A. Lindner, W. Prost; “ Analysis of ordering in GaInP by means of x-ray diffraction“, J. Appl. Phys., vol. 73, no. 6, pp. 2270-2274, March 1993.

[4] E. Kuphal, A. Plöcker; “Phase Diagramm for Metalorganic Vapor Phase Epitaxy of Strained and Unstrained InGaAsP/InP“, Jap. J. Appl. Phys., vol. 37, pp. 632-637, February 1998.

[5] J.Spieler, T.Kippenberg, J.Krauß, P.Kiesel, G.H.Döhler, W.Prost, P.Velling, F.-J.Tegude; “Electro-optical examination of the band structure of ordered InGaAs”, Appl. Phys. Lett., 76(1) 88-90, (2000).


4.1.6 MOVPE Growth of (dis-)ordered InGaAsP PIN-FET Diodes for Optical Fibre Applications

Scientist: S. Neumann, J. Spieler1) Student: Robert Blache1)

Technical Assistant: M. Haase

1): Technische Physik I, G. H. Döhler, University Erlangen-Nürnberg

Introduction

GaxIn1-xAsyP1-y layers grown by LP-MOVPE at reduced growth temperatures exhibit a high degree of ordering. This effect is used to fabricate polarization dependent devices in the optical fibre wavelength regime. A non gaseous source configuration (ngs) based on the group-V precursors TBAs and TPB enables the growth of up to 700 nm thick lattice matched quaternary absorption layers. The highest degree of ordering is observed at a growth temperature of Tg=575°C with nearly the same phosphorous to arsenic content in solid phase. This indicates a strong additional contribution of group-V ordering. A first polarization switch is fabricated combining a pin-diode and a FET exhibiting 55 dB polarization contrast. These results indicate the high potential of this approach for on-line polarisation mode dispersion (PMD) compensation circuits.

Approach

The polarisation mode dispersion (PMD) is limiting the transmission capacity of conventional multi-mode optical fibre [e.g. 1]. The on-line correction of PMD may become feasible if a dynamic polarisation dispersion measurement could trigger a PMD correction circuitry [1]. The near band-gap absorption anisotropy of ordered semiconductor layers is proposed here for polarisation measurement. Microelectronic polarisation dependent devices could be of considerable interest for PMD compensation if their wavelength of operation could be transferred to the wavelength of the optical fibre.

Under certain growth conditions [2] the epitaxial growth of ternary and quaternary semiconductors yields the spontaneous formation of a superlattice along the [111]B crystal orientations. It is formed by alternating gallium and indium rich layers along the [11-1] and [1-11] direction. The random distribution of the group-III and group-V atoms in the zinc-blende- (ZnS-) lattice structure changes to the CuPtB-lattice. In ordered layers the degeneracy of the valence band is lifted and an energy splitting between light and heavy hole valence b VBS occurs [2-4]. Moreover, due to selection rules the absorption of polarised light with an energy close to the band-gap becomes dependent on the light polarization. It is well known that the ternary layers InGaAs on InP-substrate and GaInP on GaAs-substrate exhibit a high degree of group-III ordering [2-8]. An optical anisotropy was also achieved using In0.64Ga0.36As0.12P0.88 layers on GaAs-substrates [5] resulting in a low wavelength of ~ 700 nm. A weak ordering of group V elements As and P was observed [8].

A suitable candidate for the desired wavelength regime, is an In1-xGaxAsyP1-y absorption layer lattice matched to InP. The degree of ordering depends on growth conditions such as growth temperature, composition and substrate orientation. In this work the polarisation anisotropy of ordered


In1-xGaxAsyP1-y layers adopted to the optical fibre wavelength regime of 1.3 µm and 1.55 µm is demonstrated and first polarisation dependent devices are presented.

Results

The pin-diode layers are grown by MOVPE incorporating a 700 nm thick ordered In0.72Ga0.28As0.61P0.39 absorption layer sandwiched between p- and n-type contact layers which are transparental at the wavelength of operation. (fig. 1a). Devices are fabricated with a window of 120 x 120 µm². The I-V characteristic of the device grown at Tg=575°C exhibits a reverse breakdown voltage of 25 V indicating an low background impurity density (Fig. 1b).

I [A

]

1.10-9

1.10-5

1.10-6

1.10-7

1.10-8

1.10-2

1.10-3

-25 -20 -15 -10 -5 0 5U [V]

200 nm

100 nm

700 nmInGaAsP

InP

n-InP

s.i. InP:Fe (100) substrate

2° towards (111)B

300 nm

100 nm

p+-InAlAs

InP

120 µm

Tg = 575 °C

a) b)

Fig.1 a) Layer stack of the pin-FET b) Current voltage characteristic of a 120 x 120 µm2 device.

The optical anisotropy is investigated by irradiation with polarised light. The measured quantum efficiency of polarised light shows a strong anisotropy along the (011) and the (01-1) direction up to 50 % around 1.3 µm.

The device shown in the inset of figure 1 can be understood as a combination of a junction field effect transistor with a pin-diode (pin-FET). The n-channel is formed by the top InP layer with two selective n-type contacts, acting as source and drain. The p-contact on the bottom p-layer forms the gate. The thickness and the doping concentration of the n-layer are adjusted, such that the channel becomes depleted under suitable reverse bias U. Another pin diode with a smaller band gap serves as constant reference for the polarization dependent pin-FET in figure 2.


U0

Ipn

Unn

Inn

Upn

Uload

n-InP

InP

InGaAsP

InP

p-InP

n-InP

InP

InGaAs

InP

p-InP

InP Buffer

200 nm

100 nm

500 nm

100 nm

200 nm

200 nm

100 nm

135 nm

100 nm

200 nm

pin-FET

referencepin-diode

G

SD

D S

G

U0

Fig. 2 Electric setup and layer stack of the pin-FET with in series connected pin diode

The use of optical transparent p-layers enable the stacked growth of pin diode and pin-FET resulting in a double pin-FET structure.

0 20 40 60 80 100 120 140 160 1801.10-10

1.10-9

Popt=1.3 µW

"off"

"on"

Gnn

(S)

light polarization Θ (°)

1.10-6

1.10-7

1.10-8

1.10-2

1.10-3

Fig. 3 Polarization switching of the n-channel current. The n-chanel current can be swiched “on” and “off” over several orders of magnitude by rotating the polarization angle Θ of the linearly polarized optical input.

Light gets partly absorbed in the InGaAsP diode. The generated photocurrent as well as the transmitted intensity depend on the polarization due to the anisotropic absorption of the intrinsic ordered In1-xGaxAsyP1-y. The transmitted light is afterwards absorbed in the InGaAs layer. The thickness of the two absorbing layers are adjusted to absorb the same optical intensity at Θ=45°. Depending on the angle of polarized light, the absorption in one diode increases and decreases in the other. Figure 3 shows the measured n-channel conductance Gnn as a function of the polarization angle Θ.


The conductance Gnn depends significantly on the polarization angle. For light with the polarization angle Φ = 0°, the photocurrent in the pin-FET is much smaller than that in the reference diode. As consequence, the applied reverse bias voltage U0 drops nearly entirely at the pin-FET. The resulting high reverse bias at the pin-FET corresponds to a depletion of its n-channel, i.e. the switch is non conductive (“off”) for the polarization state Φ = 0°. If the polarization is rotated, the photocurrent in the pin-FET increase while it decrease in the reference diode. The n-channel remains depleted up to a certain angle. If the polarization angel further increase, the voltage drop over the pin-FET changes rapidly until it gets nearly zero. As a consequence, the n-channel conductance Gnn increase drastically until it reaches its maximum value (“on”). The switching contrast is 5 ½ orders of magnitude within 10° of incident light orientation.

Conclusions

With low pressure MOVPE and a non-gaseous source configuration high quality In1-xGaxAsyP1-y layers were grown with different composition at low growth temperatures. The use of TBP is a key component to grow layers of high quality at growth temperatures below 600°C. In agreement with previous studies the highest degree of ordering is achieved on (100) substrates tilted by 2° against (111)B

[4]. The splitting energy of In1-xGaxAsyP1-y is comparable or even higher than in group-III ordered GaInP/InGaAs indicating a strong additional contribution of group-V ordering.

The ordered GaxIn1-xAs1-yPy absorption layer results in high quantum efficiency of up to 0.2 A/W with up to 50 % anisotropy for polarized light. A first polarization switch is fabricated combining two pin-diodes and a FET exhibiting 55 dB polarization contrast. These results indicate the high potential of this approach for on-line polarisation mode dispersion (PMD) compensation circuits.

References [1] H. Bülow; Core and ATM networks, NOC´97, Ed. D.W. Faulkner, A.L. Harmer, IOS Press 1997.

[2] F. Scholz, C. Geng, M. Burkard, H.P. Gauggel, H. Schweizer, R. Wirth, A. Moritz, , A. Hangleiter; Physica E 2, 8 (1998).

[3] T.S. Kuan, W. I. Wang, and E.L. Wilkie; Appl. Phys. Lett. 51(1), 51 (1987).

[4] J.Spieler, T.Kippenberg, J.Krauß, P.Kiesel, G.H.Döhler, W.Prost, P.Velling, F.-J.Tegude; Appl. Phys. Lett., 76(1) 88-90, (2000).

[5] A. Knauer, G. Oelgart, A. Oster, S. Gramlich, F. Bugge, M. Weyers; J. Crystal Growth, Vol. 195, pp. 694-699, 1998.

[6] Q. Liu, H. Lakner, F. Scheffer, A. Lindner, W. Prost; J. Appl. Phys., Vol. 73, No. 6, pp. 2270-2274, March 1993.

[7] W.E. Plano, D.W. Nam, J.S. Major, Jr., K.C. Hsieh, N. Holonyak, Jr; Appl. Phys. Lett., Vol. 53, No. 25, pp. 2537-2539, December 1988.

[8] M.A. Shahid, S. Mahajan, D.E. Laughlin; Phys. Rev. Lett., Vol. 58, No. 24, pp. 2567-2570, June 1987.


4.1.7 LP-MOVPE Growth of InGaAs/InP Superlattice on Si Substrate

Scientist: S. Neumann, A. Bakin1)

1): Institut für Halbleitertechnik, Technische Universität Braunschweig (TUBS)

Introduction

The growth of compound semiconductors on Si substrate is very attractive to use the familiar advantages of each material. Large mismatch of lattice constants (8 % in case of InP on Si), different thermal expansion coefficients, and crystal symmetry inevitably cause one- and two-dimensional lattice defects in III/V layers epitaxially grown on Si. At TUBS a process was developed for the growth of high quality InP layers with a smooth surface. On this first buffer layer we have grown after a 300 nm thick InP buffer a resonant tunnelling structure. This was the first realized RTD directly on a Si substrate. Devices shows at room temperature the typically negative differential resistance [1]. Thus first realized III-V RTD-structures on Si substrate shown a high impact of crystal defects. In Fig. 1 the difficult and problematic of the regrowth experiments becomes clear. In this work, we present the using of a superlattice structure to avoid the crystal defects.

Fig.1 Optical micrograph of realized RTD structure with simple InP buffer. A high concentration of defects can be observed.

Experimental Setup

At TUBS a process was developed to growth InP layers on exactly oriented (001) Si substrates. Commercially available 2 inch wafers are of inferior surface quality as TUBS demonstrated by a series of growth experiments. Therefore, we employed 4 inch wafers cutted to fit in our growth apparatus. Prior to InP growth a special nano-patterning of the Si substrate was employed, investigated and optimised [2]. The growth was performed at TUBS in a horizontal IR-heated metal-organic vapour-phase epitaxy (MOVPE) machine at low pressure (20 to 100 hPa) under a total hydrogen flow of 8 l/min. Prior to the growth the wet-chemically cleaned Si substrates were thermally treated at 950°C for 15 min in a hydrogen atmosphere in order to remove the native oxide. Arsine (AsH3) was introduced during the cooling phase to improve growth by forming double layer

0,5mm


steps and more stable Si-As bonds. Subsequently a low-temperature (400°C) InP buffer-layer is grown on the Si substrate. This buffer serves as seed for the further growth of the high quality InP main-layer which occurs at 640°C.

The regrowth experiments were done at GMUD in an AIX 200 with horizontal reactor and RF-heating. We use a non gaseous source (ngs) configuration with the precursor TBA, TBP as group V sources, DitBuSi for n-type doping and the group III sources TMIn, TEGa and TMAl. A total flow of Qtot = 3.4 slm and a pressure of ptot = 50 mbar were adjusted using nitrogen as carrier gas. Layers were characterised by HRXRD, optical microscopy and AFM.


XRD measurements of the layers grown under optimised conditions show a full width at half maximum of the (004) rocking curve of about 79 arcsec for a 2 µm thick layer [2]. This is actually the best known result for InP on Si. The InP on Si epi-wafers were transferred from TUBS to GMUD for further growth on an InP main layer.

The optical micrograph in Fig. 1 shows a high concentration of defects on the surface. It was well known that superlattice structures smoothing the surface and prevent the formation of twin lamellas [3]. Therefore, we supplement the additional InP buffer after the transfer from TUBS to GMUD with a superlattice consist of 10 pairs 10 nm InP and 30 nm InGaAs lattice matched to InP.

-12500 -10000 -7500 -5000 -2500 0 2500

log

In

ten

sity

Seconds

InP-Substrate

Si-Substrate

Si-Substrate

40 nm InP buffer

3 µm InP

250 nm InP

250 nm InP

10 nm InP

30 nm InGaAsx 10

TUBS

GMUD

Fig.2 HRXRD (004) peak of a superlattice structure grown on Si and InP substrate

In Fig. 2 the (004) reflection of realized superlattice structure regrown on the InP/Si substrate are compared with the same structure grown directly on InP substrate in the same run. It can be observed that both samples show formation of superlattice peaks on both sides from the InP peak. The intensity of this peaks indicate a higher crystal quality of the direct on InP substrate grown structure.


24

68

µm

010

nm

24

68

µm

010nm

InP layer on Si (TUBS) regrowth (GMUD)

Fig.3 Optical micrograph (x200) and AFM images of the InP surface before (left) and after the regrowth (right) with a superlattice structure.

Fig. 3 shows the surface of an InP/Si layer before and after the regrowth with the superlattice buffer structure. The optical micrograph and the AFM image show a smoothing of the micro roughness whereas the overall RMS values of the substrate roughness don’t change. Only some defects can be observed whereas the defect density is in the same range as on the directly on InP substrate grown structure. The formation of twin lamellas was no more observed

Conclusion

The growth of compound semiconductors on Si substrate is very attractive to use the familiar advantages of each material. With prepatternig of Si substrate high quality InP layers were realized. Crystal defects can be avoided by using a superlattice structure.

References

[1] S.Neumann, A.Bakin, P. Velling, W.Prost, H.Wehmann, A.Schlachetzki, F.J.Tegude, “Growth of III/V Resonant Tunneling Diode on Si Substrate”, J. Chrystal Growth 248 (2003) 380-383.

[2] A.Bakin, D. Piester, I. Behrens, H.-H. Wehmann, E. Peiner, A. Ivanov, D. Fehly, A.Schlachetzki., “Growth of InP Layers on Nanometer-Scale Patterned Si Substrates”, Journal of Crystal Growth & Design, vol. 3, nr. 1, 2003, 89-93.

[3] H. H. Wehmann, “Fehlangepasste Epitaxie von III/V-Halbleitern”, Shaker Verlag, Berichte aus der Halbleitertechnik, Aachen 2000


4.1.8 Growth and Characterisation of III-V Device Layers on Si Substrates

Student A. Che Mofor Supervisor V. Khorenko

Introduction The successful combination of high device density, high frequency suitability and relatively low cost has secured the silicon CMOS a dominant role in the microelectronic market in the past years. Unfortunately, the physical properties of silicon do not allow optoelectronic applications. By virtue of their physical properties and hence fundamental advantages like high output power and low noise, III-V semiconductors have proven substantial results in optoelectronics. An effective integration of III-V based and Si based devices at moderate cost is therefore very promising. Such combinations shall not only be useful in advanced information transfer, but also in optical interconnections within a microelectronic chip. Besides hybrid techniques, monolithic integration through heteroepitaxy of III-V semiconductors on silicon substrates is recently being intensively investigated. In our case, InP-on-Si with 8% lattice misfit is prepared as quasi substrate using MOVPE at Braunschweig University of Technology. These quasi substrates are characterised by two main defect types; twin lamellae and point defects with densities of about 103 cm-1 and 108 cm-

2 respectively. They exhibit a very undulating topography and have surface roughness values from 2.3 nm to 6.1 nm (for a standard 10x10 µm2 scan area) (fig 1a). These properties make the realisation of high quality III-V layers for (quantum) electronic and optoelectronic applications difficult. Some growth techniques ought to be sought for quality improvement of the start layer and for the growth of high quality device layers.

Approach and results In order to improve the quality of the InP-on-Si quasi substrates, strain-compensated InAlAs/InGaAs superlattice (SSL), low temperature InAlAs buffer (LT buffer) and a combination of the InAlAs buffer with SSL and InP/InGaAs superlattice (SL) were examined. Apart from the InP/InGaAs SL for which an AIXTRON Metal-Organic Vapour Phase Epitaxy (MOVPE) machine was used, a Varian GEN II Molecular Beam Epitaxy (MBE) machine was employed for all other growth experiments. The continuous introduction and compensation of strain is known to reduce defects [1]. In the case of SSL, a reference growth was carried out on conventional InP substrate before growth on InP-on-Si. Using 20 periods SSL, each time increasing and compensating the strain (±1,4 -± 3%) while reducing the layer thickness and maintaining the growth temperature and V/III ration at 460 °C and 16 respectively, a general increase in surface roughness was observed from Atomic Force Microscopy (AFM) measurements, but a correspondence in X-Ray diffractometry (XRD) (004) reflections for the reference and the experiment was noted (fig. 1b). The approach with the LT InAlAs buffer aims at giving the group III atoms (In and Al) just sufficient energy at a sufficiently high mobility, so that they find energetically stable positions assumable at the lower areas of the substrate surface [2]. A layer thickness of 200 nm was arbitrarily chosen and growth experiments were carried out with different growth parameters. For a


heater temperature of 425 °C (335 °C on growth surface) at growth rate 1.1 µm/h and V/III ratio of 2.5, both 3D and 2D growth occurred with a concentration of 3D structures in the order of 3x107 cm-2 . The growth parameters were altered in order to avoid 3D growth. The best result was obtained at a temperature of 450 °C, growth rate of 0.5 µm/h and V/III ratio of 6 (fig. 1d). This implies a 40% improvement in the surface roughness (from 3.2 nm to 1.9 nm) and an almost complete suppression of lamellae. The XRD curve (fig. 1c-d)shows that the LT InAlAs layer is lattice matched onto the InP.

-4000 -2000 0 2000 4000

2Theta (arcsec)

SSL on InP/Si

SSL on InP

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101

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104

FWHM = 86.4 arcsec

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nsity

[a.u

.]

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103

200 nm In0.52Al0.48As LT buffer on InP/Si; Tg=475° C, V/III ratio=4, Vgrowth=1 um/h

Inte

nsity

[a.u

.]

2Theta (arcsec)-1000 -500 0 500 1000

101

102

103

200 nm In0.52Al0-48As LT buffer on InP/Si; Tg=450° C, V/III ratio=6,Vgrowth=0.5um/h

2Theta (arcsec)

40nm 40nm70nm 80nm

0

10

µm

0

10

µm

0

10µm

0

10µm

Fig. 1 AFM photographs and corresponding XRD curves for InP-on-Si substrate (a), InAlAs/InGaAs SSL (b), LT InAlAs buffer grown at 475 °C (c), LT-InAlAs buffer grown at 450 °C (d)

In an attempt to further improve the quality of the start surface, 10 periods of 2.5nm-InAlAs/2.5nm-InGaAs SSL with ±2% strain were deposited on the LT InAlAs buffer. The AFM analysis showed a reappearance of some defects and no significant improvement in surface roughness. The XRD curve showed less correspondence with the model. In another trial, the LT InAlAs buffer was grown using the MBE and protected with an As cap. The sample was transferred into the MOVPE reactor where 20 periods of 5nm-InP/5nm-InGaAs SL were deposited at 600 °C. Here, a surface roughness of 7.4 nm was obtained and the XRD curve showed significant differences from the model. An analysis of the results at this stage showed that the LT InAlAs buffer was most effective. The InAlAs/InGaAs SSL and the SSL-LT buffer combination were left for further optimisation. The growth of device layers for the heterostructure field-effect transistor (HFET) and the resonant tunnelling diode on the LT InAlAs buffer was considered for further investigation.

For the growth of device layers, standard layer systems for the devices grown on conventional InP were used in order to facilitate characterisation. In the case of the HFET, the the same InAlAs(donor)/InGaAs(channel) system was used, the only difference being a 15 °C lower growth (heater) temperature (565 °C) due to the higher thermal conductivity of Si. The growth rate and the V/III ratio were maintained at 1.3 µm/h and 24 respectively. An AFM analysis (fig. 2a) of the sample surface after growth shows that the lamellae reappeared after the growth of device layers.


The rms surface roughness for a 7x7 µm2 scan area increased from 2.3 nm prior to growth to 3.2 nm after growth. A comparison of the XRD curves for the reference on InP and experiment on InP-on-Si is presented in fig. 2b. To further investigate the quality of the HFET layers, the grown layers system was processed and the HFETs were characterised with respect to the quality of the Gate contact (Schottky behaviour), transfer characteristics, and output characteristics (fig.2c-d). It was observed that the Schottky contact was very good. An analysis of the transfer characteristic shows that no pinch-off voltage exists. However, a normalised transconductance value of about 300 mS/mm was deduced. For the bias range (-3 V ≤ VGS ≤ 1 V), current gain was noticed only for 0 V ≤ VGS ≤ 1 V.

-1500 -1000 -500 0 500 1000 1500100

101

102

103

104

HFET on InP/Si

HFET on InP

Inte

nsity

[a.u

.]

2Theta (arcsec)

0 7µm -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.020

21

22

23

24

25

26

27

28

no pinch-off

VDS=1.5 VI D

[mA

]

VGS [V]0.0 0.5 1.0 1.5 2.0

0

10

20

30

VGS = 0 V

VGS = 1 V

I D [m

A]

VDS [V]

a) b) c) d)

Fig. 2 Characterization of HFET; AFM photograph (a) XRD curves for reference and experiment (b) , transfer characteristic (c) and output characteristic (d)

-4000 -2000 0 2000 4000100

101

102

103

104

RTD on InP/Si

RTD on InP

Inte

nsity

[a.u

.]

2Theta (arcsec)0 10µm

a) b)

Fig. 3 AFM photograph (a) and XRD curve (b) of a grown RTD structure

For the resonant tunnelling diode (RTD), an InAs(barrier)/InGaAs(well) layer system was employed. The growth temperature (520 °C) was the same as for the reference, since RTDs grown even at 550 °C on normal InP showed no differences in their XRD curves. Both the growth rate and the V/III ratio were maintained at 1.1 µm/h and 14 respectively. An analysis of the surface after growth showed a reappearance of the lamellae (fig. 3a). The rms roughness value for a 10x10 µm2 scan increased from 2.3 nm before growth to 4.6 nm after growth. A comparison of the XRD curves for the reference and experiment showed a broader main peak for the InP-on-Si as expected and sub

300mS/mm


peaks of lower resolution. However, the general course of the XRD curves were identical (fig 3b). Because the available masks were not optimal for the grown RTD structure, the RTDs were not processed.

Conclusion For quality improvement of the InP-on-Si substrate, the low temperature InAlAs buffer has proven to be effective. The other methods (strained-layer superlative and the combination of both need to be optimised.

The difficulty to obtain pinch-off for the transistor is attributed to parallel conductivity resulting from the InP layer on Si, which was proven to be highly doped The properties of the realised HFETs reveal that the monolithic integration of III-V based devices with Si based devices is feasible. Simple devices like RTDs ,which need only ohmic contacts, and MSM-photodiodes which need Schottky contacts can also be realised. However, the growth of device layers should be carried out at relatively low temperatures to minimise the growth of lamellae. Also, the crystal quality and the semi-isolating property of the InP layer should be improved.

References: [1] M. Tachikawa, T. Yamada, T Sasaki, H. Mori, Jpn. J. Appl. Phys. 34, L657 (1995). [2] E. S. Semenova, A. E. Zhukov, A. P. Vasil’ev, S. S. Mikhrin, A. R. Kovsh, V. M. Ustinov, Yu. G.

Musikhin, S. A. Blokhin, A. G. Gladyshev, N. N. Ledenstov; Semiconductors Vol. 37 No. 9 2003.


4.1.9 Application of Reflectance Spectroscopy in Molecular Beam Epitaxy for in-situ Surface Characterisation

Student : A. Che Mofor Supervisor : V. Khorenko

Introduction The performance of micro- and optoelectronic devices depends to a great extent on epitaxial growth, prior to which substrate cleaning is necessary. The most common source of impurity is the unavoidable or intentional surface oxidation of the substrate. The oxide layer on the substrate is only a few nm thick, but ensuring that it is completely desorbed is not trivial. Similarly, it is important to monitor the growth process, so that the quality of subsequently grown semiconductor systems can be improved if a reference growth process is available. Both oxide desorption and epitaxial growth lead to continuous change in the optical properties (e.g reflectance) of the surface. Reflectance spectroscopy (RS) was thus envisaged as a suitable in-situ diagnostic technique to monitor such epitaxy-related processes, in an attempt to optimise the oxide desorption process and facilitate real-time error recognition during growth.

Approach Assuming continuity and that no surface charges and currents arise at the interface when light travels from vacuum (refractive index n=1) to semiconductor of refractive index ( ) ( )n n ikω ω+=

%,

where n and k are the real refractive index and extinction coefficient of the semiconductor respectively, the intensity of the reflected light at normal incidence can be deduced to be

[ ][ ]

2 2

2 2

( ) 1 ( )( ) 1 ( )

ref totn k

I In kω ω

ω ω

− +=

+ + (1)

Iref reduces as surface roughness increases because of scattering at the point of incidence.

The set-up in fig. 1 was used to channel light of wavelength 482.53 1046.13nm nmλ≤ ≤ from a tungsten halogen lamp onto the semiconductor surface at normal incidence (full rays). The reflected light from the semiconductor surface, carrying structural information about the surface, was channelled through the same path (broken rays) on to the CCD array of an optical spectrometer PC PC101135 which works in the range530 1100nm nmλ≤ ≤ and is available as a PC-card on a computer motherboard. For coherence in measurements, the set up was calibrated (and correction for dark made). Experimental observations of the oxide desorption and growth process were carried out for GaAs and InP substrates, and for GaAs/AlxGa1-xAs (x=0, 0.25, 0.5, 0.75, 1.0) respectively. The substrates were heated from 300 °C (heater temperature) to 740 °C and 730 °C respectively and cooled down to 300 °C. The reflected signal (wavelength spectrum) was automatically saved every 60 seconds and the entire set of data analysed afterwards.


a) b)

Fig.1 RS set-up. Light from light source (full rays) is transmitted through 5 glass fibers, converged by convex lens and reflected onto substrate surface by reflecting mirror. Reflected light (broken rays) follows the same path and is collected by 1 fiberand channeled to spectrometer available as PC-card.

300 400 500 600 700 800

1700

1800

1900

2000

cooling

heating

complete deoxidationTsubstr=600 °C

Ref

lect

ance

(cou

nts)

Heater temperature (°C)300 400 500 600 700

1200

1400

1600

1800

2000cooling

heating

+ As

-ove

rpre

ssur

e

most oxide desorption formation of InAs

crystalline InAs

amorphous As

no As-overpressure

Ref

lect

ance

(cou

nts)

Heater temperature (°C)

Fig. 2 Oxide desorption from a) GaAs b) InP substrate. In a), besides measurement error at 500 °C, fall in reflectance above 550 °C, fluctuation in reflectance at 740 °C and continuous fall during cooling. In b), significant increase in reflectance above 600 °C. High reflectance(InAs on surface) during cooling without As-flow and sharp fall in reflectance below 600 °C (amorphous As) when cooling with As-flow.

Results Oxide desorption: After a general analysis of the entire wavelength spectrum, more critical analysis was done on a relatively sensitive wavelength (810.05 nm for GaAs and 800.41 for InP) taken from measurement data. Fig. 2 shows the heating and cooling processes for a) GaAs and b) InP.

combined fiber (6 in bundle) source and detector convex lens

MBE growth chamber semiconductor material

reflecting mirror

PC-d

halogen lamp

v1

v2

u

d


Refering to models1 based on AFM, AES and RHEED, suggesting that the GaAs-oxide desorption process starts with the desorption of the less stable As-oxides as early as 350 °C, followed by the more stable Ga-oxides and considering the GaAs-oxide desorption temperature in the literature3 (above 580 °C), the fall in reflectance above 550 °C (fig. 2a) was attributed to the desorption of As-oxides, thus increasing surface roughness and hence reducing the intensity of the reflected signal. In an earlier experiment on clean GaAs substrate, it was deduced that temperature has little or no effect on reflectance in the set-up. It follows that the continuous fall in reflectance is attributed to the desorption of Ga-oxides. De-oxidation ends at the point of intersection between the heating and cooling curves.

Similar research [2] shows that the InP-oxide is complex as it consists of about five different oxide types in different proportions. However, complete desorption can be expected at temperatures in the order of (490 +20) °C. The use of As-overpressure leads to the formation of crystalline InAs which can become critical if its thickness gets too large. The significant increase in reflectance (fig. 2b) and even at the beginning of the cooling process is attributed to the formation of crystalline InAs. Eq. (1) proves that InAs reflects more than InP. This was further confimed by the continuously high refelectance during cooling without As-overpressure and sharp fall when cooling with As-overpressure as a result of the formation of amorphous As.

Fig. 3 Fingerprints for GaAs/AlxGa1-xAs.

Epitaxial growth: A multilayer growth process was carried out for GaAs/AlxGa1-xAs (x=0, 0.25, 0.5, 0.75, 1.0). The process lasted 6850 seconds and is represented as a function of wavelength (in nm) against growth time (in seconds) as shown in fig. 3.

From fig. 3, the different layers could be distinguished. The entire growth process was represented for two wavelengths λ= 816.62 nm and 580.17 nm, leading to Fabry-Perot oscillations as indicated in fig. 4. Growth rates and layer thicknesses were calculated from the oscillations. Some calculated values differ from the expected values by more than 20%, whereas, for some layers, the difference was below 5%. The large differences between expected and calculated values were attributed to the

0 1000 2000 3000 4000 5000 6000500

600

700

800

900

1000

Intensity (counts)

GaA

s

Al .2

5Ga .7

5As

GaA

s

GaA

s

GaA

s

AlA

s

GaA

s

Exce

ssA

s

Growth time (seconds)

Wav

elen

gth

(nm

)

2000 -- 22001800 -- 20001600 -- 18001400 -- 16001200 -- 14001000 -- 1200800.0 -- 1000600.0 -- 800.0400.0 -- 600.0200.0 -- 400.00 -- 200.0-200.0 -- 0A

l .50G

a .50A

s

Al .7

5Ga .2

5As

816.62

580.17

0 1000 2000 3000 4000 5000 6000500

600

700

800

900

1000

Intensity (counts)

GaA

s

Al .2

5Ga .7

5As

GaA

s

GaA

s

GaA

s

AlA

s

GaA

s

Exce

ssA

s


Wav

elen

gth

(nm

)

2000 -- 22001800 -- 20001600 -- 18001400 -- 16001200 -- 14001000 -- 1200800.0 -- 1000600.0 -- 800.0400.0 -- 600.0200.0 -- 400.00 -- 200.0-200.0 -- 0A

l .50G

a .50A

s

Al .7

5Ga .2

5As

0 1000 2000 3000 4000 5000 6000500

600

700

800

900

1000

Intensity (counts)

GaA

s

Al .2

5Ga .7

5As

Al .2

5Ga .7

5As

GaA

s

GaA

s

GaA

s

AlA

s

GaA

s

Exce

ssA

s


Wav

elen

gth

(nm

)

2000 -- 22001800 -- 20001600 -- 18001400 -- 16001200 -- 14001000 -- 1200800.0 -- 1000600.0 -- 800.0400.0 -- 600.0200.0 -- 400.00 -- 200.0-200.0 -- 0

2000 -- 22001800 -- 20001600 -- 18001400 -- 16001200 -- 14001000 -- 1200800.0 -- 1000600.0 -- 800.0400.0 -- 600.0200.0 -- 400.00 -- 200.0-200.0 -- 0A

l .50G

a .50A

sA

l .50G

a .50A

s

Al .7

5Ga .2

5As

Al .7

5Ga .2

5As

816.62

580.17


small number of measurements taken during the growth processes. Also, reflectance from underlying layers cannot be taken into account in RS.

Conclusion Oxide desorption from GaAs could clearly be observed and results comparable to those of Wafer technologies Ltd were obtained. For both InP and GaAs, the method does not reveal the quantity of desorbed oxide, most especially in the case of InP where the thin InAs layer is formed on undesorbed oxide. Clear finger prints were obtained for GaAs/AlxGa1-xAs (x=0, 0.25, 0.5, 0.75, 1.0), however, the method is not very sensitive to small changes in mixture ratio.

0 1000 2000 3000 4000 5000 6000200

400

600

800

1000

1200

1400

1600

1800

2000

Al-composition:100%75%50%25% 0%0%

GaAs/AlxGa1-xAs

Ref

lect

ance

(cou

nts)

Deposition time (s)

Fig. 4 Fabry-Perot oscillations for AlxGa1-xAs measured at 816.62 nm

References [1] A. Guillén-Cervantes, Z. Rivera-Alvarez, M-López-López, E. López-Luna, H. Calderón; „GaAs (100)

surface oxides desorption mechanisms studied by AFM, AES and RHEED“ [2] M.-P. Besland, P. Louis, Y. Robach, J. Joseph,G. Hollinger, D. Gallet, P.Viktorovitch; „Growth of

passivating UV/Ozone oxides on InP. Correlation between chemical composition and interfacial electrical properties“, Applied Surface Science 56-58 (1992) 846-854.

[3] T. Van Buuren, M. K. Athwal, K. M. Colbow, J. A. Machenzie and T. Tiedj; „Oxide thickness effect and Surface roughening in the desorption of the oxide from GaAs“, Appl. Phys. Lett. Vol. 59. No. 4, 22 July 1991.


4.2 Device and Circuit Processing


4.2.1 Investigation of the Gate-Recess Processing Parameters of Heterojunction Field Effect Transistors

Student: A. Poloczek Supervisor: J. Degenhardt

Introduction

The gate-recess is a very important step during the processing of heterojunction field effect transistors (HFET). The depth of the gate-recess and consequently the distance between the center of the channel and the gate electrode substantially influences the threshold voltage UT of the transistor. Thus, the later can be used as a measure for the etching depth. Using a non-selective acid-mixture the threshold voltage can be controlled by the etching time. Therefore, a deep understanding of the etching mechanisms and the influence of the different processing parameters on the etching result is necessary.

Etching theory

An acid mixture based on phosphoric acid was used in this work (H3PO4:H2O2:H2O; molecular concentration: 12.75:0.20:100). The selectivity of this acid fluid on a InAlAs\InGaAs semiconductor stack is approximately 1.5.

The phosphoric acid dissociates in three levels when added into H2O (H3PO4→H2PO4-→HPO42-→PO43-). The accessory standard chemical potentials point to a very weak concentration of the second and the third splitting level so that regarding to the etching mechanism they can be neglected. The hydrogen peroxide causes an oxidation of the semiconductor. Thus, the semiconductor connects with the dihydrogen phosphates and severs.

The speed of the heterogeneus etching reaction is determined either by the reaction velocity with the semiconductor or by the diffusion coefficient of the reaction components and the reaction products or both, depending on the slowest part.

Investigated processing parameters

The pre-treatment of a sample is an important processing parameter. It decides about a total mask of a sample related with no etching of the semiconductor on the one hand and the complete transfer of the structures given by the lithography mask into the semiconductor on the other hand. Investigated pre-treatment chemicals are in water soluted propanol or mucasol (tenside based cleaner) to improve the water adhesion of the sample surface which cause an excellent starting condition for the hydrochloric acid HCL:H2O (1:10). The hydrochloric acid is important to remove the top oxide layer preparing the sample for the etching process.


Fig. 1 Micrograph images of an etched sample without pre-treatment (left) and a etched sample pre-treated with IP:H2O (1:10; 10 s), deionisated water dip (10 s) and HCl:H2O (1:10; 10 s) (right)

Fig. 1 demonstrates the difference of etching results using a pre-treatment of a sample. The left picture shows one etched structure although there were many more given by the photo resist. On the right all structures were transfered from the photo resist to the semiconductor. The second investigated processing parameter is the stirring frequency of the magnetic stir bar in the beaker during the etching periode.

Fig. 2 Dependence on etching rate and stirring frequency for two different temperatures (5°C left and 21°C right) of the etching fluid with error bars

Fig. 2 does not show a clear dependence of the etch reaction on the stirring frequency including errorbars reflecting the measurement error. Consequently, the stirring frequency is a non-critical


processing parameter. However, it should be tuned different from zero to ensure a constant temperature distribution in the beaker.

Furthermore, the dependence on the temperature of the acid fluid and the etching rate was tested.

Fig. 3 Etching rate as function of the temperature for InAlAs and InGaAs with error bars

The etch rate increases exponentially with the temperature for both materials. Chemical reactions, which rise their reaction speed with higher temperature can be characterised by the Arrhenius

equation:

The quantity WA depends on the limiting step of the heterogeneous etching reaction. With the help of the measured values shown in Fig.3 WA is calculated for InAlAs and InGaAs:

WA,InGaAs = 40 kJ/mol

WA,InAlAs = 41 kJ/mol

These results and the non-critical stirring frequency behaviour point to a heterogeneous reaction impeded by reaction speed.

TR

WA

eAk ⋅−

⋅=


Gate-recess

The results of the etching tests were applied to the gate-recess on a HFET. It was realised in the etching fluid with a temperature of 5°C and 21°C. The etching depth was fixed at 23 nm and the accessory etching time was calculated with the help of the interpolating curves at Fig.3. The completed transistors were finally characterised on their low frequency behaviour. The measured threshold voltage of the transistors processed at 21°C differ 0.1V from values based on a simple physical model. At a processing temperature of 5°C the difference was 0.19V. These results are satisfactory because of the high sensitivity between the gate-recess depth and the threshold voltage UT.

Conclusion

Three processing parameters of the gate-recess for an InAlAs/InGaAs/InP HFET were investigated in this work. The stirring, temperature and pre-cleaning was investigated. Only the later two influence the etching behaviour. This knowledge is used to get a fixed etching depth controlled by

etching time. Consequently the threshold voltage can be adjusted in a acceptable range using a phosphoric acid based etching fluid.


4.2.2 Statistical Exaltation of DC Transistor Parameters

Scientist: J. Degenhardt, G.Grah Technical Assistant: A. Osinski

Introduction

The development of complex circuits as reported in Chapter 4.3.13 depends very much on the yield of transistor functionality. The variation of technological parameters is essential for circuit development and is restricting the circuit designer to a fault-tolerant design. In most university environments, the focus on circuit design is on small scale circuits but with high skills on selected problems. Building of 'high integrated' circuits like a 1-to-16 (1-to-4) demultiplexer (DMUX) can be considered as semi-industrial, thus have to include quality control and inline process testing.

Our standard field effect transistor with a moderate 0.4 µm gate length will be used for the DMUX. Reliability tests and statistical parameter screening was performed to classify the technological capabilities. This first attempt will be later extended to a general inline test to ensure high yield.

Technology

D-HFET´s are by far more robust in process technology and electrical behavior than an E-HFET. Especially the reverse gate break-down voltage and pinch-off voltage depends very much on the quality of the gate recess and mainly determines the yield of transistor fabrication. D-HFET´s are a suitable choice in conjunction with the differential amplifier circuit design as used in the DMUX. The drawback of the negative pinch-off voltage for D-HFET´s will be eased by the differential switching transistors they do not need an extra bias voltage. Biasing of the gate will automatically adjust due to the current source transistor at the source branch of the differential transistors (see Fig. 1). Together with a medium size gate length of 0.4 µm, these transistors are fairly stable on process technology and offer sufficient high yield for the estimated de-multiplexer complexity.

Figure 2 shows the homogeneity of a statistic sample of 160 identical D-HFET on InP wafer. The transistor layout based on a 40 µm (2x20 m) wide gate with a 0.35 µm gate length (E-Beam written). The standard deviation for the pinch-off voltage was calculated to σ =10 mV based on a Gaussian distribution. The yield of 92 % for this sample is not yet sufficient for a DEMUX but further improvement in processing will meet the target.

A first layout which was realized under this technological requirements is shown in Fig. 2. Small feature sizes were defined by electron beam lithography, larger areas in particular the connection PADs and interconnects were processed by optical lithography. On both sides of the layout exist an input driver build of an input transistor, shifter diodes and a current source each. Two merged differential transistors building the centre of the circuit layout which is used as an output driver. The input line termination is 50 Ohms, according the measurement environment. The layout is used for DC measurements only and used unbuffered test lines for detailed measurements. The displayed field size is around 500 µm by 500 µm.


Fig. 1 The pinch off voltage of 160 D-HFET´s was classified and interval sorted (Wg=40 µm, Lg=0.35 µm).

Fig. 2 Fabricated differential amplifier with source-follower input and 50Ω


Summary

The reported layout is part of the inline test monitors for the fabrication process. A large amount of test lines and testing versatilities can be used as an obstacle to follow-up process parameter variation and is necessary for fail diagnostics. More comprehensive circuit and especially if there are designed for RF operation are in general not suitable for detailed testing of components and in sequence for testing bias points. Additional test lines will influence the circuit performance or impede the circuit for operation at all. Therefore, well defined test circuits are essential for a full documented quality control.


4.2.3 Current Gain Increase in Self-Aligned InGaAs/InP Heterostructure Bipolar Transistor using SiNx Passivation

Scientist: Z. Jin

Introduction

In recent years, InP-based HBTs have been widely studied for high-speed applications. In the HBT process, the passivation is a very important step. Silicon nitride (SiNx) or silicon dioxide (SiO2) dielectric films deposited by plasma-based technology have been intensively investigated for the purpose of the InP-based HBT passivation in recent years [1, 2]. But this technology suffers from degradation of current gain. It will be very attractive if the HBT performance can be improved by just SiNx or SiO2 passivation. In this work, we report a damage-free SiNx passivation of self-aligned InGaAs/InP HBT with compositionally graded base structure. This passivation results in the increase of the current gain and in the suppression of the perimeter-to-area ratio dependence.

Experiment

The HBT layers were grown by LP-MOVPE on semi-insulating (001) InP (Fe) substrate. The layer structure is shown in Tab. 1. The HBTs were fabricated by conventional wet chemical etching and optical contact lithography. The DC characteristics of the fabricated HBTs were measured by HP 4515B semiconductor parameter analyzer. The HBT samples were then covered with 100-nm-thick SiNx without any pre-treatment. For the SiNx deposition, a PlasmaLab System 90 ECR-PECVD from Oxford Instruments was used. Details about the facility were given in Ref. [3]. The temperature of the sample holder was maintained at 20 oC during the deposition. The microwave power was set to 180 W. 90 sccm silane (SiH4) diluted in helium (5%/95%) and 5 sccm nitrogen gases were used as sources. The chamber pressure was kept at 5 mTorr during the deposition process.

Layer Thickness (nm) Doping (cm-3) In composition

Cap n+-InGaAs 150 2×1019 0.53

Emitter n-InP 140 3×1017 -

Base p+-InGaAs 70 1.5×1019 0.49→0.60

Collector i-InGaAs 300 - 0.53

Subcollector n+-InGaAs 300 2×1019 0.53

InP substrate S. I.-InP (Fe) - -

Tab. 1 MOVPE grown layer structure used for HBT fabrication.


Fig. 1 shows the Gummel plots and current gain of the HBT with emitter area 2×10 µm2. As shown in Fig. 1(a), before passivation, the collector and base current ideality factors are 1.28 and 2.05, respectively. After 100 nm SiNx was deposited on the HBTs, the collector current decreases a little bit, resulting in the ideality factor of the collector current decreasing from 1.28 to 1.2. This indicates that the collector current ideality factor is not controlled by the surface recombination in our case. In


contrast, base current decreases in the whole measured range of VBE, especially, the reduction is more significant for the biases of VBE=0.2-0.7 V. This causes the ideality factor of the base current decreasing from 2.05 to 1.36. The current gains derived from the Gummel plots are shown in Fig. 1(b). After the SiNx passivation, the current gain increases, especially, at lower collector current. We got the maximum increase of 16 fold in the current gain at collector current density of 10 A/cm2. Typically when InGaAs/InP HBTs are passivated by SiNx and SiO2, the base current ideality factor increases and the current gain decreases drastically. In our case, the surface passivation drastically decreases the base current ideality factor. This indicates that the high base ideality factor is related to the surface effects. We assume that surface recombination and defects in extrinsic region give rise to the high base current ideality factor and the reduction is attributed to a reduction of surface state density and other surface leakage sources. The increase of the current gain confirms this.

0.0 0.2 0.4 0.6 0.81E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

0.01

(a)

n=1.36

n=2.05

n=1.20

n=1.28

IB

IC

Cu

rre

nt

(A)

VBE

1E-10 1E-8 1E-6 1E-4 0.01

1

10

100

(b)C

urr

en

t G

ain

Collector Current (A)

Fig. 1 The Gummel plots (a) and current gain (b) of the self-aligned HBT. The solid lines are for the HBT before SiNx passivation and the dash lines are for those after SiNx passivation. The emitter area is 2×10 µm2

To verify the passivation effects, we measure the current gains of several HBTs with various emitter width (WE) and/or emitter length (LE). The relationship between current gain β and emitter size can be expressed as [4]

++=

EEC

surfB

C

RI

LWJ

K

J

J 112

1 ,

β

where JC is the collector current density, JRI is the base current density in the intrinsic base region, KB,surf is the surface recombination current divided by the emitter periphery. Here we assume that the surface recombination current divided by the emitter periphery is independent on the crystal directions. Fig. 2 shows JC/β as a function of (1/WE+1/LE) for HBTs with various emitter widths at a


collector current density JC of 1×104 A/cm2. KB,surf can be determined from the slope of the experimental data. As seen from Fig. 2, the slope of the curve of HBTs indicates that the current gain depends on the perimeter-to-area ratio and that the surface recombination has effects on the device performances. But in comparison to AlGaAs/GaAs HBTs [4], the investigated HBTs have much smaller slope, indicating that InGaAs material has very low surface recombination velocity. The SiNx passivation causes a even further decrease of the slope, indicating KB,surf has a smaller value. This demonstrates that the perimeter-to-area ratio dependence is suppressed and that the surface recombination current is significantly reduced by our SiNx passivation process. This is consistent with the above discussion.

0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.230

40

50

60

70

80

90

1/LE+1W E (1/µ m)

Before SiN passivation

JC/

(

A/c

m2)

After SiN passivation

Fig. 2 Measured JC/β as a function of (1/WE+1/LE) for the unpassivated (solid squares) and passivated (open squares) HBTs. WE varies for 1, 2 to 3 µm and LE remains at 10 µm. These data are taken at JC=1×104 A/cm2.

Acknowledgement

Thanks to M. Haase , F. Otten, T. Reimann, and S. Neumann for helpful discussions.

References: [1] Wang, H., Ng, G. I., Yang, H., and Radhakrishnan, K.: ‘Studies on the degradation of InP/InGaAs/InP

double heterojunction bipolar transistors induced by silicon nitride passivation’, Jpn. J. Appl. Phys., 2002, 41, pp. 1059-1061.

[2] Kikawa, T., Takatani, S., Masuda, H., and Tanoue, T., ‘Passivation of InP-based heterostructure bipolar transistors in relation to surface fermi level’, Jpn. J. Appl. Phys., 1999, 38, pp. 1195-1199.

[3] iersch, A., Heedt, C., Schneiders, S., Tilders, R., Buchali, F., Kuebart, W., Prost, W., and Tegude, F. J., ‘Room-temperature deposition of SiNx using ECR-PECVD for III/V semiconductor microelectronics in lift-off technique’, Journal of Non-Crystalline Solids, 1995, 187, pp. 334-339.

[4] Hayama, N., and Honjo, K., ‘Emitter size effect on current gain in fully self-aligned AlGaAs/ GaAs HBT’s with AlGaAs surface passivation layer’, IEEE Electron Device Lett., 1990, 11, pp. 338-340.


4.2.4 Effects of (NH4)2S Passivation on the Performance of Graded-base InGaAs/InP HBTs

Scientist: Z. Jin

Introduction

InGaAs/InP HBTs have been widely investigated for the application in the high-speed electronic devices. Recently, (NH4)2S solution was used to the InGaAs/InP HBT passivation [1]. The current gain was found to be increased by the passivation, especially at small collector current. While the performance was degraded after the passivated HBTs were exposed in the air. But the mechanism of the degradation has not been well understood. The purpose of this letter is twofold: passivation of the graded base InGaAs/InP HBTs by (NH4)2S and the investigation of the degradation of the base-emitter and base-collector junction by the Gummel plots in forward and reverse modes. The current gain was also found to be independent on emitter size after passivation.

Experiment

The heterostructure was grown by LP-MOVPE on (001) semi-insulating (001) InP (Fe) substrates in the following sequence: 300 nm Si-doped (2×1019 cm-3) In0.53Ga0.47As, 140 nm Si-doped (3×1017 cm-3) InP, 70 nm C-doped (1.5×1019 cm-3) InxGa1-xAs (0.49≤x≤0.60), 300 nm unintentionally doped In0.53Ga0.47As, and 300 nm Si-doped (2×1019 cm-3) In0.53Ga0.47As. The HBTs were fabricated by conventional wet chemical etching and optical contact lithography. The (NH4)2S solution supplied by Merck KGaA company was used for the passivation. The HBTs were soaked in the solution for 2 minutes at room temperature. The samples were cleaned by propanol and acetone solvents each for one minute, respectively. They were finally blown dry by nitrogen gas. The DC characteristics of the HBTs were measured by HP 4515B semiconductor parameter analyzer.


Fig. 1 shows the Gummel plots and current gains of the HBTs before and after passivation, together with the air exposed one. After the passivation, both the collector current and base current decrease compared to those of the unpassivated ones. But the reduction of the base current is much more significant than that of the collector current, especially, at medium current region. The significant reduction of the base current is attributed to the removal of the native oxide layer and formation of ordered Ga-S-Ga and In-S-In bridge bonds [1]. This indicates the success of our passivation. When the passivated HBT was exposed to air for 10 days, the base current increased drastically and even much larger than that before passivation. This indicates that the sulfur-passivated surface is not stable in the air. Even more surface recombination centers were introduced after passivation. This is indicated by the larger base current. As shown in Fig. 1(b), the current gain was increased by the sulfur passivation, especially, at small collector current. The air-exposed HBT has even lower current gain than the unpassivated one.

In a reverse mode Gummel plot, the electrons are injected from the collector into the base and emitter through the base-collector junction. Thus the reverse Gummel plot reflects the base-collector


junction properties. Fig. 2 shows the reverse Gummel plots of the HBT before and after passivation, together with the air-exposed one. The base current has an ideality factor of 1.31. After passivation, the ideality factor decreases to 1.06. This indicates that the sulfur passivation also plays an important role in the improvement of performance of the base-collector junction. The air-exposed HBT has an ideality factor of 1.16, which is smaller than unpassivated one and is larger than the passivated one. The change in the emitter current shows the similar trend. If we check the forward Gummel plots in Fig. 1(a), the base and collector currents for the air-exposed HBT are larger than those for the unpassivated and passivated ones. This indicates that the degradations of the base-emitter and base-collector junctions are different.

0.0 0.2 0.4 0.6 0.8 1.010-12

10-10

10-8

10-6

10-4

10-2

(a) IB

IC

Fresh HBT

S passivation

10 days later

I B,

I C (

A)

VBE (V)10-11 10-9 10-7 10-5 10-31

10

100(b)

Cu

rre

nt

ga

in

IC (A)

Fig. 1 The Gummel plots and corresponding current gain of the HBT before and after passivation, together with that exposed to air for 10 days. The emitter area is 3×10 µm2.

0.0 0.1 0.2 0.3 0.4 0.5 0.610-12

10-10

10-8

10-6

10-4

10-2

n=1.12

n=1.25n=1.06

n=1.16

n=1.31

IE

IB Fresh HBT

S passivation

10 day later

I B,

I E (

A)

VBC (V)

Fig. 2 The Gummel plots in reverse mode for the HBT before and after passivation. The emitter area is 3×10 µm2.


We now discuss the transport process in the forward and reverse modes. Figure 3 shows the diagram of the configurations of the forward and reverse Gummel plots. In the forward mode, the base-emitter junction is forward-biased and the base-collector junction is shorted. The excess carrier density is very high near the base-emitter junction, while it is the equilibrium value at the base-collector junction side. The base contacts are located outside the base-emitter junction, as shown in Fig. 3(a). The base current includes the space charge recombination, the bulk recombination in the base region, the surface recombination and the interface recombination under the base contact. For a nonself-aligned HBT, because the distance between the emitter and base contact is large and the excess carrier density there is negligible, we can omit the interface recombination under the base contact. In the forward mode, the large diode current is essentially the collector current that flows from the forward-biased emitter-base junction to the collector. The surface recombination current is part of the base current, which is not added on top of the collector current. Therefore, in the forward mode, the amount of surface recombination is an important part of base current.

While in a reverse mode, the base-collector junction is forward-biased and the base-emitter junction is shorted. The excess carrier density is very high near the base-collector junction, while it is the equilibrium value at the base-emitter junction side. The extrinsic region located at the base side has lower excess carrier density. Because the surface recombination rate is proportional to the excess carrier density, the surface recombination between the emitter and base can be negligible in the reverse Gummel plot. Furthermore, the contacts are in the area above the base-collector junction, as shown in Fig. 3(b). Thus the surface recombination in the forward mode changes into the base-collector interface recombination in the reverse mode.

The interface recombination velocity is very small and can be neglected. Therefore in the reverse mode, the surface recombination in the base extrinsic region does not contribute to the base current and only the contribution of the sidewall and the components in the intrinsic and extrinsic base regions is relevant. The base current of the air exposed HBT is larger than that of the passivated one and smaller than that of the unpassivated one in the reverse mode, as shown in Fig. 2. We believe that this change is due to the increase of the surface recombination rate on the base-collector junction sidewall. The passivated surface can be oxidized in the air. The oxides are known to produce non-radiative recombination centers. In contras, the air exposed HBT has largest base current in the forward mode. One possible reason is the increase of the excess carrier density near the emitter mesa sidewall and near the base surface for the air-exposed HBT.


Fig. 3 The diagrams of the HBT in the forward mode (a) and the HBT in the reverse mode (b).

In a 3-dimensional picture of the conduction band diagram [2], the Fermi level pinning causes a surface electron channel at the base-emitter junction and a saddle point in the conduction band edge potential. The barrier causes, at low bias conditions, a narrow constricted region through which it is energetically favorable for the carriers to stream into the surface channel. This causes an enhanced increase of the excess carrier density near the surfaces of the emitter sidewall and extrinsic region and causes the increase of the surface recombination. Although the Fermi level shift may also cause the leakage channel at the base-collector junction sidewall in the reverse mode, the different behavior of the base currents between the forward and reverse modes may indicate the larger increase of the Fermi level shift of InP in the emitter sidewall compared to InGaAs material after air exposure. Another reason is that the increase of the recombination velocity of InP at the emitter sidewall is much larger that that of InGaAs material after air exposure.

References: [1] Driad R, Lu ZH, Charbonneau S, McKinnon WR, Laframboise S, Poole PJ, and McAlister SP, Appl.

Phys. Lett., 73, 1998pp. 665-667.

[2] Tiwari S, and Frank DJ, IEEE Trans. Electron Devices, 36 (1989) 2105.

Surface recombination

C

E

B

Surface recombination

E

B

C


4.2.5 Sulfur and Low Temperature SiNx Passivation of InGaAs/InP Heterostructure Bipolar Transistors

Scientist: Z. Jin

Introduction

Driad et al. [1] used (NH4)2Sx solution in the passivation of InGaAs/InP HBTs. InGaAs surface after sulfur treatment was found to be oxide-free. The current gain was improved remarkably. However, the treated surface is unstable. Silicon nitride (SiNx) passivation suffers from some limitations: such as degradation of current gain. To maintain the sulfur passivation effects, the passivated surface is typically covered with SiNx (or SiO2) [2, 3]. In this paper we investigate the combination of sulfur and SiNx passivations of self-aligned InGaAs/InP HBT with compositionally graded base structure. Our study showed that the current gain increased after the combination of S and SiNx passivation. The current gain can be further improved by annealing.

Experiment

The heterostructure was grown by LP-MOVPE on (001) semi-insulating (001) InP (Fe) substrates in the following sequence: 300 nm Si-doped (2×1019 cm-3) In0.53Ga0.47As, 140 nm Si-doped (3×1017 cm-3) InP, 70 nm C-doped (1.5×1019 cm-3) InxGa1-xAs (0.49≤x≤0.60), 300 nm unintentionally doped In0.53Ga0.47As, and 300 nm Si-doped (2×1019 cm-3) In0.53Ga0.47As. The HBTs were fabricated by conventional wet chemical etching and optical contact lithography. The (NH4)2Sx solution was prepared from commercial (NH4)2S solution (20 %) with excess pure sulfur. The concentration of (NH4)2Sx is about 3 %. The HBTs were soaked in this solution for 10 minutes at 40 oC. The samples were cleaned by propanal and acetone solvents. After the cleaning process, the sample was blown dry by nitrogen. Then the samples were transferred into an ECR-plasma enhanced CVD chamber. The HBTs were then covered with 100-nm-thick SiNx. For the SiN deposition, a PlasmaLab System 90 ECR-PECVD from Oxford Instruments was used. To check the thermal effects, we annealed HBTs at 300 oC for 5 minutes in a N ambient after SiNx deposition. The DC characteristics of the fabricated HBTs were measured by an HP 4515B semiconductor parameter analyzer.


Fig.1(a) shows the common-emitter I-V characteristics of the HBTs before and after S/SiN passivation. The characteristics of the HBT annealed after passivation is also shown in this figure. Before the passivation, the current gain larger than 100 was derived. Figure 1(b) shows that the offset voltage is 0.17 V. The S/SiNx passivation results in the increase of the collector current by 15 % at the same base current, indicating that the current gain increases by about 15 %. The offset voltage decreases to 0.15 V, which is smaller than that before passivation. The annealing causes the further collector current increases by 5 % compared with passivated HBT. As shown in Fig. 1(b), the offset voltage increases to 0.17 V, which is the same as that before passivation.


Fig. 1 The common-emitter I-V characteristics of HBTs studied (a) and the I-V characteristics of HBT near the offset voltage (b). The emitter area is 3×10 µm2.

Fig. 2 The Gummel plots (a) and corresponding current gain (b) of HBT. The HBT structure and the treatment are the same as those in Fig. 1.

Fig. 2 shows the Gummel plots and corresponding current gains of the HBTs before and after passivation. Before S/SiN passivation, the collector current increases much faster than the base current and they cross at base-emitter bias VBE=0.3 V, as shown in Fig. 2(a). After S/SiNx passivation, the base current decreases in the whole range of VBE compared with that before passivation. This indicates that the surface recombination is suppressed by the passivation. In contrast, the passivation results in the increase of collector current. Especially, at small applied voltage, the collector current is much larger than that before passivation. A similar phenomenon was also found in SiNx passivation of InP/InGaAs/InP double HBT and this is attributed to the leakage current of base-collector junction [4]. But the increase of the collector current at the small applied voltage is accompanied by the large increase of the base current. The increase of the base current is due to the increase of the leakage at the surface of the base-emitter junction. While in our case, the base current is smaller than that before passivation in the whole measured voltage. This indicates that the S/SiNx passivation affects the emitter-base diode and base-collector diode differently. The decrease of the base current indicates that the surface recombination is suppressed by the S/SiNx passivation. The S passivation typically decreases drastically the base current in InGaAs/InP HBTs by removing the native oxide layer and forming the In-S-In and Ga-S-Ga bonds [5]. The native oxide acts as non-radiative recombination center. But this surface is sensitive to the plasma conditions. Our results show that the room-temperature deposited SiNx is suitable for the over passivation of the S-treated surface. The annealing causes further decrease of base current, as shown in Fig. 2(a). It also causes the decrease of collector current. The collector current is even less than that before passivation. This indicates that the annealing process can effectively suppress the base-collector leakage current caused during S/SiNx passivation. The current gain increases after the passivation and annealing, as shown in Fig. 2(b). However, the behaviors of their increases are different. For S/SiNx passivated HBT without annealing, the current gain decreases with the decrease of the collector current at first, it increases after it passes its minimal value. The current gain has a valley at IC=10-8 A. If we check the Gummel plots, we find that the collector current is

0.0 0.5 1.0 1.50

2

4

6

8

10

12(a)

Unpassivated

Passivated

Annealed

IB=10 µ A/step

I C

(m

A)

VCE (V)0.10 0.15 0.20 0.25

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

Unpassivated

Passivated

Annealed

(b)

VCE (V)

0.0 0.2 0.4 0.6 0.810-12

10-10

10-8

10-6

10-4

10-2

Unpassivated

Passivated

Annealed

IB

IC

(a)

I (A

)

VBE (V)10-12 10-10 10-8 10-6 10-4 10-2

0.1

1

10

100

(b)

Unpassivated

Passivated

Annealed

Cu

rre

nt

ga

in

IC (A)


larger than that before passivation in this region. This is due to the leakage current of base-collector junction. The current gain of the HBT after annealing increases monotonously with the increase of the collector current. The current gain is much larger than that before passivation in the whole measured range. It is larger than that before annealing when IC>10-8 A, indicating that the annealing can further improve the current gain. This is consistent with the results of the common-emitter I-V characteristics, as shown in Fig. 1. It is notable that the peak of the current gain at the low collector current disappears, indicating the leakage current is suppressed by the annealing process.

Fig. 3 shows the I-V characteristics of base-collector junctions. The passivation and annealing do not affect the forward characteristics. While the reverse current increases drastically after the passivation, the annealing results in two-order decrease of the reverse current.

Fig. 3 The I-V characteristics of base-collector diodes in HBTs before and after passivation.

References:

[1] R. Driad, Z. H. Lu, S. Charbonneau. W. R. McKinnon, S. Laframboise, P. J. Poole, and S. P. McAlister, Appl. Phys. Lett. 73, 665 (1998).

[2] S. Shikata, and H. Hayashi, J. Appl. Phys., 70, 3721 (1991).

[3] U. Mohideen, W. S. Hobson, S. J. Perton, F. Ren, and R. E. Slusher, Appl. Phys. Lett., 64, 1911 (1994).

[4] H. Wang, G. I. Ng, H. Yang, and K. Radhakrishnan, Jpn. J. Appl. Phys., 41, 1059 (2002).

[5] R. Driad, S. Laframboise, Z. H. Lu, S. P. McAlister, and W. R. McKinnon, Solid-State Electronics, 43, 1445 (1999).

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.010-10

10-8

10-6

10-4

Unpassivated

Passivated

Annealed

I (A

)

VBC (V)


4.2.6 DC Characterization of a GaAsSb-Heterojunction Bipolar Transistor based on InP

Student: Ingo Regolin Supervisor: Stefan Neumann

Introduction

The compound semiconductor GaAsSb as a base layer opens up further improvements to the InP-based Double Heterojunction Bipolar Transistor. GaAsSb forms a type-II transition to InP. Thus, the employment of InP as a collector material is enabled and has the following advantages [1,2], as illustrated in Fig. 1:

- a high breakdown voltage because of the wide-bandgap collector material InP - a reduction of the offset voltage, because, due to the type II transition, no conduction band

barriers are formed. - compared to InGaAs base a higher valence band-offset ∆EC to InP emitter.

Fig. 1. shows a comparison of InP D-HBT bandstructure using a GaAsSb- and a InGaAs-base. A GaAsSb-base causes no barriers along the conduction band, which could block the current flow.

EC

EF

EV

EmitterEV∆

∆

ECBase

n p++ nid

D-HBT-GaAsSbD-HBT-InGaAs

E(x

)

x

Collector

Fig. 1 Band structure comparison of a npn D-HBT along with p++-InGaAs and p++-GaAsS -base layer


As a part of this study a GaAsSb-HBT, which was produced in the Solid-State Electronics Department for the first time, has been statistically characterised. Therefore, the collector current- as well as the breakdown voltage of this transistor was investigated. The suitability of ohmic contacts has also been examined. In addition, the influence of a sulphur-ammonia surface treatment was explored, as this technology has improved the performance of the InGaAs-based HBT [3]. In the following, the results of these investigations will be discussed and an outlook will be given.

Results

Although this technology process was carried out for the first time, the devices show good DC- as well as dynamic-characteristics. By means of the MOVPE-method an ideal base-collector transition was already produced. An ideally factor of about nC=1.05 was shown by small devices with an emitter area of 1x5 µm2, while the base-emitter transition still needs some improvement (nE=1.35). In addition the first devices exhibited some problems with the ohmic TiPtAu metal-contact to the p-GaAsSb base-layer, but new studies have already improved the behaviour of that contacts. The TiPtAu metal-contact to the n-InGaAs-layers exhibits a low resistance with values about 0.1 Ω – 0.2 Ω. Measured cut-off frequencies of about fT=100 GHz and fMAX=60 GHz, show reasonable high frequency characteristics. Nearly all devices exhibit breakdown voltages VCE,Br > 7 V due to the use of InP as collector material. If the transistor is operated at higher current densities, the component will no longer be usable in the whole voltage range. The maximum collector current densities were shown by smaller components with values about 1x105A/cm2. The measured devices show good offset-voltage values between 0.01 V and 0.04 V, because of the barrier-free conduction band. Smaller emitter area devices show a somewhat higher value of about 0.07 V. The transfer characteristics of GaAsSb based D-HBT are compared in Fig. 2 with InGaAs based S-HBT. In agreement with data from the Simon Fraser University the GaAsSb based D-HBT exhibit better turn-on characteristics attributed to the lacking conduction band spike at the emitter-base junction [4].

* Daten nach C.R. Bolognesi [4]

GaInAs-HBT *

GaAsSb HBT *

M1520: InGaAs

M2747: this work

Col

lect

or C

urre

nt

(A

/cm

2 )

1.00.80.60.40.20.0VBE /V

GaAsSb

InGaAs

1E-5

1E-3

1E-1

1E1

1E3

1E5

Fig. 2 Comparison of Emitter-Turn-On-Characteristics of InP HBT with InGaAs and GaAsSb base


The influence of a sulphur-ammonia surface treatment was evaluated in this study. Therefore the devices were first split and then dipped into 3 different solutions for 5 minutes.

a) (NH4)2 : H2O = 1 : 4 at T = 20°C b) (NH4)2 : H2O = 1 : 4.5 at T = 20°C c) (NH4)2 : H2O = 1 : 4.5 at T = 50°C

Only some devices, which were treated with the solution at 50°C showed an increased current gain. But this result could not be shown clearly, because at this course of treatment a large part of the previously measured devices were destroyed during the treatment. To show the increased current gain, Fig. 3 presents the output characteristic(a) as well as the Gummel-Plot(b) of an ammonia-treated HBT. The increased DC-gain could already be recognized in the output characteristic. Although the base-current was equal before and after the surface treatment, the measured collector-current increases. Also the increased DC-gain may be recognized in the Gummel Plot on the right because the difference between the collector- and base-current increased. This could be easily seen at the voltage area from 0 V – 0.55 V. There the base-current decreased after the treatment although the collector-current has the same values as before. At a voltage higher than 0.55 V the collector-current leaves the previous course, so that from this point the increased DC-gain becomes lower. This result was selected to show the maximum increased reinforcement and therefore does not reflect all results.

∆IB=5µA

before treatment after treatment

IC

IB

I C /

mA

I / A

UCE / V UBE / V

0

1

2

3

6420 0.4 0.6 0.81E-9

1E-7

1E-5

1E-3

a) b)

Fig. 3 Common-emitter characteristic, as well as Gummel-Plot of a 3x15 µm2 not-self-aligned HBT before and after the surface treatment

Devices which were treated at 20°C however showed an decreased breakdown voltage. This were shown by nearly all measured devices in the output characteristic, as well as in the diode diagram. This means, that the surface did not become passivated, but additional surface condition by the deposition of sulphur were produced, which causes a larger leak-current at the surface. It was not possible to eliminate the produced surface conditions by means of etching or to show an ageing effect. In the future the surface treatment should flow firmly into the technologic process, so that a verification of the results is eased. Also the sample surface should be sealed directly after the surface treatment, to avoid a temporal change of the effect. In comparison the produced transistor


already shows good results. Further the metal-semiconductor-contact to the p-GaAsSb base-layer as well as the surface treatment has to be improved, and the alloying of the TiPtAu metal contacts has no positive influence to the DC-characteristic.

References [1] Michael S. Chang; “Indium Phosphide npn Heterojunction Bipolar Transistor (HBT) : Project I +

Project II”, Proceedings for EECS 521, 2002.

[2] C. R. Bolognesi, N. Matine, M. W. Dvorak, X. G. Xu, J. Hu, S. P. Watkins; “Non-Blocking Collector InP/GaAs0,51Sb0,49/InP Double Heterojunktion Bipolar Transistors with a Staggered Lineup Base-Collector Junction”, IEEE ELECTRON DEVICE LETTERS, VOL. 20, NO. 4, APRIL 1999.

[3] R. Driad, Z. H. Lu, S. Charbonneau, W. R. McKinnon, S. Laframboise, P. J. Poole and S. P. McAlister; “Passivation of InGaAs surfaces and InGaAs/InP heterojunction bipolar transistors by sulfur treatment”, Appl. Phys. Lett., Vol 73, No. 5 3 August 1998

[4] C. R. Bolognesi; Compound Semiconductor Device Laboratory, http://css.sfu.ca/sites/cdsl/research.html


4.2.7 Comparison between InP/InGaAs- and InP/GaAsSb-DHBT

Scientists: J. Driesen, S. Topaloglu

Introduction

Main task of the project “InP-based Electronic Devices for +80 GBit/s” is to improve HBT performance to at least up to fT = 200 GHz, mainly for InP/GaAsSb-DHBT. Since also InP/InGaAs-HBT are developed (SHBT and DHBT), a comparison can be made between currently achieved results of transistors of both material systems.

In the subsequent sections, the dc and rf behaviour of transistors of both material systems is described. A comparison is made, and it leeds to some predictions for the future performance of InP/GaAsSb-DHBT. Finally, some problems are discussed and an outlook for upcoming devices is given.

DC Measurements

In fig. 1 and 2, the output characteristics of the three transistors are compared. The first two transistors are InP/InGaAs-DHBT. Both of them contain a composite collector structure to reduce the conduction band barrier on the base-collector side. One sample (M2870) additionally consists of a compositionally graded base while the other one (M2874) has none. In Fig. 1, the output characteristic of the transistor without grading can be seen, the other’s curves look the same, with higher values of IC respectively.

These transistors are compared with an InP/GaAsSb-DHBT. Since this material system has type-II heterojunctions without any barrier in the conduction band, no compositional grading has to be applied. This transistor is one of the first in this project, so more optimised structures will follow.

Fig. 1 Output characteristic of an InP/InGaAs-DHBT with composite collector (M2874); depicted is a 2x10 self-aligned devic, IB = 25µA / step, β=80, nBE=1.7, nBC=1.29

0 1 20

2

4

6

8

10

12

14

I C /

mA

VCE

/ V


In all three cases, transistors with a 2x10 µm² emitter with self-aligned bases have been compared, all with one emitter finger. Besides the output characteristics depicted here, additionally the gummel plots and further typical viewgraphs for the HBT have been measured.

As result of these measurements, the current gain B and the ideality factors of the diodes nBE and nBC can be deduced and then compared. As was expected for the InP/InGaAs-DHBT, the transistor with grading has a much higher gain as the other one (B = 360 and B = 80, respectively), due to the additional electric field in the base induced by the grading. The ideality factors are quite the same for both cases, and with nBE = 1.7 and nBC = 1.29 rather high values have been measured. The offset voltage for these transistors is comparably high (Voff = 0.2 V), and the turn-on slope is rather smooth. Nevertheless, these are acceptable values for these kind of transistors.

Fig. 2 Output characteristic of an InP/GaAsSb-DHBT (M2748); depicted is a 2x10 self-aligned device, IB = 75µA / step, β=360, nBE=1.22, nBC=1.09

Fig. 3 RF performance of all three transistors, depicted by fT as figure of merit

0 1 2 30

2

4

6

8

10

12

14

16

18

I C/ m

A

VCE

/ V

0

10

20

30

40

50

60

70

80

90

100

1E-03 1E-02 1E-01 1E+00 1E+01

Jc [mA/µm²]

fT [

GH

z]

GaAsSb, 1V

InGaAs, 1.5V

InGaAs, graded Base, 1.5V


In comparison, the InP/GaAsSb-DHBT has a lower gain of B = 35, but since the underlying structure has yet to be optimised, this is no real disadvantage. On the other hand, this HBT achieves lower ideality factors of nBC = 1.09 and nBE = 1.22 and a lower offset voltage of Voff < 0.1 V with a much steeper turn-on slope. Therefore, even in this early stage of the development a good performance is obtained.

RF Measurements

Subsequently, the s-parameters of all three transistor have been measured, and fT as figure of merit has been plotted in dependence of the current density JC. Fig. 3 depicts this comparison. The same transistors have been measured as for the dc measurements.

As it can be directly seen from the viewgraph, the InP/GaAsSb-DHBT shows the best performance of the three transistors. It has not only the highest peak value for fT but also reaches its highest peak at higher current densities. Since the measurement was made for a lower VBE in case of the InP/GaAsSb-DHBT, the performance should even be better for an equal voltage. The lower voltage has been chosen because of the lower offset voltage and steeper turn-on slope of this HBT in comparison to the InP/InGaAs-DHBT.

Additionally, first noise measurements have been made. Since there is no comparison available to the InP/InGaAs-DHBTs presented here, these are not described. Nevertheless, some promising results have been found, and comparable measurements will be made for the next devices.

Conclusions and Outlook

Despite the fact that neither the layer stack nor the layout of the InP/GaAsSb-DHBT have been optimised yet, it has already a promising performance with currently fT ≥ 100 GHz, and since this contains no de-embedding of any parasitic pad elements, even better performance is to be expected for the transistor itself.

The first versions of InP/GaAsSb-DHBT still have some challenges left to overcome. Compared with InP/InGaAs-DHBT with and without compositional grading, the gain of the InP/GaAsSb-DHBT could be higher, but even with these first non-optimised structures a low offset voltage, a steep turn-on of the output characteristics and high maximum frequencies fT and fmax at high current densities is achieved. And further investigations show that this type of HBT has a higher breakdown voltage, and the noise performance is also promising.

Several approaches for improving the devices have been developed meanwhile, and these will be introduced in the design for future versions of the HBT. Namely passivation and related treatments will contribute to the device performance, as well as a new technology for a base undercut, and dry etching ability, of course, that will be available in the near future. Therefore, by help of the developments that are pursued, HBT with better performance are expected soon.


4.2.8 On the Improvement of HBT Performance Provided by Lateral and Vertical Design Optimisation

Scientist: J. Driesen

Introduction

Most of the InP/GaAsSb-DHBT processed throughout the work within the project “InP-based Electronic Devices for +80 GBit/s” in the department have been made on the basis of existing layouts of former projects. Since the results have to be improved, a new mask set has been in the focus of development. The goal of the work described in this contribution is to obtain a rough estimation of how the device performance changes by vertically and laterally varying the standard transistor design.

Basic Parameters and Constraints

The calculations are based on the physical device behaviour as it is known from literature [1], [2], [3]. Starting point are the layer and layout descriptions of the device as well as a number of material parameters, e.g. band gap energy, permittivity of the different materials, conduction band energy, sheet and contact resistances of the materials, mobility, doping densities, and some more.

The estimation calculations concentrate mainly on the inner transistor. These do not take into ac-count homojunctions like the collector to sub-collector junction, and do not consider any electrical field if this is not included in the used formulas (e.g., the current crowding effect is considered in the calculation of the base resistance rBB). Therefore, that can be considered as a fast but rough estimation which cannot substitute for the physical device simulations. But since these calculations were only intended to give design optimisation hints, they are nevertheless useful for understanding the device.

Fig. 1 depicts the structure as it is considered in these calculations. Some of the parameters are denoted in the sketch. The program for the calculations has been developed in the Visual C++ environment, and it allows to calculate the device behaviour at one operating point as well as curve tracing, i.e. if one of the input device parameters such as base thickness or emitter length is varied.


Fig. 1 Description of the HBT and some of the parameters used for the calculations.

Results of the Estimation Calculations

Several investigations have been made, and some substantial curves as results are depicted in the following figures. First of all, the emitter design has been in the focus of the calculations. In fig. 2 and 3, the dependence of the maximum frequencies, i.e. the transit frequency fT and the maximum frequency of oscillation fmax, on the emitter dimensions is shown. For emitter width as well as for emitter length, mostly fmax is affected, so mainly this figure of merit may be improved by lateral scaling and layout design. For all investigations, the calculations start from one standard device, and only one of the parameters is varied. This standard device is in all cases a 2x10 µm² self-aligned transistor with 1 µm overhang of base over emitter. The figures show that especially decreasing the emitter width will improve fmax drastically. Regarding the length of the emitter, the ratio of width to length is important.

Fig. 2 Dependence of fT and fmax on width of emitter for two different base collector areas

Fig. 3 Dependence of fT and fmax on length of emitter for two different base collector areas.

0

50

100

150

200

250

300

350

400

450

500

0 5 10 15 20Le [µm]

f [G

Hz]

fT[GHz] - 0.5fmax[GHz] - 0.5fT[GHz]fmax[GHz]

0

200

400

600

800

1000

1200

0 1 2 3We[µm]

f [G

Hz]

fT[GHz] - 0.5

fmax[GHz] - 0.5

fT[GHz]

fmax[GHz]

Le, We dltb dltbc

dlte

decap

dedb

dc

dsc

Recon

2 Rbcon

Rsccon

Resem

Rscsem1

Rcsem

2 Rbsem 2 RbbCjc

Cje

Rscsem2Rksc, Rshsc, Ltsc


Secondly, the influence of the base-collector capacitance has been investigated. The above discussed viewgraphs also depict the curves for a thinner base area (0.5µm greater than emitter). As one can deduce from the graphs, the smaller base increases especially fmax. This due to a decreased capacitance of cjC.

Fig. 4 Dependence of fT and fmax on the thickness of the base

Fig. 5 Dependence of fT and fmax on the on the emitter doping density

Furthermore, the vertical and material related parameters have been analysed. In fig. 4 the dependence of fT and fmax on the base layer thickness is depicted. Since the layer thickness has an influence on the transit time τF, the directly related transit frequency fT improves. Due to the relationship between fmax and fT, also fmax is increased. On the other hand, increasing the base layer thickness reduces the small signal current gain β (not shown here). This even decreases furthermore with increasing base doping density. Therefore, a compromise for the thickness and doping has to be found at this point.

Finally, the influence of the emitter doping density can be seen from fig. 5. With increasing emitter doping fmax increases due to the decreasing emitter resistance. On the other hand, fT decreases since the depletion region on the emitter side is reduced, and therefore the junction capacitance cjE increases.

Conclusion and Outlook

The calculations made in this work were not intended as quantitative, physical simulations of the devices. They were based on the principle device behaviour relationships of mainly the inner transistor, and were used to illustrate the dependencies between the various device design parameters and the resulting device performance. The maximum frequencies have been investigated as figures of merit for the high frequency behaviour of the HBT.

The estimation underlines the principle that the lateral design of the HBT affects the maximum frequency of oscillation fmax much more than the transit frequency fT, while the latter is determined by the vertical structure and material parameters of the device. Since also dc purposes of the device, for instance current gain or bulk resistances, depend on these vertical design parameters, a good working compromise has to be found to improve both, dc and rf behaviour of the device.

0

50

100

150

200

250

300

0 20 40 60 80 100

db [nm]

f [G

Hz]

fT[GHz]

fmax[GHz]

0

20

40

60

80

100

120

140

160

10 100 1000Ne [1e17 1/ccm]

f [G

Hz]

fT[GHz]

fmax[GHz]


Several approaches have been found to achieve these improvements. The lateral design of the transistors will be optimised using a new mask set, to give just one example. This mask set will also facilitate a newly developed base undercut technology to reduce the feedback capacitance CBC and therefore improve the device’s rf performance.

Furthermore, it is advisable to have a closer look on the doping profile. And finally, the parasitic bulk resistances for all three terminals have to be reduced. In case especially of the base, this could be achieved by developing a regrowth process, for instance. In regard to the emitter, the design of T-shaped emitters has been proposed, despite the fact that this increases the base bulk resistance.

References: [1] Jiann S. Yuan

"SiGe, GaAs, and InP Heterojunction Bipolar Transistors“ Wiley Interscience Publication, John Wiley & Sons, Inc., New York ISBN 0-471-19746-7

[2] William Liu "Handbook of III-V Heterojunction Bipolar Transistors“ Wiley Interscience Publication, John Wiley & Sons, Inc., New York ISBN 0-471-24904-1

[3] M. Reisch "High-Frequency Bipolar Transistors“ Springer-Verlag, Berlin, Heidelberg, New York ISBN 3-540-67702-X


4.2.9 HBTs with Directly Contacted Emitters

Scientists: S. Topaloglu, J. Driesen

Introduction

To improve the performance of HBT and the layouts also in the outlook for use with circuits, it is necessary to scale down the HBT’s lateral dimensions. One step to realize this is to implement direct emitter contact and so; to remove the emitter dummy pads.

In the following sections further advantages and the implementation methods will be discussed. And these results will be presented.

Implementation Methods

Directly contacted emitters are important for thermal behaviour. In conventional emitters (emitters with dummy pads) dissipated heat in the emitter has to be conducted away over µ-bridges to dummy pads and this degrades the performance. In directly contacted emitter configuration, there will be the chance of taking away the heat much more efficiently. A simple and repeatable solution may be realized in the regular air bridge process step. In the normal airbridge process, after processing thr complete HBT, the wafer is covered with a photoresist and it is exposed to define the pads and the landing points for connections, and it is hard baked, and later on another photoresist is used to cover the wafer and to define the interconnection metals. At this point between these two photoersist steps, it is proposed to make an plasma ashing process just before the hard bake of the first photoresist layer. By the help of this, the resist covering the emitter will be ashed until it is free. The critical point here is to be careful with this ashing process because if it is done too much, there can be the probability of opening the base metal coverage as well and this will provoke a short circuit with emitter in the following metallization step.

Fig. 1 Photoresist thickness vs. rotation speed

1,46 1,33 1,24

3,14

2,22 2,1 3,5

y = -1.2ln(x) + 3.5

0 0.5

1 1.5 2

2.5 3

3.5 4

0 1 2 3 4 5 6 7 8

Rotation Speed /min (x1000)

Thic

kne

ss µ

m


To prevent this, the photoresist thickness and ashing parameters have been optimized. In figure1 photoresist thickness vs. rotation speed can be seen.

Fig. 2 SEM pictures of the HBT just after the ashing process.

As it is clearly seen from the SEM picture in Fig.3, the emitter metal is free and interconnect metal can directly climb to the emitter without a dummy pad. Here is the final SEM picture of a complete HBT with directly contacted emitter.

Fig. 3 SEM pictures of complete HBT with directly contacted emitter.


On the other hand, during the researches with GaAsSb HBTs, it has been observed that after some time the processed HBTs are degrading because of the oxidation of base emitter diode and after a short dipping in the acid (this means cleaning the oxide layer), HBTs start functioning properly again. Taking into account this problem and the advantages of direct emitter contact, some solutions have been searched and it is identified that using durimide can be a good solution for that.

In principle processing of durimide is approximately the same as processing with photoresist. To implement this, the properties of durimide ( thickness with different speed of spin coating, with different mixture ratios, ashing rate with O2 Plasma) have been investigated. Just after the base metalisation, the wafer is covered with durimide and the active base emitter area is defined, and at this point the durimide is ashed ( with O2 plasma asher) until emitter is free or about to be free. Later on it has to be cured to convert this liquid phase to glass phase and have better and robust protection in the active base emitter area. In figure 4 the complete HBT with the Base emitter isolation with durimide and direct contact emitter can be seen.

Fig. 4 SEM pictures of complete HBT with directly contacted emitter with durimide.

Conclusions

Realization of directly contacted emitters gives the chance of having smaller area devices and better thermal behaviour. On the other hand by using this configuration better interconnection with less parasitic effects can be achieved as well. Finally, with durimide direct emitter contacting can be realized and at the same time the protection of sensitive base emitter area can be established.


4.2.10 Different Approaches for Integrating HBTs and EAMs

Scientists: T. Reimann, S. Neumann M. Schneider (Fachgebiet Optoelektronik, Univ. Duisburg-Essen) Technical Assistant: M. Haase

Introduction

Heterojunction bipolar transistors (HBTs) and electroabsorption waveguide modulators (EAMs) are two major parts of opto-electronic circuits for transmission as well as signal processing. III/V-semiconductors are especially suited for tuning to the desired operating wavelength while providing high carrier mobilities. To further increase the flexibility in circuit design and for cost reduction one may integrate HBTs and EAMs monolithically onto a single substrate. There are different approaches for integrating HBTs and EAMs on InP. Camargo Silva et al. [1] grew the HBT-layers directly on top of the EAM-layer stack. Special care was taken of the pn-junction placement inside the modulator. A different approach results from over-growth techniques where the HBT is deposited and processed first while the EAM is regrown and manufactured thereafter [2]. A bandwidth around 30GHz could be achieved. These methods suffer from large layer stacks with substantial processing requirements. A different solution for integration is to create a layer stack where the layers for the waveguide are merged into the HBT-structure.

a) b)

Vin

Vm-

EAMHBT

Vin

HBT-EAM

VC

B (

V)

IC (A)

E=0

E≠0

c)

RL

IB

VCC

VCB

IC RL

VCC

Fig. 1 Comparison between the different approaches. a) common emitter HBT-driver and EAM as distinguished parts for concepts (1) and (2), b) merged HBT-EAM device with load resistor RL (3), c) switching characteristic of the setup according to b). Two bias-points are shown corresponding to different electric fields inside the waveguide.

Integration concept

In our approach we shift the waveguide into the collector region of the HBT (HBT-EAM). By variation of the base-collector voltage it is possible to modulate the electric field and therefore the optical absorption inside the collector via the Franz-Keldysh effect (FKE). This corresponds to a modulator with an integrated amplifier. The goal of this work is to get a better understanding of the capabilities of HBT-EAMs in comparison to other integration schemes. Thus three different variations are fabricated and measured. Fig. 1 shows the schematics of the concepts realized. Fig.


1a) plots the simplest HBT-driver circuits for an EAM. The HBT and the EAM are separate devices with their individual layout. In the first approach the HBT-layer stack is grown on top of the EAM (Fig. 2b). In the second realization the same HBT-driver circuit is made from the merged layer stack which contains the EAM. The layer stack is shown in Fig. 2a). This structure enables also HBT-EAMs as a third approach which can be operated in conjunction with a load resistor RL (Fig. 1b). The principle of operation is plotted in Fig. 1c).

Fig. 2 Integration of HBT- and EAM-layers by a closed growth step. a) merged layer stack

where the collector is reused as waveguide, b) growing layers on top of each other

Fig. 3 a) Scanning electron micrograph of the stacked EAM and HBT-driver, b) optical micrograph. During processing of the EAM the HBT was protected by mesa-resist

a)InP-substrate

Emitter-Cap140 nm

Cla

ddin

gG

uid

e

E

Substrate

EmitterBase Collector

nip

Cla

dd

ing

n+-In0.53Ga0.47Asn = 1×1019 cm-3

n-InPn = 5×1017 cm-3

p+-In0.53Ga0.47Asp = 1.3×1019 cm-3

Emitter60nmBase

75 nmIn0.53Ga0.47As Spacer 30 nm

InP

n+-InPn = 5×1018 cm-3

sub-Collector250 nm

Collector450 nm

Collector420 nm

In0.64Ga0.36As0.77P0.23

npn

CladdingGuideCladding

HB

TE

AM

b)

1.5 µm 3.5 µm

Thickness:


If the transistor is in the off-state the voltage drop VCB across the base-collector junction is high resulting in an considerable electric field inside the waveguide. Thus the EAM absorbs light. On the other hand if the transistor is switched on, the resulting voltage drop across the load resistor reduces the base-collector voltage VCB and the waveguide becomes transparent.

Fabrication

The layer structures were grown on InP-wafers with LP-MOVPE. The merged layer structure is shown in Fig. 2a). Processing was done using optical lithography and conventional wet-chemical etching and metallisation steps. The HBT-EAM and the EAMs have a length of 50 µm and a width of 8 µm. The HBTs have three emitter fingers with a size of 3*10 µm² each. Fig. 3 shows pictures of the circuit made from the stacked layer structure. To reduce the processing effort of this circuit the layer for the sub-collector contact was reused as the top EAM-contact for the upper cladding. This requires a n-doped upper cladding while the lower contact has to be p-type. To make a connection to the lower cladding the contact area is pulled out to the side. However this increases the RC time constant due to the higher sheet resistance in p-type material.

The same circuit was also processed from the merged layer structure (according to Fig. 2a). In this case the resistor in the collector branch is 500 Ω. The third variant is the HBT-EAM. It is also a common-emitter circuit with a load resistor of 500 Ω, to result in base-collector voltage swings which simultaneously modulate the built-in EAM. The active area for modulation of the devices is always 50µm long and the passive waveguide made from semiconductor material around 400 – 500 µm, depending on cleaving.


For optical measurements the laser source is fed into the devices by a tapered single-mode fiber. A cleaved single-mode fiber is used to pick up the optical output. Electrical connections are made by coplanar probes. The gain of the fiber amplifier (EDFA) is tuned to 1 mW average power at a photodiode. In the measurement the relative optical modulation is plotted where 0 dB acts as a reference line. This setup enables a quantitative comparison of the different approaches.

A comparison between the HBT-EAM and an EAM made from the same merged layer stack (c.f. Fig. 2a) results in a higher relative optical modulation for the HBT-EAM than for the single EAM up to 20 GHz. This demonstrates the amplification of the integrated HBT. However the cutoff frequency is considerably reduced due to the higher RC time constant. Fig. 4 plots the relative optical modulation for three different approaches. The doted curve shows the characteristic of the HBT-EAM. In a second approach an EAM is driven by a HBT made from the same merged layer structure (concept (2)). A simple common-emitter circuit with load resistor of 500 Ω is used (c.f. Fig. 1a). The relative optical modulation is plotted in Fig. 4. (hollow circles). Despite the same layer structure the result differs by more than 5 dBm in favour to the HBT-EAM, which has a cutoff frequency around 7GHz. Though nominally the same load resistances were used the HBT-EAM has a much more compact layout reducing parasitics like inductances.

Additionally the measurements are compared to the approach with the stacked layer structure (concept (1) and c.f. Fig. 2b). The result is shown again in Fig. 4 (crosses). Below 100MHz the circuit exhibits a better optical modulation of 8dBm in relation to the results from the merged layer stack. This comes from the improved electric field characteristic inside the waveguide. In the


merged layer structure the doping of the upper cladding is below 1017cm-3 resulting in a thick low doped/intrinsic layer. The arrow in Fig. 2a) plots the region where the electric field applies. In the stacked layer structure the field is contained only inside the guide therefore giving a higher field and modulation. However, at higher frequencies the optical modulation drops quickly indicating a component with a high time constant. The RF-characteristics of the three-emitter HBT are fT = 28 GHz and fmax = 21GHz. These results are somewhat below a comparable DHBT grown directly on InP-substrates. On the other hand the EAMs behave moderate with a cut-off frequency below 1 GHz, limiting the circuit (Fig. 4, crosses). Due to the thinner guide the capacitance is increased. Because the p-type cladding consists of InP doped with zinc, the doping profile changes during epitaxial growth. This growth process has to be improved by employing an adequate setback layer. To raise the cutoff frequency further the upper cladding should be again p-type to reduce the series resistance inside the EAM structure. The saving of one mesa layer should be less important.

0.01 0.1 1 10-50

-40

-30

-20

-10

0λ Laser = 1543 nm

PRF,el = 0 dBm

rel.

op

tica

l mo

du

latio

n (

dB

)

frequency f (GHz)

A) EAM with HBT driver, stacked layers B) HBT-EAM C) EAM with HBT driver, merged layers

Fig. 4 Comparison between the three different approaches. The HBT-EAM with load resistor R = 500Ω shows considerable performance. (Samples: filled circles: M2243A HM03, hollow circles: M2243A CIR09, cross: M2575B CIR11)

Conclusions

Though the circuit made from the stacked layer structure needs improved epitaxial growing conditions, the advantages of the merged layer stack are visible. This layer stack enables the processing of HBT-EAMs which act simultaneously as transistors and electroabsoption modulators. By means of the layout, fabrication of compact circuits are comparably easy enabling cost reductions and allowing space for other components on the substrate.


4.2.11 HBT-EAM with InGaAlAs Base

Scientists: T. Reimann, S. Neumann M. Schneider (Fachgebiet Optoelektronik, Univ. Duisburg) Technical Assistant: M. Haase

Introduction

For monolithic integration it is possible to merge the layer stacks from a heterostructure bipolartransistor (HBT) and an electroabsorption modulator (EAM). This results in a layer structure enabling a HBT-EAM, which corresponds to a modulator with an integrated amplifier. In the first approach the collector layer is split to accommodate the upper cladding and the waveguide layer from the EAM (see Fig. 1a). The sub-collector layer is used as the lower cladding. In normal transistor operation the base-collector junction is reversed biased. This produces an electric field inside the collector, which is very low doped in the range of 1017cm-3. In the case of the HBT-EAM the waveguide has a doping in the order of 5*1016cm-3. Therefore the electric field drops also at the upper cladding layer and not only at the waveguide, i.e. the field is weakened in the guide. As an alternative the upper cladding layer can be shifted into the emitter, i.e. the emitter is reused as a cladding layer as shown in Fig. 1 b). In that case the base layer comes in contact to the waveguide. The base material InGaAs has a bandgap of 0.75eV a would absorp light at 1.55µm. In the second approach a transparent base layer has to be used. This is achieved by adding aluminium to the base which increased the bandgap.

Fabrication

Both types of layers according to Fig. 1 were realized. The layer structures were grown on InP-wafers with LP-MOVPE using alternative non-gaseous precursors. Both types of base layers were deposited at 500°C only to yield high carbon doping. Concerning the InGaAlAs layer a characterization with x-ray and photoluminescence measurements resulted in an Al-content around 0.08 suited to get low absorption at 1.55 µm wavelength. This was verfied by optical transmission measurements with a with light source at bulk layers. Technological realization employs a four mesa process, to define, additionally to the known HBT-mesas, a passive waveguide besides the emitter, base and sub-collector mesa. Processing was done using optical lithography, conventional wet-chemical etching and metallisation steps. To reduce optical absorption in the passive waveguides due to the base layer the upper cladding was removed and replaced by photoresist (Allresist AR-P 3740). Fig. 2 shows a HBT-EAM made from the layer stack with InGaAlAs-base. Length of the active region is 50µm and the width of the emitter is 7 µm.


The common-emitter characteristic of a HBT-EAM with InGaAlAs-base layer is shown in Fig. 3a). Current driving capability is approximately 15mA and breakdown voltage is above 8V, showing the compatibility with EAMs. The current gain however is about 8. Fig. 3b) shows the RF-performance with fT = 24GHz and fmax =13GHz. The reason for the degraded current gain is a reduced valence


band discontinuity between the base and the InP-emitter therefore weakening the wide gap emitter effect. In addition, minority carrier lifetime is probably reduced due to impairment of crystal quality by incorporation of Al and impurities. First experiments, reducing base doping and increasing emitter doping, resulted in a current gain of 3.5 at an Al-content of 0.15.

Fig. 1 a) HBT-EAM with collector as upper cladding, b) layer-stack with upper cladding moved into the emitter. This reduces collector-thickness and the electric field in the guide/collector increases. An InGaAlAs-base is used

Fig. 2 SEM-picture of the HBT-EAM with InGaAlAs-base. "W" denotes the passive waveguide. Base contacts are applied from both sides to the emitter contact

Cla

dd

ing

Cla

dd

ing

Gu

ide

p+-In0.53Ga0.39Al0.08Asp = 5×1018 cm-3

InP-substrate

In0.64Ga0.36As0.77P0.23

InP-substrate

Emitter-Cap140 nm

Cla

dd

ing

Gu

ide

E

a) b)

E

Cla

dd

ing

n+-In0.53Ga0.47Asn = 1×1019 cm-3

n-InPn = 5×1017 cm-3

p+-In0.53Ga0.47Asp = 1.3×1019 cm-3

Emitter60nmBase

75 nmIn0.53Ga0.47As Spacer 30 nm

InP

n+-InPn = 5×1018 cm-3

sub-Collector250 nm

Collector450 nm

Collector420 nm

Emitter-Cap50 nm

n+-In0.53Ga0.47Asn = 1×1019 cm-3

n-InPn = 5×1018 cm-3

Emitter540nm

Emitter60nm

n-InPn = 1×1018 cm-3

Base60 nm

In0.64Ga0.36As0.77P0.23Collector

420 nm

n+-InPn = 5×1018 cm-3

sub-Collector350 nm


By adjusting the aluminum content to around 0.08 the gain could be raised to a value of eight, as shown above, while keeping the optical aborption edge below 1.55 µm. Because of the lower base doping the maximum frequency of oscillation fmax is reduced. In the case of an InGaAs-base fmax lies around 20 GHz.

Fig. 4 shows the modulation contrast of a HBT-EAM operated as EAM (i.e. modulating directly VBC and therefore not relying on current gain) for the wavelength range 1520nm – 1580nm. The contrast reaches up to 13dB for a voltage swing of 8V and typical values around 10dB are available at operation wavelengths. Because of the thinner collector the electric field available in the guide is increased. This demonstrates the possibility to get the same contrast at lower voltage swings and would enable simpler driver circuitry.

0 1 2 3 4 5 602468

101214161820

a)

M2781A

HM07 (nsa)AE = 7*50 µ m2

Bmax=8

1.5mA

I B =

30

0µ

A/S

tep

I C (

mA

)

VCE (V)0.1 1 10

0

10

20

b)

VCE=5V, IB=1.2mAM2781A (HM07)

fmax=13GHz

fT=24GHz

unilateralgain GU

short circuitcurrent gain h21

|h2

1|,

GU

(d

B)

frequency f (GHz)

Fig. 3 a) Common-emitter characteristic of a HBT-EAM with InGaAlAs-base. Current gain is around eight, b) corresponding RF-measurements

1520 1540 1560 15800

5

10

15

20P in,opt=1 mW switch from

VCC = 0.0 V to 8.0 V

InGaAlAs-Base InGaAs-Base

mo

du

latio

n c

on

tra

st (

dB

)

wavelength (nm)

Fig. 4 Modulation contrast of a HBT-EAM used as an EAM (directly modulated by VBC). The device with the InGaAlAs-base shows higher optical modulation contrast due to the increased electric field in the collector region.


Conclusions

The alternative layer stack opens the possibility to increase the electric field in the waveguide and therefore the optical modulation. On the other hand the usage of aluminum decreases current gain and RF-performance. The doping in the base and its aluminum content can still be optimized to increase device performance. A new possibility in our group is opened now by the use of strained GaAsSb, which is a preferable material for the base and has a bandgab higher than 0.78 eV.


4.2.12 A 2.5 Gbit/s Operation InP Based RTD/HBT MOBILE

Scientist: S.O. Kim1, H.van Husen, W.Prost

1now with Ferdinand-Braun-Institut, Berlin, Germany. P. Glösekötter2, K.F. Goser2

2Universität Dortmund, Lehrstuhl für Elektronsiche Bauelmente Introduction

The possible implementation of Resonant Tunnelling Diodes (RTD) in circuits is strictly coupled to a successful exploitation of the negative-differential resistance (NDR) characteristic. The most promising approach is the InP-based monostable-bistable logic transition element (MOBILE) [1]. The heterostructure field-effect-transistor (HFET) is successfully used as the input terminal. However, the InP-based HFET suffers from a low Schottky barrier resulting in a poor enhancement type device and strong limitations in terms of direct coupled logic. On the contrary, the heterobipolar transistor (HBT) is a robust enhancement type device.

In this work a monolithically integrated series combined RTD and HBT forming a RTBT is adopted as a MOBILE input terminal. The on-wafer high speed operation of the gate is preliminarily measured at the highest available clock frequency of 2.5 GHz.

CLK

VEE

Vref

RT

BT

ref

RTD

VEE2

RT

BT

a

RT

BT

b a b

GND

Vout

Vout

Vext

Rext=0.1kA = 2 A = 1 A = 1

A = 2.5

50 Ω

samplingoscilloscope

Fig. 1 InP-based NOR-gate circuitry in MOBILE configuration. In this design the emitter area A = 1 corresponds to 30 µm²

Design

A RTBT is series-connected to the driver RTD building a novel MOBILE. The MOBILE function (bifurcation curve) is proven by varying VEE and measuring the output voltage. The input HBT is just acting as a switch opening the gate branch. The final gate is biased in the bistable section (e.g. VEE = -1.4 V). The logic function is a comparison of the current of driver RTD (here AE = 2.5) with


the current sum from the active inputs a, b. The current of branch i is directly proportional to the RTD area Ai. Hence, the remaining design parameter is the RTBT/RTD area, only. In addition, a latch function of the MOBILE output is provided until clk return to a logic low level [3]. In Fig. 2 a MOBILE type NOR gate is presented. The gate output VMP follows the input signals a, b and shows OR-function. Using the inverter buffer (here a differential amplifier) the NOR-function (Vout) is achieved including level compatibility.

Fabrication and Results

The InP/InGaAs:C HBT is grown by MOVPE followed by an AlAs/InAs RTD grown by MBE. The fabrication is performed using optical lithography and wet chemical selective etching. A non-alloyed Ti/Pt/Au metal system is used for all electrodes. Fig.2 shows the measured timing diagram of a NOR-gate at the highest available frequency of f(clk) = 2.5 GHz. The input a is fixed at a DC bias of –0.5 V while b is varied with half the clocking frequency. At a high clock voltage clk = 0V the gate is activated and the output Vout is high if the input b is low (NOR function). The amplitude of the output Vout is reduced according to the limited driving capability compared to the characteristic impedance of 50 successful demonstration of pseudo-dynamic MOBILE gate with HBT input terminals showing multi Gb/s logic operation.

a b

0,0 0,5 1,0 1,5 2 ,0 2 ,5 3,0 3,5-0 ,6

-0 ,5

-0 ,4

-0 ,3

-0 ,2

-0 ,5

-0 ,4

-0 ,3

-0 ,2

-0 ,1

0 ,0

-0 ,5

-0 ,4

-0 ,3

-0 ,2

-0 ,1

0 ,0

Vo

ut

[V]

time [ns]

Vc

lk [

V]

Vb [

V]

Fig. 2 MOBILE NOR gate (cf. Fig.1 ) (a) SEM picture of fabricated chip and (b) measured timing diagram at fclk = 2.5 GHz (Va = -0.5 V, VEE = -1.4 V)

References: [1] K. Maezawa and T. Mizutani, "A New Resonant Tunneling Logic Gate Employing Monostable-

Bistable Transition", Jpn. J. Appl. Phys., Vol. 32, part 2, No. 1A/B, pp. L42 - L44, January 1993.

[2] C.Pacha, U.Auer, C.Burwick, P.Glösekötter, A.Brennemann, W.Prost, F.-J.Tegude, K.F.Goser; Threshold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices, IEEE Trans. Very Large Scale Integration Systems, vol.8, no.5, pp. 558-572, 2000.

[3] P.Glösekötter, C.Pacha, K.F.Goser, W.Prost, S.Kim, H. van Husen, T. Reimann, F.J.Tegude; Pseudo Dynamic Gate Design based on the Resonant Tunneling-Transistor (RTBT), Proc. ESSDERC, Florence 24-26. September 2002.


4.2.13 Influence of Layer Structure on the IV-Characteristic of Si/SiGe Interband Tunnelling Diodes

Scientist: E. Khorenko M. Stoffel1, O.G. Schmidt1 1Max Planck Institut für Festkörperforschung, Stuttgart, Germany

Introduction Compatibility with existing CMOS-technology, specific IV-characteristic owing to the negative differential resistance (NDR) region and last not least relatively simple, just two-terminal design make the Si-based Interband Tunnelling Diodes (ITDs) very attractive candidates for application in high speed threshold logic circuits [1]. The appearance of NDR in the ITD structures crucially depends on the quality and thickness of few nanometer thick tunnelling barrier between p- and n-contact layers. In this contribution we investigated the I-V characteristics of Si/SiGe interband tunneling diodes for various spacer combinations between the n-doped p-doped layer towards the i-Si0.55Ge0.45 tunnelling layer. In addition, the peak current density as a function of device area was studied.

Technology of Si/SiGe interband tunnelling diodes The Si/SiGe based layer stacks were grown by solid source molecular beam epitaxy (MBE) on high resistivity p--Si substrate at the Max-Plank-Institute in Stuttgart, Germany. The undoped intrinsic region of ITD structures consists 3 nm of Si0.55Ge0.45 placed between Si spacers. The thickness of the spacers was varied from 1 to 2 nm (Table 1). The contact layers were heavily (Np,n=1019 cm-3) doped with P (n-doping) and B (p-doping), respectively. In order to provide more charge carriers for tunneling, the intrinsic region was additionally sandwiched between δ-doped p- and n-layers (Np,n=1014 cm-2).

i-SiGep+-Si n+-Sii-SiX2

i-SiX1

growth direction

δ p δ n

Ec

Ev

Table 1. Fig.1 Layer structure of studied Si/SiGe ITDs

spacer thicknesssample spacer XP spacer XN

S1408 0 nm 1 nm

S2067* 0 nm 1 nm

S2045 0 nm 2 nm

S2046 1 nm 0 nm

S1731 1 nm 1 nm

S2066 1 nm 2 nm

S1735 2 nm 1 nm

S1736 2 nm 2 nm


The layer structure of the studied Si/SiGe ITDs is presented on Fig. 1. The fabrication of the planar 2-metal ITD (Fig. 1b) starts with the evaporation of a non-alloyed ITD cathode finger electrode (30 nm Ti/30 nm Pt/340 nm Au).The structure was etched down to the p+-Si in order to isolate anode and cathode. For etching of n-Si a 10 % solution of KOH at 40 °C was used. SiGe and p-doped Si were etched with a mixture of 65 % HNO3 and 5% HF (4:1). Further on 30 nm Ti/30 nm Pt/60 nm Au as anode contact was deposited. Both the anode and cathode contacts were annealed in N2 atmosphere 10 seconds at 300 °C. Finally, after mesa isolation the big contact pads and air bridges were formed on the substrate.

Fig. 2 Studied Si/SiGe ITDs: (a) SEM micrograph of the 2-metal diode and (b) room temperature IV characteristics of the structure with XP =0 nm and XN =1nm (S1408)

Measurement results

The measured IV-characteristics for the sample with 1 nm thick Si spacer between n-δ-doped and SiGe layer (XN spacer) for the cathode areas of 45, 30, 20 and 15 µm2 are presented on the Fig. 2. For the 45 µm2 devices the peak current density Jp is about 16 kA/cm2 and peak-to-valley current ratio PVCR is about 2.7. Homogeneity of these parameters over the whole sample area was less that 8 %. Among investigated samples series this structure shows the best values for both, Jp and PVCR. Increasing the thickness of spacer XN or (and) inserting a spacer XP between p-δ-doped and SiGe layer (XP spacer) results in fast degradation of the peak current (Fig. 3a). PVCR has not such strong dependence on the spacer position, but, as expected, continuously decreases in the samples with common thickening of the tunnelling barrier (Fig. 3b). At the same thickness of the XP and XN spacers, the first one's has much more pronounced influence on the Jp. Because the overlapping of the wave functions of electron and hole in the δ-doped layers has a maximum in the SiGe layer, increasing of the tunnelling barrier for the holes (spacer XP) lead to the drastically decreasing of the tunnelling current.

Obtained IV-curves clearly show an inverse dependence of Jp and Jv on the cathode area, i.e. decrease of the area lead to the increase of the current density (Fig. 4). Temperature-dependent IV-measurements were carried out in order to estimate the possible influence of the diode self-heating due to the high current flow. In the temperature range from 30 K to 300 K the peak current quite

0.2 0.4 0.6 0.8 1.0 0

2

4

6

8 X P =0 nm; X N =1 nm

20 µm 2

15 µm 2

30 µm 2

45 µm 2

curr

ent [

mA

]

voltage [V]

a) b)


linearly increases with the temperature raised up. Common increase of the peak current was about 30% from the starting value. The constant peak and valley voltage vs. temperature indicate that I-V characteristics of the ITD are dominated by tunnelling and only very small contributions from thermoionic emission are visible at voltage < 0.5 V. The valley current density Jv shows a bit more complicated scalability behaviour. Besides enough similar increase with the reduction of the cathode area, Jv exhibit also dependence on the cathode perimeter.

1

1

0

2

2

0

1.35

2.7

1.4

2.5

1.35

1

1

0

2

2

0

0.023

16

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0.028

a b

Fig. 3 The Jp (a) and PCVR (b) for the investigated samples series as a function of the spacer thickness

0 10 20 30 40 504

6

8

10

12

14

16

18

20

22

24

26

catho de sizewid th x leng th [nm ]

Jvalley

Jpeak

cathode length 10 µm

cathode leng th 15 µm

cathode length 5 µm

1x5

3x15

3x10

2x152x10

1 x101x15

2x5

1x5

3x15

3x10

2x15

2x1 0

2x5

1x1 5

1x1 0

curr

ent

den

sity

(kA

/cm

2 )

diode area (µ m 2)

Fig. 4 Dependence of the Jp and Jv on the diode area and geometry

PV

CR

J p [

kA/c

m2 ]


As presented on Fig. 4, for our device design (see Fig. 2a) the valley current practically doesn't changes in the diodes with the same cathode length, which defines the current flow path from the cathode to anode contact. This fact pointed out a significant role of the surface recombination in the investigated ITDs and has to be investigated more detailed especially due to the its importance for the downscaling the ITDs.

Acknowledgment

The work is sponsored by the European project QUDOS in framework of the Information Society Technologies (IST) Programme (contract number IST-2001-32358)

References [1] C. Pacha et al., “Threshold Logic Circuit Design of Parallel Adders Using Resonant Tunnelling

Devices” IEEE Transactions on Very Large Scale Integration, v.8, no. 5, pp.558-572 (2000).

[2] R. Duschl, O.G. Schmidt, K. Eberl, Appl. Phys. Lett. v.76, p.879 (2000).

[3] U. Auer, W. Prost, F-J. Tegude, R. Duschl, K. Eberl, "Low-voltage MOBILE logic module based on Si/SiGe Interband Tunnelling Diodes", Electron Device Letters, v.22, no. 5, pp.215-217 (2001).


4.3 Device and Circuit Simulation, Measurement

and Modeling


4.3.1 Physical Simulation of Transmission-Line-Measurements with TCAD

Student: S. Deragopian Supervisor: B. Schlothmann

Introduction

The "Transmission Line Measurement" (TLM) method is used to determine the ohmic contact and layer properties of condcuting semiconductor materials. The structures will be simulated in an environment of “Technology Computer Aided Design” (TCAD) from Silvaco and will be compared to processed structures. However, the accuracy of computer models is always subject to question. The process for determining these parameters is called calibration. The calibration of the simulation software is done for III/V semiconductors devices produced in the department, taking into consideration the TLM structure. TLM allows us to determine the contact and active layer sheet resistances separately through measuring the voltages between contacts with different distances (see Fig.1). This allows us to estimate material parameters describing the material under the contacts. For the reliability of the results the electric field in the active layer must not be too high, to avoid saturation of the charge carrier velocity causing non-ohmic behaviour.

Fig. 1 TLM structure diagram with contacts on the active layer.

TCAD Simulation and Results

Through many years of research and development, TCAD has matured to a stage where complex semiconductor processes and devices can be simulated with reasonable accuracy. For calibrating the TCAD Simulation the results of contact resistance from TLM – method and the mobility of the charge carriers from the Hall- measurement are deployed. As a result of this process the simulation


parameters are optimized, thereby the standard characterization measurement techniques TLM- and Hall become important tools for extracting material and model parameters. For the implementation of metal-contact simulation, many criterions have to be taken into consideration. It has to be sure that there are enough grid points where the electric field is high. Since the accuracy and speed of a simulation are highly grid dependent, this makes the simulation retrieval more critical. An alternative solution is the use of resistance parameter in contact statement for setting arbitrary contact resistance. By doing so, the potential characteristic by applied voltage on the active layers is linear. This behaviour can be seen in Figure 3 following the cutline between the two ohmic contacts.

Fig. 2 Calibration flow chart through Hall- und TLM- measurement.

Fig. 3 Potential characteristic of the basis layer

TLM

Hall- measurement

simulation

mobility

Carrier concentration

Active layer sheet resistance

contact resistance

proofed model- and

material parameters


As an example the p+-InGaAs base layer of InP based HBT id investigated (fig. 4). The base layer has a mobility of µn=40cm2/V.s. The contact resistance of a Ti/Pt/Au metal is RK=0.1 Ohm and the simulated resistance between two contacts with 40 µm spacing is approx. 310 Ohm. The measured value was 350 Ohm as . This is shown in. These differences in the results can be explained by dopant diffusion during component fabrication. With a mobility of µn=30cm2/V.s the simulated results are matched with the measured ones.

Fig. 4 Comparison of simulated and experimental TLM measurement appliedto a p+-InGaAs base layer of InP based HBT

Conclusion

In the framework of this thesis, methods are developed for implementing metal-semiconductor contact resistance in simulation environment. With this simulation, it is possible to improve the agreement with TLM experiment enabling faster device development.

References [1] Physik und ihre Anwendungen in Technik und Umwelt , Leute, Ulrich 1995.

[2] http://ece-www.colorado.edu/~bart/ecen3320/indexf01.html, B. Van Zeghbroeck, 2002

[3] Physical Properties of III/V Semiconductors Compounds, Sadao Adachi, 1992

[4] Silvaco ATLAS Handbuch, November 1998.

[5] Festkörperelektronik Script, Gerhard-Mercator Universität Duisburg

[6] Zweidimensionale physikalische Simulation von InP- Heterostruktur-Bipolartransistoren mit TCAD Diplomarbeit - Gerhard-Mercator Universität Duisburg, Schlothmann Bjoern, 2000

[7] Bestimmung des Source-Widerstandes von Feldeffekttransistoren, Studienarbeit – Gerhard-Mercator Universität Duisburg, Michael Iding, 1989.


4.3.2 Simulation of n-GaAs/N-AlGaAs Heterojunction

Scientist: B. Schlothmann

Introduction

Simulation of semiconductor devices play a major role in device development, because of time and cost saving. Therefore a simulator is needed which is able to simulate the given device. Recently, heterostructure devices, such as heterojunction bipolar transistors (HBT) or heterojunction field effect transistor (HFET), have stimulated great interest because of their potential for high-speed, high-frequency and monolithic integration of amplifiers and optical components like pin-diodes. Simulating these devices is a big challenge because of their special behavior at the heterojunction. In contrast to homojunction devices with continious bandstructure, for a abrupt heterojunction it is necessary to extend the established diffusion model to meet the requirements of a heterojunction. The current transport across the abrupt heterojunction interface is usually predominated by the thermionic emission mechanism, which is compareable to the behavior of a metal-semiconductor Schottky contact.

In this work we compare simulation results of Horio et. al. [1] and simulation results of our inhouse simulator (ATLAS from Silvaco). The comparison and calibration of the simulator with different sources is very important for the understanding of the simulation process and also for device understanding. With a prooven simulation technique an engineer is able to develop new devices and optimize existing ones.

Simulation Environment

In the paper from Horio et.al. [1] is a model described which is similar the same used in our inhouse software from Silvaco [2]. In this work we compare the simulations of a n-GaAs/N-AlGaAs heterojunction device, described in the work of Horio et.al. [1] and our simulator. We used the given device dimensions (fig. 1), material parameters, and model parameters given in the paper.

Fig. 1 Device structure for discussed results


Fig. 2 Current-voltage characteristics for an n-GaAs/N-AlGaAs diode, calculated with thermionic emission model (solid lines) presented in [1], diffusion model (dashed lines), and simulations of our inhouse simulator from Silvaco (solid lines with tick marks).

Results

Horio et.al. compare in his work the influence of the presented model and discussed the physical reliability. In fig. 2 the current-voltage characteristic for an n-GaAs/N-AlGaAs diode is shown, calculated using the thermionic emission model, well known diffusion model, and our results. As seen in both cases, our results show a good agreement to those calculated from Horio. In congruence with him the thermionic emission model calculated a smaller current density, at a given voltage, than the diffusion model, because the thermionic emission mechanism limits the transport process over the heterojunction. As known the thermionic emission mechanism becomes important in the case, when high barriers for majority carriers are present, also recognised at metal-semiconductor Schottky contacts. Fig. 3 shows the band diagram of the two cases, with and without thermionic emission model. Our calculated results are plotted each case 0.5 eV higher for a better synopsis. If they are plotted in the right manner, the agreement is as that good as also show in the current-voltage characteristic (fig. 2).


Fig. 3 Energy band diagram of the n-GaAs/N-AlGaAs diode under 0.15 V forward bias. The upper diagram shows the calculation using the diffusion model, the band diagram below is calculated with thermionic emission model. For a better readability our results are plotted 0.5 eV higher than the results calculated from Horio et.al. [1].

Conclusion

The presented comparison gives more security to the used simulator and demonstrates the importance of the thermionic emission model.

References:

[1] Kazushige Horio, Hisayoshi Yanai; "Numerical Modeling of Heterojunctions Including the Thermionic Emission Mechanism at the Heterojunction Interface“; IEEE Transactions on Electron Devices, VOL. 37, No. 4, April 1990.

[2] Silvaco International; "User’s Manual“; Santa Clara, December 2002.


4.3.3 Simulation of Heterostructure Bipolartransistors with Various Collector-Designs and their Influence on the High-Frequency Behaviour

Student: L. Schneider Supervisor: B. Schlothmann

Introduction To analyze the influence of different design parameters on the performance of semiconductor devices, it is helpful to do a physical simulation which allows the analysis of semiconductor devices in a cheap and time-saving way. This work was done by means of SILVACO´s device simulation software TCAD. It had to be investigated in what way the thickness of the collector-layer exerts influence on the high-frequency behaviour. Therefore four samples with a 150 nm, 300 nm, 500 nm and a 1000 nm thick collector and a 30µm2 emitter where simulated. After a rough calibration of the material parameters and a short DC-characterisation of the sample with the 300 nm collector the microwave characteristics of the same sample where simulated and compared to a measured sample. The simulation results of the overall high-frequency behaviour in particular the current gain and the unilateral power gain of all samples, was compared with literature reviews [2]. In the following the results of these simulations will be discussed.

Results The comparison of the simulated and measured current gain and the unilateral power gain, respectively as a function of frequency showed a slightly difference. As mentioned above this simulation was made for the sample with the 300 nm collector. The simulated current gain shows a good approximation to the measured characteristic although being somewhat smaller than the measured current gain. While the measured cutoff frequency was about 13 GHz, the simulated value was approximately 11.5 GHz. But on the other hand the simulated maximum oscillation frequency of 9.5 GHz is about 2.5 GHz higher than the measured value. On balance one can say that the comparison of simulated and measured high frequency characteristics show a good agreement. After a comparison of measured and simulated high frequency behaviour, the dependence of current gain and unilateral power gain on the collector thickness was simulated. Fig.1 shows a slightly decrease of the cutoff frequency for an increase of collector thickness. This behaviour springs from the higher transit time of electrons through a thicker collector. While the cutoff frequency of the 150 nm collector was about 13 GHz a decrease up to 9 GHz for the 1000 nm collector was simulated. In contrast to the current gain the behaviour of the unilateral power gain revealed a stronger dependency on the collector thickness. An increase of collector thickness resulted in a decrease of maximum oscillation frequency. This issue is due to the reduced parasitic capacities in the collector. Fig.1 as well, shows the unilateral power gain as a function of frequency for the four collector thicknesses. As can be seen in figure 2 the maximal oscillation frequency is about 6.3 GHz for the 150 nm going up to a value of about 20 GHz for the 1000 nm collector.


Fig. 1 Current gain and unilateral power gain vs frequency for different collector thicknesses

Fig. 2 Matine´s et al. measurement results of the current gain behavior for different collector thicknesses

To evaluate the quality of the simulated results a comparison between simulation and real measurements had to be made. Unfortunately it wasn’t possible to get measurement results of real samples. So a comparison with data of literature reviews had to be made. As illustrated in fig. 2 there was a work of N. Matine et al [2] where the dependence of the high frequency behaviour of similar DHBTs on the collector thickness WC was investigated as well. Although there was


deficient data of lateral dimensions and especially the bias point of the measurements it was suitable for a qualitative evaluation. The extracted cutoff frequencies where 78 GHz and 40 GHz for the 300 nm and 500 nm thick collector respectively. To contrast the simulated results with these values it had to be found out for what collector current the cutoff frequency is the biggest. Therefore a simulation of the cutoff frequency as a function of collector current had to be made (Fig. 3).

Fig. 3 Approximation off maximum cutoff frequency as a function of collector current

The result was that a cutoff frequency of 60 GHz for the 300 nm thick collector which is just 18 GHz smaller than the measured value. The simulation of the 500 nm thick collector resulted in a cutoff frequency of 30 GHz. This value is just 10 GHz smaller than the measured value.

To sum up, the simulation is a good convergence to measurement results. Differences between simulation and measurement may spring from different latereral dimensions and doping levels. Furthermore as mentioned above just a rough calibration of the material parameters was made.

References [1] C. R. Bolognesi; Compound Semiconductor Device Laboratory,

http://css.sfu.ca/sites/cdsl/research.html

[2] N. Matine, X. G. Xu, M. W. Dvorak, S. P. Watkins C. R. Bolognesi; “InP/GaAsSb/InP Double Heterojunction Bipolar Transistors with High Cut-off Frequencies and Breakdown Voltages”, Simon Fraser University, Burnaby


4.3.4 Current Transport Mechanisms of InP-Based Double Heterojunction Bipolar Transistors with Different Base Structures

Scientist: Z. Jin

Introduction

InP/InGaAs/InP and InP/GaAsSb/InP double heterostructure bipolar transistors (DHBTs) [1]. The InP/InGaAs materials form type-I heterostructure, while InP/GaAsSb materials form type-II heterostructure. Different band line-up is expected to result in different current transport mechanisms. Here we study the current transport mechanism of InP-based DHBTs with InGaAs bases including a step graded base-collector junction and GaAsSb base.

Experiment

The InGaAs/InP DHBT (sample A) consists of a 270 nm In0.53Ga0.67As subcollecter (Si: 2×1019 cm-

3), a 200 nm InP collector (unintentionally doped), unintentionally doped 20 nm In0.73Ga0.27-As0.58P0.42, 10 nm In0.64Ga0.36As0.77P0.23 and 20 nm In0.53Ga0.67As layers to eliminate the blocking effect, a 70 nm InGaAs base layer (C: 1.5×1019 cm-3), a 65 nm InP emitter (Si: 3×1017 cm-3), and a 135 nm In0.53Ga0.67As cap layer (Si: 2×1019 cm-3). The GaAsSb/InP (sample B) has a 300 nm In0.53Ga0.67As subcollecter (Si: 2×1019 cm-3), a 200 nm InP collector (unintentionally doped), a 20 nm GaAs0.6Sb0.4 base layer (C: 9×1019 cm-3), a 10 nm unintentionally doped InP layer and a 60 nm InP emitter (Si: 3×1017 cm-3), and a 100 nm In0.53Ga0.67As cap layer (Si: 2×1019 cm-3). The DHBTs under study have the same emitter areas and collector areas. The emitter area is 3×15 µm2. DHBTs were fabricated by conventional wet etching and metal deposition with 3-mesa design.


In general, the terminal current (the collector current in the forward mode or the emitter current in the reverse mode) is limited by the transport of carriers across either the base layer or the conduction band barrier of the emitter-base (forward mode) or the base-collector junction (reverse mode) [2]. When the device operates in the forward mode, the base-emitter junction is forward-biased, the electrons are injected from the emitter-base junction and part of them is collected by the collector. In contrast, when the device operates in the reverse mode, the base-collector junction is forward-biased, the electrons are injected from the base-collector junction and part of them is collected by the emitter.

Fig. 1 illustrates the measured collector and emitter currents of the samples in both the forward and reverse Gummel plots. Here, VBC=0 V for the forward Gummel plot measurement and VBE=0 V for the reverse Gummel plot measurement. It has been demonstrated that [2], when the current is limited by the carrier transport through the base layer, the current depends solely on the doping profile and thickness of the base layer, independent on the structures of the emitter-base or the base-collector junctions. Furthermore, the current increases with bias with an ideality factor of unity. In contrast, when carrier transport is limited by the conduction-band barrier of a heterojunction, the


current critically depends on the magnitude of the conduction-band barrier and its associated ideality factor has a value larger than unity. For sample A, the emitter current have an ideality factor of near unity (nBC), while the collector currents have an ideality factor much larger the unity (nBE). This indicates that the current transport of the base-collector junction is limited by carrier transport through the base region, in contrast, the current of the base-emitter junction is limited by the conduction band barrier of emitter-base junction. For the sample B, both the collector and emitter currents in the forward or reverse modes have ideality factor of unity. This indicates that the current transport is limited by the transport of the carriers across the base region. This is further confirmed by overlaying each other. The emitter currents of the two DHBTs have almost the same ideality factor. The IE curves of the sample A and that of sample C are spaced about 63 mV apart. The reason is that the GaAsSb has a larger band gap than InGaAs in our case because of high C-doping capability.

Fig. 1 The collector currents in the forward Gummel plots and the emitter currents in the reverse Gummel plots of the three DHBTs with different base structures.

Fig. 2 (a) The forward and (b) reverse Gummel plots of the three DHBTs with different base structures.

We now check the Gummel plots of the samples to further understand the current transport in the three devices. Figure 2(a) shows the forward Gummel plots. At small bias, the base current is

0.0 0.2 0.4 0.6 0.8 1.010-11

10-9

10-7

10-5

10-3

IC

IE

Sample A

Sample B

I C,

I E (

A)

VBE, VBC (V)

0.0 0.4 0.810-10

10-8

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10-4

10-2

(a)

IB

IC

I (A

)

VBE (V)

0.0 0.4 0.810-10

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10-6

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10-2

I (

A)

(b)

IE

IB

Sample A

Sample B

VBE (V)


dominated by the space charge recombination and surface recombination at the base-emitter junction, while at large bias, it is dominated by the bulk recombination in the neutral base region [3]. Sample B has a much sharper increase in the base current. In very highly doped base, say 9×1019 cm-3 in Sample B, the base current is dominated by the Auger recombination current. This results in larger bulk recombination current, the bulk recombination has an ideality factor of 1. The surface recombination is a smaller part compared to that in a lower doped layer. This results in a smaller ideality factor in Sample B. Moreover, the base current in Sample B is much larger than those of sample A because of the high doping density in sample B. Fig. 2(b) shows the reverse Gummel plots. The curve shifts to the high VBC in sample B. For the base current in the reverse mode, the surface recombination at the base-collector junction sidewall is included [4]. The sample A has the smaller base current ideality factor than sample B. This indicates that sample A has the smaller surface recombination that sample B. This further confirms that the smaller ideality factor of Sample B in the forward Gummel plot is due to the competition of the bulk recombination and surface recombination.

References:

[1] C. R. Bolognesi, M. W. Martin, W. Dvorak, N. Matine, O. J. Pitts and S. P. Watkins, Jpn. J. Appl. Phys. 41, 1131 (2002).

[2] W. Liu, S. Fan, T. Kim, E. Beam, and D. Davito, IEEE trans. Electr. Dev. 40, 1378 (1993).

[3] Z. Jin, F. Otten, S. Neumann, T. Reimann, W. Prost, and F.-J. Tegude (submitted)

[4] Z. Jin. S. Neumann, W. Prost, and F.-J. Tegude, Physica Status Solidi (a) (to be published)


HP-IB Bus

coaxial-Cable

HP4192A

Keithley Multimeter

4.3.5 Experimental Set-Up for CV- Measurement

Student: R. Schlangen Supervisor: M. Haase, W. Prost

Introduction

For the development of new semiconductor devices it is important to know as precisely as possible the used layer structures and their doping densities. One commonly used method to determine the doping density profile, and other parameters, is the differential CV measurement [1]. The aim of this work was to build up a Measurement- and Analysis-Environment and to proof there functionality with some measurements on HBT-Base-Emitter- and MIS-Diode Structures.

The Hardware set-up was realized as it is shown in Fig.1. The HP4192A CV bridge is the central measurement device. The HP4192A is connected to the probe station via four coaxial cables using the “Four Terminal Pair Method” and receives its measurement instructions via a HPIB-bus from the Remote Computer. The Multimeter is also driven by the Remote Computer but it is only used for an additional DC-IV-Characteristic which is recorded at the beginning of each CV-Measurement routine.

Fig. 1 Experimental set-up


The measurement programm, written in HP VEE, enables to recorde the usual CV-curve, providing every usefull function of the HP 4192A [3]. Furthermore the software checks during the ongoing measurement weather the measured data underlies systematical errors.

Because the capacitance values which are to be measured were expected to be at the lower end of the effective range of this set up a reliable calibration was important. The HP4192A provides an internal rectification wherein the values of one applied calibration, executed at a certain frequency, are extrapolated for other frequencies out of the same frequency range. Once a measurement routine is ended, the data can be stored into an external MS Excel file. This feature was realized to separate measurement- and analysis software because it was considered to use a text based language to build up the analysis software. The main advantages of this approach were that we could reduce the HP VEE part to a general CV-measurement routine with a high degree of freedom in selecting the measurement parameters and that the analysis software, realized in VBA, can now be used on almost every MS based system and is also open to be complemented by other analysis parts for future projects.

Results

In fig. 2 one can see a typical measurement curve observed at a HBT base-emitter-diode. Both, the recorded curve and the calculated doping density profile were in the expected value range and the whole set-up showed reliable results in this test measurements. Even thought the relatively small, device architecture based capacitance values of these structures have already been very close to the lower end of the effective range. This can easily be seen as the progression of the curve in Fig. 3b is already a little noisy in the left part of the plot which is not consistent with the expected CV-curve [2] and only to explain with a growing influence of errors once the absolute capacitance values drop below 1 pF. This lower edge of the effective value range varies with the device Structure and the measurement frequency and turned out to be a problem when HBT Structures with specially reduced gate length were about to be measured.

Fig. 2 Calculation of the doping density based on the CV-measurement at the Base-Emitter-Diode of a HBT

1E+16

1E+17

1E+18

1E+19

1E+20

20 40 60 80

Place x rellative to the pn-junction (nm)

N(x

) in

cou

nts/

cm^3

7E-13

1,2E-12

1,7E-12

-1 -0,7 -0,4 -0,1 0,2 0,5

Voltage (V)

Cap

acita

nce

(F)


3E-11

4E-11

5E-11

6E-11

7E-11

-13 -11 -9 -7 -5 -3 -1 1

Voltage (v)

8E-13

9E-13

1E-12

-2 -1,25 -0,5 0,25

Voltage (V)

Fig. 3 a) MIS-Diode b) HBT-Base-Emitter-Diode

The measurement system has also been tested on MIS-Structures which were specially processed with bigger active areas to encrease the capacitance values. Fig. 3a shows one examlpe for this type of diode. The very smooth curve leads to the concusion that specially these wider structures should mainly be utilized for this measurement set-up.

Acknowledgement

Thanks to the whole Solid-State Electronics Department and specially to Mr. M. Haase for his committed assistence.

References: [1] S.M. Sze

Physics of Semiconductor Devices 2nd Edition

John Wiley & Sons, New York, 1981

[2] E.H. Nicollian, J.R. Brews

MOS Physics and Technology

John Wiley & Sons, New York, 1982

[3] Manual

LF Impedance Analyzer, Model 4192A

Hewlett Packard, USA, 1983


4.3.6 Development of a DC Test System

Scientist: G.Grah

Background

For the development of complex high-speed-circuits, which contain a high number of devices, testing is not even trivial but also essential for design changes. For this reason a test has to provide more information than even to verify the function of the circuit. Mainly this information is received by contacting the necessary (input, output, control) circuit pins. To apply changes within the next design loop one has to gather more information from a circuit-test. This requires a possibility to detect points that cause malfunction which may arise from damaged devices, unintended shorts or opens or even devices that differ from their intended characteristics. There are two things needed to do this. First, a tester is needed that supplies the specific signals to the DUT and second, there must be accessible test points inserted in the circuit layout.

Testing may be done at the normal operating frequency of the circuit which is in the rf frequency range in this case or may be done at low frequencies nearly dc. A final test should of course be done at the conventional operating frequency of the circuit but for detecting malfunctions it is more useful to use a quasi-static test, which eliminates rf effects that may occur additionally. Summarizing the requirements of this test system: a tool is needed that supplies several signals with the specific waveforms to the DUT at quasi-dc operation and is able to measure quasi-time- dependent voltages at multiple test points.

Implementation & Testing

Concerning a MS-D-FF for rf application, as it has to be tested here, two differential complementary signals are needed. One differential signal represents the data and the second one represents the clock signal. To realize a test system for quasi-dc operation, that supplies two freely adjustable differential complementary signals in amplitude and phase and also measuring the voltage levels of several points, four independent D/A and multiple A/D channels are required. In order to perform these measurements we developed a system adequate to the demands.

The principle of this tester is shown in fig.1. It consists of an A/D converter with 8 input channels and 12 bit resolution, corresponding to 1 mV, assuming a voltage range of about 4 V. The D/A converters which generate the data and clock signal have the same resolution as the A/D converter. The core of the test system is a micro controller-unit (MCU) which controls the whole test procedure and transmits the measured data to the PC for further analysis.

Connecting the system the measurement set-up has to be modified to be able to connect the inserted test pads. This can be done with additional probe tips that have to be placed very carefully. The modified measurement set-up in combination with the test system allows us to obtain data about the quasi-dc operation of the circuit.


Fig. 1 Tester Principle for complex circuitry

Fig.2 illustrates how a possible test looks like. The data D and clock signal C is supplied by the four D/A channels to the circuit. With every change of the input signal the voltage level at the test points chosen is measured and put into the memory of the test system. Reasonable test points are the upper load resistors and the points behind the level shifter diodes. The voltage levels at the load resistors show whether the cascaded differential amplifiers are switching correctly; measuring the voltage levels at the level shifter diodes show whether the source followers are working properly. Further measurements can be performed using other test points which of course have to be implemented in the circuit layout.

Fig. 2 Measurement example using the DC test system


Fig. 3 Top view of the DC test system

The entirely assembled test system consists of two PCBs (printed circuit boards), shown in fig.3. On the upper side PCB there is the user interface with a keyboard and an LCD Display. And on the lower side PCB there is the main part of the electronic system (shown in fig.4).

Fig. 4 Bottom view of the DC test system


4.3.7 Development of a Calibration Technique for On-Wafer Optoelectronic S-Parameter Measurements

Student: A. Matiss Supervisor: W. Brockerhoff, M. Agethen, D. Cheskis1

Fa. Multilink, USA

Introduction

This work presents some initial thought and techniques that deal with the characterization of on-wafer level optoelectronic devices (i.e. pin-diodes). Basically, it tries to convert existing electrical techniques to an optoelectronic environment. The main subject is the development of an on-wafer calibration technique.

Description

A common Lightwave Component Analyzer offers several optoelectrical calibration modes for connectorized devices. In an early state of circuit developement it is necessary to characterize integrated optoelectronic circuits on wafer. These devices have to be connected with special optical and electrical probes to measure their performance in high-frequency range. The process of modifying the Lightwave Component Analyzer to fit the requirements of an on-wafer measurement is successively described in this work. The first attemp was to use the existing optoelectronic calibration technique, which were thought to be used for coaxial connected devices, for on-wafer level pin-diodes with an additional de-embedding of the probes from the measurement data. This technique delivered some useful data but was very complicated to perform because of the complex mathematical correction process of the data after the measurement. The next step was the idea of replacing the existing coaxial connected calibration standard with an on-wafer pin-diode and use an easy calibration technique with a new on-wafer calibration standard. The on-wafer calibration method avoids the mathematical de-embedding of the probes because they are already included to the calibration setup and therefore increases the accuracy of all measurements.

Fig.1 Light wave Component Analyzer


Using the electrical frequency response calibration technique modified for optical to electrical s-parameter measurements as a simple technique to compare different pin-diodes, and to determine the capability of creating on-wafer calibration standards for easier on-wafer measurements, the following picture shows the difference between an on-wafer performed calibration and an calibration performed on an connectorized pin-diode.

Fig.2 Recorded optical to electrical forward transmission data (S-parameter) with the frequency response calibration technique performed on different on-wafer level pin-diodes and on a coaxial connected pin-diode (coaxial calibration performed on a Light wave component Analyzer).

Some of the presented curves in Fig.2 show strong differences from the initially used Light wave Component Analyzer calibration (Fig.2, curve: ”coaxial cal.”), and some of them look very similar to it. The first two curves are measured on the same pin-diode, one time using the LCA-coaxial calibration with the de-embedding technique, and the upper one using the LCA-results as reference pin-diode data for an on-wafer calibration as explained above. The other two curves are measured using the on-wafer calibration on a 12 um diameter pin-diode as calibration standard. Both curves show some kind of jitter in the higher frequency range. This is due to reflections at the output of the pin-diode in dependence on their diameter. The frequency response calibration does not include reflection error correction to the measurements and therefore for different diodes with different impedances the reflection error differs stronger. In general it seems to be possible to use existing electrical to electrical calibration methods in a modified way to make them fit to optical to electrical on-wafer calibrations.

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Frequency / GHz

12 umcal.diode (on-wafer cal.)coaxial cal.(LCA cal.)

15 umcal.diode (on-wafer cal.)20 umcal.diode (on-wafer cal.)


Content

The work reflects the theoretical and technical background that is necessary to understand the basics of optical to electrical high-frequency measurements. It introduces some specific instruments and measurement stations that allow o/e measurements and calibrations. Different techniques are presented to correct the data and to calculate different coefficients like transmission of the probe or also different error coefficients. Furthermore it contains many investigations of pin-diodes in many different ways. Especially the change from electrical to optical measurement is discussed and the problems and advancements are turned out. For manual use of the presented measurement station an additional source code is described that allows the user to influence the process of calibration. It allows a separation of different instrument parts, which is useful to develop own optoelectronic measurement routines and measurement/calibration techniques.

Acknowledgement

Thanks to Multilink Technology Corporation for their support and special thanks to David Cheskis for for coordinating this student exchange.

Also I would like to thank Michael Agethen from Innovative Processing AG for his continuous advice and support.

Furthermore special thanks to the Innovative Processing AG for supporting me with many different pin-diodes.

References: [1] P. Debie, L. Martens, and D. Kaiser; "Improved Error Correction Technique for On-Wafer Lightwave

Measurements of Photodetectors“; IEEE Photonics Technology Letters, VOL. 7, No. 4, April 1995.

[2] Johan Sjöström; “Measurement and Modeling of Photodetectors for Monolithic Optoelectronic Receivers for Bit Rates up to 40 Gb/s.” ;Master of Science Thesis, Stockholm, April 1998

[3] David M. Pozar; “Microwave Engineering”; University of Massachusetts, June 1990

[4] “Agilent 86030A Lightwave Component Analyzer System User’s Guide”; Agilent Technologies Inc., August 2001

[5] “HP 8510C Network Analyzer System Operating and Programming Manual”; Hewlett Packard, January 1994


4.3.8 Implementation of the Cadence Design Framework for Use with III-V-Technologies

Scientist: J. Driesen

Introduction

In the recent years, there were simple design and layout tools used in this department. Nevertheless, it has been sufficient, since solely single components and small circuits had to be designed. But it brought a lot of work with it: Each mask set had to be designed on a tool with only a small amount of commands for depicting and manipulating the layout structures. Each mask set had to be cross-checked manually by the designers. And the more complex the design was the higher the probability of any error has been.

With the introduction of the Cadence Design Framework the most striking disadvantages have been eliminated. With this framework, as its name says, the whole design process from the idea up to the mask set is completely integrated into one graphical user interface. There are tools implemented for schematic entry, circuit simulation, layout design, administration of whole design libraries, physical layout verification, layout extraction and layout cross-check with the corresponding schematic, and parasitic extraction. Figure 1 shows a screenshot of the layout editor windows.

Schematic entry and circuit simulation

Before introducing the Cadence Design Framework, no consistent tool for schematic entry was used. All circuit designs were made by hand. But the most striking advantage of the schematic entry with Cadence is the immanent interface to a number of circuit simulators. The Analog Artist tool of the Cadence Design Framework is an interface to circuit simulators like the Cadence cdsSpice, Spectre and Spectre RF as well as third party tools like Agilent ADS, Libra and others. But most important, there is an interface to HSPICE from Avanti (a tool which is also available at the department).

Layout design with III-V based semiconductors

A layout design with III-V based components is slightly different compared to silicon, which is the standard technology for the Cadence design software. I.e., the III-V substrate is normally undoped, and mesa structures are used for device isolation. Furthermore, with the technology used in the department, there is normally no insulator between the two metal layers like it is a standard with silicon processes. Therefore, the connection scheme for metal wires is the opposite as with a standard silicon technology.

All these differences had to be taken into account throughout the implementation of technologies of the department. Currently, two technologies have been implemented. The first one is a kind of an interface technology for the electron beam direct layout writing tool that is available at the department. Using this technology, rapid prototyping can be easily done.


The second technology is still under construction. This technology is focused on RTDs and HFETs, but can be extended to PIN diodes and HBTs. Since a completely new process has to be created, the rules for this technology are still in the early stages.

Access to the database of the department via Cadence

It is very important for the department to maintain access to the old design data. Since the former program as well as Cadence has an interface to the common GDS II design data standard, all data can be transfered to the Cadence design database. Scripts have been written to ease this process, and the most important libraries have already been transfered.

Layout verification

One of the most striking advantages of the Cadence design tools is the possibility of checking the layout. There are two kinds of verification tools already available.

First of all, the physical rules can be checked. With this tool, the layout is checked for minimum sizes of the structures, like whether notches and separations are too great or too less, and structures should lay on or should avoid each other, and many more. The intended aim is to prevent design errors that result in structures or structure relations, that could not be physically realised in the laboratory with the corresponding technology. Limitations are caused by optical resolutions (of resists, masks, etc.), alignment of the masks, the mesa structures, growth of layers, underetching and anisotropy of etches, and other process conditions. To use this checking tool, rules have to be defined by the process engineers, and have to be implemented into the Cadence technology. Further information has to be declared, such as sheet resistances of the conducting layers, and others.

The second verification tool is divided into the layout extraction tool and the Layout-Versus-Schematic (LVS) check, which depend on each other. With the extraction tool, the software tries to recognise shapes as components and wires, and to gather a netlist from the layout. Therefore, a set of rules has to be established to tell the program what combination of shapes result in what kind of component, how to extract dimensions of these components, and how the nets are connected. Once an extraction has been made, the resulting netlist can be cross-checked by the second part, the so-called LVS checker. This program compares two netlists, and tries to fit the amount of components, nets and pins, and checks whether both netlists have the same topology, all components of both netlists have the same parameters, e.g. Therefore, a further set of rules has to be provided.

Cadence extensions using SKILL code

An advantage of the Cadence Design Framework is its ability to be extended by customer programs. Cadence has its own language to do so, named SKILL, a language that is based on the LISP programming language. With this language, some extensions of the design framework have been programmed, to provide the department with the ability to write texts on the masks. Further code is planned to be made, for easing the constuction of tapers and resistances.


Technology implementation process

As one can expect after the short description of the main parts of the Cadence software tools above, there are certain scripts and technology description files necessary to provide the department with a new technology.

First of all, the technology file itself is needed. In this file the basic information is defined for the layout and verification tools, such as the available layers, the corresponding layer numbers (for GDSII export), electrical connection of the layers, sheet resistances, area capacitances, and much more. Secondly, a database for use with the schematic entry and simulation tools has to be established. Components that should be designed using this technology have to have a corresponding element in this database, and the components have to be described by CDF (Component Description Format) data, to be available for the simulation and extraction tools. And last but not least, models have to be made available for the simulation tools that should be used. The third important part is the implementation of the rules set for the physical design rule checker, the extraction tool and the LVS tool. It depends greatly on the elaborateness of these files whether the checking tools work properly and all errors were found, or not.

Outlook

The implementation and introduction process for the Cadence Design Framework is still in progress. The access to the database of former designs is established or at least prepared for each library. The current technologies that are used in the department are available, even though they are still under construction.

Fig. 1 Screenshot of Cadence Design Framework windows.


Normally, a lot of further work has to be done. Libraries can ease much work, such as libraries for aligment patterns, test structures, mask sets, predesigned components, or sample circuits. Nevertheless, not just these libraries, but as well the component descriptions, component models and all rule files can only be written with a well defined technology. That is all quite complicated with a technology that is still under construction.

As soon as the processes have been defined, these rules will be improved. And as soon as the models are available, they will be introduced for the available simulation tools as well. A next step will be the implementation of an interface to the now available Agilent ADS microwave simulation tool, that could be an alternative to the simulation with HSPICE, especially for microwave simulations.


4.3.9 Evaluation of a Small-Signal Model for Si/SiGe Interband-Tunneling Diodes

Student: M. Tekloth Scientist: S. Ehrich

Introduction

Interband Tunneling Diodes (ITD) are of interest for high speed applications based on the Monostable-Bistable transition Logic Element (MOBILE). For the design of these circuits, device models are required. In this work we describe as a first step a small-signal ITD model. It is nessecary that the model provide an exact matching. Also it should be scaleable and represent the physical effects within the device.

Electrical behavior

The geometry of the used sample S1408 is described in chapter 4.2.13. In fig.1 the I-V characteristic of an ITD with an anode area of A = 30 µm2 is shown. The characteristic consists of three parts, the region with ohmic behavior (1), the Negativ Differential Resistent (NDR) region (2) and the well known diode-characteristic (3). The region with ohmic behaviour ends here at aproximately Vd = 0.27 V. The voltage for the current peak is Vd peak = 0.32 V. The characteristic shows exponential proportionality beond the valley voltage Vd valley = 0.55 V. For voltages between the peak voltage and the valley voltage the characteristic shows a NDR manner, fig 1 grey symbols. For example the increasing voltage leds to a decreasing current.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.0 0.2 0.4 0.6 0.8Vd/V

(1)

(2)(3)

Fig. 1 Measured I-V characteristic for an Interband Tunneling Diode with an area of A = 30 µm2 1) ohmic region 2) NDR 3) exponential behaviour


The small-signal model

The new model is an enhancement of the standard RTD model [2]. This modification is necessary due to the fact that silicon has a limited conductivity and so a parasitic shunt resistance in the substrate region has to be concidered. The small-signal elements representing the parasitic effect is marked in fig. 2 by dotted elements. The small-signal model consists out of three parts with different dependencies. The first part is built by Lin, Cin and Rin and represents the extrinsic environment. Due to the fact that these elements are extrinsic and independent from the design, geometry and the chosen biaspoints they can be extracted using a multi-bias and multi-device optimisation. These elements represent the pad environment. The second part is on the one hand dependent from the geometrie and on the other hand independent from the biaspoint. This part represents the substrate loss of the silicon by the elements Csub and Rsub. The elements of the last part depend on the device geometrie and voltage. This intrinsic part describes the effect of the interband tunneling and is built by the elements Cj and Rj. The resistor Rj has the ability to become negative values in case of the NDR region to simulate the rf-behavior of the ITD.

1

1`

Cin

Lin Rin

Cj

Rj

Rsub

Csub

extrinsic device andbias independent

extrinsic bias and device dependent intrinsic biasand devicedependent

Fig. 2 Small-signal-model of the ITD consisting of three different dependent parts.

Results

Fig.3 schows the good agreement between modelled and measured data in the whole treated frequency range from 45 MHz up to 40 GHz. The modeled devices have an anoden area of A = 30 µm2. The impressed bias voltage is Vd = 0.49 V, the maximum difference between measured and modelled values in this case is 0.17 %, the biaspoint is in the region where the device shows negativ differential behavior. Which is indicated by an absolute value higher than one of the S-parameter S11:

For modelling the ITD rf parameters the small-signal circuit elements are optimised by evolutionary algorithms. Fig.4 shows the extracted intrinsic elements for different bias conditions. The dependency of the intrinsic conductivity and the intrinsic capacity in the region of the negative differential resistance (NDR) can clearly be seen.


S11 modeled

S11 measured

Fig. 3 Measured (black symbols) and modeled (gray symbols) input matching coefficient of a device with an area of A = 30µm2 by a supplied voltage of Vd = 0.49 V

Fig 4 also shows the investigation of scaling the anoden area. The conductance is scaling proportional to the device area as well as the capacitance scales with the device area. Doubling the area leeds to two times higher conductivity and twice capacitance.

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02468

0.15 0.2 0.25 0.3 0.35

GjA

/mS

Vd/V

0.3

0.4

0.5

0.6

0.7

0.15 0.2 0.25 0.3 0.35

CjA

/pF

Vd/V

Fig. 4 Comparison of the bias dependency of the modelled conductivity on the left handside and capacity on the right of a nonself aligned device with an area of A = 5 µm2 (x) and A = 10 µm2 (+).

References: [1] E. Khorenko, S. Ehrich, W. Prost, and F.-J. Tegude

"Tunneling Diodes for Compact Very High Speed Circuits“ Thirt Joint Symposium on Opto- and Microelectronic Devices and Circuits Mach 21-31, 2004.

[2] J.P. Sun, G.I. Haddad, P. Mazumder and J.N. Schulman ”Resonant Tunneling Diodes: Models and Properties” Proceedings of the IEEE, VOL.86, NO 4, April 1998


4.3.10 A Combined Large-Signal and Small-Signal Model for InP Based Single HBT

Scientist: Silja Ehrich

Introduction

The design of complex high-frequency electronic circuits is very difficult and strongly depends on the models used for the single device. In case of HBT the large-signal behaviour is often described by using the Gummel-Poon-model as implementd in simulation software such as PSPICE or ADS, resp.. For modelling the rf-behaviour small-signal equivalent circuits are used.

Combined Model

The investigated HBT all base on a typical three-mesa design of InP based HBT devices as described in [1]. Therefore all small-signal equivalent elements are associated to specific device regions and build up the used small-signal equivalent circuit. The model presented here is based on the physical relevant “T”-like model and combines the large-signal description and the small-signal-model. The resulting model is given in fig. 1. In case of large-signal application the base-collector diode DBC and the base-emitter diode DBE is used.

CIO

CIN COUT

LB RB RBP RbbRcc RC LC

DBE

Rje

RE

LE

Cje

CjcCfb

Rjc

DBC

CBP

B C

Eextrinsic

intrinsic

Fig. 1 Combined large-signal and small-signal equivalent circuit of HBT consisting of an intrinsic and an extrinsic part


Parameter-Determination

First of all standard dc-characterization like measuring the output-characteristic and the forward and reverse gummel-plot are done. Also s-parameter are measured in a frequency range from 45 MHz up to 40 GHz at different bias-conditions in respect to the collector-emitter voltage VCE and the collector current density SC using the HP8510C networkanalyzer. Additional the rf-noise-parameter characterization (minimum noise figure Fmin, equivalent noise resistance Rn and optimum generator reflexion coefficient Γopt) is performed in a frequency range from 2 GHz up to 18 GHz using the ATN NP5 system. Device under test is a carbon doped InP/InGaAs self-aligned HBT with an emitter-area of AE = 1x2x10 µm², grown by LP-MOVPE with non gaseous sources. Rf-characterization are done at bias-condition where the HBT is in the active region as well as in the saturation region.

The parameter determination starts with finding the extrinsic elements in form of a multi-bias s-parameter-optimization using evolutionary optimization strategies. Subsequently the intrinsic elements have to be extracted keeping the extrinsic elements constant. The bias-dependence of the intrinsic elements can now be described by mathematical equations.

In the end the diode-parameters of the base-emitter and base-collector diode have to be found, getting a good fit between measured and simulated data for both gummel-plots.

DC-Simulation

To prove the new combined model dc-simulations are done and compared to those resulting from simulation using the standard Gummel-Poon model as implemented in the simulation software ADS. In fig. 2 the comparison between the Gummel-Poon Model, the combined model and the measured data of the output-characteristic of a single HBT with an emitter-area of AE = 1x2x10 µm² is shown. The agreement between measured and simulated data in case of the combined model is excellent. This new model takes into account specific effects of InP devices like basewidth modulation, more accurately.

a)

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Fig. 2 Measured (symbols) and simulated (lines) output-characteristics of a 1x2x10 µm² HBT (IB = 0 µA up to 400 µA, steps 80 µA)

a) Standard Gummel-Poon Model b) Combined large- and small-signal model


S-Parameter Simulation

Besides dc-characterization the rf-behaviour of the investigated device is very important. In fig. 3 the agreement between measured and simulated data at constant bias-conditions (VCE = 1V, IC = 20 mA) is presented for different kinds of models: the standard Gummel-Poon large-signal model and the new combined model. The excellent agreement for the combined model can clearly be seen. Also the difficulties using a large-signal-model for s-parameter simulation are pointed out in fig. 3a.

a)

-15 -10 -5 0-20 0.05 0.10 0.15 0.20

b)

0.05 0.10 0.15 0.20-15 -10 -5 0-20

Fig. 3 Measured (symbols) and modeled (lines) S-Parameters at VCE = 1 V and IC = 20 mA for a) Standard Gummel-Poon large-signal model b) combined small- and large-siganl model

Conclusion

Excellent agreement between measured and simulated data using the new combined modell is demonstrated for both dc- and s-parameter simulation. The main advantage of this combined model is, that it can be used for all kinds of simulation for large-signal as well as for small-signal application without changing the parameters. This combined model can be used for all bias-conditions in the saturation region as well as in the active region. This is an advantage compared to the small-signal-model where the intrinsic parameters have to be extracted for each bias-point.

Acknowledgement

Thanks to Innovative Processing AG for providing their HBT.


4.3.11 Scaling of Intrinsic Small-Signal Elements with Respect to the Emitter-Area of Single HBT Based on InP

Scientist: Silja Ehrich

Introduction

This work presents the scaling-capability of the intrinsic small-signal model with respect to the emitter-area of single HBTs based on InP. We focus on the investigation of the intrinsic elements in dependence on the geometry, which are associated with specific device regions to localize the physically relevant phenomena. Scalability of the emitter-area is also important for circuit simulation and design. In this work the scaling-performance of the model for the intrinsic elements is presented.

The small-signal and rf-noise parameter equivalent circuit

The investigated HBT all base on a typical three-mesa design of InP based HBT devices [1]. All small-signal equivalent circuit elements are associated to specific device regions and build up the small-signal model used. This small-signal equivalent circuit is a “T”-like equivalent circuit with a feedback capacitance Cfb. It consists of an intrinsic and an extrinsic part due to the parasitic environment e.g. the pads. The RC-combination RBP and CBP at the base contact takes into account a frequency dependence of the non alloyed ohmic base contact.

Investigated devices

All devices investigated are carbon doped InP/InGaAs self-aligned HBT with scaled emitter-areas. The layer was grown by LP-MOVPE with non gaseous sources (TBAs/TBP) [2]. Three of the five HBT types are single emitter-finger devices where the length is scaled up from AE = 1 x 2 µm x 10 µm to AE = 1 x 2 µm x 30 µm. The other scaling parameter is the number of fingers keeping the length constant, resulting an emitter of AE = 2 x 2 µm x 20 µm and AE = 3 x 2 µm x 20 µm. Basis-area and collector-area are scaled linearly with emitter-size.

The good rf-behaviour of the investigated devices is demonstrated in tab. 1 where the maximum frequency of ozillation fmax and the extrinsic transit frequency is given for bias-conditions at VCE = 1.5 V and fixes collector current density SC = 1*105 A/cm2. The maximum frequency of ozillation fmax and the extrinsic transit frequency is fT = 113 GHz and fmax = 189 GHz for the device with an emitter-area of AE = 40 µm2. The number of emitter-fingers has more impact on the rf-performance then the emitter-size itselfs. Rising the number of emitter-fingers leads to slightly lower fT and fmax values because the fabrication is more complicated.


20 µm² 40 µm² 60 µm² 80 µm² 120 µm²

fT / GHz 107.6 112.9 115.1 104.8 94.6

fmax / GHz 189.7 188.5 165.5 164.1 110.8

Tab 1: fT and fmax for all investigated devices with different emitter-areas AE

Rf-Performance

For modelling the rf-parameters, all equivalent circuit elements are optimized using evolutionary optimisation strategies. These strategies combine deterministic and stochastic search algorithms. Evolutionary optimisation has demonstrated its performance in high dimensional optimisation problems and results in the global optimum.

Optimisation procedure and extraction strategy

The optimisation procedure takes into account the bias independence of the extrinsic small-signal equivalent elements. The intrinsic elements are optimised for all investigated devices at different bias-conditions keeping the extrinsic elements constant.

Modelling results and extraction of the intrinsic elements

The optimisation procedure described above leads to excellent agreements between measured and modelled data for all parameters the s-parameters with an total error less than 0.6%. The extracted extrinsic small-signal equivalent circuit elements are device independent.

Besides the agreement between measured and modelled data it is important to have a closer look on the extracted intrinsic elements to investigate the influence of the emitter-area scaling. The magnitude of the intrinsic collector resistance is very small, so the influence of this element can be neglected. The value of the resistance is independent of the current density and is correlated to the device geometry.

The following figures demonstrate the influence of the geometrical scaling for the relevant intrinsic elements in the active region at constant collector-emitter voltage VCE = 1.0 V and for constant collector-current densities in the range of SC = 1*103 A/cm2 up to SC = 1*105 A/cm2.

In fig. 1 the extracted values of the combination between the intrinsic base-collector and the feedback capacitance Cjc+Cfb is given versus the collector-current density. The values of the extracted elements of the single-emitter finger HBT are nearly independent of the collector-current density as expected, but an increase of the value for the multi-finger devices with rising density is observed. The magnitude of the capacitances scale up with the emitter-area.


0 10 20 30 40 50 60 70 80 90 1000

50

100

150

200

250

current density Sc [kA/cm2]

intr

insi

c ba

se-c

olle

ctor

cap

acita

nce

plus

feed

back

cap

acita

nce

Cjc+C

fb [f

F]

Fig. 1 Extraction of the combination of the intrinsic base-collector and the feedback capacitance in dependence of the emitter-area at constant bias-conditions ( AE = 1x2x10; : AE = 1x2x20; : AE = 1x2x30; : AE = 2x2x20; : AE = 3x2x20)

The extracted intrinsic base-emitter capacitance is scaled up with the emitter-area, too. The curves saturate for the larger devices at higher current densities. This effect is pronounced for the multi-finger devices due to coupling between the emitter-fingers.

The intrinsic base resistance depends linear on the geometry as shown in fig. 2. For devices with smaller emitter-area the value of the resistance is of cause higher. A decrease with the current density is also observed.

0 10 20 30 40 50 60 70 80 90 1000

5

10

15

20

25

30

35

40

current density Sc [kA/cm2]

intr

insi

c ba

se

resi

stan

ce R

bb [ Ω

]

Fig. 2 Extraction of intrinsic base resistance in dependence of the emitter-area at constant bias-conditions ( AE = 1x2x10; : AE = 1x2x20; : AE = 1x2x30; : AE = 2x2x20; : AE = 3x2x20)

The intrinsic base-collector resistance and the base-emitter resistance strongly depend on the collector-current density and they are linear scaled down with the emitter-area of the investigated device.


Conclusion

The applicability of scaling the intrinsic elements in dependence on the emitter-area using the presented rf-small signal model is demonstrated. The intrinsic elements scale nearly linear with the emitter-area, this information can be used as a scaling tool for circuit simulation.

References [1] D. Peters et al., “RF-Characterization of AlGaAs/GaAs HBT down to 20K”, Proc. Of the 20th Int.

Symposion on GaAs and Related Compunds, Freiburg, Germany, Aug. 1993, pp. 177-182

[2] P. Velling, “A comparative study of GaAs- and InP-based HBT growth by means of LP-MOVPE using conventional and non gaseous sources”, Progress of Crystal Growth and Characterization of Materials, Vol. 41, pp. 85-131, Dezember 2000

[3] M. Agethen et al., “Consistent small-signal and rf-noise parameter modelling of carbon doped InP/InGaAs HBT”, 2001 IEEE MTT-S Int. Microwave Symp., Phoenix, USA, May 2001


4.3.12 Large-Signal Model for the HBT-EAM in PSpice

Student: S. Mahmud Supervisor: T. Reimann

Introduction

The HBT-EAM is a novel electronic device combining a Hetero-junction-Bipolar-Transistor (HBT) with an Electro-Absorption-Modulator (EAM). This is achieved by integrating the 1.55 µm electro-absorption-modulator layers in the collector region of the HBT as shown in fig. 1. The strong electric field in the reverse biased base-collector junction is used to alter the absorption coefficient of the modulator wave-guide according to the Franz-Keldysh-effect. This multifunctional device corresponds to an EAM with an integrated amplifier. Beside its operation as a transistor and a modulator the device can also be used as a photo detector by illuminating the base region and generating a photo current, hence allowing the optical switching of the device. In order to simulate the device an appropriate large signal model is needed. In this report the Gummel-Poon-Model (GP-Model), which is already implemented in PSpice, is extended to describe the DC- and AC-characteristics of the device.

Substrate

n+ Emitter-Cap

n Emitterp+ Base

n+ Sub-Collector/CladdingBuffer

VCB

VBE

(i) Collector/Cladding

(i) Collector/Guide

HBT-EAM

EAM

D

C

B

E

RC

Iph= k*P in

PSpice-Model

Fig. 1 Structure of the HBT-EAM. Fig. 2 Large signal model of the HBT-EAM.

DC-Behaviour

To model the DC- and AC-behaviour of the HBT-EAM the bipolar transistor model in PSpice is extended with additional elements. The additional grown layers of the EAM that are merged in the collector region of the HBT lead to a non-ideal behaviour of the base-collector diode. Hence to fit the DC-behaviour of the model to measured device characteristics a diode between the external and internal collector nodes was added as shown in the in fig. 2. By choosing the appropriate parameters of the diode a good match of the measured und simulated DC-characteristics is achieved as shown in fig. 3. An additional feature of the modified model is a forth-input port (Iph) to allow the optical


control of the device. Here a linear dependence between the incident optical power and the generated current in the base region was assumed. The optical power (Pin) was represented in PSpice by the input voltage of the voltage-controlled-current-source (K*Pin) as shown in fig. 2. The proportionality factor K between the generated current and optical power can be easily obtained by a fit to the measured data. Experiments of the fabricated device showed that only a small part of the light intensity is absorbed in the base region. This is mainly due to the inefficient coupling of the light wave in the experimental set-up. For further simulations though we assume that the optical power absorbed in the device is sufficient for switching the HBT-EAM.

0 1 2 3 4 50

2

4

6

8

10

measurement simulation

colle

cto

r cu

rre

nt

I C (

mA

)

collector emitter voltage VCE

(V)

Fig. 3 Simulated und measured DC-Output-Characteristics of the device.

AC-Behaviour

The parameters of the parasitic capacitances (CJE, CJC, MJE, MJC, VJE, VJC and FC) of the PSpice model were extracted from the measured S-parameters based on a small signal model of the HBT. The parameters for describing the current dependent transit time f are also obtained from measured S-parameters for different biasing points. Since the comparison between the simulated and measured S-parameters was not satisfying the AC-parameters were modified further manually. Here the main effort was concentrated on getting a rough match of the simulated frequency behaviour of the short circuit current gain h21 with the measured results (Fig. 4).

HBT-EAMs

wave guide &Y-divider

100 µm

HBT-EAMR420k

Opt Opt

00

0

R140k

HBT-EAM

R240k

0

OUT

R320k

Ucc10V

V_RESETV_SET

RC1500

0

0

RC2500

0

OUT


Fig. 4 Photograph and a schematic of the fabricated RS-Flip-Flop.

Applications

Finally some simple HBT-EAM circuits were simulated based on the large-signal-model introduced earlier. A possible application of the HBT-EAM is an RS-Flip-Flop, which can either be switched by an electrical or an optical signal. This circuit can be used as a light switcher as an example. Using 2V SET/RESET signals in the simulations only a maximum operation frequency of about 200MHz was achieved. This applies also for the optically initiated switching. In the case of the optical switching the proportionality factor K was adjusted in the simulations so that an optical input signal of 5mW generates a 12mA collector- current at the output of the device. By SET/RESET signals of higher amplitude the simulated circuits become faster. But since the RF-measurements of the device showed a maximum cut-off frequency of about 24GHz higher operation frequencies are to be expected by optimized circuits. fig.4 shows a photograph of a fabricated RS-FF and the schematic of the circuit. Simulation results of an electrically and optically controlled RS-FF by an operation frequency of 200MHz are shown in fig.5. The electrical switching of the RS-FF was also confirmed by measurements for 1MHz operation frequency.

Another application of the HBT-EAM is a simple differential amplifier with an optical input. The optically initiated switching of the Diff-Amp was also confirmed by measurements using an optical signal of 100kHz and a signal power of 3mW.

60 65 70 750

2

4

6

8

10

12

4mW

OUTOUT

OP_RESETOP_SET

optical input OP_SET=4mW, f=200MHz, Ucc=10V

Sig

nal (

V)

t(ns)

Fig. 5 Simulation of the RS-Flip-Flop by optical input signals.

Conclusion

We described here a large signal model of the HBT-EAM based on the Gummel-Poon-Model, which is already implemented in PSpice. At first the DC-behaviour of the device was matched through extending the GP-Model. On the other hand and due to the non-ideal behaviour of the


device the correct extraction of the AC-parameters of the model was extremely difficult, therefore the high frequency behaviour of the device could only be matched roughly. The optical control of the device was modelled by a voltage-controlled-current-source between the internal collector node and the external base node of the GP-Model. Finally basic electronic circuits were simulated to demonstrate possible applications of the new device.


4.3.13 Design of 1:16 Time-Division Demultiplexer for 16 Gb/s

Scientist: J. Degenhardt, G.Grah Technical Assistant: A. Osinski

Introduction

In modern telecommunications the demand on devices capable of working with high data rates increases enormously, not only for transferring data between long distances e.g. optical fiber networks but also for medical systems using high speed electronics like magnetic resonance tomographie.

In high data rate systems bit-streams are generated which have to be reduced in data rate, without loss of information, so that the signals can be processed by baseband electronics. For this task a demultiplexer is used. It divides up a single bit-stream into parallel bit-streams which are reduced in data rate by the same factor as the parallelism increases. A typical application for example a Delta-Sigma ADC generates a sequential bit stream of 16 Gb/s. This is far more as conventional electronic can handle. After signal splitting into 16 channels the data stream was slowed down to a value which is capable for CMOS electronic.

Principles

The circuit topology for the demultiplexer designed in our institute is shown in figure 1. The structure is built up hierarchically with every level dividing the bit-stream by a factor of 2. After splitting every second incoming bit will follow one data flow path. This means that one outgoing bit doubles its length because it takes just one further incoming bit length until the next bit appears at the output. This process equals a division of the data rate by 2.

The selection of every second bit from a bit-stream is done by a MS-D-Flip-Flop.

To realize the function of demultiplexing two MS-D-FFs are needed which operate with an inverted clock signal so that the alternating function of the MS-D-FF isolates single bits out of the incoming bit- stream. This principle is continued on every level in the structure and for any generated bit-stream. So the structure is symmetrical, which is advantageous with respect to timing.

Design

The circuit technique chosen is SCFL (Source Coupled FET Logic) which is based on the differential amplifier as main element which is symmetrical itself. The main element of the demux circuit is the MS-D-FF consisting of two unique D-FFs. The D-FF function is realized by cascaded differential amplifiers, called series gating.


Fig. 1 Circuit topology of the demultiplexer

Fig. 2 Master-Slave D Flip Flop in SCFL


The main advantage of the SCFL is that it can manage differential signals. This is very advantageous at high frequencies not only because of the doubled voltage swing but also because common mode interferences are removed. The SCFL operates between a negative supply voltage and ground to simplify impedance matching, because in this case the load resistor is connected to ground. Both input and output circuit (not show here) are designed to handle 50 Ω line impedance. The input terminal of the DEMUX also consist of an asymmetric-symmetric converter to offer a differential signal for the following stage. The output driver at the join to the CMOS generating the voltage swing by a simple differential amplifier which only one side is used to provide a asymmetric signal.

Compared to other circuit techniques, using D-type FETs, SCFL only needs one supply voltage. In addition, using SCFL, the output swing only depends on the current source and the load resistor.

Device Modeling

These circuit-simulations are only valid if the used models of the circuit elements represent the device behaviour and are accurate to yield a quantitative prediction of the circuit behaviour. Especially in the high frequency operation range modeling of all major devices is very important. Major devices are HFET, diodes, resistors and transmission lines. Necessary for the circuit simulation are large signal models, for adjusting the dc bias point and representing the rf-behaviour of the device with the time-varying bias points caused by the input signal.

Starting point of the device modeling is measured device data. For the most important device, the HFET, the procedure is the following. The dc-characteristics and the scattering-parameters at several dc-bias points are measured between 45 MHz and 40 GHz. With an optimizer program based on genetic methods the values of the small-signal equivalent circuit elements for the HFET(see figure 3) are fitted so that there is maximum agreement between measured and calculated scattering paramters. This optimization is done with the scattering paramters for all measured bias points yielding the small-signal equivalent circuit for every measured bias point. There are bias point dependent and bias point independent elements.

Fig. 3 Small signal equivalent circuit


With this data a large-signal model is established. This can be done using a level 2 MOS-model acting as bias point dependent current source. The bias point dependent Gate-Source and Gate-Drain capacitances can be realized by the capacitance model of a pn-junction diode. These elements, adding some resistors and inductors, can be combined to a subcircuit which represents the large-signal HFET model(see figure 4).

Fig. 4 Large signal model for HFET

Summary

To summarize the reqiurements for the circuit to be developed, a stable design which is robust against variations of technological paramters can be named first. It should have a simple structure to simplify layout and to reduce timing problems, because these are difficult to handle at high frequencies. Apart from this the interface and operating conditions have to be met e.g. data rate, voltage swing, impedance matching, temperature.


4.3.14 Development and Simulation of Digital Circuits for Measure-ment Applications based on HBT-Technology

Student: M. Brysch Scientist: J. Driesen

Introduction

For the characterization of high-speed digital circuits, signal generators are required which are able to provide periodic rectangular signals or even bit-patterns at these high frequencies. The intention of this work was the extension of the existing measurement equipment. As complex circuits a shift-register and a frequency-divider have been realised. These circuits are constructed by standard logic gates (NOR, NAND, XOR) and flip-flops which have been developed prior to these. Additionally, the drive capability into a 50Ω-system and the transformation of a single-ended signal into a differential will be delivered by specially designed input and output buffers.

Development

The central task of these buffers (fig. 1) is to provide a good matching to the 50Ω-system. This is achieved by 50Ω-resistors on the input or on the outputs of corresponding buffer. To guarantee a maximum of failsaveness, all of the circuits in this work are controlled differentially. Therefore, a transformation of the single-ended input signal into a differential signal is needed which is accomplished by the input buffer. Both buffers are based on a differential amplifier stage controlled by emitter followers to increase the drive capability. Higher gain and better determination capabilities are the reasons for the darlington stage implementation of the output buffer. External biasing voltages allow to adjust the current drawing through the current mirror of the output buffer and to adjust the base voltage reference point of the right HBT of input-buffer’s differential pair, respectively. These external control possibilities are responsible for the high flexibility of the buffering circuits referring to supply voltage and input voltage swing.

U

C2

B,T2

T9

M2610CA = 20

R150

R6

R3

bias

R2

T6

M2610CA = 20

T4

M2610CA = 20

R9

Out

T3

M2610CA = 20

R5T7

M2610CA = 20

T1

M2610CA = 20

T8

M2610CA = 20

Uee

In

OutN

C1

biasT1

R4

R8

UT2

M2610CA = 20

R7

T5

M2610CA = 20

U

ee

R5

T10

M2610CA = 20

OutN

R4

T9

M2610CA = 20

T3M2610CA = 20

T8M2610CA = 20

T2

M2610CA = 20

R150

T1

M2610CA = 20

Out

U

T6

M2610CA = 20

R7

In

R3

InN

R6

T7

M2610CA = 20

T4M2610CA = 20

R2 50

biasU

Fig. 1 Schematic diagrams of the input-buffer (left) and the output-buffer (right)


All logic gates and flip-flops designed in this thesis have been implemented in E2CL technology which is based on a differential amplifier stage. An additional and especially typical characteristic for this logic family is the emitter follower at each input. Not only the schematic diagrams of the NAND and the NOR logic gates shown in figure 2, but also the schematic diagrams of the XOR logic gate and the simple D-type flip-flop shown in figure 3 present a very similar topology.

AN

M2610CA = 20

M2610CA = 20

BN

R2

T3M2610CA = 20

T8

T14

M2610CA = 20

T5M2610CA = 20

M2610CA = 20

R1

R5T13

R7

M2610CA = 20

T2M2610CA = 20

B

R4

M2610CA = 20

M2610CA = 20

A

QN

T10

M2610CA = 20

T12

T7

T1M2610CA = 20

U

R8

ee

T6

T11

T9

T4M2610CA = 20

R6

M2610CA = 20

Q

R3

BN

R2 R1

R3

T4M2610CA = 20

M2610CA = 20

T11

R4

M2610CA = 20

T2M2610CA = 20

Q

M2610CA = 20

M2610CA = 20

R5

T7

M2610CA = 20

T3M2610CA = 20

M2610CA = 20

M2610CA = 20

T14

T5M2610CA = 20

T6

T1M2610CA = 20

QN

T10

T12

T9

ee

A

M2610CA = 20

AN

R7

B

T13R6

T8

R8

U

M2610CA = 20

Fig. 2 Schematic diagrams of the NAND logic gate (left) and the NOR logic gate (right)

Fig. 3 Schematic diagrams of the XOR logic gate (left) and the D-type flip-flop (right)

To increase the maximum working frequency, the use of a current feedback resistor (e.g. R3 for the NAND gate) becomes necessary. It connects the emitters of the lower differential pair. To achieve lower influence of supply voltage fluctuations, current mirrors with two output transistors are used as current sources instead of emitter resistors. Furthermore, the collector currents are independent of the output voltage swings and the current limiting effect of this current source implementation prevents a possible destruction of the HBT. The D-type flip-flop shown in figure 3 is a simple latch. It is level-triggered, and it stores the incoming data when the clock signal is low, otherwise it is transparent.

R7

T1

M2610CA = 20

T14R6

T10M2610CA = 20

M2610CA = 20

R8

R2

BN

R3

R1

M2610CA = 20

T6

T3

M2610CA = 20

T12T11

R4

M2610CA = 20

M2610CA = 20

A

QB

R5

T7

T15

M2610CA = 20

T8M2610CA = 20

M2610CA = 20

QN

U

T2

M2610CA = 20

T13

T5M2610CA = 20

M2610CA = 20

T9M2610CA = 20

T4

M2610CA = 20

ee

AN

T2

M2610CA = 20

D

T4

M2610CA = 20

M2610CA = 20

R7

Q

CLKM2610CA = 20

R5T14

M2610CA = 20

M2610CA = 20

T7

M2610CA = 20

R6T15

R8

T8

R2

T1

M2610CA = 20

M2610CA = 20

QN

CLKN

U

R3

R1

M2610CA = 20

T6

T13

M2610CA = 20

T12

ee

T11

T3

M2610CA = 20

T5M2610CA = 20

DN

T9M2610CA = 20

T10M2610CA = 20

R4


T24

T8

R2

M2610C

T21

M2610C

A=20

A=20

QN

T13

M2610CA=20

A=20R13

ee

T11

M2610CA=20

A=20

R12

M2610C

T22

R8M2610C

A=20

A=20

T25

M2610C

T23

R5

M2610C

A=20

A=20

R3

R10

M2610C

T27

R6

M2610C

A=20 R4

M2610C

T5

CLK

A=20

A=20

T14

T1

M2610C

R9

M2610C

DN

A=20

A=20

T15

T2

M2610C

R15

T6

A=20

U

M2610C

T3

M2610C

R16R7

M2610C

T4

M2610C

T28

A=20

T12

M2610C

T9

M2610C

T16

A=20

A=20

T7

Q

D

M2610C

T10

A=20

T17

A=20

A=20

T26

M2610CM2610C

T18

A=20

A=20

R11

CLKN

M2610C

T19

A=20

A=20

M2610C

R14

R1

M2610C

T20

M2610CA=20

A=20

M2610C

Fig. 4 Schematic diagram of the master-slave D-type flip-flop

The master-slave D-type flip-flop shown in figure 4 consists of two stages. The left one is called master and the right one slave. It reads the data on the input and let it pass to the output on the falling edge of the clock. Both stages, the master and the slave stage, are transparent alternately - when the clock signal is high the master-stage is transparent, the slave is latched, and vice versa. Flip-flops of that kind are required for the synchronous clocked shift register shown in figure 5 whereas the frequency divider requires simple latches with inverted clock signal to each other. All circuits were designed using HSPICE and ADS.

Out

AN

OutN

BN

D-FF

B

D

Q

DN

QN

OutN

CLK

Input-Buffer

NOR

High

CLKN

OutQDN

QN QNCLKIn

A

Q

OutCLK

D

OutN

Output-BufferCLKN

In

D-FF

InN

Low

Input-Buffer

QN

Out

OutN

DN

CLK

CLKN

D

D

CLK Output-BufferDN

QQ

CLKN

Q

OutN

QN CLK

D Out

CLK

InN

In

QN

QDN

Out

DND

MS-D-FF MS-D-FF

CLKN

Out

Input-Buffer

In

CLKN

MS-D-FF

In

QNCLK

MS-D-FF

D

OutN

OutN

Fig. 5 Schematic diagrams of the 4-Bit shift-register (left) and the 2:1 frequency-divider (right)

Simulation results

The developed circuits have been simulated referring to following criteria: input voltage swing and supply voltage flexibility, low reflection, noise margin, fan-out. A very important property is the ability to operate with smallest input voltage swings down to 0.25V. But input voltage swings below 0.5V have an influence on the gain – the output voltage swing decreases. Many kinds of input voltage waveforms will be accepted including sinusoidal voltages with and without DC offsets. The supply voltage has no influence on the transmission behavior down to |-3V| for the input buffer and down to |-3.5V| for the output buffer.


Input-Buffer Output-Buffer

maximum working frequency <20GHz <25GHz propagation delay time 15ps 10ps

reflection coefficients (S11, S22) S11=-10dB at 33GHz S22=-10dB at 25GHz supply voltage >|-3V| >|-3.5V|

input voltage swing >0.25V -

Tab. 1 Technical specifications of the input- and the output-buffer

This kind of flexibility is only given when the current drawing through the current mirror will be adjusted correspondingly. The essential simulation results are summarized in table 1. The supply voltage flexibility is a criterion that played an important role analyzing the behavior of the logic gates. Due to decreasing collector currents which cannot be adjusted by a biasing voltage and the saturation behavior of bipolar transistors, the performance decreases drastically at supply voltages lower than |-4.5V|. But lower supply voltages have no influence on the noise margin. To determine the propagation delay time of each gate type, ring oscillators have been designed. Table 2 contains the essential simulation results of the standard logic gates.

NOR-gate NAND-gate XOR-gate

maximum working frequency

<15GHz <15GHz <8.3GHz

propagation delay time 10ps 10ps 12ps fan-out 6 6 6

supply voltage >|-4.5V| >|-4.5V| >|-4.5V|

Tab. 2 Technical specifications of the standard logic gates

To check their functionality, the 4-bit shift register and and the 2:1 frequency divider have been simulated. The fan-out is a limitating factor in constructing synchronous clocked shift registers because the distorted clock signal steepness gets low and both stages of the master-slave D-type flip-flop are transparent for a short time. The working frequency range of the 2:1 frequency divider is between 9.5GHz and 20GHz.

Acknowledgement

Thanks to Innovative Processing AG (IPAG), Duisburg, for providing the device models based on their technology for this thesis.


4.3.15 Developement of a D-FF as Part of a Demultiplexer

Scientist: J. Degenhardt, G.Grah Technical Assistant: U.Doerk

Introduction

As part of the EU project No. IST-2001-33468, „SuperADC”, the HLT is developing an 1:4 demultiplexer. The design is based on MS-D Flip Flops, build in differential amplifier technology shown in Fig.1 . The differential line driver are capable to support 50 Ohm line impedance. For a flexible developement of the circuit layouts most of the layers were exposed by EBL.

Fig. 1 Circuit diagram of MS-D Flip Flop including input and output line driver

Due to the general problem of testing sub-sequentional functions in complex circuits and to decouple in-circuit testing from the impedance of the probe tips, a set of modified circuit was build. These layouts allow to access partitional functions of the circuit with a proper out-coupling of RF signals by line driver. Additional, test pads were placed in a 2nd layout at the signal lines to monitor the set-point of transistor biasing. Fig. 2 shows the test layout for a direct link between an input driver and an output driver. This test circuit was build and tested on RF performance (whitout test pads), shown in Fig. 3 .


Fig. 2 Test layout with IO-Buffers and modified D-FF core including differential high speed signal lines

Fig. 3 Timing of input-output signals for periphery buffer configuration with differential signal line


The RF – performance of the IO-driver with a long, differential, signal path shows good transmission results to about 2.7 GHz but suffer from not optimal matched termination resistors (see Fig.3). The input reflection and output signal are not consistent with the simulation.

D-FF core with IO-buffers

In a next development step we include a D-FF core in the center of the circuit layout from Fig. 2. A second input is necessary to feed the clock signal in the D-FF core additional to the data-in port. This input driver is placed on the bottom line of the layout field (not fully visible in Fig. 2).

The layout in Fig. 2 is part of the layout studies, technological process optimization and DC circuit tests. DC measurement at half side of a D-FF demonstrating the static functionality of the circuit, as displayed in Fig. 4. With high clock signal at the left branch of the D-FF, the left differential amplifier is activated. This state can be seen in the data plot as a diagonal step in the output data field. Otherwise with low clock input the output data is high with any input signals. The differential input signals are represented by the vector (Uin1, Uin2 ) depict in Fig. 4b. Along this direction the differential amplifier switches from high to low. These measurements were performed with a HP4145 curve tracer and data enhancement software.

a) b)

Fig. 4 Switching behavior of a part of the D-FF related to the clock and data signals

Summary

The handling of all ports and test pads of complex circuits reveal the basic conflict of testing. To explore the circuit behaviour in specific detail aspects, specialized layouts are extracted from a master layout where the complete circuit is covered in. Extracted layout with special adaption to core testing was used and produced by electron beam lithography. Down scaling of circuit elements will be the next step in development which goes along with a reduction of parasitic circuits elements to meet the specified RF performance.

146 Bi-Annual Report 2002/03 - Solid-State Electronics Department

4.3.16 Development of an Optoelectronic Preamplifier Based on HBT-Technology

Student: R.Bednorz Supervisor: G.Janssen, J. Driesen, W. Brockerhoff

Introduction

The monolithic integration of photodetectors and HBT-preamplifiers provides several advantages like small parasitic capacitance, inductance and short feedback paths due to the vertical structure of the HBTs. Additionally the InP/InGaAs-material-system offers a simple fabrication: By using the InGaAs-base-collector junction of the HBT neither additional epitaxial steps nor additional processing steps are necessary for the fabrication of the PIN-diode. The transimpedance amplifier is a well suited concept for such a realization.

Development

The receiver circuit utilizes a high-gain three stage transimpedance amplifier. Two different amplifiers have been realised comprising a common-emitter and cascode input stage. The feedback resistor Rf is connected through a buffer stage for decoupling the input and the output of the first stage. The third stage output buffer delivers the drive capability into a 50 Ω-system. All circuits were designed using SPICE. Additional simulations have been done with a model of an optimized standalone PIN-diode structure (M2299) to show the influence of the HBT structure on the behaviour of the PIN-Diode response.

Fig. 1 Schematic diagram of the three stage transimpedance amplifier comprising a common-

emmiter amplifier for the first stager followed by two buffer stages

R

Q

pin

R

Q

Q

1C

2

V

4

Q

Q

pin

Q

LR

f

c

R

V

1

3

V

2

cc

R

Q

R5

ee

f

6

7

b2

D

Rb1

Bi-Annual Report 2002/03 - Solid-State Electronics Department 147

Simulation results

Fig. 2 shows the transimpedance function of both simulated optoelectronic amplifiers optimized for maximum bandwidth. According to the value of ZTBW in figure 3 the main amplifier response improves using the cascode input, but only at higer values for the transimpedance. At lower values where the bandwidth increases, peaking around the cutoff-frequency becomes inacceptably high and the feedback resistor has to be set to greater values compared to the common-emitter input stage. In this case no bandwidth increase can be achieved using the cascode input, but an optimized behaviour for higher values of ZT. So in applications with desired high bandwidth the common-emmiter input amplifier should be preferred where the cascode amplifier is suited for lower bandwidth applications i.e.10 GHz. In this case the feedback resistor can be increased with the effect of reaching very high values of transimpedance. The integrated PIN-Diode M2610 shows an inferior performance compared to the optimized standalone PIN-Diode M2299. Nevertheless the achieved bandwidth of about 30 GHz represents a good result for an optoelectronic receiver using a transimpedance amplifier structure.

Fig. 2 Simulation results for the optoelectronic preamplifiers with common-emmiter amplifier showing the simulated transimpedance function for several input configurations

Fig. 3 Achieved values for bandwitdh and corresponding transimpedance

Frequency

100KHz 1.0MHz 10MHz 100MHz 1.0GHz 10GHz 100GHzdb(V(out)/ I(Iin))

30

35

40

45

w/o PIN-Diode

PIN-Diode M2610

PIN-Diode M2299

Tra

nsim

peda

nce

ZT /

dB Ω

→

≈ 10000 ΩGHz ≈ 3000 ΩGHz ZTBW

45.3 dBΩ 40.6 dBΩ M2610

46.5 dBΩ 40.6 dBΩ M2299

49.2 dBΩ 43.1 dBΩ w/o PIN-D. ZT

20.7 GHz 29.2 GHz M2610

24.1 GHz 36.3 GHz M2299

24.4 GHz 39.9 GHz w/o PIN-D. BW

TIA w/ cascode amp. TIA w/ c.emitter amp


Parasitics

Parasitic capacitances and the length of the feedback path have been extracted from the realised layout and included into the circuit to show the influence on the performance of the optoelectronic receiver (Figure 4). The feedback path has been simulated by a transmission line model. Figure 5 shows that capacitances due to crossings of different mettalization paths don`t affect the amplifier performance at all. On the other hand the length of the feedback path is very important for the bahaviour of the amplifier and has to be considered when setting the value of Rf. With increasing length of this path the peaking around the cutoff frequency drastically reaches inacceptable values. So in the design of the mask layout the lenghts of the connections should be kept as short as possible.

Fig. 4 Schematic of the transimpedance amplifier with common-emmiter input amplifier with

extracted parasitic elements

Fig. 5 Simulation results for the transimpedance with extracted parasitic elements showing the response for ideal and included capacitances and transmission line model

Frequency

1.0GHz 3.0GHz 10GHz 30GHz 100GHzdb(V(out)/ I(Iin))

30

35

40

45

Tra

nsim

peda

nce

ZT /

dB

ideal

+parasitic.

+parasitic cap & transmission line

1.92f

2.24f

T

1

R

2

5

c

Q

4

Input

R

b2

1.92f

Q

R

1.92f

R

2

Z =130

Q

1.92f

L0

ee

R

V

3

R

Q

tau=1.8ps

1.92f

b1

1.92f

cc

7Q

6

f

V

Q

R

Q1


4.3.17 Re-Design of a 40 GHz Broadband Amplifier Based on HBT-Technology

Student: R. Bednorz Supervisor: G. Janßen, W. Brockerhoff

Introduction

Broadband amplifiers play an important role in optical transmission systems and test instruments. In case of fiber optical communication systems the commercial use has reached the 10 Gbit/s domain and there`s a demand to increase the data rate to 40 Gbit/s in next generation systems like OC-768. HBT-technology is well suited for achieving the requirements for the realisation of such systems.

Development

The pre-designed post-amplifiers were based on lumped circuit design and showed a insufficient performance for the use in 40Gbit/s-systems. In the re-design process amplifiers comprising a distributed structure have found to be the best choice to cover up all the requirements. Post-amplifiers with two different output configurations were developed using this circuit architecture, single ended and differential, respectively. Fig. 1 shows the schematic diagram of the two stage single ended post-amplifier. A three stage version has also been realised. By adding a single ended to differential converter and an output buffer (Figure 2) differential outputs can be provided.

Fig. 1 Schematic diagram of the two stage distributed amplifier comprising an emitter follower and cascode stage per amplifier cell

7

41

V

Q

A = 2x10

13

7CPW

2

V

Q

A = 2x10

CPW

Vb1

14

CPW

3R

V

term2

Q

A = 2x10

15

4

6

CPW

CPWR

R

Q

A = 2x20

5

CPW

term1

1

8

V VV

9

cc

2

10

Q

A = 2x5

Q

A = 2x5

cc

10

9

Q

A = 2x20

cc

11

ext

6

R

R

V

In

cc

12

1

Q

A = 2x5

b2

3

2

Q

A = 2x10

Q

A = 2x5

V

Out

b1

R

3

Q

A = 2x5

CPW

Q

C

Q

A = 2x10

b2V

5

1

C

C

CPW

cc

6

3

CPW

cc

4

5

R

CPW

Q

A = 2x5R

C

8

2

Q

A = 2x10


Good matching characteristics between both output channels have been achieved by using optimized micro-strip-line (MSL) and coplanar wavegide (CPW) elements in the converter and output buffer stage. All post-amplifiers utilize a distributed amplifier structure comprising an emitter follower and cascode stage per amplifier cell. The wiring ist accomplished by CPW. All circuits were designed using Agilent`s Advanced Design System.

Fig. 2 Schematic diagram of the single ended to differential converter and output buffer featuring additional active microstrip and CPW-elements to improve matching between both channels

Simulation results

Fig. 3 shows the simulation results for the re-designed two and three stage post-amplifiers with single ended output. The voltage gain was optimized for a Bessel-filter type characteristic to achieve low group delay variations which corresponds to an improved impulse response of the amplifier. Voltage gains of AV=12.9dB and AV=18.8dB at bandwidths of f-3dB=49.5GHz and f-3dB=44.4 GHz have been reached for the two and three stage versions of the distributed amplifier. Also low group delay variations ∆τgrp and low input and output reflection coefficients s11, s22 have been achieved for both amplifiers. According to Fig. 4 the post-amplifier with differential outputs achieved much larger values of voltage gain. That was possible by using the converter and output buffer stages for additional gain to achieve a total voltage gain of AV=28,6dB per channel at a bandwidth of f-3dB=44,8 GHz. This corresonds to gain-bandwidth-products of GBWSE=1,21 THz and GBWDiff=2,42 THz in single ended and differential mode respectively.

13

R

Q

A = 2x10

R

MSL

C

14

11

12

R

Out

1

1 R

Q

A = 2x10

9

QA = 2x10 5

cc

R

R

Q

A = 2x10

byp

4

9

2

V

Q

A = 2x10

R5 6

10

15

7

R

10

R

Q

A = 2x10

R

MSL

5

Q

A = 2x10

Q

A = 2x10

3

2

CPW

R

13

2

8

MSL

17

CPW

8

MSL

TWA

3

7

R

MSL

3

2

QA = 2x10

CPW

N

7

6

R

Bias

MSL

11

3

R

MSL

R

1

4

R

6

CPW

Q

A = 2x10

16

Q

A = 2x5

12

Out

Q

A = 2x5

1

Q

A = 2x5

R

4

MSL

4

8

P


Fig. 3 Simulation results for the re-designed two and three stage post-amplifiers with single ended output

Layout

Fig. 5 shows the realised mask layout of the three stage post-amplifier with single ended outputs. By the use of a co-design between circuit and layout, it was possible to consider most of the critical parasitic and distributed effects of the layout. Also an optimized on-chip wiring of the power rails was used to mnimize the parasitic inductance of this paths. The resulting chip-size is 1500x1000µm² each.

Fig. 4 Mask layouts of the re-designed post-amplifiers with single ended (left) and differential output (right)

0 10 20 30 40 50 600

2

4

6

8

10

12

14

16

18

20

Bessel

volta

ge g

ain

AV /

dB

frequency f / GHz

2 stages

3 stages


4.3.18 Development of a Low-Noise Optoelectronical Front-End Amplifier Based on HEMT/HBT Layers

Student: A. Matiss Supervisor: W. Brockerhoff, G. Janssen (IPAG)

Introduction Each optoelectronic circuit has a defined optical minimum power level that has to be applied to the entrance of the photodetector to detect a certain bit stream pattern at the output of the amplifier[1,2]. This required minimal power defines the optical sensitivity of the circuit[3]. This thesis deals with the development of an optoelectronic transimpedance amplifier and the optimization of the optical sensitivity. The paper will explain those parts of an amplifier that contribute to the entrance noise current, which is a direct proportion of the optical sensitivity. Also, other parts that have influence on the optoelectronic performance of the device will be looked at.

Description Based on an Indium-Phospide-Substrate (InP), an optoelectronic transimpedance amplifier (TIA) has been developed. The InP substrate is covered with several different layers that allow the production of certain electrical and optoelectronical elements. For the amplifier that is being presented a combination of Heterostructure-Bipolar-Transistor (HBT), High-Electron-Mobility-Transistor (HEMT) and, based on the base-emitter layers of the HBT, a pin-Diode has been used. Therefore the resulting amplifier consists only of monolithically integrated elements.

The first stage of the electrical amplifier has been build up with a HEMT-cascode that provides a 7dB lower input noise current than an equivalent HBT-cascode. Due to the HEMT noise parameters and the higher 3dB-frequenzy, the HEMT shows a better performance as low-noise amplifier than the HBT. Although the HEMT shows good parameters as an amplifier, the output of the first stage has to be decoupled against unwanted influence of the load towards the amplifier. A capacitive load decreases the bandwidth of the HEMT-cascode to a great extend. Therefore a HBT collector circuit has been put behind the HEMT-cascode output to compensate this effect. The HBT collector circuit provides the HEMT with a low load capacity due to its small emitter-size. To avoid mismatches between the output and the load, a third stage has been implemented which involves using a HBT collector circuit with a serial resistance to adjust the output reflection parameter. The collector circuit with a serial resistance is the easiest way to realize an output circuit matched to 50Ω, and it also provides a lower influence on the noise current at the entrance of the amplifier than a differential output. The differential circuit design with HBT has a slightly higher influence on the input noise current due to the resistors that provide the fitting to the 50Ω environment. The resulting three stage amplifier, consisting of a pin-diode connected to the HEMT-cascode and HBT in the transimpedance amplifier, was tested to optimize the minimally required input power. A significant effect on the optical sensitivity has been related to certain parameters in the TIA-design.


Fig.1 Optical sensitivity in dependence on Gate width

Fig.2 Input noise power in dependence on feedback resistor Rf

The gate-width as well as the impedance of the cascode-resistor show a slight decrease of the optical sensitivity under some circumstances. The cascode-resistor effects the optical sensitivity mainly at high frequencies. This influence can be minimized by increasing its value. The gate-width on the other hand shows a minimum of the optical sensitivity at a certain width (Fig.1). Therefore it is necessary to determine this point and adjust the stage to fit the optimal parameters. Furthermore the optical sensitivity is very much influenced by the feedback resistor (Fig.2).

The optical noise power decreases with the value of the feedback resistor. Another critical point in the circuit is the optical to electrical behaviour of the pin-diode. Due to a direct proportion of the responsivity of the pin-diode to the optical sensitivity (Fig.3), the best results will be achieved by increasing the responsivity to a maximum value.

40 60 80 100 120 140 160 180 20 200

-19.0

-18.8

-18.6

-18.4

-18.2

-19.2

-18.0

Gate width / µm

Opt

ical

sen

sitiv

ity /

dBm

1E9 1E10 1E8 2E10

10

20

30

40

50

0

60

Frequency / Hz

I

nput

noi

se p

ower

/ pW

/√H

z

200Ω

2000Ω

Rf


Fig.3 Input noise power in dependence on pin-diode

Furthermore it has been determined that the length of the micro strip line between pin-diode and the input of the amplifier also influences the optical sensitivity. It was not possible to improve the performance of the whole circuit by adding a matching network between the pin-diode and the TIA. It also turned out that special attention has to be paid to the length of the micro strip lines while designing the layout of the amplifier. Every line that carries the RF-signal, especially in the feed-back conductor, takes influence on the input noise power and therefore on the optical sensitivity.

Conclusion

This thesis covers different topics. It starts with some basic noise theories that are necessary for the understanding of the noise processes in the transistor models. Furthermore it contains the applied models for the HBT, HEMT and pin-diode with some characteristic diagrams and parameters. Also, the basic parameters of optoelectrical amplifiers and some basic noise-related optical sensitivity theories are covered. Different amplifier designs have been tested and are presented. The thesis describes how a transimpedance amplifier is build up and focuses on the critical elements in the design that have to be considered when optimising for high optical sensitivity. Five design parameter have been determined. First, the feedback resistor and the pin-diode mainly dominate the optical sensitivity. Furthermore, the influence of the electrical connection between pin-diode and amplifier has to be considered. Additional effect show the cascade resistor and the gate-width of the HEMT-cascode.

Also, some details about the different stages are discussed and their advantages and disadvantages are pointed out. Finally two complete optoelectronic transimpedance amplifier have been created and are presented. Some examinations about the dependency of different parts in the amplifier towards the optical sensitivity were done and the results are presented. This thesis closes with presentation of the final circuit layouts and the simulation results.

1E9 1E10 1E8 2E10

10

20

30

40

50

0

60

Frequency / Hz

I

nput

noi

se p

ower

/ pW

/√H

z

integrated pin-diode (R=0.405)

improved pin-diode (R=0.474)


References: [1] Johan Sjöström; “Measurement and Modeling of Photodetectors for Monolithic Optoelectronic

Receivers for Bit Rates up to 40 Gb/s.”; Master of Science Thesis, Stockholm, April 1998

[2] G. Janssen, R. M. Bertenburg, F.-J. Tegude; “Optimierung eines Transimpedanzverstärkers für optische Empfangssysteme mit Bitraten von 500 Mbit/s bis 2.5 Gbit/s und hoher Empfindlichkeit”; Universität Duisburg, 1994

[3] Stefan van Waasen; “Wanderwellenverstärker für hochbitratige monlithisch integrierte Photoempfänger auf Basis von InAlAs/InGaAs/InP-Heterostruktur-Feldeffekttransistoren”; Universität Duisburg, Dissertation, 1999


4.3.19 Design and Fabrication of a MOBILE-Gate with an Optical Input

Student: S. Mahmud Supervisor: E. Khorenko, J. Driesen

Introduction

The ultra-fast switching speed and the negative differential resistance characteristic of resonant tunnelling diodes (RTD) make them ideally suited for the design of high-speed, high compact, low-power logic circuits. The MOnostable-BIstable transition Logic Element (MOBILE) [1] exploits the negative differential resistance (NDR) of the RTD to perform logic functions. It consists of two serially connected RTDs, that are driven by an oscillating bias voltage, combined with a current modulation device. In recent years many MOBILE circuits based on RTDs in conjunction with high-performance III/V-devices such HBTs und HFETs have been studied and demonstrated. One promising application of MOBILE gates is the optical control of high-speed electronic systems by using high speed photodiodes as input gates for MOBILEs instead of transistors [2]. Such a circuit is very attractive for realizing regenerative functions in optical communications. In this report we describe the design and fabrication of a monolithically integrated MOBILE circuit with a pin-diode at the input and an output amplifier based on HFETs.

Circuit Design and Layout

The optical controlled MOBILE-Gate introduced in [2] makes use of a Uni-Travelling-Carrier Photodiode (UTC-PD) as the current modulation device. In our circuit the optical input is realized by a pin-diode connected parallel to the driver RTD. For simulating the circuit with HSpice an analytical RTD-Model based on the Large-Signal DC-Model of Z. Yan, M. J. Deen [3] was implemented. Fig. 1 shows the schematic of the optoelectronic circuit and a micrograph of the fabricated IC.

To ensure high frequency operation of the MOBILE the devices must be scaled properly. On one hand the ac-currents must be taken into account while scaling the devices, on the other hand the cut-off frequency of the pin-diode must not be the limiting factor of circuit’s operation speed. The fabricated pin-diodes have a diameter of 15/25 µm depending on the area of the RTDs in the circuit. The realized RTDs have areas between 5-45 µm². The out-put amplifiers were realized by HFETs with a channel length of 1 µm.

Process Technology

The whole layer stack was grown by Metal Organic Chemical Vapour Deposition (MOCVD). The layers of the Hetero-Structure-Field-Effect Transistor (HFET) were grown at first on the InP-substrate, followed by the layers of the RTD. The pin-Diode was grown on top of the RTD-layers resulting in 1400 nm thick layer stack. The HFET consists of a heavily doped InGaAs contact layer, an i-InGaAs layer, an InAlAs (or InP) schottky layer, a heavily doped InP, an i-InP spacer (3,5 nm), an i-InGaAs channel and an InP-buffer, which separates the transistor and the substrate. The RTD is made of an InAlAs/InGaAs/InAlAs (5 nm /5 nm /5 nm) double-barrier structure and n+-InGaAs


contact layers. The double-barrier structure and the contact layers are separated by a thin i-InGaAs spacer (3 nm). The pin-diode layers consist of a p-InGaAs contact layer and a 600 nm i-InGaAs absorption layer. To reduce the process steps, the n-contact of the pin-diode and the Anode of the RTD are combined in one layer (n+-InGaAs).

RTDLoad

RTDDriver

pin-Diode

Vout

Vref

Vclock

MOBILE DiffAmp

50 Ohm

Iph

50 Ohm

a) b)

RTDD

RTDL

Fig. 1 The Schematic of the optoelectronic circuit a) and a micrograph b) of the fabricated IC.

The circuit was processed by conventional wet-etching. For forming the mesa of the pin-diode and RTD a phosphorus acid/hydrogen peroxide solution was used. The mesa of the HFET was formed by a citric acid/hydrogen peroxide solution. For the Gate-Recess either phosphorus acid or citric acid/hydrogen peroxide solution was used depending on the type of the barrier layer (InP or InAlAs). The layers of the different devices were separated by i-InP etch-stopper layers to enable selective wet etching with the phosphorus acid. All electrodes were formed by metal evaporations and lift-off technique. Due to the high mesa of the pin-diode and the RTD air bridges were used to contact these devices.

Results

The DC and RF-measurements of the pin-diode showed that it exhibits a responsivity of 340 µA/mW and a cut-off frequency of 7.2/4.5 GHz (15 µm/25 µm) by a bias voltage of 0,25 V. The differential amplifier operated up to a frequency of 1.5 GHz. The RTDs in the first fabricated samples failed. It showed almost a pure linear behaviour. One possible reason for this problem might be the silicon diffusion from the heavily doped contact layers of the RTD into the thin double barrier structure. After reducing the doping concentration in the contact layers functioning RTDs with a PVR of 2 were demonstrated. Fig. 2. shows the output characteristics of the fabricated MOBILE –output buffer circuit at fclock=150 MHz.


0

0.05

0.1

0.15

0.2

0.25

0.3

7.20E-08 7.40E-08 7.60E-08 7.80E-08 8.00E-08 8.20E-08

Time / s

Iin=2.5mA

Iin=0mA

Fig. 2 Output characteristics of the fabricated MOBILE –Output buffer circuit at fclock=150 MHz.

Summary

An optoelectronic integrated circuit composed of RTDs, pin-diodes and HFETs was fabricated. The layer stack was grown by MOCVD on an InP-substrate. Whereby the HFET was grown at first on the substrate, the RTD in the middle and the pin-diode on top of the stack. After optimising the epitaxy process RTDs with almost the same characteristics as the RTDs grown directly on the InP-substrate were demonstrated. Measurements of the circuit at frequencies up to 10 GHz is in progress.

Acknowledgments

The authors are grateful to Mr. P. Velling from Innovative Processing AG for the MOCVD growth of the fabricated chips.

References: 1) K. MAEZAWA and T. MIZUTANI; “A New Resonant Tunneling Logic Gate Employing

Monostable-Bistable Transition”, Jpn. J. Appl. Phys. 1993.

2) K. Sano, K. Murata, T. Otsuji, T. Akeyoshi, N. Shimizu and E. Sano, IEEE Journal of Solid State Circuits, VOL. 36, NO. 2. February 2001.

3) Z. Yan, M. J. Deen; “A New RTD Large-Signal DC Model suitable for PSPICE”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VOL. 2, NO. 14, February 1995.

160 Annual report 1996 , Fachgebiet Halbleitertechnik/Halbleitertechnologie

160

4.4 Nanoelelectronics


4.4.1 Formation of Zero-Dimensional Nanostructures by Epitaxial Overgrowth of Gas Phase Generated Indium Nanoparticles

Scientist: V. Khorenko K.Nanda1, E.Kruis1 1Dept.of Process- and Aerosol Measurement Technology, University

Duisburg-Essen

Introduction

The use of nanoparticles allows for the massive parallel fabrication of quantum structures without the necessity of very high resolution lithography. Within the framework of the project “Nanoparticles in epitaxial heterostructures” we develop a novel approach to fabricate zero-dimensional nanostructures (quantum dots) eliminating the restrictions of the well known Stranski-Krastanov growth method [1] on the size and number of the particles constituting quantum dots, as well as on the type of materials available (from isolators to metals). By particle generation and subsequent epitaxy a nanostructures shall be produced and embedded into the host lattice. As a model system, we started with Indium nanoparticles which are to be implemented as group III element into a III-V-compound semiconductor.

Synthesis and deposition of nanoparticles

The monocrystaline nanoparticles were synthesised in the gas phase by condensation of the indium vapour in nitrogen flow followed by in-flight heat treatment (for details please refer to [2]).

Fig. 1 Technological realization of proposed approach for fabrication of zero-dimensional nanostructures

MBE Varian Gen II

facilities for nanoparticles deposition

Carrier gas

N2

furnace 1(T up to 1100 °C)

furnace 2(T up to 200 °C)

differentialmobility analysor

evaportation and coagulation HV

HV

sintering monodisperse size distribution

depositionchamber

charger

size selection

monocrystalline nanoparticles


For our experiments, the size of the nanoparticles selected by a differential mobility analyser (DMA) was 20 nm with a standard deviation of less than 10%.

.Fig. 2 In nanoparticles after deposition on substrate. Left – TEM, right – SFM image

For the chosen deposition time of 10 minutes the density of nanoparticles on the surface was ~ 5.1 irmed near tothe spherical shape and narrow size distribution of the synthesised nanoparticles (Fig 2). The data of EDX and XPS measurements show that indium in nanoparticles were presented mostly in metalic form, but a small part of this one (surface) is oxidised. A reason for this oxidation is transfer of the sample after nanoparticles deposition to the EDX chamber in air.

Epitaxial overgrowth

Preparation of the substrates and overgrowth of indium nanoparticles were performed by standard solid source molecular beam Epitaxy. The MBE Varian Gen II machine was used. The preparation step before deposition of nanoparticles included growth of the 200 nm GaAs buffer layer followed by a few nanometer thick layer of metallic As in order to protect the sample surface from oxidation during transfer. After nanoparticles deposition and transfer back to the MBE, the samples were overgrown with GaAs. For the overgrowth process, different temperatures from 200 to 400 °C were tested. The possible mechanisms for transformation of metallic In nanoparticles to semiconductor In(Ga)As nanostructures are the material exchange between the particles and surrounding GaAs matrix and the interaction of the nanoparticle material with As molecular beam. Efficiency of these processes is depend on the purity of the nanoparticles and the temperature. Despite the melting of In already at 146 °C, only temperatures higher then 350 °C can be used. This limit is defined by desorption of protective As layer. Unfortunately, unavoidable oxidation of nanoparticles during sample transfer and the presence of the thin oxide layer on the surface of nanoparticles strongly influenced interdiffusion as well as the quality of the following epitaxial layer. The sample with In nanoparticles overgrown at 450 °C was characterised by photoluminescence. The PL spectra taken at 30 K show a peak at ~0.72 eV corresponding to InxGa1-xAs (Fig.3). An exact identification of the composition of the nanoparticles modified by the overgrowth process is difficult yet .

~20 nm

T= 30 K

FWHM = 18 meV

E = 0.752 eV

E [eV]


Fig. 3 Low temperature PL spectra from the nanoparticles overgrown at 500°C

The FWHM of 18 meV confirm the SFM data about narrow size distribution of nanoparticles. Very strong peak at ~ 1.49 eV corresponds to the photon recombination on the deep levels in the band gap of GaAs . The origin of these defects is usually growth defects which are most probably caused by oxidation of nanoparticles as well as by not optimised overgrowth process.

Conclusion

By the combination of the in-flight synthesis technique and molecular beam epitaxy we have generated and embedded the nanometer size In nanoparticles in GaAs epitaxial layer. By the low temperature photoluminescence, a weak but very narrow peak corresponding to the InGaAs was observed. In order to improve the material quality a protection of nanoparticles from the oxidation and an optimization of the overgrown process is still nesessary.

Acknowledgement

This work is supported by Sonderforschungsbereich 445 “Nanoparticles from the gas-phase”

References: [1] D. Bimberg, M. Grundmann, N.N. Ledentsov „Quantum Dot Heterostructures“,

ISBN: 0-471-97388-2, John Wiley & Sons Ltd, 1998

[2] F.Kruis et al, „Preparation of sizeclassified PbS nanoparticles in the gas-phase“, Applied Physics Letters v.73, n.4 pp547-549 (1998)


4.4.2 Electrical Characterization of Laterally Structured Nanocrystal Films

Scientist: F. Otten F.E. Kruis1, H. Fißan1

1Dept. of Process- and Aerosol Technology, University Duisburg-Essen

Introduction

Nanoparticle films can be used in sensors [1] and other electronic devices [2]. For multi-sensors laterally structured nanoparticle films are necessary. This can be achieved by electrostatic lenses formed by charged and patterned photo resist for controlling the deposition process of the nanoparticles [3,4].

Electrical I-V characterization of as-deposited and laterally structured nanoparticle films is performed. The substrate is GaAs substrate passivated by 200 nm thick SiNx. The films are composed of 22 nm PbS single-crystals. The as-deposited films have the dimensions 220 x 3 x 0.05 µm3. The structured films have the dimensions 0.25 x 3 x 0.7 µm3. The I-V characteristic obtained are these of back-to-back Schottky diodes and can be simulated by the equation

21 )(

0VVc FBeII −−⋅= [5].

Fig. 1 Current voltage characteristics of as-deposited and laterally structured nanocrystal films.

10-12

10-11

10-10

curr

ent

I Abs

. / A 10-9

10-8

10-7

10-13

applied voltage V/V

-1.5 -1.0 -0.5 -0.0 0.5 1.0-2.0 1.5 2.0

patterned

as deposited

measured

simulated


Here I0 is the backward saturation current through the diode, c1 = e/(4kBT·VFB) is a constant, VFB is the flat-band voltage, e is the unit charge, kB the Boltzmann constant and T the temperature.

In Fig. 1 the results of the I-V characterization in experiment and simulation is depicted. Fig. 1a) shows the characteristic for an as-deposited film, whereas in b) the characteristic for the laterally structured film is shown.

The comparison of the simulation parameters I0, c1 and VFB are shown in Table 1. c1 and VFB are similar in both cases, for the as-deposited and the laterally structured films. I0 is about 1700 times larger for the as-deposited film compared to the structured film. Since the width of the first case film is about 800 times larger than this of the latter case, This points to a charge transport through the surface of the films.

As-deposited nanoparticle film Laterally structured nanoparticle film

neg. saturation current I0,neg 3.2·10-8 A 2.6·10-11 A

pos. saturation current I0,pos 4.5·10-8 A 2.0·10-11 A

constant c1 1.0 V-2 2.1 V-2

Flat-band voltege VFB 2.45 V 1.1 V

Tab. 1 Comparison of simulated data for nanoparticle films.

In conclusion it is shown, that nanoparticle films composed of 22 nm nanocrystals exhibit back-to-back Schottky diode behaviour. The backward saturation current scales roughly with the width of the films and not with the volume.

Acknowledgement

The financial support by Deutsche Forschungsgemeinschaft is greatly acknowledged.

References: [1] M. Kennedy, F.E. Kruis, H. Fissan; “Tailored nanoparticle films from monosized nanocrystals:

particle synthesis, film formation and size-dependent gas-sensing properties”, submitted to J. Appl. Phys. 2002.

[2] V. Colvin, M. Schlamp, A.P. Alivisatos; “Light-emitting diodes made from cadmium selenide nanocrystals and a semiconductor polymer”, Nature, 370, 1994, p.354.

[3] W. Prost, F.E. Kruis, F. Otten, K. Nielsch, B. Rellinghaus, U. Auer, A. Peled, E.F. Wassermann, H. Fissan and F.J. Tegude, Microelectron. Eng.,1998, 41/42, 535.

[4] F. Otten, U. Auer, F.E. Kruis, W. Prost, F.J. Tegude, H. Fissan, “Lithographic tools for producing patterned films composed of Gasphase generated nanocrystals”, Material Sci. Technol., 18, 2002, p.717.

[5] S.M. Sze, Physics of Semiconductor Devices 2nd ed., John Wiley & Sons, New York, 1981.


4.4.3: Potentials Measurements with Electrostatic Scanning Probe Microscopy

Student: Q.T.Do Supervisor: F.Otten, W.Prost

Introduction

In recent years, electrostatic force microscopy (EFM) have emerged as useful tools for nanoscale characterization of electronic properties and functionality in materials and devices [1]. The goal of this work is the development of potential measurements techniques for quantitative investigation of nano devices for circuit design and failure analysis.

The principle of EFM is based on commercial atomic force microscope Dimension 3000 with Extender Electronics Module where surface topography and electric surface potential are obtained sequentially using Lift ModeLM [2]. On the first trace, the sample topography is measured by Tapping ModeTM [2]. The second trace measures immediately the surface potential distribution at a set lift-height of typically 20 – 100 nm above the surface of the previously determined sample topography. In EFM operation a sinusoidal ac voltage Vacsin(ωt) is applying to the cantilever. The deflection is receipted by an array photosensitive position detectors (PSPDs) by shinning a laser beam on the upper end of the cantilever. This deflection is proportional to the electric force acting on the tip-cantilever system. The total amplitude of the ω component of the force F(ω) acting on the tip-cantilever system is due to the change of the capacitive energy and is measured by Lock-In technique.

At first we have applied for the special test structure. Figure 1(a). shows the surface topography of three Au metal lines with 3 µm width and 1 µm gap. During the measurement, an external voltage was symmetrically applied to the test structure. The voltage difference between adjacent metal line is 1V. Fig 1(b) depicts the potential distribution of the sample, in which white stripes are the Au metal wires. The scan height is set by 50 nm. The potential difference measured is 0.3V smaller than the applied voltage (1V) towards the step height calculation fig.1(c). The step height analysis shows that the edges amplitude is nearly 1V. There is additional capacitance effect between the tip side and the wall of micro strip. The resolution is certainly depends on a plurality of uncertainties. We have to consider for example the effect of the cantilever, geometry of the tip, tip-sample distance, and tip apex radius. Therefore the calibrating of the tip is precondition for accurate results. More accurate measurements are possible at smaller tip-sample distances because the capacitance gradient of the tip increases at a increasing rate compared to the cantilever. Other works [3] approve that the spatial resolution can be smaller than <100nm and potential sensitivity <1mV.

The results obtained for a test structure show that we have more development in potential measurement for quantitative predication. This will allow much more exact investigation for nano structure devices in next time.


(a) (b)

(c)

Fig. 1 3-dimensional topography and surface potential images of the EFM test structure: (a) topography profile with a height of about 300 nm, a 3000 nm width, a 1000 nm gap between the wires, (b) potential plot under applied bias of 1 V, (c) step height profile from the potential plot.

References: [1] P.A.Rosental, E.T.Yu, R.L.Pierson, P.J.Zampardi, Jour. of Appl. Phys., 2000, Vol. 87, Nr. 4.

[2] Command References Manual, D3000, Digital Instruments & Veeco

[3] H.O.Jakobs, H.F.Knapp, A.Stemmer, Rev. of Sci. Instr. 1999, Vol.70, Nr.3


4.4.4 3-Dimensional Self-Assembly of Nanoparticles on Microcrystal Surfaces: an SFM/SEM Study

Scientists: V. Khorenko Students: M. Barth, T. Do D. Cunningham1, J.-L. Martinez-Albertos1, B. Moore1

1Dept. of Pure and Applied Chemistry, University of Strathclyde, UK)

Introduction

The visions of nanotechnology – smaller, faster, cheaper, smarter information-manipulating and storage devices – crucially depend on the ability to make and manipulate objects on the nanometer scale. The most of currently used techniques for fabrication of nanostructures can be divided into two big groups. The engineer’s “top-down” approach is to carve out the nanometer size objects lithographically from a substrate, the chemist’s “bottom-up” approach is to assemble them from molecular scale precursors. In the present work, which is a part of the European project “Self-assembled block for nanocomputers”, one of such “bottom-up” approaches was used to synthesize an inorganic few hundred nanometer size crystals coated with a metal, semiconductor or dielectric nanoparticles (further - nanoparticles coated crystals, NCCs). Due to the well defined rectangular shape of the NCCs, resulting from the features of the synthesis process, the arrangement of NCCs on a surface becomes possible. Because the conductivity of NCCs depends on the conductivity of nanoparticles (inorganic salts used for carrier crystals are an insulators), the nanometer scale metal-metal, metal-semiconductor and metal-insulator junction can be realized.

The main goal on the first stage of the work was to investigate the topology of NCCs with different nanoparticles and crystal materials as well as the possibility to modify the surface of NCCs by temperature treatment.

Synthesis and deposition of NCCs

NCCs were prepared in a single step self-assembly process by co-precipitating a mixture of commercially available gold nanoparticles protected by N-(2-mercaptopropionyl)-glycine and the crystalline material from aqueous solution using a water miscible solvent. Under conditions where both components simultaneously precipitate the high crystal lattice energy of the core material ensures the nanoparticles arrange over the microcrystal surface. This procedure termed Crystal Lattice Mediated Self-assembly (CLAMS)[1] and gives more than 1012 very regular and high reproducible NCCs in one experiment.

The well-defined form of the NCCs is an essential feature of the fabrication process and just in presence of nanoparticles possible. The tiopronin acts as the “interlayer” providing fixation of the Au nanoparticles on the surface and stabilisation of the crystal form. After fabrication the NCCs were deposited onto GaAs or Au surface by spin coating technique. A part of the prepared samples were annealed for 3 min at 300 °C in nitrogen flow. For the further characterization of NCCs, transmission and scanning electron microscopy (at the University of Strathclyde) and atomic force microscopy were used.


Shape and surface topology of NCCs

The following NCCs were investigated: uncovered potassium sulphide (K2SO4) carrier crystals, covered with Au nanoparticles and covered with polymers (dendrimers). Also the rubidium sulphide (Rb2SO4) crystals covered with Au nanoparticles were characterized. In confirmation of the prediction about features of NCCs, formation a strong influence of the Au nanoparticles on the form of the bricks was found. In absence of nanoparticles, the bricks have mostly rectangler but significantly rounded shape. Covering the bricks with Au nanoparticles led to the clearly outlined rectangular NCCs with typical sizes of about a few hundred nanometers (up to 700 nm) long and wide and about 50-100 nm thick NCCs in case of K2SO4 (Fig.1), and up to 10 µm long and 50-150 nm wide and thick NCCs in case of Rb2SO4 (Fig.1).

Fig. 1 NCCs based on K2SO4 (left, SFM image) and Rb2SO4 (right, SEM image)

The Au nanoparticles on the brick surface were also resolved. As presented on Fig.2 (left) the high-density coverage form a continuous 2-dimensional structure, the period of which roughly corresponds to the size of used nanoparticles (taking the SFM-tip convolution effect into account).

Fig. 2 Changes in topology of the surface of Au-K2SO4 NCC after annealing (5 min at 300 °C) (the same NCC was measured)

By thermal treatment of NCCs the Au nanoparticles can be melted and the brick surface becomes smooth. Due to the nanometer size of the covering particles the melting process will be observed at drastically reduced temperatures [2]. In our case, annealing only at 300 °C led to the disappearing

Sample Escher 8_10 Sample Escher 8_6t

annealing 300 C,5 min

a

b

00

100

100

200

200

[nm]

[nm]

before annealing

a

b

0 100 2000

100

200

[nm]

[nm]

after annealing

5.00

10.0

µm


of periodical structure on the surface (Fig.2 (right)). The form and size of NCCs were not changed. Summarizing the results obtained on the Au-covered bricks it may be concluded that they already seem to be very suitable for further application in the project as conducting units.

In order to investigate the topology of NCCs with other as gold covering, the bricks with dendrimers (polymer chains, insulator) were also studied. It was found that, these NCCs tend to stick in suspension to each other forming a lump. Despite the using of ultrasonic bath before deposition, the separation of the dendrimer-NCCs is difficult. Moreover, these dendrimer-NCCs have a round shape and very wide size distribution. In order to carry out further investigation of the electrical properties of these bricks, a more development of the synthesis technology is necessary.

The results obtained on investigated NCCs are also presented in compact form in Table 1

Materials Covering Shape of NCCs Surface

sub monolayer right rectangle nanoparticles arranged into

anisotropic geometric pattern K2SO4 + Au (isopropanol solution) high density

(> 1 ML) right rectangle

nanometer size periodic roughness

Rb2SO4 + Au

(DMF solution)

high density (> 1 ML)

elongated rectangles up to 10 µm long bars

nanometer size periodic roughness

K2SO4 without Au (isopropanol solution)

no nanoparticles

rectangle but strong smoothed

very flat

K2SO4 + dendrimers (isopropanol solution)

covering with polymers

formless structures difficult to define (the NCCs

mostly sticked together)

Tab. 1

Publications:

The major part of this work was presented on the International Symposium on Structure and Dynamics of Heterogeneous Systems – SDHS’02, November 28-29, 2002, Duisburg, Germany. The proceedings (full paper) will be published in “Phase Transitions” journal in 2003.

Acknowledgement

The work is funded by the European Project ESCHER within the Future and Emerging Techologies Programme (Contract number IST-2001-33287).

References: [1] M.Kreiner, B.D. Moore, M.C. Parker, Chemical communications, 2001,12, pp.1096-1097.

[2] M. Magnusson et al, J. of Nanoparticle Research, v.1, pp.243-251, 1999


4.4.5 Microelectronic Patterning Technics for K2SO4/Au Nano-Crystals

Student: M. Barth Supervisor: Q. T. Do

Introduction

The nanoparticle coated crystal (NCC) is a very promising candidate for the self-assembled fabrication of electronic devices at the nanoscale (cf. chapter 4.4.4 and 4.4.6). In this work the compatibility of NCC to standard technological processes is investigated. In practical the thermal budget of NCC is given and their compatibility to a complete optical lithography procedure is shown. Finally, the conductivity of Au-K2SO4 NCC bridging a metal-finger structure is given.

Nanoparticle coated micro-crystals (NCC) with a K2SO4 core and Au nanoparticles were provided by the University of Strathclyde, Glasgow, in a suspension diluted in propanol at the ratio 7:1. The process of NCC deposition onto a wafer is described in chapter 4.4.4. For the ease of identifying specific NCC the wafers were patterned with a numbered Pt test grid. The topology of the NCCs was measured using an atomic force microscope DI 3000 in tapping mode. The size of the investigated NCC is a few hundred nanometres long and wide (700-2000 nm) and the height is about 50-250 nm.

Compatibility to Optical lithography

Au-K2SO4 NCC were deposited on GaAs substrates. In order to identify a specific NCC a numbering grid on the substrates were fabricated before deposition. The shape and surface of identical NCC was investigated using scanning force microscope using a DI 3000 in tapping mode. The following standard lithography procedure was applied: (1) Spinning-on of photo resist at 7000 rpm, annealing on a hot plate at 95°C; (2) Exposure of a pattern using UV light, (3) Development in one-to-one solution of sodium hydroxide (alkaline) and pure water, and (4) Stripping of the photo resist using hot Aceton

(a) (b) (c)

1 µm

Fig. 1 AFM micro scans of a selected NCC (a) before lithography steps, (b) after the first lithography step, (c) after the second lithography step


The steps 1-4 were repeated twice. The adhesion of the NCC on the wafer is so high that there is neither a loss of NCC nor a change of position regardless of any treatment tested. A more detailed analysis of the NCC surface shows even no surface integrity modification or a change of the height and shape of the NCC. This investigation shows that the NCC withstands all chemical treatments of a full lithography technology. The NCCs of investigation were covered with photo resist and not exposed to water or developer which may solve the salt core of the NCC.

Annealing treatment

A set of samples based on Au-K2SO4 NCC on Si-substrates was prepared in order to study the surface after annealing. The heat treatment was carried-out in a rapid thermal annealer (RTA) at temperatures ranging from 300°C to 560°C. The roughness is analysed using the AFM in a scan field of approximately 1 x 1 µm² in the central part of the NCC surface. The roughness data are plotted in Fig. 2 vs. annealing temperature. Up to temperatures of 500°C almost no modification is observed and the surface roughness remains at about 1 nm. At temperatures above 500°C the surface roughness increases rapidly attributed to a clustering of the Au nanoparticles. The Au-K2SO4-NCC surface after the annealing experiment is shown in Figure 2a, b. After annealing at 560°C a steeper increase of surface roughness and a significant clustering (fig. 2a,b) indicate that this is the critical temperature.

0.0

0.5

1.0

1.5

2.0

as deposited 300 400 500 600

annea ling tem pera tu re [°C ]

N C C B

N C C A

0 nm 500 nm

0 nm

500

nm

0 nm 500 nm

0 nm

500

nm

(b) 560 °C(a) 300 °C

su

rfa

ce

ro

ug

hn

es

s [

nm

]

(c)

Fig. 2 Surface of Au-K2SO4 NCC measured with AFM: topology scan of the NCC (a) after 300°C treatment, (b) after560 °C treatment, and (c) development of surface roughness vs. annealing temperature for two NCC samples A, B.


The mean radius of the Au nanoparticles used for NCC fabrication has been determined to 1.025 by high-resolution AFM without tiopronin coating after deposition on a Si wafer. Using the model from Borel and Buffat [1] the melting-point of a gold nanoparticles at this size can be calculated to 619°C. This analysis indicates that the change of the surface roughness beyond 500 °C is driven by initial melting of the Au nanoparticles as indicated in dark islands in Fig. 2b.

Au-K2SO4-NCC Current-Transport

In the final part of the work the conductivity of a single Au-K2SO4 NCC was measured. The test structure consists of 1 µm fingers of 100 nm Au separated by 1 µm spacing. In order to suppress the leakage current to below 10 pA the structure was realized on a SiO2-coated Si-wafer by optical contact printing. The Au-K2SO4 NCC was deposited onto the pattern such that it forms a bridge between two neighbouring contacts (cf Fig. 3a). Finally, the same metallisation was defined and evaporated such that the NCC is sandwiched between two metallisation layers. The I-V characteristic (cf. Figure 3b) exhibit a symmetric but somewhat non-linear behaviour with a current of typically 100 nA at 1 V. It was measured three times over the same NCC giving reproducible results. This also indicates that the NCC must be photo resist resistant.

NCC

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

voltage [V]

0.3

0.2

0.1

0.0

-0.1

-0.2

-0.3

curr

ent [

µA]

a b

Fig. 3 Conductivity test of a Au-K2SO4 NCC: (a) metal finger pattern on with a NCC bridging the contact and (b) I-V characteristic of a single NCC at room-temperature

Conclusions

The Au-K2SO4-NCC sticks on the wafer surface and is resistant against the tested resists. It is fully compatible to an optical lithography process. The thermal budget of the NCC exceeds 500 °C which opens-up various process technologies. The conductivity of a single NCC is high enough aim at electronic devices.

References [1] K. Schaber; “Thermodynamik disperser Systeme”, Skriptum, Karlsruhe 2003


4.4.6 A Nanoparticle Coated Nanocrystal Gate for an InP-Based Heterostructure Field-Effect Transistor

Scientist: Q.T. Do Technical Assistant: R. Geitmann K.Katzer1, J.-L. Martinez-Albertos2, B. Moore2

1Dept. of Materials of Electrical Engineering, University Duisburg-Essen

2Dept. of Pure and Applied Chemistry, University of Strathclyde, UK

Introduction

In the present work, we explore the basic electronic functionality of nanoparticles-coated micro crystal (cf 4.4) and investigate whether they could eventually be used in a technologically useful application [1]. After a short description about the building of NCC and the experimental set-up, we demonstrate and discuss at first the diode properties between NCC and n-doped GaAs by electrical measurements with the AFM tip. On particular, we combine a semiconductor heterostructures and a NCC fabrication of NCC-FET systems by applying self-assembly and contact-AFM. Subsequently, we describe NCC-FET output characteristics. Finally we present and discuss initial results obtained by the electrical characterization of NCC-FET devices.

Shape and surface topology of Rb2SO4 NCC

For the further characterization, the NCCs were deposited onto n-doped GaAs by spin coating technique. Structure characterization AFM and HREM were employed. Fig. (1) shows the AFM topography of one of such Rb2SO4 NCC. The height, width, and length of the NCC are 360, 450 and 2000 nm, respectively on GaAs (n-doped 1018 cm-3) substrate and a HREM imaging from Rb2SO4 NCC to the edge. We assign the black dots as Au particle with 2-3 nm a radius.

nm

1 m

Fig. 1 HREM (left) and AFM (right) images of Au Rb2SO4 NCC. The radius range of Au nanoparticles is 2-3 nm.


Diode characteristics

The current-voltage characteristic between semiconductor and tip as a reference curve and then between semiconductor–NCC junction has measure (Fig. 2). The expected diode characteristic can be clearly recognized. The reverse current is nearly zero for the negative voltage. For positive voltage the current increase exponentially at 0.4V threshold voltages. The typical barrier height of metal on n-doped GaAs is approx. ΦGaAs -doped GaAs/tip junction is higher because the current transport through the tip is like the bulk, while the current transport through NCC to limited 2D array of tunneling junctions systems. The current through a linear square array is predicted to behave as I ∼ (V/VT – 1)α where α is between 5/3 and 2 [3]. In semi logarithmic diagram (Fig. 3) we get an ideality factor of about 2 for n-doped GaAs for both curves. But for higher voltage of about 0.6V, the ideality factor of about 3 for NCC. A possible current transport mechanism is the superposition of both tunneling through a Schottky barrier and hopping transport through metal particles.

-1.0 -0.5 0.0 0.5 1.00.0

2.0x10-6

4.0x10-6

6.0x10-6

8.0x10-6

1.0x10-5

GaAs(n)/Tip junction

GaAs(n)/Rb2 SO4 /Tip junction

Voltage [V]

I[A]

1 m

Fig. 2 Diode characteristic between AFM-tip/n-doped GaAs and AFM-tip/ NCC/ n-doped GaAs. (b) AFM images NCC on GaAs substrate.

0.00 0.20 0.40 0.60 0.80 1.001.0x10-10

1.0x10-9

1.0x10-8

1.0x10-7

1.0x10-6

1.0x10-5

1.0x10-4

log

I [A

]

Voltage [V]

GaAs/Tip

GaAs/NCC/Tip

Fig. 3 Semi logarithmic plotting from diode characteristic

Device fabrication

In order to demonstrate the usability of the NCCs as an electronic device component, an HFET with the NCC based gate was fabricated [2]. Epitaxial layers were grown on semi-insulating (100)-oriented InP substrates by MBE. The epi structure of lattice-matched HFET without cap layer is shown in Fig. 4. The used epi layer comprises of a 90 nm In0.52Al0.48As buffer layer, the active channel with the 15 nm In0.53Ga0.47As, followed by the high band gap In0.52Al0.48As, 2 nm undoped In0.52Al0.48As spacer, 12 nm Si doping plane as donor layer, 15 nm undoped In0.52Al0.48As Schottky layer.


Devices fabrication started with mesa etching in a phosphoric acid based solution for removal of the active layers, followed by an etch step in a succinic acid to reduce the sidewall leakage from

the gate to channel. The ohmic contacts were formed by UV photo lithography following by depositing the metal system Ge/Ni/Ge/Au. Source and Drain electrodes were annealed at 360°C to

30 sec. The contact resistance as measured by the transmission line model (TLM) method ranged from 0.2 to 0.3 Ωmm. For the structure without cap layer, the mobility was 8500 cm2/Vs and a sheet resistance 350 Ω at room temperature. The NCC solution is poured on the device while applying a bias of 1 V to the side electrodes. Intrinsically negatively-charged of NCC to the ordering of these one’s on the positive side electrode and forming of the gate electrode (cf. Fig. 5 inset). The output characteristics show with/out NCC on the conductivity catwalk in Fig (5).

The typical output current is nearly 200 mA/mm at VG = 0V. Like standard gate negative biased NCC depleted the electron concentration in 2DEG, which in turn effectively reduces the current by ∆IDS = 10 mA/mm. For electrical gate contacting, we use a commercial atomic force microscope from Topomatrix. We utilize conducting diamond boron-doped AFM-tips with radius of 20 nm. Our procedure is described in the following steps:

Step 1: The NCC is located on the FET structure in non-contact mode. The typical scan rate is 0.01 Hz and the setpoint amplitude is 60 nm.

Step 2: In order to make contact with NCC, the tip is withdrawn. The operation is switched to the contact mode. The force is chosen 2.5µN and subsequently the feedback loop of the AFM is disabled. Then the gate voltage was swept to the NCC.

Figure 5 (b) shows the AFM image of the fabricated NCCFET. One of the NCCs is covered across the conduction catwalk between source and drain. The distance between the source and drain is 10µm and the width 1µm. The height, width, and length of the NCC are 360, 450 and 2000 nm. The gate length LG is 360nm in this case. Figure 6 shows drain source current IDS as a function of drain voltage VDS for NCCFET. The gate voltage applied on the NCC is swept from -2V to 1V in step of 0.5V. This devices has shown a maximum drain current ISAT = 175mA/mm at VG = 0V; the value of

Substrate InP

Buffer 90 nmInGaAs/InAlAs

Channel 15nm InGaAsSpacer 2nm InAlAsDonor layer 12nm InAlAs:SiSchottky Layer 15nm InAlAs

Source Drain

Fig. 4 Schematic epi layer and device struc-ture of an Au-NCCFET as a gate.

0 1 2 3 40.00

0.05

0.10

0.15

0.20V

G=0V

with NCC

without NCC

UDS[V]

IDS[mA]

Source

Drain

Side gate

NCC

m

Fig. 5 Output characteristics with/out NCC on the FET devices.


drain saturation current measured is IDS = 290mA/mm at VG = 1V. The maximum extrinsic transconductance gm defined by gm = ∆ID/ G is 160 mS/mm (cf. fig. 6), however, a complete pinch-off of the drain current is not possible, because NCC-gate did not cover the conduction channel. The important result of this investigation is the finding of the sufficiently high value of transconductance functionality devices.

In summary, a new fabrication technology for a submicrometer FET gate has been developed based on a bottom-up and self-assembly approach. Using the transport properties of an InP-based two-dimensional electron gas, a high performance FET-device has been realized.

Acknowledgement

The work is funded by the European Projekt ESCHER within the Future and Emerging Technologies Programme (Contract number IST-2001-33287).

References [1] M.Kreimer, B.D.Moore, M.C.Parker, Chemical communications, 2002, 12, pp. 1096-1097.

[2] U.Auer, R.Reuter, C.Heedt, H.Künzel1), W.Prost, F.J.Tegude, Proc. of 'InP and Related Materials Conf.', Santa Barbara, USA, 1994, pp. 443-446.

[3] A.Alan Middleton, Ned S. Wingreen, Phy. Rev. Lett., vol. 71, pp. 3198, (1993).

0 1 2 3 40.00

0.05

0.10

0.15

0.20

-1.5 -1.0 -0.5 0.0 0.5 1.0

0.00

0.02

0.04

0.06

0.08

0.10

UGS

[V]

gm[S/mm]

UDS

[V]

IDS

[A/mm]Gate voltage

1V 0.5V 0V -0.5V -1.0V -1.5V

Out

put c

hara

cter

istic

s

Tran

scon

duc

tanc

e

Fig. 6 Drain current IDS as a function of drain voltage VDS for a NCCFET with NCC length of 360 nm. Gate voltage VG was swept from -1.5 to 1V in 0.5V steps.


4.5 Conference Contributions

1. S. EHRICH, M.AGETHEN, W.BROCKERHOFF, F.-J.TEGUDE

A Consistent PSPICE-Model for InP HBT '13th Workshop on Physical Simulation of Semiconductor Devices', Ilkley, U.K., March 2002

2. B.SCHLOTHMANN, R.M.BERTENBURG1, M.AGETHEN

1, P.VELLING1, W.BROCKERHOFF, .F-

J.TEGUDE 1now with PAG – Innovative Processing AG, Duisburg RF-Simulation of InGaAs/InP Heterostructure Bipolar Transistors '13th Workshop on Physical Simulation of Semiconductor Devices', Ilkley, U.K., March 2002


1, P.VELLING1, W.BROCKERHOFF, .F-

J.TEGUDE 1now with PAG – Innovative Processing AG, Duisburg Two Dimensional Physical Simulation of InGaAs/InP Heterostructure Bipolar Transistors 'Workshop on Expert Evaluation and Control of Compound Semiconductor Materials and Technology' (EXMATEC 2002), Budapest, Hungary, May 2002

4. T.REIMANN, M.SCHNEIDER1, S.NEUMANN, A.STÖHR

1, D.JÄGER1, F-J.TEGUDE

1: Gerhard-Mercator-Universität Duisburg, Dept. of Optoelectronics

Waveguide HBT Electroabsorption Modulators: Devices and Circuits 'Int. Conf. on InP and Related Materials' (IPRM 2002), Stockholm, Sweden, May 2002

5. S.NEUMANN, J.SPIELER1, R.BLACHE

1, P.KIESEL1, W.PROST, G.DÖHLER

1, F-J.TEGUDE 1 : Universität Dortmund, LS Bauelemente der Elektrotechnik

MOVPE Growth and Polarisation Dependence of (dis-)ordered InGaAsP PIN Diodes for Optical Fibre Applications 'Int. Conf. on InP and Related Materials' (IPRM 2002), Stockholm, Sweden, May 2002

6. F.OTTEN, F.E. KRUIS, W.PROST, F.J.TEGUDE, H.FISSAN1

Deposition of Gas-Phase Generated PbS Nanocrystals onto Patterned Substrates Nao-7, ECOSS-21, 24.-28.06.02, Malmö Schweden

7. P.GLOSEKÖTTER1, C.PACHA

1, K.F.GOSER1, W.PROST, S.KIM, H.VAN HUSEN, T.REIMANN, F.-

J.TEGUDE 1 : Universität Dortmund, LS Bauelemente der Elektrotechnik

Pseudo Dynamic Gate Design based on the Resonant Tunneling Bipolar Transistor (RTBT) 'Europ. Conf. on Solid-State Devices and Circuits', (ESSDERC 2002), Florence, Italy, Sept. 2002

8. T.REIMANN, M.SCHNEIDER1, S.NEUMANN, D.JÄGER

1, F.-J.TEGUDE 1: Gerhard-Mercator-Universität Duisburg, Dept. of Optoelectronics

Different Approaches for Integrating HBTs and EAMs 'EDMO 2002', 18.-19.11.02, Manchester, U.K.


9. J.SPIELER1, R.BLACHE

1, A.LESE1, P.KIESEL

1, G.H.DÖHLER1, S.NEUMANN, P.VELLING, W.PROST,

F.J.TEGUDE 1: Inst. of Technical Physics 1, University Erlangen

Spontaneous Group III and V Superlattice Ordering in InGaAsP '26th Int. Conf. on the Physics of Semiconductors, Edinburgh, U.K., 2002





Spontaneous Group III and V Superlattice Ordering in InGaAsP '6th Int. Conf. on Signbal Processing', Bejing, China, 26.-30.08.02

11. W.PROST

Resonant Tunneling Diodes for Digital Applications '4th Advanced Semiconductor Devices and Microsystems', Smolenice, Slovakia, 14.-16.10.02

12. S.NEUMANN, W.PROST, F.J.TEGUDE

Growth of Carbon Doped InAlAs with LP-MOVPE and non Gaseous Sources ICMOVPE XI, 2002, February 2003, Berlin

13. S.NEUMANN,A.BAKIN1,P. VELLING

2, W.PROST, H.WEHMANN1, A.SCHLACHETZKI

1, F.J.TEGUDE 1 : TU Braunschweig, Inst. for Solid-State-Electronics 2: now with IPAG – Innovative Processing AG, Duisburg

Growth of III/V Resonant Tunneling Diode on Si Substrate ICMOVPE XI, 2002, February 2003, Berlin



1, F-J.TEGUDE 1 : Inst. of Technical Physics 1, University Erlangen

MOVPE Growth and Polarisation Dependence of (dis-)ordered InGaAsP PIN Diodes for Optical Fibre Applications ICMOVPE XI, 2002, February 2003, Berlin

15. P.GLÖSEKÖTTER1, C.PACHA

1, K.F.GOSER1, W.PROST, S.KIM

2, H.V.HUSEN, T.REIMANN, F.J.TEGUDE 1 : Dept. of Microelectronics, University of Dortmund 2: Ferdinand-Braun Institut für Hochfrequenztechnik, Berlin

Asynchronous Circuit Design Based on the RTBT Monostable-Bistable Logic Transition Element (MOBILE) '15th Symposium on Integrated Circuits and System Design', Chip in the Pampa, Porto Alegre, RS, Brazil, 09.-14.09.02


16. W.PROST, S.O.KIM2, P.GLÖSEKÖTTER

1, C.PACHA1, H.V.HUSEN , T.REIMANN , K.F.GOSER

1, F.J.TEGUDE 1 : Dept. of Microelectronics, University of Dortmund 2: Ferdinand-Braun Institut für Hochfrequenztechnik, Berlin

Experimental Threshold Logic Implementations based on Resonant Tunneling Diodes 'Conf. Electronic Circuits and Systems', Spec. Session on Threshold Logic (IEEE ICECS Conf), Dubrovnik, 15-18.09.02

17. V. KHORENKO, M. BARTH, F. OTTEN, W. PROST, D. CUNNINGHAM1, J.-L. MARTINEZ-ALBERTOS

1, B. MOORE

1, K.KATZER2, W.MERTIN

2, F.J.TEGUDE 1: Dept. of Pure and Applied Chemistry, University of Strathclyde, UK; 2: Dept. of Materials for Electrical Engineering, Gerhard-Mercator-Universität Duisburg, Germany

3-dimensional self-assembly of the gold nanoparticles on microcrystal surfaces: an SFM/ SEM study ' Int.Symp.on Structure and Dynamics of Heterogenous Systems' (SDHS'02), 28.-2911.02, 2002, Duisburg

18. V. KHORENKO, K.NANDA1, W. PROST, E.KRUIS

1, H, FIßAN1, F.-J.TEGUDE

1): Gerhard-Mercator-Universität - GH Duisburg, Dept. of Aerosol Measurement Technology

Gasphasengenerierte Nanopartikel in epitaktische Matrix - Alternative zu den selbstorgani-sierten Quantenpunkten? XVII. DGKK Arbeitskreistreffen "Epitaxie von III/V-Halbleitern", Marburg, 12.-13.12.02

19. W.PROST, S.NEUMANN, P.VELLING1, F.J.TEGUDE

1: IPAG-Innovative Processing AG, Duisburg

LP-MOVPE growth for high-speed electronic devices on InP 'Europ. Workshop on MOVPE (EW-MOVPE)', Lecce, Italy, 08.-11.06.03

20. W.PROST

Beiträge der Nanotechnologie zur ERrhöhung der Funktionalität und Dichte in der Elektronik Workshop 'Kontrollierte Selbstorganisation für zukünftige technische Anwendungen', Düsseldorf, Germany, 16.-17.06.03

21. S.EHRICH, M.AGETHEN1, P.VELLING

1, A.BRENNEMANN1, R.M.BERTENBURG

1, W.BROCKERHOFF, F.J.TEGUDE

Scaling of Small-Signal and RF-Noise Parameters with Respect to the Emitter-Area of Single HBT based on InP '14th Workshop on Modelling and Simulation of Electron Devices', Barcelona, Spain, 16.-17.10.03,

22. S. NEUMANN, W. PROST, F.-J. TEGUDE

InP based double heterojunction bipolar transistor with carbon doped GaAsSb:C base grown by LP-MOVPE '11th Gallium Arsenide Application Symposium (EuMC/ECWT/GAAS), Munich, Germany, 6.10.-7.10.03


23. Z.JIN, S.NEUMANN, W.PROST, F.-J.TEGUDE

Mechanism of Current Gain increase of Heterostrucutre Bipolar Transistors Passivated by Low-Temperature Deposited SiNx '11th Gallium Arsenide Application Symposium (EuMC/ECWT/GAAS), Munich, Germany, 6.10.-7.10.03


Growth of Highly p-type Doped GaAsSb:C for HBT Application 'Int. Conf. on InP and Related Materials' (IPRM 2003), Santa Barbara, USA, May 2003

25. Z.JIN, F.OTTEN, S.NEUMANN, R.REIMANN, W.PROST, F.-J.TEGUDE

Passivation of Graded-Base InP/InGaAs/InP Double Heterostrucutre Bipolar Transitors by Romm-Temperature Deposited SiNx

'Int. Conf. on InP and Related Materials' (IPRM 2003), Santa Barbara, USA, May 2003



LP-MOVPE growth for high-speed electronic devices on InP 'Europ. Workshop on MOVPE (EW-MOVPE)', Lecce, Italy, 08.-11.06.03

27. V. KHORENKO(1), K. K. NANDA(2), W. PROST(1), F. E. KRUIS(2), H.FISSAN(2), F.-J. TEGUDE(1) (1)Solid State Electronics Dept., University of Duisburg-Essen,

(2)Process- and Aerosol Measurement Technology, University of Duisburg-Essen

Embedding of the gas-phase generated indium nanoparticles in epitaxial matrix Nanoparticle Science and Engineering Summer Workshop, Minneapolis,USA, July 17-18, 2003.

28. V. KHORENKO(1), K. K. NANDA(2), W. PROST(1), F. E. KRUIS(2), H.FISSAN(2), F.-J. TEGUDE(1) (1)Solid State Electronics Dept., University of Duisburg-Essen,

(2)Process- and Aerosol Measurement Technology, University of Duisburg-Essen

Formation of zero-dimensional nanostructures by epitaxial overgrowth gas-phase generated indium nanoparticles European Material Research Society (EMRS) Meeting, Strasbourg , France, 10 - 13. 06.2003.


29. K.D. KATZER(1), V. KHORENKO(2), Q.T. DO(2), W. MERTIN(1), F.J. TEGUDE(2), W. PROST(2) University Duisburg-Essen,

(1)Dept. Werkstoffe der Elektrotechnik,

(2)Solid-State-Electronics Dept.,

D. Cunningham, J.-L. Martinez-Albertos, B. Moore,

Dept. of Pure and Applied Chemistry, University of Strathclyde, UK. Talk

Electrical Characterisation of Self-Assembled Nanoparticle Coated Crystals Electronic Materials Conference, Salt Lake City, June 25-27, 2003

30. S.EHRICH, M.AGETHEN, W.BROCKERHOFF, F.J.TEGUDE

RF- and Noise Modeling of Semiconductor Devices based on InP 'ITG-Fachtagung', 2003

31. S.EHRICH, R.M.BERTENBURG, M.AGETHEN, W.BROCKERHOFF, F.J.TEGUDE

A Consistent and Scalable PSPICE HFET-Model for DC- and S-Parameter Simulation 'Int. Conf. On Microelectronic Test Structures' (ICMTS) 2003,


4.6 Publications

1. S. EHRICH, M.AGETHEN, W.BROCKERHOFF, F.-J.TEGUDE

A Consistent PSPICE-Model for InP HBT Proc. '13th Workshop on Physical Simulation of Semiconductor Devices', Ilkley, U.K., March 2002

2. B.SCHLOTHMANN, R.M.BERTENBURG1, M.AGETHEN1, P.VELLING1, W.BROCKERHOFF, .F-J.TEGUDE 1now with PAG – Innovative Processing AG, Duisburg RF-Simulation of InGaAs/InP Heterostructure Bipolar Transistors Proc. '13th Workshop on Physical Simulation of Semiconductor Devices', Ilkley, U.K., March 2002

3. B.SCHLOTHMANN, R.M.BERTENBURG1, M.AGETHEN1, P.VELLING1, W.BROCKERHOFF, .F-J.TEGUDE 1now with PAG – Innovative Processing AG, Duisburg Two Dimensional Physical Simulation of InGaAs/InP Heterostructure Bipolar Transistors Proc. of 'Workshop on Expert Evaluation and Control of Compound Semiconductor Materials and Technology' (EXMATEC 2002), Budapest, Hungary, May 2002

4. T.REIMANN, M.SCHNEIDER1, S.NEUMANN, A.STÖHR

1, D.JÄGER1, F-J.TEGUDE

1: Gerhard-Mercator-Universität Duisburg, Dept. of Optoelectronics

Waveguide HBT Electroabsorption Modulators: Devices and Circuits Proc. of 'Int. Conf. on InP and Related Materials' (IPRM 2002), Stockholm, Sweden, May 2002




MOVPE Growth and Polarisation Dependence of (dis-)ordered InGaAsP PIN Diodes for Optical Fibre Applications Proc. of 'Int. Conf. on InP and Related Materials' (IPRM 2002), Stockholm, Sweden, May 2002

6. F.OTTEN, F.E. KRUIS, W.PROST, F.J.TEGUDE, H.FISSAN1

Deposition of Gas-Phase Generated PbS Nanocrystals onto Patterned Substrates Proc. Nao-7, ECOSS-21, 24.-28.06.02, Malmö Schweden

7. P.GLOSEKÖTTER1, C.PACHA

1, K.F.GOSER1, W.PROST, S.KIM, H.VAN HUSEN, T.REIMANN, F.-

J.TEGUDE 1 : Universität Dortmund, LS Bauelemente der Elektrotechnik

Pseudo Dynamic Gate Design based on the Resonant Tunneling Bipolar Transistor (RTBT) Proc. of 'Europ. Conf. on Solid-State Devices and Circuits', (ESSDERC), Florence, Italy, 24.-26.09.02

8. T.REIMANN, M.SCHNEIDER1, S.NEUMANN, D.JÄGER

1, F.-J.TEGUDE 1: Gerhard-Mercator-Universität Duisburg, Dept. of Optoelectronics

Different Approaches for Integrating HBTs and EAMs Proc. of 'EDMO 2002', 19.-19.11.02, Manchester, U.K.





Spontaneous Group III and V Superlattice Ordering in InGaAsP Proc. of '26th Int. Conf. on the Physics of Semiconductors, Edinburgh, U.K., 2002






Spontaneous Group III and V Superlattice Ordering in InGaAsP Proc. of '6th Int. Conf. on Signal Processing', Bejing, China, 26.-30.08.02

11. W.PROST

Resonant Tunneling Diodes for Digital Applications Proc. of '4th Advanced Semiconductor Devices and Microsystems', Smolenice, Slovakia, 14.-16.10.02

12. F.OTTEN, U,AUER, F.E.KRUIS, W.PROST, F.-J.TEGUDE, H.FISSAN1

1 Process- and Aerosol Measurement Technology Division, Gerhard-Mercator-University Duisburg

Lithographic Tools for Producing Patterned Films Composed of Gas Phyase Generated Nanocrystals Materials Science and Tehcnology, July 2002, Vol.18, pp.717

13. S.NEUMANN, W.PROST, F.J.TEGUDE

Growth of Carbon Doped InAlAs with LP-MOVPE and non Gaseous Sources Journal of Chrystal Growth, Spec.Issue on ICMOVPE 2002

14. S.NEUMANN,A.BAKIN1, W.PROST, H.WEHMANN

1, A.SCHLACHETZKI1, F.J.TEGUDE

1 : TU Braunschweig, Inst. for Solid-State-Electronics

Growth of III/V Resonant Tunneling Diode on Si Substrate Journal of Chrystal Growth, Spec.Issue on ICMOVPE 2002




MOVPE Growth and Polarisation Dependence of (dis-)ordered InGaAsP PIN Diodes for Optical Fibre Applications Journal of Chrystal Growth, Spec.Issue on ICMOVPE 2002


1, K.F.GOSER1, W.PROST, S.KIM

2, H.V.HUSEN, T.REIMANN, F.J.TEGUDE 1 : Dept. of Microelectronics, University of Dortmund 2: Ferdinand-Braun Institut für Hochfrequenztechnik, Berlin

Asynchronous Circuit Design Based on the RTBT Monostable-Bistable Logic Transition Element (MOBILE) Proc. of '15th Symposium on Integrated Circuits and System Design', Chip in the Pampa, Porto Alegre, RS, Brazil, 09.-14.09.02

17. W.PROST, S.O.KIM1, P.GLÖSEKÖTTER

2, C.PACHA2, H.V.HUSEN, T.REIMANN, K.F.GOSER

2, F.J.TEGUDE 1: Ferdinand-Braun Institut für Hochfrequenztechnik, Berlin 2 : Dept. of Microelectronics, University of Dortmund

Experimental Thershold Logic Implementations Based on Resonant Tunneling Diodes Proc. of 'IEEE ICECS Conf.', Dubrovnik, 15.-18.09.02


18. M.SAGLAM1, B.SCHUMANN

2, V.MÜLLERWIEBUS2, A.MEGEJ

1, U,AUER, M.RODRIGUEZT-GIRONÉS1,

R.JUDASCHKE2, F.J.TEGUDE, H.-L.HARTNAGEL

1 1: Inst. für Hochfrequenztechnik, Technische Universität Darmstadt 2: Arbeitsbereich Hochfrequenztechnik, Technishce Universität Hamburg-Harburg

450 GHz mm-wave signal from a frequency tripler with heterostructure barrier varactors on gold substrate Electronic Letters, vol.38, no.13, June 2002, pp.657-658


1, P.VELLING1, W.BROCKERHOFF,

F.J.TEGUDE 1: IPAG-Innovative Processing AG, Duisburg

Two-Dimensional Physical Simulation of InGaAs/InP Heterostructure Bipolar Transistors phys.stat.sol. (c), No.3, pp.922-927, 2003



LP-MOVPE growth for high-speed electronic devices on InP Proc. of 'Europ. Workshop on MOVPE (EW-MOVPE)', Lecce, Italy, 08.-11.06.03

21. W.PROST

Beiträge der Nanotechnologie zur ERrhöhung der Funktionalität und Dichte in der Elektronik Workshop 'Kontrollierte Selbstorganisation für zukünftige technische Anwendungen', Düsseldorf, Germany, 16.-17.06.03

22. S.EHRICH, M.AGETHEN1, P.VELLING

1, A.BRENNEMANN1, R.M.BERTENBURG

1, W.BROCKERHOFF, F.J.TEGUDE

Scaling of Small-Signal and RF-Noise Parameters with Respect to the Emitter-Area of Single HBT based on InP Proc. of '14th Workshop on Modelling and Simulation of Electron Devices', Barcelona, Spain, 16.-17.10.03,



Growth of Carbon doped InAlAs with LP-MOVPE and non gaseous sources J. Crystal Growth 248 (2003) 130-133.


1, P.KIESEL1, W.PROST, G.H.DÖHLER

1, F.J.TEGUDE; 1: Inst. of Technical Physics 1, University Erlangen

MOVPE Growth and Polarisation Dependence of (dis-)ordered InGaAsP PIN Diodes for Optical Fibre Applications J. Crystal Growth 248 (2003) 158-162.

25. S. NEUMANN A. BAKIN1, W. PROST, H.-H. WEHMANN

1, A. SCHLACHETZKI1, F.J.TEGUDE

1 : TU Braunschweig, Inst. for Solid-State-Electronics

Growth of III/V Resonant Tunnelling Diode on Si Substrate with LP-MOVPE J. Crystal Growth 248 (2003) 380-383.



1, K.F.GOSER1, W.PROST, S.KIM, H. VAN HUSEN, T.REIMANN,

F.J.TEGUDE; 1 : Dept. of Microelectronics, University of Dortmund

Circuit and Application Aspects of Tunneling Devices in a MOBILE configuration J Circuit Theory and Applications, vol.31, no.1, p.83-103, 2003.


InP based double heterojunction bipolar transistor with carbon doped GaAsSb:C base grown by LP-MOVPE Proc. of '11th Gallium Arsenide Application Symposium (EuMC/ECWT/GAAS), Munich, Germany, 6.10.-7.10.03

28. Z.JIN, S.NEUMANN, W.PROST, F.-J.TEGUDE

Mechanism of Current Gain increase of Heterostrucutre Bipolar Transistors Passivated by Low-Temperature Deposited SiNx Proc. of '11th Gallium Arsenide Application Symposium (EuMC/ECWT/GAAS), Munich, Germany, 6.10.-7.10.03


Growth of Highly p-type Doped GaAsSb:C for HBT Application Proc. of 'Int. Conf. on InP and Related Materials' (IPRM 2003), Santa Barbara, USA, May 2003

30. Z.JIN, F.OTTEN, S.NEUMANN, R.REIMANN, W.PROST, F.-J.TEGUDE

Passivation of Graded-Base InP/InGaAs/InP Double Heterostrucutre Bipolar Transitors by Romm-Temperature Deposited SiNx

Proc. of 'Int. Conf. on InP and Related Materials' (IPRM 2003), Santa Barbara, USA, May 2003

31. V. KHORENKO1, K. K. NANDA

2, W. PROST1, F. E. KRUIS

2, H.FISSAN2, F.-J. TEGUDE

1 1 : Solid State Electronics Dept., University of Duisburg-Essen, 2 : Process- and Aerosol Measurement Technology, University of Duisburg-Essen

Embedding of the gas-phase generated indium nanoparticles in epitaxial matrix Proc. of Nanoparticle Science and Engineering Summer Workshop, Minneapolis,USA, July 17-18, 2003.

32. V. KHORENKO1, K. K. NANDA

2, W. PROST1, F. E. KRUIS

1, H.FISSAN2, F.-J. TEGUDE

1 1 : Solid State Electronics Dept., University of Duisburg-Essen, 2: Process- and Aerosol Measurement Technology, University of Duisburg-Essen

Formation of zero-dimensional nanostructures by epitaxial overgrowth gas-phase generated indium nanoparticles Abstract book of European Material Research Society (EMRS) Meeting, Strasbourg , France, 10 - 13. 06.2003.

33. K.D. KATZER1, V. KHORENKO

2, Q.T. DO2, W. MERTIN

1, F.J. TEGUDE2, W. PROST

2, D. CUNNINGHAM

3, J.-L. MARTINEZ-ALBERTOS3, B. MOORE

3 1 : Dept. of Materials of Electrical Engineering, University Duisburg-Essen, 2 : Solid-State-Electronics Dept., University Duisburg-Essen, 3 : Dept. of Pure and Applied Chemistry, University of Strathclyde, UK. Talk

Electrical characterisation of self-assembled nanoparticle coated crystals Proc. of Electronic Materials Conference, Salt Lake City, June 25-27, 2003


4.7 Research Projects

• Waveguide modulators supported by Deutsche Forschungsgemeinschaft (DFG) together with the Dept. of Optoelectronics, Gerhard-Mercator Universität, Duisburg

• RTDs and HBTs for dynamic digital circuits supported by Deutsche Forschungsgemeinschaft (DFG)

• Lateral Deposition Control supported by Deutsche Forschungsgemeinschaft (DFG), together with the Dept. of Process and

Aerosol Technoogy

• Development of a Monolithically Integrated 40Gb/s Optoelectronic Receiver Front-End on InP

supported by Fa. Multilink

• Development of Highly Linear Transmitter Amplifier supported by Bundesministerium für Bildung und Forschung (BMBF), subcontractor of the

United Monolithic Semiconductors UMS

• Simulations of Heterostructure Bipolar Transistors supported by Deutsche Forschungsgemeinschaft (DFG)

• Quantum Tunneling Device Technology on Silicon (QUDOS) supported by European Union (EU)) together with

- Max-Planck Gesellschaft zur Förderung der Wissenschaften e.V., Max-Planck-Institut fuer Festkörperforschung

- Technische Universitaet Braunschweig, Institut fuer Halbleiterforschung - University of Cambridge, Department of Physics, U.K. - University of Ulster, Department of Physics, U.K.

• Self-assembled building blocks for nanocomputer (ESCHER) supported by European Union (EU) together with

- Department of Materials of Electrical Engineering - University College London, U.K. - University of Strathclyde, U.K. - Institute of Microelectronics, NCSR 'Demokritos' Athens, Greece


• A/D converter in superconductor-semiconductor hybrid technology (Super ADC) supported by European Union (EU)) together with

- Chalmers University of Technology, S - University of Twente, NL - THALES, F - Air Liquide, F - Ericcson Microelectronics, S

• InP-Electronic for +80Gbit/s supported by Bundesministerium für Bildung und Forschung (BMBF) together with

- Fraunhofer-Institu für Angewandte Festkörperphysik (IAF), Freiburg - Ferdinand-Braun-Institut für Höchstfrequenztechnik (FBH), Berlin

• Nano Particles from the Gas Phase Sonderforschungsbereich 445 (SFB 445), supported by Deutsche Forschungsgemeinschaft (DFG)

together with other departments at the University Duisburg-Essen


4.8 Other Activities During the last two years, the department was responsible for the organisation of several European and national project meetings at University Duisburg-Essen:

• Quantum Tunneling Device Technology on Silicon (QUDOS) (december 2002)

• Self-assembled building blocks for nanocomputer (ESCHER)

• A/D converter in superconductor-semiconductor hybrid technology (Super ADC) (november 2002)

• BMBF-InP-Electronics, status meeting ( january 2003)

Additionally, members of the department together with other colleagues from other departments of the faculty are strongly engaged in the public relations work to recruit new students for the study of electronics and to increase the number of beginners. The department was involved in establishing a new marketing concept within a common project together with students from the "Verwaltungs- und Wirtschaftsakademie" in Essen. The new faculty internet presence (http://www.dueti.de) for interested pupils demonstrates the new concept which was realized under the leadership of Dr. P.Waldow.

Besides the organization of exhibition stands on base of this new concept at various fairs in the area surrounding Duisburg (e.g. BOOT in Duesseldorf, didacta in cologne, azubi-tage in Essen et al.), alumni activities were started and intensified during the last years together with some colleages under the leadership of Prof. H.Luck (http://alumni.uni-duisburg.de). More than 350 actual and former students became member of the electronics alumni network "netzwerkElektroDU" during the last years. This group also organizes a newsletter which is regularly published four times per year. Since two years, this group is engaged to establish a traditional ceremony finishing the academic year including the presentation of awards for the best final examinations and doctor thesis, a date which allows many former colleages and students to keep in touch with the faculty and the university.

The exhibition stand of the electronics at the BOOT in Duesseldorf demonstrationg the new marketing

concept of the electronics faculty. Minister Schartau was one of the first interested visitors


A group of pupils interested in the study of electronics during a lab tour at the centre for

solid-state electronics and optoelectronics (ZHO)

"azubi-tage" in Essen

Many pupils are interested in informations about study courses and the university

"Schülertag" at the University Duisburg-Essen with lab tours

The dean of the faculty, Prof.Dr.Klaus

Solbach, presents the award for the excellent Ph.D. thesis to Dr. Peter Velling


Guide to the Solid-State Electronics Department (HLT)

B M

Hbf

Mülheimerstr.Mülheimerstr.

Landfermannstr.

Königstr.

Neu

dorf e

r Str.

Komm

anda

nten

str.

Koloniestr.

Bism

arck

str.

Ster

nbus

chwe

g (B8

)

Ster

nbus

chweg

(B8)

Sch

wei

zer S

tr. (B

8)

Mozart

str.

Loth

arst

r.

Loth

arst

r,Finkenstr.

Bürgerstr.

Kammerstr.

Zoo

Abfahrt (exit)Duisburg-Kaiserberg

Abfahrt (exit)Duisburg-Wedau

Autobahnkreuz Duisburg-Mitte

A59 Wesel A2/A3Hannover/Emmerich

A40

A3

Köln

A59Düsseldorf

A40Krefeld/ Moers

Rathaus

Düs

seld

orfe

r Str.

Düs

seld

orfe

r Str.

Düs

seld

orfe

r Str.

(B8)

Sportpark Wedau

N

*) ZHO: Zentrum für Halbleitertechnik und Optoelektronik(Center for solid-state electronics and optoelectronics)

LLo

thar

str.

(Haupteingang)main entrance

HighwayLT

ZHO*)

Travel by car: The Solid-State Electronics Department (HLT) at the ZHO (Zentrum fuer Halbleitertechnik und Optoelektronik) can be reached by car via various highways: A3 from the South, A40 from the Netherlands and the East, A2/A3 from the North. Exit: Duisburg-Kaiserberg or Duisburg-Wedau (see map).

Travel by train: The main station (Hauptbahnhof (Hbf)) is 25 min (walk) away from the Solid-State Electronics Department (HLT) and the ZHO (see map). Take the bus 933, 936 or 924 to "Universität/Städtische Kliniken" and leave it at "Universität (Uni-Nord)" or take the tram 901 to "Mülheim" and leave it at "Universität".

Travel by plane: After landing at Duesseldorf Airport (the next airport to Duisburg) take the city-train (S-Bahn) S1 from Duesseldorf to Duisburg main station (Hauptbahnhof (Hbf)). For further informations see: "Travel by train":

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