Digital Logic Design

CS-3023-0-0 : 3 Credit

Switching Circuits: Logic families: TTL, nMOS, CMOS, dynamic CMOS and pass transistor logic (PTL) circuits, inverters and other logic gates, area, power and delay characteristics, concepts of fan-in, fan-out and noise margin.

Switching theory: Boolean algebra, logic gates, and switching functions, truth tables andswitching expressions, minimization of completely and incompletely specified switching functions, Karnaugh map and Quine-McCluskey method, multiple output minimization, representation and manipulation of functions using BDDs, two-level and multi-level logic circuit synthesis.

Combinational logic circuits: Realization of Boolean functions using NAND/NOR gates,Decoders, multiplexers. logic design using ROMs, PLAs and FPGAs. Case studies.

Sequential circuits: Clocks, flip-flops, latches, counters and shift registers, finite-state machinemodel, synthesis of synchronous sequential circuits, minimization and state assignment,asynchronous sequential circuit synthesis.

ASM charts: Representation of sequential circuits using ASM charts, synthesis of output andnext state functions, data path control path partition-based design.

Syllabus

Book:

# Digital Design- Moris Mano & Michael D Ciletti# Digital Electronics William Kleitz

References1. H. Taub and D. Schilling, Digital Integrated Electronics, McGraw-Hill .2. Z. Kohavi, Switching and Finite Automata Theory, Tata McGraw-Hill.3. Randy H. Katz and Gaetano Borriello, Contemporary Logic Design, Prentice Hall of India.4. Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, Tata McGraw-Hill.

Evaluation Procedure :

Class test : 20Attendance: 05Class Performance : 05Examination: 70 (Mid+End)

Digital Logic Design

3-6

Transistor: Building Block of ComputersMicroprocessors contain millions of transistors

Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple PowerPC G5 (2003): 58 million

Logically, each transistor acts as a switchCombined to implement logic functions

AND, OR, NOTCombined to build higher-level structures

Adder, multiplexer, decoder, register, Combined to build processor

LC-3

Moore's Law

In 1965, Gordon Moore co-founder of the Intel corporation predicted that "The number of transistors and resistors on a single chip will double every 18 months" regarding the development of semiconductor gate technology. When Moore made his famous comment way back in 1965 there were approximately only 60 individual transistor gates on a single silicon chip or die. Today, the Intel Corporation have placed around 2.0 Billion individual transistor gates onto its new Quad-core Itanium 64-bit microprocessor chip and the count is still rising!.

Logic Families

In order to assure correct operation when gates are interconnected they are normally produced in familiesThe most widely used families are:- complementary metal oxide semiconductor (CMOS): the 4000 series of chips

- transistor-transistor logic (TTL): the 7400 series- emitter-coupled logic (ECL)

Logic Families Logic Families TTL (Transistor Transistor Logic) Integrated-circuit technology that uses the bipolar transistor as the principal circuit element.

CMOS (Complimentary Metal Oxide Semiconductor) Integrated-circuit technology that uses the field-effect transistor as the principal circuit element.

ECL (Emitter Coupled Logic) Integrated-circuit technology that uses the bipolar transistors configured as a differential amplifier. This eliminates saturation and improves speed but uses more power than other families.

Logic Family Characteristics

Complementary metal oxide semiconductor (CMOS)most widely used family for large-scale devicescombines high speed with low power consumptionusually operates from a single supply of 5 15 Vexcellent noise immunity of about 30% of supply voltagecan be connected to a large number of gates (about 50)many forms some with tPD down to 1 ns

power consumption depends on speed (perhaps 1 mW)

Transistor-transistor logic (TTL)based on bipolar transistorsone of the most widely used families for small- and medium-scale devices rarely used for VLSItypically operated from 5V supplytypical noise immunity about 1 1.6 Vmany forms, some optimised for speed, power, etc.high speed versions comparable to CMOS (~ 1.5 ns)low-power versions down to about 1 mW/gate

Emitter-coupled logic (ECL)based on bipolar transistors, but removes problems of storage time by preventing the transistors from saturatingvery fast operation - propagation delays of 1ns or lesshigh power consumption, perhaps 60 mW/gatelow noise immunity of about 0.2-0.25 Vused in some high speed specialist applications, but now largely replaced by high speed CMOS

DIGITAL IC SPECIFICATIONS Drive Capabilities- sometimes referred to as fan-in

or fan-out.

Fan out- number of inputs of a logic family that can be driven by a single output. The drive capability of outputs.

Fan in- the load an input places on an output.

Propagation delay- has to do with the speed of the logic element. Lower propagation delays mean higher speed which is a desirable characteristic.

Power Dissipation- generally, as propagation delays decrease, power consumption and heat generation increase. CMOS is noted for low power consumption.

A Comparison of Logic Families 25.5

Parameter CMOS TTL ECL

Basic gate NAND/NOR NAND OR/NOR

Fan-out >50 10 25

Power per gate (mW) 1 @ 1 MHz 1 - 22 4 - 55

Noise immunity Excellent Very good Good

tPD (ns) 1 - 200 1.5 33 1 - 4

1. The drive capability of logic device outputs is sometimes called ___ (fan in, fan out). It is the number of inputs of a logic family that can be

driven by a single output.

(Left click mouse for questions and answers)

Fan Out

2. CMOS devices are noted for their extremely ___ (high, low) power consumption.

Low

3. A logic device with a low propagation delay would be considered to be a ___ (high, low)

speed device.High

4. Several desirable characteristics of logic devices are good drive capabilities, low power consumption, and ___ (high, low)

propagation delays.

Low

TEST

Key Points

Physical gates are not ideal componentsLogic gates are manufactured in a range of logic familiesThe ability of a gate to ignore noise is its noise immunityBoth MOSFETs and bipolar transistors are used in gatesAll logic gates exhibit a propagation delay when responding to changes in their inputsThe most widely used logic families are CMOS and TTLCMOS is available in a range of forms offering high speed or very low power consumptionTTL logic is also produced in many versions, each optimised for a particular characteristic

Classification of Integrated Circuits:

Small Scale Integration or (SSI) - Contain up to 10 transistors or a few gates within a single package such as AND, OR, NOT gates.

Medium Scale Integration or (MSI) - between 10 and 100 transistors or tens of gates within a single package and perform digital operations such as adders, decoders, counters, flip-flops and multiplexers.

Large Scale Integration or (LSI) - between 100 and 1,000 transistors or hundreds of gates and perform specific digital operations such as I/O chips, memory, arithmetic and logic units.

Very-Large Scale Integration or (VLSI) - between 1,000 and 10,000 transistors or thousands of gates and perform computational operations such as processors, large memory arrays and programmable logic devices.

Super-Large Scale Integration or (SLSI) - between 10,000 and 100,000 transistors within a single package and perform computational operations such as microprocessor chips, micro-controllers, basic PICs and calculators.

Ultra-Large Scale Integration or (ULSI) - more than 1 million transistors - the big boys that are used in computers CPUs, GPUs, video processors, micro-controllers, FPGAs and complex PICs.

3-18

Simple Switch Circuit

Switch open: No current through circuit Light is off Vout is +2.9V

Switch closed: Short circuit across switch Current flows Light is on Vout is 0V

Switch-based circuits can easily represent two states:on/off, open/closed, voltage/no voltage.

3-19

n-type MOS TransistorMOS = Metal Oxide Semiconductor

two types: n-type and p-typen-type

when Gate has positive voltage,short circuit between #1 and #2(switch closed)

when Gate has zero voltage,open circuit between #1 and #2(switch open)

Gate = 1

Gate = 0Terminal #2 must be

connected to GND (0V).

3-20

p-type MOS Transistorp-type is complementary to n-type

when Gate has positive voltage,open circuit between #1 and #2(switch open)

when Gate has zero voltage,short circuit between #1 and #2(switch closed)

Gate = 1

Gate = 0Terminal #1 must beconnected to +2.9V.

3-21

Logic GatesUse switch behavior of MOS transistorsto implement logical functions: AND, OR, NOT.

Digital symbols: recall that we assign a range of analog voltages to each

digital (logic) symbol

assignment of voltage ranges depends on electrical properties of transistors being usedtypical values for "1": +5V, +3.3V, +2.9Vfrom now on we'll use +2.9V

3-22

CMOS CircuitComplementary MOSUses both n-type and p-type MOS transistors

p-typeAttached to + voltagePulls output voltage UP when input is zero

n-typeAttached to GNDPulls output voltage DOWN when input is one

For all inputs, make sure that output is either connected to GND or to +,but not both!

CMOS Inverter

p

n

GND

VDD

A Y = A'

Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting.

When input A is grounded (logic 0), the N-channel MOSFET is unbiased, and therefore has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line disconnected from ground. At the same time, the P-channel MOSFET is forward biased, so it has a channel enhanced within itself, connecting the output line to the +Vsupply. This pulls the output up to +V (logic 1).

When input A is at +V (logic 1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output state.

CMOS Inverter - Operation

3-25

Inverter (NOT Gate)

In Out

0 V 2.9 V

2.9 V 0 V

In Out

0 1

1 0

Truth table

3-26

AND Gate

Add inverter to NAND.

A B C

0 0 0

0 1 0

1 0 0

1 1 1

3-27

OR Gate

Add inverter to NOR.

A B C

0 0 0

0 1 1

1 0 1

1 1 1

3-28

A B C

0 0 1

0 1 0

1 0 0

1 1 0Note: Serial structure on top, parallel on bottom.

NOR Gate

3-29

A B C

0 0 1

0 1 1

1 0 1

1 1 0Note: Parallel structure on top, serial on bottom.

NAND Gate (AND-NOT)

30

Constructing Gates

Transistor A device that acts either as a wire that conducts electricity or as a resistor that blocks the flow of electricity, depending on the voltage level of an input signal A transistor has no moving parts, yet acts like a switchIt is made of a semiconductor material, which is neither a particularly good conductor of electricity nor a particularly good insulator

31

Constructing Gates

A transistor has three terminals

A source A base An emitter, typically

connected to a ground wire

If the electrical signal is grounded, it is allowed to flow through an alternative route to the ground (literally) where it can do no harmFigure 4.8 The connections of a transistor

32

Constructing Gates

The easiest gates to create are the NOT, NAND, and NOR gates

Figure 4.9 Constructing gates using transistors

3-33

Basic Logic Gates

3-34

DeMorgan's LawConverting AND to OR (with some help from NOT)Consider the following gate:

A B

0 0 1 1 1 0

0 1 1 0 0 1

1 0 0 1 0 1

1 1 0 0 0 1

ABBA AB

Same as A+B!

To convert AND to OR (or vice versa),

invert inputs and output.

3-35

More than 2 Inputs?AND/OR can take any number of inputs.

AND = 1 if all inputs are 1. OR = 1 if any input is 1. Similar for NAND/NOR.

Can implement with multiple two-input gates,or with single CMOS circuit.

3-36

SummaryMOS transistors are used as switches to implementlogic functions.

n-type: connect to GND, turn on (with 1) to pull down to 0 p-type: connect to +2.9V, turn on (with 0) to pull up to 1

Basic gates: NOT, NOR, NAND Logic functions are usually expressed with AND, OR, and NOT

DeMorgan's Law Convert AND to OR (and vice versa)

by inverting inputs and output

3-37

Building Functions from Logic GatesCombinational Logic Circuit

output depends only on the current inputs stateless

Sequential Logic Circuit output depends on the sequence of inputs (past and present) stores information (state) from past inputs

We'll first look at some useful combinational circuits,then show how to use sequential circuits to store information.

3-38

Decodern inputs, 2n outputs

exactly one output is 1 for each possible input pattern

2-bitdecoder

3-39

Multiplexer (MUX)n-bit selector and 2n inputs, one output

output equals one of the inputs, depending on selector

4-to-1 MUX

3-40

Full AdderAdd two bits and carry-in,produce one-bit sum and carry-out. A B Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

3-41

Four-bit Adder

3-42

Logical CompletenessCan implement ANY truth table with AND, OR, NOT.

A B C D

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 0

1. AND combinations that yield a "1" in the truth table.

2. OR the resultsof the AND gates.

3-43

Combinational vs. SequentialCombinational Circuit

always gives the same output for a given set of inputsex: adder always generates sum and carry,

regardless of previous inputsSequential Circuit

stores information output depends on stored information (state) plus input

so a given input might produce different outputs,depending on the stored information

example: ticket counteradvances when you push the buttonoutput depends on previous state

useful for building memory elements and state machines

3-44

R-S Latch: Simple Storage ElementR is used to reset or clear the element set it to zero.S is used to set the element set it to one.

If both R and S are one, out could be either zero or one. quiescent state -- holds its previous value note: if a is 1, b is 0, and vice versa

1

0

1

1

1

1

0

0

1

1

0

0

1

1

3-45

Clearing the R-S latchSuppose we start with output = 1, then change R to zero.

Output changes to zero.

Then set R=1 to store value in quiescent state.

1

0

1

1

1

1

0

0

1

0

1

0

0

0

1

1

3-46

Setting the R-S LatchSuppose we start with output = 0, then change S to zero.

Output changes to one.

Then set S=1 to store value in quiescent state.

1

1

0

0

1

1

0

1

1

1

0

0

3-47

R-S Latch SummaryR = S = 1

hold current value in latchS = 0, R=1

set value to 1R = 0, S = 1

set value to 0

R = S = 0 both outputs equal one final state determined by electrical properties of gates Dont do it!

3-48

Gated D-LatchTwo inputs: D (data) and WE (write enable)

when WE = 1, latch is set to value of DS = NOT(D), R = D

when WE = 0, latch holds previous valueS = R = 1

3-49

RegisterA register stores a multi-bit value.

We use a collection of D-latches, all controlled by a common WE.

When WE=1, n-bit value D is written to register.

3-50

Representing Multi-bit ValuesNumber bits from right (0) to left (n-1)

just a convention -- could be left to right, but must be consistentUse brackets to denote range:D[l:r] denotes bit l to bit r, from left to right

May also see A, especially in hardware block diagrams.

A = 0101001101010101

A[2:0] = 101A[14:9] = 101001

015

3-51

MemoryNow that we know how to store bits,we can build a memory a logical k m array of stored bits.

k = 2nlocations

m bits

Address Space:number of locations(usually a power of 2)

Addressability:number of bits per location(e.g., byte-addressable)

3-52

22 x 3 Memory

addressdecoder

word select word WEaddress

writeenable

input bits

output bits

3-53

More Memory DetailsThis is a not the way actual memory is implemented.

fewer transistors, much more dense, relies on electrical properties

But the logical structure is very similar. address decoder word select line word write enable

Two basic kinds of RAM (Random Access Memory)Static RAM (SRAM)

fast, maintains data as long as power appliedDynamic RAM (DRAM)

slower but denser, bit storage decays must be periodically refreshed

Also, non-volatile memories: ROM, PROM, flash,

3-54

State MachineAnother type of sequential circuit

Combines combinational logic with storage Remembers state, and changes output (and state)

based on inputs and current state

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs

3-55

Combinational vs. SequentialTwo types of combination locks

4 1 8 430

15

5

1020

25

CombinationalSuccess depends only onthe values, not the order in which they are set.

SequentialSuccess depends onthe sequence of values(e.g, R-13, L-22, R-3).

3-56

StateThe state of a system is a snapshot ofall the relevant elements of the systemat the moment the snapshot is taken.

Examples: The state of a basketball game can be represented by

the scoreboard.Number of points, time remaining, possession, etc.

The state of a tic-tac-toe game can be represented bythe placement of Xs and Os on the board.

3-57

State of Sequential LockOur lock example has four different states,labelled A-D:

A: The lock is not open,and no relevant operations have been performed.

B: The lock is not open,and the user has completed the R-13 operation.

C: The lock is not open,and the user has completed R-13, followed by L-22.

D: The lock is open.

3-58

State DiagramShows states and actions that cause a transition between states.

3-59

Finite State MachineA description of a system with the following components:

1. A finite number of states2. A finite number of external inputs3. A finite number of external outputs4. An explicit specification of all state transitions5. An explicit specification of what determines each

external output value

Often described by a state diagram. Inputs trigger state transitions. Outputs are associated with each state (or with each transition).

3-60

The ClockFrequently, a clock circuit triggers transition fromone state to the next.

At the beginning of each clock cycle,state machine makes a transition,based on the current state and the external inputs.

Not always required. In lock example, the input itself triggers a transition.

10

timeOneCycle

3-61

Implementing a Finite State MachineCombinational logic

Determine outputs and next state.Storage elements

Maintain state representation.

State Machine

CombinationalLogic Circuit

StorageElements

Inputs Outputs

Clock

3-62

Storage: Master-Slave FlipflopA pair of gated D-latches, to isolate next state from current state.

During 1st phase (clock=1),previously-computed statebecomes current state and issent to the logic circuit.

During 2nd phase (clock=0),next state, computed bylogic circuit, is stored inLatch A.

3-63

StorageEach master-slave flipflop stores one state bit.

The number of storage elements (flipflops) neededis determined by the number of states(and the representation of each state).

Examples: Sequential lock

Four states two bits Basketball scoreboard

7 bits for each score, 5 bits for minutes, 6 bits for seconds,1 bit for possession arrow, 1 bit for half,

3-64

Complete ExampleA blinking traffic sign

No lights on 1 & 2 on 1, 2, 3, & 4 on 1, 2, 3, 4, & 5 on (repeat as long as switch

is turned on)

DANGERMOVERIGHT

1

2

34

5

3-65

Traffic Sign State Diagram

State bit S1 State bit S0

Switch onSwitch off

Outputs

Transition on each clock cycle.

3-66

Traffic Sign Truth Tables

Outputs(depend only on state: S1S0)

S1 S0 Z Y X

0 0 0 0 0

0 1 1 0 0

1 0 1 1 0

1 1 1 1 1

Lights 1 and 2Lights 3 and 4

Light 5

Next State: S1S0(depend on state and input)

In S1 S0 S1 S0

0 X X 0 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 1

1 1 1 0 0

Switch

Whenever In=0, next state is 00.

3-67

Traffic Sign Logic

Master-slaveflipflop

3-68

From Logic to Data PathThe data path of a computer is all the logic used toprocess information.

See the data path of the LC-3 on next slide.

Combinational Logic Decoders -- convert instructions into control signals Multiplexers -- select inputs and outputs ALU (Arithmetic and Logic Unit) -- operations on data

Sequential Logic State machine -- coordinate control signals and data movement Registers and latches -- storage elements

3-69

LC-3 Data Path

CombinationalLogic

State Machine

Storage

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