MODELING, SIMULATION AND IMPLEMENTATION MODELING, SIMULATION AND IMPLEMENTATION OF A NON-COHERENT BINARY FREQUENCY OF A NON-COHERENT BINARY FREQUENCY

SHIFT KEYING (BFSK) RECEIVER-TRANSMITTER SHIFT KEYING (BFSK) RECEIVER-TRANSMITTER INTO A FIELD PROGRAMMABLE GATE ARRAY INTO A FIELD PROGRAMMABLE GATE ARRAY

(FPGA)(FPGA)

Juan P SvenningsenJuan P Svenningsen

CaptCapt USMCUSMCAdvisor: H.H. LoomisAdvisor: H.H. LoomisCo-Advisor: F.E. KraghCo-Advisor: F.E. Kragh

Sponsored by MCTSSASponsored by MCTSSA

AgendaAgenda

• BackgroundBackground

• Design ApproachDesign Approach

• Design parametersDesign parameters

• DesignsDesigns

• ResultsResults

• ConclusionsConclusions

• RecommendationsRecommendations

BackgroundBackgroundSingle Channel Ground and Airborne Radio System (SINCGARS)Single Channel Ground and Airborne Radio System (SINCGARS)

• MCTSSA requested that research be done regarding MCTSSA requested that research be done regarding the SINCGARS (RT-1523C) manpack variant’s the SINCGARS (RT-1523C) manpack variant’s ineffectiveness in data transfer when in foot-mobile ineffectiveness in data transfer when in foot-mobile operationsoperations– Reports via data reduce channel trafficReports via data reduce channel traffic– Orders via data increase speed of info exchangeOrders via data increase speed of info exchange– Networking of foot mobile unitsNetworking of foot mobile units

• SINCGARS ground radio has been enhanced for SINCGARS ground radio has been enhanced for vehicle and stationary operations, the foot-mobile vehicle and stationary operations, the foot-mobile variant was only expected to perform voice variant was only expected to perform voice communicationscommunications

• RT-1523C antennas have been identified as a RT-1523C antennas have been identified as a weakness in the system (PRC-77 legacy, never weakness in the system (PRC-77 legacy, never updated)updated)

BackgroundBackgroundSingle Channel Ground and Airborne Radio System (SINCGARS)Single Channel Ground and Airborne Radio System (SINCGARS)

• RT-1523C Characteristics:RT-1523C Characteristics:– Carrier Sense Multiple Access (CSMA) channel Carrier Sense Multiple Access (CSMA) channel

access algorithm access algorithm – Binary Frequency Shift Keying (BFSK) modulationBinary Frequency Shift Keying (BFSK) modulation– Frequency Hopping WaveformFrequency Hopping Waveform– Non-coherent detectionNon-coherent detection– RRbb = 16 kbps = 16 kbps

– ffcc = 12.5 MHz = 12.5 MHz– Allocated Channel BW = 25 kHz Allocated Channel BW = 25 kHz – Frequency range: 30 – 87.975 MHzFrequency range: 30 – 87.975 MHz– Reed-Solomon CodingReed-Solomon Coding

BackgroundBackgroundProgrammable DevicesProgrammable Devices

• The programmable logic market started with the programmable The programmable logic market started with the programmable logic array device (PLA) and worked it’s way to the FPGA and logic array device (PLA) and worked it’s way to the FPGA and complex programmable logic devices (complex programmable logic devices (CPLDsCPLDs) that we see ) that we see today.today.

• FPGAFPGAs are Integrated Circuits (ICs) that are made of many s are Integrated Circuits (ICs) that are made of many small programmable logic blocks and a fully programmable small programmable logic blocks and a fully programmable distribution network that dominates the area of the chip; in distribution network that dominates the area of the chip; in contrast CPLDs arrange logic elements into PLDs and link the contrast CPLDs arrange logic elements into PLDs and link the PLDs with a programmable switch matrixPLDs with a programmable switch matrix

• FPGAs have a FPGAs have a denser logic element denser logic element count than CPLDs and are count than CPLDs and are volatile in nature, so when the chip is power down it loses it’s volatile in nature, so when the chip is power down it loses it’s programmed definition programmed definition

• CPLDs are permanent or semi-permanent programmable CPLDs are permanent or semi-permanent programmable devices that once programmed, they hold their logic definition devices that once programmed, they hold their logic definition until it is reprogrammed (if possible, it depends on the device)until it is reprogrammed (if possible, it depends on the device)

Stratix FPGAStratix FPGA

PLDPLD

Stratix FPGA Logic ElementStratix FPGA Logic Element

BackgroundBackgroundProgrammable DevicesProgrammable Devices

• Due to nature of FPGAs and CPLDs, it is Due to nature of FPGAs and CPLDs, it is possible to create systems that use both; the possible to create systems that use both; the CPLD can be programmed to recall the CPLD can be programmed to recall the hardware definition from memory in order to hardware definition from memory in order to program the FPGA at system start-upprogram the FPGA at system start-up

• If a system start-up CPLD is not used, the FPGA If a system start-up CPLD is not used, the FPGA must be reprogrammed each time the system is must be reprogrammed each time the system is powered downpowered down

• FPGAs tend to be larger in area and more FPGAs tend to be larger in area and more expensive than CPLDsexpensive than CPLDs

BackgroundBackgroundMCTSSA Request for WorkMCTSSA Request for Work

• MCTSSA provided two Altera Stratix Edition DSP MCTSSA provided two Altera Stratix Edition DSP Development BoardsDevelopment Boards, with a Stratix FPGA , with a Stratix FPGA onboard, for the purpose of implementing the onboard, for the purpose of implementing the RT-1523C onto the boards for testing and RT-1523C onto the boards for testing and system examination purposessystem examination purposes

• MCTSSA requested a solution that would at MCTSSA requested a solution that would at least implement the RT-1523C modulation and least implement the RT-1523C modulation and lessons learned for further work with the DSP lessons learned for further work with the DSP boardsboards

Altera DSP Development BoardAltera DSP Development Board

Design ApproachDesign ApproachDesignDesign FlowsFlows

Design ApproachDesign Approach

• Stair Step ApproachStair Step Approach• Design and evaluate in software:Design and evaluate in software:

– OOK TransmitterOOK Transmitter– BFSK TransmitterBFSK Transmitter– BFSK ReceiverBFSK Receiver– BFSK RTBFSK RT

• Program into hardware:Program into hardware:– 8-bit counter (hardware familiarization)8-bit counter (hardware familiarization)– OOK TxOOK Tx– BFSK TxBFSK Tx– BFSK RxBFSK Rx– BFSK RTBFSK RT

Design ApproachDesign ApproachSoftware DesignSoftware Design ToolsTools

• MATLABMATLAB– SimulinkSimulink

• DSP BuilderDSP Builder: installed in Simulink via the MATLAB : installed in Simulink via the MATLAB command window. It allows for the use of Simulink as command window. It allows for the use of Simulink as the design input method by using the Simulink the design input method by using the Simulink environment and the DSP Builder blocks that are installed environment and the DSP Builder blocks that are installed in the DSP Builder library within the Simulink libraryin the DSP Builder library within the Simulink library

– SignalCompilerSignalCompiler: a DSP builder block that allows for the use of : a DSP builder block that allows for the use of Quartus II directly from the Simulink environment; allows design Quartus II directly from the Simulink environment; allows design analysis, synthesis and programming file creation from Simulinkanalysis, synthesis and programming file creation from Simulink

• AlteraAltera– Quartus IIQuartus II

• Device ProgrammerDevice Programmer

Design ParametersDesign ParametersSystem Diagram and ParametersSystem Diagram and Parameters

7.5 MHzBWn2n

1.25 MbpsRb

800 nsTb

10 MHzf1

5 MHzf0

80 MHzfclock

DesignsDesignsOOK TxOOK Tx

DesignsDesignsBFSK TxBFSK Tx

Noncoherent BFSK ReceiverNoncoherent BFSK Receiver

DesignsDesignsBFSK RxBFSK Rx

Receiver

Detector

DesignsDesignsBFSK RTBFSK RT

Results – OOK TxResults – OOK Tx

Results – BFSK TxResults – BFSK Tx

Results – BFSK RTResults – BFSK RT

FPGA Fitter ResultsFPGA Fitter Results

Average fan-out 5.40

Total fan-out 10537

Maximum fan-out 1110

Maximum fan-out node clock

SERDES receivers 0 / 152 ( 0 % )

SERDES transmitters 0 / 152 ( 0 % )

Fast regional clocks 0 / 32 ( 0 % )

Regional clocks 0 / 16 ( 0 % )

DSP block 9-bit elements 40 / 176 ( 22 % )

Total RAM block bits 626,688 / 7,427,520 ( 8 % )

Total memory bits 557,056 / 7,427,520 ( 7 % )

M-RAMs 0 / 9 ( 0 % )

M4Ks 136 / 364 ( 37 % )

M512s 0 / 767 ( 0 % )

Global signals 13

Clock pins 1 / 20 ( 5 % )

I/O pins 57 / 692 ( 8 % )

Virtual pins 0

User inserted logic elements 0

Logic elements in carry chains 617

Total LABs 209 / 7,904 ( 2 % )

Total logic elements 1,721 / 79,040 ( 2 % )

ConclusionsConclusions

• A non-coherent BFSK RT was successfully A non-coherent BFSK RT was successfully implemented into an FPGAimplemented into an FPGA

• Hardware usage was minimal and has space for Hardware usage was minimal and has space for possible expansionpossible expansion

• The use of industry provided intellectual The use of industry provided intellectual property (IP) is becoming more and more property (IP) is becoming more and more useful and commonplace… research and useful and commonplace… research and development efforts should not shy away from development efforts should not shy away from it because it saves time and maybe even it because it saves time and maybe even moneymoney

RecommendationsRecommendationsFor follow-on workFor follow-on work

• Conduct bit-error analysis on Conduct bit-error analysis on this implementation this implementation and and compare the FPGA results to the RT-1523C results, compare the FPGA results to the RT-1523C results, and make changes to the system to evaluate the and make changes to the system to evaluate the effects of different parameters effects of different parameters

• Analyze Analyze this system this system using actual SINCGARS equipment using actual SINCGARS equipment (antennas) in a wireless channel and make changes to (antennas) in a wireless channel and make changes to the implementation to evaluate the effects of different the implementation to evaluate the effects of different parametersparameters

• Modify Modify this design this design to perform Reed-Solomon to perform Reed-Solomon coding/decoding and Frequency-Hopping and maybe coding/decoding and Frequency-Hopping and maybe even interface with the computer to transmit certain even interface with the computer to transmit certain messages that can be input to the hardware via messages that can be input to the hardware via SimulinkSimulink

SourcesSources• U.S. Department of Defense. U.S. Marine Corps. MCRP 6-2.2.2 U.S. Department of Defense. U.S. Marine Corps. MCRP 6-2.2.2 Talk II – SINCGARS: Multiservice Talk II – SINCGARS: Multiservice

Communications Procedures for the Single-Channel Ground and Airborne Ra-dio SystemCommunications Procedures for the Single-Channel Ground and Airborne Ra-dio System, , Washington D.C.: GPO, 1996.Washington D.C.: GPO, 1996.

• ITT Industries. “SINCGARS: Evolution to Revolution”, Ft Wayne, Indiana, No Date Given.ITT Industries. “SINCGARS: Evolution to Revolution”, Ft Wayne, Indiana, No Date Given.• Hamilton, Bradley J. “SINCGARS System Improvement Pro-gram (SIP) specific radio Hamilton, Bradley J. “SINCGARS System Improvement Pro-gram (SIP) specific radio

improvements”, Tactical Commu-nications Conference, 1996: 397-406.improvements”, Tactical Commu-nications Conference, 1996: 397-406.• Green, Max. “SINCGARS Signal Output Power Test: Test Report - DRAFT”, MCTSSA, Camp Green, Max. “SINCGARS Signal Output Power Test: Test Report - DRAFT”, MCTSSA, Camp

Pendelton CA, 18 August 2004.Pendelton CA, 18 August 2004.• ““Joint Tactical Radio System – JTRS”, [http://jtrs.army.mil/index.htm], last accessed on March Joint Tactical Radio System – JTRS”, [http://jtrs.army.mil/index.htm], last accessed on March

05, 2005.05, 2005.• Wakerly, John, F. Wakerly, John, F. Digital Design: Principles and PracticesDigital Design: Principles and Practices, Prentice Hall, New Jersey, 2001., Prentice Hall, New Jersey, 2001.• Barr, Michael. "Programmable Logic: What's it to Ya?", Embedded Systems Programming, June Barr, Michael. "Programmable Logic: What's it to Ya?", Embedded Systems Programming, June

1999, pp. 75-84. 1999, pp. 75-84. • Altera Corp. “Stratix Device Handbook”, San Jose, CA, September 2004.Altera Corp. “Stratix Device Handbook”, San Jose, CA, September 2004.• Altera Corp. “Stratix EP1S80 DSP Development Board Data Sheet”, San Jose, CA, July 2003.Altera Corp. “Stratix EP1S80 DSP Development Board Data Sheet”, San Jose, CA, July 2003.• Altera Corp. “DSP Builder User Guide”, San Jose CA, August 2004.Altera Corp. “DSP Builder User Guide”, San Jose CA, August 2004.• Altera Corp. “Application Note 320: OpenCore Plus Evaluation of Megafunctions”, San Jose CA, Altera Corp. “Application Note 320: OpenCore Plus Evaluation of Megafunctions”, San Jose CA,

June 2004.June 2004.• Atera Corp. “Quartus II Handbook, Volumes 1-4”, San Jose CA, December 2004.Atera Corp. “Quartus II Handbook, Volumes 1-4”, San Jose CA, December 2004.• U.S. Department of Defense. U.S. Marine Corps. U.S. Department of Defense. U.S. Marine Corps. TM 5820-45&P/1-1 Volume I, U.S. Marine TM 5820-45&P/1-1 Volume I, U.S. Marine

Corps Technical Man-ual, Intermediate and Depot Maintenance, Single Channel Ground and Corps Technical Man-ual, Intermediate and Depot Maintenance, Single Channel Ground and Airborne Radio System (SINCGARS),Airborne Radio System (SINCGARS), Washington D.C.: GPO, 1997. Washington D.C.: GPO, 1997.

• Sklar, Bernard. Sklar, Bernard. Digital Communications: Fundamentals and Applications 2d ed.,Digital Communications: Fundamentals and Applications 2d ed., Prentice Hall, Prentice Hall, New Jersey, 2001.New Jersey, 2001.

Final DesignFinal Design

MODELING, SIMULATION AND IMPLEMENTATION OF A NON-MODELING, SIMULATION AND IMPLEMENTATION OF A NON-COHERENT BINARY FREQUENCY SHIFT KEYING (BFSK) COHERENT BINARY FREQUENCY SHIFT KEYING (BFSK)

RECEIVER-TRANSMITTER INTO A FIELD PROGRAMMABLE GATE RECEIVER-TRANSMITTER INTO A FIELD PROGRAMMABLE GATE ARRAY (FPGA)ARRAY (FPGA)

Thank your for your timeThank your for your time

Juan P SvenningsenJuan P SvenningsenCaptCapt USMCUSMCAdvisor: H.H. LoomisAdvisor: H.H. LoomisCo-Advisor: F.E. KraghCo-Advisor: F.E. KraghSponsored by MCTSSASponsored by MCTSSA