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Basics of Low Power Circuit and Logic Design
Anantha Chandrakasan
Massachusetts Institute of Technology
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 2
High Performance Processors
75 80 85 90 95Year
0
10
20
30
Pow
er (W
att)
Microprocessor Power (source ISSCC)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 3
Portable Devices
(40+ lbs)Battery
• Radio transceiver
• Modem • Voice I/O • Pen Input• Text/Graphics Processing• Text/Graphics display• Video decompression• Full-motion video display
Portable FunctionsRequired
How to get 8 hours of operation ???
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 4
Battery Trends
Year
Nom
inal
Cap
acity
(Wat
t-ho
urs /
lb)
Nickel-Cadmium
Ni-Metal Hydride
(from Jon Eager, Gates Inc. , S. Watanabe, Sony Inc.)
65 70 75 80 85 90 95 0
10
20
30
40
50 Rechargable Lithium
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 5
Where Does Power Go in CMOS?
Short-circuit or direct-path currents
Leakage currents
- Charging and discharging parasitic capacitors
- Sub-threshold conduction- Reverse bias diode leakage
Dynamic or switching currents
- Direct path between supply rails during switching
Static currents
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 6
Dynamic Power of a CMOS GateVdd
Vout
isupply
CL
E0->1 = CLVdd2
PMOSNETWORK
NMOS
A1
AN
NETWORK
E0 1→ P t( )dt0
T∫ Vdd isupply t( )dt
0
T∫ Vdd CLdVout
0
Vdd
∫ CL Vdd• 2= = = =
Ecap Pcap t( )dt0
T∫ Vouticap t( )dt
0
T∫ CLVoutdVout
0
Vdd∫
12---CL Vdd• 2= = = =
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 7
Modification for Circuits with Reduced Swing
CL
Vdd
Vdd
Vdd -Vt
E0 1→ CL Vdd Vdd Vt–( )••=
Can exploit reduced swing to lower power(e.g., reduced bit-line swing in memory)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 8
Physical Capacitance of an Inverter
0.8 1.0 1.2 1.4 1.6 1.80.0
10.0
20.0
30.0
40.0
50.0
Cgate
Cjunction
Cjunction + CgateC
apac
itanc
e, fF
2.0
VDD
Important to account for capacitive non-linearitiesin power estimation
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 9
Node Capacitance is a Function of Voltage
0.8 0.9 1.0 1.1 1.2 1.3 1.450
60
70
80
90
100
110 Sw
itche
d C
apac
itanc
e, fF
C2MOS
TSPCR
1.5
LCLR
VDD, V
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 10
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
EN CL Vdd• 2 n N( )•=
n(N): the number of 0->1 transition in N clock cycles
EN : the energy consumed for N clock cycles
Pavg N ∞→lim
ENN-------- fclk•= n N( )
N------------N ∞→
lim⎝ ⎠⎛ ⎞ C•
LVdd• 2 fclk•=
α0 1→n N( )
N------------N ∞→
lim=
Pavg = α0 1→ C•L
Vdd• 2 fclk•
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 11
Factors Affecting Transition Activity, α0->1
“Dynamic” or timing dependent component
→ Type of Logic Function (NOR vs. XOR)“Static” component (does not account for timing)
→ Circuit Topology
→ Type of Logic Style (Static vs. Dynamic)
→ Signal Statistics→ Inter-signal Correlations
→ Signal Statistics and Correlations
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 12
Type of Logic Function: NOR vs. XOR
A B Out0 0 10 1 01 0 01 1 0
Truth Table of a 2 input NOR gate
Example: Static 2 Input NOR Gate
Assume:p(A=1) = 1/2p(B=1) = 1/2
p(Out=1) = 1/4p(0→1)
= 3/4 × 1/4 = 3/16
Then:
= p(Out=0).p(Out=1)
α0->1 = 3/16
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 13
Type of Logic Function: NOR vs. XOR
A B Out0 0 00 1 11 0 11 1 0
Truth Table of a 2 input XOR gate
Example: Static 2 Input XOR Gate
Assume:p(A=1) = 1/2p(B=1) = 1/2
p(Out=1) = 1/2p(0→1)
= 1/2 × 1/2 = 1/4
Then:
= p(Out=0).p(Out=1)
α0->1 = 1/4
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 14
Type of Logic Style: Static vs. DynamicVdd
CL
CLK
A B
CL
A
B
A B
Vdd
CLK
STATIC NOR DYNAMIC NOR
α0->1 = 3/16 α0 1→N0
2N------- 34---= =
Power is only dissipated when Out=0!
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 15
Another Logic Style: Dynamic DCVSL
Vdd
I
I
Vdd
IN
INB
OUTB OUT
Guaranteed transition for every operation!
α0->1 = 1
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 16
Influence of Signal Statistics on α0->1
00.2
0.40.6
0.8
1
PA
0
0.2
0.4
0.6
0.8
1
PB
0
.1
2
00.2
0.40.6
0.8
1
PA
0
0.2
0.4
0.6
0.8
1
PB
0
.1
2
B
B
A
A CLpb
0
1
0
1pa
p0->1
α0->1 is a strong function of signal statistics
p1 = (1-pa) (1-pb)
p0->1 = p0 p1 = (1-(1-pa) (1-pb)) (1-pa) (1-pb)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 17
Inter-signal Correlations
(a) Logic circuit withoutreconvergent fanout
(b) Logic circuit withreconvergent fanout
A
BZ
CA
Z
C
B
p0->1 = (1- pa pb) pa pb = 3/16p0->1 = 0
pZ = p(C=1|B=1) • p(B=1)
Need to use conditional probabilities to modelinter-signal correlations!CAD tools required for such analysis
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 18
0 5 100.0
2.0
4.0
Time, ns
Sum
Out
put V
olta
ge, V
olts
Cin
S15
S10
6
5
4
3
2S1
Add0 Add1 Add2 Add14 Add15
S0 S1 S2 S14 S15
Cin
α0->1 can be > 1 due to glitching!
“Dynamic” or Glitching Activity in CMOS
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 19
Glitch Reduction Using Balanced Paths
A7
F
A6A5A4A3A2A1
A0
A0A1
A2A3
A4A5
A6A7
F
Ripple
Lookahead
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 20
Comparison of Adder Topologies
from [Callaway92]
16 bit 32 bit 64 bit
Ripple Carry 3.09 0.81 0.27Carry Lookahead 10.0 3.54 1.76Carry Bypass 5.45 2.39 0.99Carry Select 4.44 2.08 1.00Conditional Sum 3.82 1.23 0.42
Power-Delay-Product-1
Logic Transition Histogram
(VLSI Signal Processing, V)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 21
Glitching at the Datapath Level
Tree vs. Chain
A B
C
D+ +
+
A B C D+
++
+
(A + B) + C + D(A + B) + (C + D)
Can be reduced by reducing the logic depth and balancing
ChainTreeInputs
4
8
1.45
2.5
1
1
Normalized # of Transitions
signal paths
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 22
Short-circuit Component of Power
Vin Vout
CL
Vdd
I VD
D (m
A)
0.15
0.10
0.05
Vin (V)5.04.03.02.01.00.0
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 23
Short-Circuit Current vs. Load Capacitance
from [Veendrick84] (IEEE Journal of Solid-State Circuits, August 1984)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 24
Minimizing Short-circuit Power
Keep the input and output rise/fall times the same (< 10% of Total Consumption)
If Vdd < Vtn + |Vtp| then short-circuit power can be eliminated!
0.0 0.5 1.0 1.5 2.00.0
0.1
0.2
0.3
0.4
0.5
Vdd = 5V
Vdd = 3V
W/LP = 7.2µm/1.2µmW/LN = 2.4µm/1.2µm
Device Sizes:
∆E /
E(t R
in=
0)
tRin/tRout
from [Veendrick84] (IEEE Journal of Solid-State Circuits, August 1984)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 25
Reverse Biased Diode Leakage
Np+ p+
Reverse Leakage Current
+
-Vdd
GATE
IDL = JS × A
JS = 1-5pA/µm2 for a 1.2µm CMOS technology
Js double with every 9oC increase in temperature
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 26
Subthreshold Leakage Component
Leakage control is critical for low-voltage operation
VDS=1VID
+-VGS
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.010-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
I D, A
VGS, V
VT = 0.4 VVT = 0.1V
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 27
Static Power
Vin=5V
Vout
CL
Vdd
Istat
Pstatic = p(In=1).Vdd . Istat
• Not a function of switching frequency
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 28
Ultra Low Power System Design
Technology
Circuit/Logic
Architecture
Algorithm
System
Threshold Reduction,
Transistor Sizing, Logic optimization,
Concurrency, Instruction set selection,
Complexity, Concurrency, Locality,
Design partitioning, Power Down
Lower Supply Voltage and Switched Capacitance
Activity Driven Power Down,
Advanced packaging
Signal correlations, Data Representation
Regularity, Data representation
low-swing logic, adiabatic switching
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 29
Signal Processing Attributes
0 5 10 15 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Bit Number
Tran
sitio
n P
roba
bilit
ySign-extension
Spe
ech
Dat
a
-4000
-2000
0
2000
4000
Time
Throughput constrained computing
Knowledge of signal statistics
“water all year”
- Optimize power supply voltages
Time-varying computational requirements- Adaptive signal processing techniques
- 30ms refresh rate requirement for video
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 30
Energy Efficiency Metric: Fixed Throughput
For this mode (most DSP applications), minimizing energy/sample is both Energy and Power Efficient
Example: Video Compression
P = (Σ (NiCiVdd2)) fsample
fsample is fixed
Energy/Sample
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 31
Energy Efficiency Metric: Max Throughput
ETR Energy/operationThroughput-------------------------------------------≡ Power
Throughput2-----------------------------------=
Process Queue
A lower ETR (higher efficiency) indicates lower energyfor constant throughput, or higher throughput forconstant energy
Other metrics such as E x D, see [Horowitz94],
(1994 Symposium on Low-power Electronics)
from [Burd95](HICSS 95)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 32
Supply Voltage Scaling
Lowering Vdd reduces energy but increases delays
CL • VddI
=Td
Td(Vdd=5)
Td(Vdd=1.5)=
(1.5) • (5 - 0.7)2
(5) • (1.5 - 0.7)2
≈ 8
I ~ (Vdd - Vt)2
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
2.0 4.0 6.0 Vdd (volts)
NO
RM
AL
IZE
D D
EL
AY
adder (SPICE)
microcoded DSP chip
multiplier
adder
ring oscillator
clock generator2.0µm technology
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 33
Vin
Vdd
Vout
CL 0.9Vdd0.1Vdd
VDSATVout
time
Vin
Technology Based Voltage Scaling
Exploit velocity saturated sub-micron devices to lower
τ1∼ const.
Power Supply Voltage: Vdd(V)
Fall
Tim
e: τ
τ2 ∝ Vdd -1
τ = τ1 + τ2
voltage without significant loss in device speed
from [Kakumu90]
Technology based “Optimal” Vdd: 2.43V for 0.3µm CMOS
(IEEE Tran. on Electron Devices)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 34
Supply Voltage Scaling Using VT Reduction
0.05 0.15 0.25 0.35 0.450.0
0.25
0.5
0.75
1.0
1.25
1.5V D
D,V
VT, V
tpd=840pS
tpd=645pStpd=420pS
Threshold voltage reduction enables voltage scaling without performance loss
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 35
also see [Burr94]
Optimizing Continuous Mode Circuits
Optimum VDD/VT point trades-off switching andleakage power and is a strong function of activity
0.05 0.15 0.25 0.35 0.450.0
0.25
0.50
0.75
1.00
1.25En
ergy
(pJ)
VT (V)
VDD=1.4V
VDD=1V
VDD=0.34V
VDD=0.55V
VDD=1.02V
VDD=0.67V
tpd=840pS
tpd=420pS
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 36
Limits of Supply Voltage Scaling
0.6
0.5
0.4
0.3
0.20.15
0.1
0.2 0.3 0.4 0.5 0.6 0.70.20
Input Voltage (V) Vin
Vout 0.7
0.6
0.5
0.4
0.3
0.2
0.1
Ou
tpu
t Vo
ltag
e (V
)
0.7 V = Vs
Experiment
Calculation
CMOS Inverter Transfer Curves
Vsmin ≥ 2-4 kT / q
from [Swanson72](IEEE JSSC, April 1972)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 37
Burst Mode or “Event Driven”Computation
Trace1
Trace2
Trace3
Trace Length (sec) 5182.48 26859.9 995.16Toff (sec) 5047.47 26427.4 960.82Ton (sec) 135.01 432.5 34.34Toff/(Toff+Ton) 0.9739 0.9839 0.9655
BLOCKED(waiting for
hardware eventsand client requests)
RUNNING(doing actualcomputation)
Tblocked
Trunning
“On”“Off”
For an X-server application, processor spends most of thetime in the blocked or off state.
from [Srivastava95](IEEE Trans. on VLSI Systems)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 38
Techniques for Burst Mode Computation
Low VT
SLEEP High VT
SLEEP High VT
Multiple VT Technology
(Disable high VT devices during idle periods)
High VT transistor sizing issuesPreserving state requires extra transistors
e.g., [Sakata93] (Symposium on VLSI Circuits),[Mutoh93] (International ASIC Conference)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 39
Latch Design in MTCMOS
SLEEP High VT
SLEEP High VT
CLK
JSSC, August 1995From S. Mutoh, et. al.
SLEEP High VT
SLEEP High VT
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 40
Vin Vout
VDD
Substrate Bias ControlledVariable VT Devices -
(Increase VT during idle periods)
-+ VN < 0
standby
ON
-+ VP > 0ON
standby
Techniques for Burst Mode Computation
Needs large body factors - large well capacitancesTriple well process needed
from [Seta95] (ISSCC 1995)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 41
SOI with Active Substrate (SOIAS)
n+ n+p np+ p+
p+ n+i-poly
SiO2
SiO2
SiO2
Silicon Substrate
tfox tt
sibox
Loverlap
Backgate Control Enables Dynamically Varying Threshold Voltages
from [Yang95]
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 42
NMOS Device Characteristics
-0.2 0 0.2 0.4 0.6 0.8 1
Vgf (V)
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
Id (
mA
/um
)
0
0.01
0.02
0.03
Id (
mA
/um
)
~ 4 Dec
1.8x
VDS=1.0 Vtbox=100 nmtfox=9 nmtsi=4.5 nmLeff=0.44 um
Vt=0.448 V (Vgb=0.0 V)Vt=0.184 V (Vgb=3 V)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 43
Ring Oscillator Characteristics
Varied VTP onlyVTN = 0.512V
Varied VTN onlyVTP= - 0.2V
Processor speed is adjustable on demand
0.0 0.1 0.2 0.3 0.4 0.5 0.66
8
10
12
0.7Rin
g O
scill
ator
Fre
quen
cy (M
Hz)
Backgate Controlled Variable |VT| (V)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 44
Architectural Model & Activity Parameters for SOIAS
ADD ON ADD ONADD OFF
fga = Module Activity Factor
CLK ADD
CLK BACKGATE
LOW VT HIGH VT LOW VT
bga = Backgate Switching Activity
Add15
00.2
0.40.6
0.8
1
PA
0
0.2
0.4
0.6
0.8
1
PB
0
.2
4
00.2
0.40.6
0.8
1
PA
0
0.2
0.4
0.6
0.8
1
PB
0
.2
4 1αx
CLK ADD CLK BACKGATE
Add1
01pa
0 pb
Circuit Node Transition Activity
ab
x
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 45
Generic Architecture Model for All Technologies
TechnologyLeakage Control
Mechanism(hence affecting bga)
Multiple Threshold Technology Switching the High VT devices ON/OFF
Substrate Bias Control Controlling the Substrate Voltages
Silicon On Insulator Active Substrate Switching the Backgate Voltage
Hierarchy of Profilers and Statistical ModelsRequired for “Virtual Prototyping”
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 46
Energy Estimation Models for SOI and SOIAS
ESOI = α fga CfgVdd2
ESOIAS = α fga CfgVdd2
fga = Module Activity Factorbga = Backgate Switching Activityα = Node Transition Activity Factor
+ fga Ileak_lowVT Vdd Tcycle + (1-fga)Ileak_highVT Vdd Tcycle + bgaCbgVbg
2
+ Ileak_lowVT Vdd Tcycle
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 47
Architectural Profiling to Determine fga and bga
Table 1. SPEC benchmark espresso
Number fga bgaTotal Instructions 900158847 - -
Additions 543616709 0.6039 0.1954 Shifts 57000715 0.0633 0.0541
Multiplications 172883 0.0002 0.0002Table 2. SPEC benchmark Li
Number fga bgaTotal Instructions 1737729538 - -Total Additions 661236960 0.6023 0.2233
Total Shifts 52224367 0.0087 0.0086Multiplications 7088 0.0000 0.0000
Table 3. Data Encryption (IDEA)
Number fga bgaTotal Instructions 2125 - -
Additions 1250 0.5882 0.2635 Shifts 186 0.0875 0.0753
Multiplications 3 0.0014 0.0014
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 48
SOI vs. SOIAS Technology Evaluation
−4−3.5
−3−2.5
−2−1.5
−1−0.5 −4
−3.5
−3
−2.5
−2
−1.5
−1
−2
−1
0
1
o*
.
o
.
*
Adder
log(
back
-gat
e ac
tivity
fact
or)
*
*
Shifter
Mult.0.0
-0.5
-1.0
0.5
log(front-gate activity factor)
log
(ES
OIA
S/E
SO
I)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 49
Transistor Sizing for Low-Power
Minimum sized devices are usually optimal for low-power
Small W/L’s
Large W/L’s
Higher Voltage
Lower Voltage
Lower Capacitance
Higher Capacitance
Larger sized devices are useful only when interconnect dominated
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 50
Transistor Sizing for Fixed Throughput
α = 0
adder
0.5
0.7
1.0
1.52
345
7
10
1 3 10
α = 0.5
α = 1
α = 1.5
α = 2
W/L
NO
RM
AL
IZE
D E
NE
RG
Y
CP = Cwiring + CDF
Cg = W/L CMIN I ∝ W/L CMIN
CMIN = Minimum sized gate (W/L=1) W /L after sizing
HIGH PERFORMANCE
W/L >> CP / (K CMIN)
LOW POWER
W/L = 2 CP / (K CMIN) (if CP ≥ K CMIN)
W/L = 1 ELSE
α = CP / (K CMIN)
from [Chandrakasan92](IEEE JSSC, 1992)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 51
Capacitance Breakdown
MODULE LEVEL
DATAPATH LEVEL
MODULE GATE DIFFUSION INTERCONNECT
ADDER (Conventional Static) 30% 45% 25%
ADDER (Carry Select) 37% 31% 32%
TSPC COUNTER 32% 26% 36%
LOG SHIFTER (8 bit shift by 4) 15% 42% 43%
COMPARATOR 33% 38% 29%
MODULE GATE DIFFUSION INTERCONNECT
ADDER CHAIN ( 7 adders ) 38% 38% 24%
WAVE DIGITAL FILTER 31% 29% 40%
ADDRESS GENERATION (STD CELL) 56% 24% 20%
VIDEO SYNC GENERATOR (STD CELL)
45% 25% 30%
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 52
Choice of Logic Style
A
B
A
B
B
CIN CIN
B
VDD VDDPRE
CO CO
A
CIN
ACIN
CIN
B B
CIN
VDD VDDPRE
SUMSUM BB
CONVENTIONAL CMOS Adder
CPL AdderDCVSL Adder
GND
AA BB
P
CIN GEN
CIN PROP
GEN
VDDGND
A
B
A B
VDD
GEN
CINSUM
CIN
CIN
P
PB
P
B
A
PA
B
COUT
GND
CIN
P GEN
CIN P
GEN
VDD
COUT
OPTIMIZED static Adder
A
A
B
B
C C
GND
VDD
A
A
B
B
AB
AB
AB
AB
Sum
B
C
AB
A
VDD
A
B
A
B
VDD
CoutA B C
AA
B B
CC
Sum Sum
ACC
B
CoutCout
B
AA
A A
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 53
Choice of Logic Style
Power-delay product improves as voltage decreases.
The “best” logic style minimizes power-delay for a given delay constraint.
3
5
7
10
1520
30
50
70
100
150200
10 30 100
8-bit adders in 2.0µm
POW
ER
-DE
LAY
PR
OD
UC
T (p
J)
DELAY (ns)
Decreasing Vdd
CPL - LOW Vt
Optimized
Standard Cell
CSA
DCVSL
ConventionalStatic
Static
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 54
Reducing the Energy/Operation at a Fixed Vdd
oo 6/2 3/9
7/29/2
4/2
< >
o
Vdd (=1.5V)
Ceff = 5pF
ϕ
ϕ
Vin
Vout
HeavilyLoadedBit-line
0 20 40 60 80 1000
0.5
1.0
1.5
v(line)
v(out)v(out)v(ϕ)
t (ns)
Volts
SignalAmplification
M1 M2
M3M4
M5
V(out)
Reduced Signal Swing Example: FIFO Memory
Power Reduction Over Rail-to-Rail Swing = Vdd/(Vdd-Vt)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 55
R
Ctr
E = (RC/tr)CV2 (for tr >> RC)
Applying slow input slopes reduces E below CV2
Useful for driving large capacitors (Buffers)Power reduction > 4 for pad drivers (1 MHz) ISI
ADIABATIC CHARGING
Reducing the Energy/Operation at a Fixed Vdd
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 56
Example: Stepwise Adiabatic Driver
CLV1 1
2
N
V2
VN
0
Estep Q Vavg• CLVdd
N----------Vdd2N----------⋅•
12--- CL Vdd
2••
N2---------------------------------= = =
Etotal N
12--- CL Vdd
2••
N2---------------------------------•Econventional
N----------------------------------------= =
RC charging steps
from [Svensson94]
Vi = (i/N) V(IEEE Symposium on Low Power Design, 1994)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 57
Activity Driven Logic Level Power Down
MSBREG
REG
CLK
COMPARATOR
forbits
0->N-2
MSBA[N-1]B[N-1]
COMPARATOR
forbits 0->N-2
REGforbits
0->N-2
GATED_CLK
A > B
A[N-2:0]
B[N-2:0]
A > B
REG
CLK
MODIFIED REGISTER
COMBINATIONAL
LOGIC
CONDITIONALLYSWITCHED
BLOCK
50% reduction possible for random inputs
from [Alidina94](1994 International Workshop on Low-power Design)
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 58
Activity Reduction in Shift Registers
fCLK
Data In Data Out
fCLK/2
Data In Data Out
N Length Shift Register
N/2 Length Shift Register
Pserial = NCreg V2 fclk
Pparallel= 2 x (N/2 Creg V2 fclk/2) + Poverhead
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 59
Shift Register Power for Various Lengths
0 8 16 24 32 Degree of Parallelism
0.0
0.2
0.4
0.6
0.8
1.0
Nor
mal
ized
Pow
er D
issi
patio
n
32-bit
64-bit
128-bit
256-bit
Basics of Low Power Circuit and Logic Design © Anantha Chandrakasan 1997 60
Summary
• Power dissipation is a prime design constraint for portable systems
• Low Power design requires optimization at all Levels
• Sources of power dissipation have been analyzed
• Technology, circuit, and logic design techniques havebeen described
References[Alidina94] M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, “Precomputation-Based Sequential Logic
Optimization for Low Power,” 1994 International Workshop on Low-power Design, pp. 57-62, April 1994.[Burd95] T. Burd, R. Brodersen, “Energy Efficient CMOS Microprocessor Design,” Proceedings of the 28th Annual HICSS Con-
ference, Vol. I, pp. 288-297 Jan. 1995. [Burr94] J. Burr, J. Shott, “A 200mV Self-Testing Encoder/Decoder using Stanford Ultra-low Power CMOS,” IEEE ISSCC, pp.
84-85, 1994. [Callaway92] T. Callaway and E. Swartzlander, Jr., “Optimizing Arithmetic Elements for Signal Processing,” VLSI Signal Pro-
cessing V, pp. 91-100, IEEE Special Publications, 1992.[Chandrakasan92] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power Digital CMOS Design,” IEEE Journal of
Solid State Circuits, pp. 473-484, April 1992.[Horowitz94] M. Horowitz, T. Indermaur, R. Gonzalez, “Low-Power Digital Design,” Proceedings of the Symposium on Low
Power Electronics, 1994.[Kakumu90] M. Kakumu and M Kinugawa, “Power-Supply Voltage Impact on Circuit Performance for Half and Lower Submi-
crometer CMOS LSI,” IEEE Transactions on Electron Devices, Vol 37, No. 8, pp. 1902-1908, August 1990.[Mutoh93] S. Mutoh, T. Douseki. Y. Matsuya, T. Aoki, and J. Yamada, “1-V High-speed Digital Circuit Technology with 0.5µm
Multi Threshold CMOS,” IEEE Int. ASIC Conf., pp. 186-189, 1993.[Sakata93] T. Sakata, M. Horiguchi, K. Itoh, “Subthreshold-Current Reduction Circuits for Multi-GIGABIT DRAM’s,” 1993
Symposium on VLSI Circuits, pp. 45-46.[Seta95] K. Seta, H. Hara, T. Kuroda, M. Kakumu, T. Sakurai, “50% Active-Power Saving Without Speed Degradation Using
Standby Power Reduction (SPR) Circuit,” IEEE ISSCC 95, pp. 318-319.[Srivastava95] M. Srivastava, A.P. Chandrakasan, R. Brodersen, “Predictive System Shutdown and Other Architectural Tech-
niques for Energy Efficient Programmable Computation”, to appear in the IEEE Trans. on VLSI Systems, March 1996.[Svensson94] L.“J.” Svensson and J.G. Koller, “Driving a capacitive load without dissipating fCV2,” IEEE Symposium on Low
Power Design, pp. 100–101, 1994. [Yang95] I. Yang, C. Vieri, A. P. Chandrakasan, D. Antoniadis, "Back Gated CMOS on SOIAS for Dynamic Threshold Control,"
1995 IEEE International Electron Devices Meeting, December 1995.[Veendrick84] H.J.M. Veendrick, ‘‘Short-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer
Circuits,’’ IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 468-473, August 1984.