1

Basic Circuit Elements

Standard TTL Small-Scale Integration:1 chip = 2-8 gates

Requires numerous chips to build interesting circuits

Alternative: Complex chips for standard functions Single chip that performs very complex computations

PALs/PLAs: Programmable for arbitrary functions

Multiplexer/Decoder/Encoder: Standard routing elements for interconnections

2

Programmable Logic Arrays (PLAs/PALs)

Pre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gates

Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array of AND gates Product

terms

Dense array of OR gates

Outputs

3

Benefits of PLAs

Example:F0 = A + B CF1 = A C + A BF2 = B C + A BF3 = B C + A

Equations

Personality Matrix

Key to Success: Shared Product Terms

1 = asserted in term0 = negated in term- = does not participate

1 = term connected to output0 = no connection to output

Input Side:

Output Side:

Outputs Inputs Product t erm

Reuse of

t erms

A 1 - 1 - 1

B 1 0 - 0 -

C - 1 0 0 -

F 0 0 0 0 1 1

F 1 1 0 1 0 0

F 2 1 0 0 1 0

F 3 0 1 0 0 1

A B B C A C B C A

4

Unprogrammed PLA

All possible connections are availablebefore programming

5

Programmed PLA

Unwanted connections are "blown"

6

Simplified PLA Diagrams

Short-hand notationso we don't have todraw all the wires!

Notation for implementingF0 = A B + A' B'F1 = C D' + C' D

7

PLA Example

F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A xor B xor C

F6 = A xor B xor C

Multiple functions of A, B, C

F1 F2 F3 F4 F5 F6

8

PALs vs. PLAs

What is difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA)?

PAL concept: constrained topology of the OR Array

A given column of the OR arrayhas access to only a subset of

the possible product terms

PLA concept — generalized topologies in AND and OR planes

9

PAL Example

X = BCD + ABCD + AD

Y = CD + AB + ACD + BCD

10

PLA Design Example: 2’s Comp. Compare

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

K-map for GT

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

K-map for LT

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

K-map for NE

AB

CD 00 01 11 10

00

01

11

10

D

B

C

A

K-map for EQ

EQ NE LT GT

11

Design Example: Basic Telephone System

Put together a simple telephone system

D/A

A/D

Ear

Mouth

Bell

Start

E

M

B

S

12

Basic Telephone System (cont.)

Multiple subscribers, one operator. Operator controls all connections

E

M

B

S

E

M

B

S

E

M

B

S

E

M

B

S

EMBS

Operator

13

Standard Circuit Elements

Develop implementations of important “Building Blocks” Used in Networks, Computers, Stereos, etc.

Multiplexer: Combine N sources onto 1 wire Decoder: Determine which input is active Encoder: Convert binary to one-of-N wires

14

Decoders

Used to select one of 2N outputs based on N input bits Input: N bits; output: 2N outputs -- only one is active A decoder that has n inputs and m outputs is referred to as

an n x m, N:M, or n-to-m decoder Example: 3-to-8 decoder

3:8dec

01

234567

A B C

S2 S1 S0

D0

D1

D2

D3

D4

D5

D6

D7

15

Decoder Implementation

16

Enabled Decoder Implementation

Active High enable

17

Decoder Expansion

Construct a 4:16 decoder using 2:4 decoders

18

Decoders in General Logic Implementation

Implement F = WXZ + XZ w/4x16 Decoder0123456789

101112131415S3 S2 S1 S0

4:16decEn

19

Encoders

Performs the inverse operation of decoders Input: 2N or less lines -- only 1 is asserted at any

given time Output: N output lines Function: the output is the binary representation

of the ID of the input line that is asserted

20

Encoder Implementation

4:2 Encoder

21

Priority Encoder

Use priorities to resolve the problem of 2 or more input lines active at a time.

One scheme: Highest ID active wins Also add an output to identify when at least 1

input active

22

Priority Encoder Implementation

23

Priority Encoder Implementation (cont.)

24

Multiplexer

An element that selects data from one of many input lines and directs it to a single output line

Input: 2N input lines and N selection lines Output: the data from one selected input line Multiplexer often abbreviated as MUX

25

Multiplexer Implementation

4:1 MUX

26

Multiplexer Expansion

Construct a 16:1 MUX using 4:1 MUX’s

27

Multiplexers in General Logic

Implement F = XYZ + YZ with a 8:1 MUX

8:1MUX

01234567 S2 S1 S0

F

28

Multiplexers in General Logic (cont.)

Implement F = XYZ + YZ with a 4:1 MUX

S1 S0

4:1MUX

0123

F