band-pass sigma-delta modulators - digital...
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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 0 of 56 IMSE-Σ∆ Design Group
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SE
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M D
esig
n G
roup
. To
tal o
r pa
rtia
l usa
ge o
r re
prod
uctio
n re
qui
res
the
writ
ten
perm
issi
on o
f Pro
f. A
nge
l Ro
drig
uez-
Váz
quez
IMSE
Avda. Reina Mercedes s/n,41012-Sevilla, SPAIN
FAX:
Instituto de Microelectrónica de Sevilla(IMSE-CNM-CSIC)
E-mail: [email protected]
Phone: +34 95 505 6666/6669+34 95 505 6686
Camino de los Descubrimientos s/n,41092-Sevilla, SPAIN
Escuela Superior de Ingenieros
Universidad de SevillaDpto. Electrónica y Electromagnetismo
Phone: +34 954487377
IMSE
Band-Pass Sigma-Delta Modulators:
Angel Rodríguez-Vázquez and José M. de la Rosa
Avda. Reina Mercedes s/n,41012-Sevilla, SPAIN
FAX:
Instituto de Microelectrónica de Sevilla(IMSE-CNM-CSIC)
E-mail: [email protected]
Phone: +34 95 505 6666/6669+34 95 505 6686
Camino de los Descubrimientos s/n,41092-Sevilla, SPAIN
Escuela Superior de Ingenieros
Universidad de SevillaDpto. Electrónica y Electromagnetismo
Phone: +34 954487377
Principles, Architectures and Circuits
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 1 of 56 IMSE-Σ∆ Design Group
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Outline
• Motivation and Applications
• Basic Concepts
• Architectures
• Circuit Errors
• State-of-the-Art
• TEXTJ.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez, Systematic Design of CMOS Switched-Current BandPass Sigma-Delta Modulators. ISBN 0-7923-7678-1, Kluwer Academics Pub. 2002.
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 2 of 56 IMSE-Σ∆ Design Group
Motivations©
IMS
E-S
DM
De
sign
Gro
up. T
otal
or
part
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or
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rof.
Ang
el R
odr
igue
z-V
ázqu
ezDigital Wireless Communications Scenario
Digital Cellular Phones(GSM, CDMA, UMTS-2000) Traffic Telematic Applications
(GPS)
Digital Radio Receivers(Software controlled broadcast AM, FM radios)
Telemetry Instrumentation(Ultrasounds, narrowband-source generators...)
Wireless LANsDigital RF Communication
(PDAs, others...)Portable Devices
RF, IF(BANDPASS Σ∆)
ANALOG-TO-DIGITALCONVERTERS
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 3 of 56 IMSE-Σ∆ Design Group
Motivations©
IMS
E-S
DM
De
sign
Gro
up. T
otal
or
part
ial u
sage
or
repr
odu
ctio
n re
quir
es th
e w
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n p
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Ang
el R
odr
igue
z-V
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ezReceiver Architectures I
Analog (Superheterodyne) Receiver
Digital Receiver
RF Bandpass FilterLO1
Common Tuning
Antenna
LNA
IF Bandpass FilterLO2
RF Section IF Section Dem. Section
DemodulatorLNA
• Processing in the analog domain (Filtering, mixing, demod.)
• Limited functions: voice telephony, paging.(AMPS, NMT,...)First-Generation
AntennaADC
& DEMODULATION
DIGITAL SIGNAL PROCESSING (DSP)
ANALOG SIGNAL PROCESSING (ASP)
• Most functions in the digital domain: programmability, multi-stand-ard,...
• New functions: ISDN-compatible data, call forwarding, short mes-saging, software controlled receivers (in radio app.), etc...
• Continuous technology scaling will allow one-chip receivers
Second-Generation (GSM, CDMA,...)
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 4 of 56 IMSE-Σ∆ Design Group
Motivations©
IMS
E-S
DM
De
sign
Gro
up. T
otal
or
part
ial u
sage
or
repr
odu
ctio
n re
quir
es th
e w
ritte
n p
erm
issi
on o
f P
rof.
Ang
el R
odr
igue
z-V
ázqu
ezReceiver Architectures II: Digital RF Receivers
Superheterodyne Receiver
Direct-Conversion Receiver
IF-Conversion Receiver
RF Bandpass FilterLO1
Common Tunning
AntennaLNA
IF Bandpass FilterLO2
RF IF Baseband
Lowpass
ADCDSPLNA
Section Section
Two much analog cir-cuitry: High-Q High-F BPfilters
Not appropriate for one-
Better suited for integratedreceivers
Sensitive to RF mixer errors:offset, flicker noise,...
RF ADCs required
RF Bandpass FilterLO1
Common Tuning
AntennaLNA
RF Baseband
LowpassADC
DSP
Section
RF Bandpass FilterLO1
Common Tuning
AntennaLNA DSP
RF IF
IF (Bandpass)
ADCIF mixing realized in thedigital domain
An IF ADC is required
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 5 of 56 IMSE-Σ∆ Design Group
Motivations©
IMS
E-S
DM
De
sign
Gro
up. T
otal
or
part
ial u
sage
or
repr
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Ang
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odr
igue
z-V
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ezTwo Approaches to IF Digitization
Analog Domain Digital Domain
Analog quadrature mixer
(= I/Q mismatch, 1/f noise, offset)
Two lowpass ADCs needed
LP Filter
LP Filter
π 2⁄
I data
Q data
IF
LP Filter
LP Filter
π 2⁄
I data
Q data
2πf IFt( )cos
2πfIFnTs( )cos 1 0 1 0 1 0 …, , , ,–, ,=
fIF fs 4⁄=
signal
LowpassADC
LowpassADC
IF
ADC
(Bandpass)Digital quadrature mixer
One IF (bandpass) ADC
Digital channel selec-tion, gain control...
fIF fs 4⁄=Digital mixing simplified for
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 6 of 56 IMSE-Σ∆ Design Group
Motivations©
IMS
E-S
DM
De
sign
Gro
up. T
otal
or
part
ial u
sage
or
repr
odu
ctio
n re
quir
es th
e w
ritte
n p
erm
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Ang
el R
odr
igue
z-V
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ezInterest of BandPass Converters for IF Digitization
0 0.1 0.2 0.3 0.4 0.5-120
-100
-80
-60
-40
-20
0
Normalized frequency (to fs)
PSD of the digitized signal (dB)
Signal BandBandPass Σ∆ Converters:
Quantization noise has to be smallonly in the band of interest
Oversampling reduces the quantiza-tion noise within the band
Noise-shaping further reduces thenoise within the band
Nyquist-Rate Data Converters
Quantization noise has to bereduced within the whole Nyquistband
Basic Concepts
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 7 of 56 IMSE-Σ∆ Design Group
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Sampling of BandPass Signals
fS2fS1
> PE2PE1
<⇒
PE1 2,
XFS2
12M1 2, 2B 1–( )2
------------------------------------------=
Oversampling Ratio, M In-band noise power
x
xD
fS1 2,
xD x eq x( )+=
PSDxD
fS12⁄BW fS2
2⁄BW
PSDxD
Freq Freq
M
fs fIF
BW2
----------+
BW⁄
2 fIF BW+( )---------------------------------------------------------=
Basic Concepts
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 8 of 56 IMSE-Σ∆ Design Group
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BandPass Error Feedback and Noise Shaping
Y z( )X z( )
2Lth BP Filter–DAC
++G
Eq z( )fn
As for LPΣ∆M, something more than just oversampling is needed for practical BPΣ∆Ms
Y z( ) STF z( )X z( ) NTF z( )Eq z( )+=
•♦ In-band:
♦ Out-of-band: for stability
♦ for causality
NTF z( )
NTFf fn→lim 0=
NTF 1,6<
NTFz ∞→lim 1=
•♦ In-band: Constant gain and lin-
ear phase
♦ Out-of-band: High Attenuation
STF z( )
Error feedback results into selective filtering for signal and noise
STF NTF
BWfn
PSD
Freq
Basic Concepts
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 9 of 56 IMSE-Σ∆ Design Group
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About the Influence of Noise Shaping
NRES z( ) 1 z 1– zn–( ) 1 z 1– zn∗–( )+ 1= ⇒ NTF z( ) 1 2 2π fnTs( )cos z 1–– z 2–+[ ]
L=
In-band quantization noise power
Dynamic range
fn
1 2 4 8 16 32 64 128 2560
20
40
60
80
100
120
DR
dB()
M
6th-Order BP L 3=( )
4th-Order BP L 2=( )
2nd-Order BP L 1=( )
9dB/octave
15dB/octave
21dB/octave
B 1=
fn fs 4⁄=
Hbp z( )NRES z( )
1 z 1– zn–( ) 1 z 1– zn∗–( )
-------------------------------------------------------------L
=
1st
Resonator
2nd
Resonator
Lth
Resonator
zn e2π fnTs=( )
PQ2πfnTs[ ]sin( )2Lπ2LXFS
2
12 2B 1–( )2
2L 1+( )M 2L 1+( )--------------------------------------------------------------------------≅
DR3 2B 1–( )
22L 1+( )M2L 1+
2π2L 2πfnTs[ ]sin( )2L-------------------------------------------------------------------≅
Basic Concepts
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 10 of 56 IMSE-Σ∆ Design Group
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Decimation for BandPass Σ∆ ADCs I
Y z( )X z( )
HbpD/A
BP Antialiasing filter
Analog fn
BP Σ∆ Modulator
Digital BP filter Downsampler
Bandpass Decimator
fnInput
Yd z( )MW z( )
fn
ff
f f
fs fs
fsfs
fs 2⁄
fs 2⁄ fs 2⁄fn
Bw
Bw 2Bw
H f( )
Y f( ) Yd f( )
W f( )
Decimation Process
Basic Concepts
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 11 of 56 IMSE-Σ∆ Design Group
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Decimation for BandPass Σ∆ ADCs II
I DATA
Q DATA
1 2
1 0 1 0 …, ,–, ,
0 1 0 1 …,–, , ,
yTime interleaved LP Filter
I DATA
Q DATA+ DownsamplerComplex LP
Decimatore
j2πfnnT s–
YI f( )
YQ f( )
yd
yyd
f
f
f
fsfs 2⁄
fs 2⁄ fs
fs 2⁄ fs
Y f( )
YI f( )
YQ f( )
fnfs4----=
Process of mixing the digital outputdown to baseband
Previous approach requires high-Q bandpass filter
Basic Concepts
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 12 of 56 IMSE-Σ∆ Design Group
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Signal PassBand Location
Trade-off at the RF Stage
The lower fn the lower B irf
Trade-off at the IF Stage
The larger fnthe lower BafFreq
fs
Bw
fnfs 2⁄–f– s
Bw
f– nfs– fn+
IF Signal IF MirrorBaf
Antialiasing FilterMag.
fs 2⁄ fs fn–
FreqfLO
fLO fIF– fRF
RF Image
RF Signal
Image-reject FilterMag. LO
fL O fRF fIF–=( )
f– LOf– LO fIF+f– R F
LOB irf
• Optimum location for (at the middle of Nyquist band)
♦ Forward path (analog) modulator filter realization can be simplified
♦ Simplifies LP-to-BP transformation,
♦ Digital mixing to baseband is notoriously simplified:
fn fs 4⁄=
z 1– z 2––→
2π fIFnTs( )cos 1 0 1 0 1 0 …, , , ,–, ,=
Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 13 of 56 IMSE-Σ∆ Design Group
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Y z( )X z( )
DAC
Y z( )X z( )
DAC
Lth-Order LP Filter 2Lth-Order BP Filter N-bit N-bit
L-order Lowpass Σ∆ Modulator 2L-order bandpass Σ∆ Modulator
z 1– z 2––→
Re(z)
Im(z)
UnityCircle
Im(z)
UnityCircle
NTF 1 z 1––( )L
=
L zeroes at DC
NTF 1 z 2–+( )L
=
L zeroes at +fs 4⁄
STF z L–= STF z 2––( )L
=
L zeroes at − fs 4⁄
Re(z)
SNRQ12 2B 1–( )
22L 1+( )M2L 1+
8π2L----------------------------------------------------------------------=
The LP-to-BP Transformation Method I
Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 14 of 56 IMSE-Σ∆ Design Group
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The LP-to-BP Transformation Method II
z1–
1 z1–
–------------------
+
−
x
DAC
g1gDAC1
z1–
1 z1–
–------------------
gDAC2
g2
+
−
z1–
1 z1–
–------------------
+
−
DAC
g3'
gDAC3
z1–
1 z1–
–------------------
gDAC4
g4
+
−
g31 z–
1–
2
d1
d0
+−
z1–
y
+
+
Y z( ) X z( )z 4– d12 1 z 1––( )
4E2 z( )+=
g1 gDAC3 0,25= =
g2 g4 0,5= = ;g3 1 g3';= 0,375=
g3 1=
g3' 0,375=
z– 2–
1 z 2–+-----------------
+
−
x
DAC
g1
gDAC1
z– 2–
1 z 2–+-----------------
gDAC2
g2
+
−
z– 2–
1 z 2–+-----------------
+
−
DAC
g3'gDAC3
z– 2–
1 z 2–+-----------------
gDAC4
g4
+
−
g31 z+ 2–( )
2
d1
d0
+−
z– 2–
y
+
+
4th-order BP-SDM
4th-order BP-SDM
Y z( ) X z( )z 8– d12 1 z 2–+( )
4E2 z( )+=
All features of the LPmodulator are preserved
SNR,
PQ, DR,
Stability, . . .
Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 15 of 56 IMSE-Σ∆ Design Group
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Noise Pattern I
z–2–
1 z2–
+------------------
+
−
x y
DAC
gxgDAC
z1–
1 z1–
–------------------
+
−x y
DAC
gxgDAC
1st-order Lowpass 2nd-order Bandpass
z 1– z 2––→
The correlation between quantization error and input signal is also translated from LP to BPThe worst case corresponds to B = 1 and L = 1
-1 -0.8-0.6-0.4-0.2 0 0.2 0.4 0.6 0.8 1-70
-65
-60
-55
-50
-45
-40
-1 -0.8-0.6-0.4-0.2 0 0.2 0.4 0.6 0.8 1-65
-60
-55
-50
-45
-40
-35
In-band quantization error power (dB)
Input level referred to ∆/2Input level referred to ∆/2
DC input signal Single tone at fs 4⁄M 64=( )
Noise Pattern
Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 16 of 56 IMSE-Σ∆ Design Group
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Noise Pattern II
Non-linear quantization error manifests as Idle TonesNon-linear analysis is required [Gray90]
DC input
ftlpnn
12---
Ax∆
-------± ⟨ ⟩fs=
n 1 2 …, ,=( )ftbpn
fs
n 14---
Ax2∆-------±
⟨ ⟩
n12---
Ax2∆-------±
⟨ ⟩
=
Single tone at fs 4⁄DC fs 4⁄→
1st-order Lowpass 2nd-order Bandpass
0 0.1 0.2 0.3 0.4 0.5-80-70-60-50-40-30-20-10
0
Ax∆------ 0,1=
fL2 fL1 fR1 fR2
Normalized frequency to fs
Magnitude (dB)
0 0.1 0.2 0.3 0.4 0.5-80-70-60-50-40-30-20-10
0
Ax∆------ 0,14=
fL2fL1 fR1 fR2
Normalized frequency to fs
Magnitude (dB)
0 0.1 0.2 0.3 0.4 0.5-80-70-60-50-40-30-20-10
0
Ax∆
------ 0,18=
fL2 fL1fR1 fR2
Experimental results
Magnitude (dB)
Normalized frequency to fs
fL1fs4----
Ax
2∆-------– fs= fR1
fs
4----
Ax2∆------- fs+= fL2
Ax2∆------- fs= fR2
fs2----
Ax
2∆-------– fs=
Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 17 of 56 IMSE-Σ∆ Design Group
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Noise Pattern III
ftlpnfs
nfifs----⟨ ⟩
nfi
fs----
12---–⟨ ⟩
=
Sinusoidal input
ftbp nfs
14--- n
δfn2
--------± ⟨ ⟩
12--- n
δfn2
--------± ⟨ ⟩
=
Single tone at fs 4 δ fn–⁄
DC fs 4⁄→
1st-order Lowpass 2nd-order Bandpass
0.2 0.23 0.25 0.28 0.30-80-70-60-50-40-30-20-10
0
0.2 0.23 0.25 0.28 0.30-80-70-60-50-40-30-20-10
0
0.2 0.23 0.25 0.28 0.30-80-70-60-50-40-30-20-10
0n 18=n 10=
n 6=n 14=
n 18=
n 2= n 6=
n 18=n 10=
n 6=n 7=
n 14=n 18=n 10=
Normalized frequency to fs
Magnitude (dB)
Normalized frequency to fs
Magnitude (dB) Magnitude (dB)
Normalized frequency to fs
Experimental resultsAx∆------ 0,1= Ax
∆------ 0,16=
Ax∆
------ 0,28=
Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 18 of 56 IMSE-Σ∆ Design Group
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From Integrators to Resonators
The LP to BP transformation converts the Integrators into Resonators
DCFreq.
Infinite
HRES z( ) z a–
1 z 2–+-----------------= 0 a 2≤<
fs 2⁄fs 4⁄
H ω( )
Resonator transfer function after
Different alternatives for resonators:
Based on Delay Elements,
Based on Integrators
. . .
Errors in component ratios alter the transferfunction:
Incorrect shaping of quantization error
Instabilities
z 1– z 2––→
Architectures
Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 19 of 56 IMSE-Σ∆ Design Group
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SC Resonator Based on Delay Elements
Unity Circle
Loop gain >1
Loop gain <1
C
C
φ2
φ1
φ2
φ1
φ2
φ1
+
−+−
C
C
φ2
φ1
φ2
φ1
φ2
φ1
C φ1φ2
φ1 φ2
Cφ1φ2
φ1 φ2
C
C
φ2
φ1
φ2
φ1
φ2
φ1
+
−+−
C
C
φ2
φ1
φ2
φ1
φ2
φ1
C φ1φ2
φ1 φ2
Cφ1φ2
φ1 φ2 φ1
φ2
C
φ1
φ2
C
+
−
vout
+
−
vin
a 1=
Im(z)
Re(z)
The Concept
SC Implementation [Longo, 1993]
+
−z 2 a–( )–
z a–
Pole shift with loop gainPole shift with loop gain
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ngel
Ro
drig
uez-
Váz
quezIntegrator-Based Resonators
z 1–
1 z 1––-----------------z 1–
1 z 1––-----------------
-2
-2
+
+
z 1–
1 z 1––-----------------1
1 z 1––-----------------
-2
+
+
[Singor, 1995]
LDI
FE
1
Loop gain error =1%
IdealLoop gain error = -1%
0 20 40 60 80 100-1.2
-0.8
-0.2
0.2
0.8
1.2
Error in the resonant frequencyAlways stable
h n( )
n Ts( )0 20 40 60 80 100-2.5
-1.5
-0.5
0.5
1.5
2.5
It can be unstable Use chaos to reduce idle tones !?
h n( )
n Ts( )
+
−+−
1(2)
2(1)
2(1)
1(2)
2
2
1
1
1
1
2
2+
−+−
2(1)
1(2)
1(2)
2(1)
2
2
1
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SI Resonators
φ2 φ1
φ1
2Ibias Ibias
φ1 φ2
φ2
2Ibias 2Ibias Ibias
φ1
1 : 1 1 1 : 1 -2 1: :
ii io
:
φ1
io1 -2io
LDI Integrator Feedback stage
z a–
1 z 2–+-----------------ii io
Integrator based(a=1)
(a=2)Delay element based
φ1
φ1
φ2
φ2
φ1
φ1
φ2
φ2 φ1 φ1
Ibias Ibias Ibias Ibias Ibias Ibias
1 1 1 1 -1 1: : : : :
ii io
Double delay
Delay element
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 110
-6
10-5
10-4
10-3
10-2
10-1
100
Error (%)
Q Sensitivity respect to loop gain
Integrator based
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Pro
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2-Path Resonator
[Hairapetian, 1996]
+
− +
−
B1
B2
2
1
A2
A1
Cb
Ca
Ch
12
A
B
Cs1
2
2
Cs 1
2
2
B2
B1
2
1
A2
A1
Cb
Ca
Ch
21
A
B
+
−Vin
+
−Vout
1
2
A1
A2
B1
B2
A
B
HRES
Cs Chz 1–⁄
1 z 2–+---------------------------=
Previous approaches toBP Modulators:
Start from a Lth LowPasswith L active blocks
Result into a 2Lth Band-Pass with 2L activeblocks
Using double samplinghalves the number ofopamps
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Pro
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ngel
Ro
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quez
Generalized LP-to-BP Method I
Mag
nitu
de
(dB
)
0 0.1 0.2 0.3 0.4 0.5-100
-80
-60
-40
-20
0 × ×
Tones at DC Tones at fs 2⁄Input Tone
0.2 0.225 0.25 0.275 0.3-100
-80
-60
-40
-20
0
Frequency / Sampling FrequencyM
agni
tude
(dB
)Frequency / Sampling Frequency
Intermodulation Product
Counters of transformation:Stronger demand on than placing between and
Intermodulation products inside the signal band
z 1– z 2––→
fs fn fs 4⁄ fs 2⁄
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Generalized LP-to-BP Method II
Constantinides’ Transformation z 1– z 2–– 2πfn fs⁄( )z 1–cos+
1 2πfn fs⁄( )z 1–cos–---------------------------------------------------------------→
Preserves properties of the original LP modulator
Suitable for programmable band location [Corm97]
Magnitude
Frequency
z zp±→
NTFLowpass1 z 1––( )
LNTFBandpass
→ 1 z p–±( )L
= = zn e2πfnTs=
fn
fs2p------=Notch frequency at
Modulator order increased unnecessarily for p > 2
Stability conditions are not preserved
Generalized Transformation
Re(z)
Im(z)
UnityCircle
zn e2– πfnTs=
NTF Bandpass
1 2 2πfn fs⁄( )z 1– z 2–+cos–
1 2πfn fs⁄( )z 1–cos–----------------------------------------------------------------------
L
=
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Optimized Synthesis of STF(z) and NTF (z)
Direct synthesis of and
Optimize poles and zeroes according to a given specification
can be designed to perform a bandpass function
Architecture (interpolative) is more sensitive to mismatch
STF z( ) NTF z( )
STF z( )
z1–
1 z1–
–------------------ z
1–
1 z1–
–------------------
R1b1
a1 a2
b2
z1–
1 z1–
–------------------ z
1–
1 z1–
–------------------
R2b3
a3 a4
b4DAC
x
y
0 0.1 0.2 0.3 0.4 0.5-80-70-60-50-40-30-20-10
0
Frequency / Sampling Frequency
+
−φ1φ2
φ2φ1
Ca0Ci0
Cx1
+
−φ1φ2
φ2φ1
Ca1Ci1
Cx2
+
−φ1φ2
φ2φ1
Ca2Ci2
Cx3
+
−φ1φ2
Ca3Ci3
+
−
φ1
φ2+
−
IN
φ2
φ1Cr1
Cb0 Cb1φ2
φ1Cr1
Cb2 Cb3
φ2
φ1
φ2
φ1
OUT
Vref
[Jantzi, 1994]
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Pro
f. A
ngel
Ro
drig
uez-
Váz
quez
Quadrature Bandpass Σ∆ Modulators I
RF Bandpass Filter
LOCommon Tuning
AntennaLNA
RF Bandpass Filter
LOCommon Tuning
AntennaLNA
BPΣ∆ ADC
BPΣ∆ ADC
BPΣ∆ ADC
QuadratureMixer
DSP
I DATA
Q DATA
RF Bandpass Filter
LOCommon Tuning
AntennaLNA Quadrature
MixerDSP
I DATA
Q DATA
QuadratureBPΣ∆ ADC
I
Q
I
Q
Digital QuadratureMixer & DSP
RF Stage IF Stage
Image spectral components corrupt the signal unless a
Quadrature mixer solves in
One quadrature modulator directly digitizes I and Q compo-
nents
narrow-band high-Q RF filteris used.
part this problem, but twomodulators are required.
1
2
3
[Jantzi, 1997]
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Pro
f. A
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quez
Quadrature Bandpass Σ∆ Modulators II
+
-
xQ
DAC
fn
Complex Filter
+
-xI
DAC
yQ
yI
NTF 1 z2–
+
2= vs NTF 1 jz
1––
4
=Example
-0.5 -0.3 -0.1 0.1 0.3 0.5-100
-80
-60
-40
-20
0
20
40NTF dB
Re(z)
Im(z)
zn ejπ2---
=
zn ej– π2---
=
UnityCircle
Normalized frequency to fs
Quadrature bandpass Σ∆ modulators
Use complex bandpass filters
has complex-coefficients (not
symmetric with respect to DC)
Can place L zeroes at fn without plac-ing any zero at −fn
NTF z( )
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Pro
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quez
Complex Filters for Quadrature BP Σ∆ Modulators
+
-xiRe
HRe z( )
HRe z( )
HIm z( )
HIm z( )
+-
xiIm
xoRe
xoIm
XoReHRe z( )XiRe
H Im z( )X iImz( )–=
Xo ImHRe z( )XiIm
HIm z( )X iRez( )+=
Xo z( ) XoRez( ) jXo Im
+=
Usually realized through cross-coupled real-filters
+xiRez
1–
1 z1–
–-----------------
+
+xiImz
1–
1 z1–
–-----------------
+
xoRe
xoIm
b
b
+
-
a 1–( )
a 1–( )
Example
H z( )1
z a jb+( )–-----------------------------=
Two integrators to make a complex pole
A complex Lth-order BP Σ∆M uses 2L inte-grators but has 2L zeroes at NTF z( ) fn
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Pro
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ngel
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quez
+−
Cd
Ci
Cc
φ1φ2
φ2 φ1
+−
Cd
Ci
− Cc
φ1
φ2 φ2φ1
xiRe
xiIm
xoRe
xoIm
Fourth-Order Quadrature BP Σ∆ Modulator
[Jantzi, 1997]
Undesired Image due to mismatch between real and imaginary channels
It can be partially cancelled by placing one zero at the image frequency
b1
a1 a2
b2 b3
a3 a4
b4 DAC
x
y1z p2–------------- 1
z p3–------------- 1
z p4–-------------
Complexintegrator
pn 1 dn jcn+ +=
H z( )1
z pn–---------------=
1z p1–-------------
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5-120
-100
-80
-60
-40
-20
0
Normalized frequency to fs
Mag. (dB)
Image band zero
complexsignal path
Complex SC Integrator
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Pro
f. A
ngel
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drig
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quez
N-Path Architectures I
H zp( )Φ1 Φ1
H zp( )Φ2 Φ2
H zp( )ΦN ΦN
X z( ) Y z( )
Φ1
Φ2
ΦN
Tp
Y z( )X z( )------------ H zp( )
zp zN==
H z( )z 2–
1 z 2–+-----------------
zp1–
1 zp1–+
-----------------
zp z2=
= =
++
2–
zp1–
1 zp1–
–----------------------
zp1–
1 zp1–
–----------------------
2πfs2----
nTscos πn( )cos 1 1 1 1…–, ,–,= =
Alternative 2-path resonators
Each path clocked at 1/N the overall rate
[Ong, 1998]
Opamp bandwidth requirements can be relaxed using N-path filters [Gregorian, 1986]
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Examples of N-Path BP Σ∆Ms I
0,4–zp
1–
1 zp1–+
--------------------zp
1–
1 zp1–+
--------------------+
+
+
+
0,5
DAC
Φ1 Φ1
0,4–zp
1–
1 zp1–+
--------------------zp
1–
1 zp1–+
--------------------+
+
+
+
0,5
DAC
Φ2 Φ2
X z( )
φ2 φ1φ1
+
−
vrefφ2
+
−
vout+
− +
−
φ1+
−
vin
φ1
φ1
φ2
φ2 φ1φ1
φ2
φ1
φ1
φ2
φ2
φ1
φ2
[Ong, 1997]
A 2-path 4th-order modulator
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Pro
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Examples of N-Path BP Σ∆Ms II
bzp1–
1 zp1–+
--------------------azp
1–
1 zp1–+
--------------------+
+
+
+
4 bit DAC–
Φ1
X z( )
Quantizerbzp1–
1 zp1–+
--------------------
1,-1,1,-1...
+
+
1 bit DAC–
bzp1–
1 zp1–+
--------------------azp
1–
1 zp1–+
--------------------+
+
+
+
4 bit DAC–
Φ2Quantizerbzp
1–
1 zp1–+
--------------------
1,-1,1,-1...
+
+
1 bit DAC–
I DATA
Q DATA
[Tabatabaei, 1999]
A 2-path 6th-order modulator (dual quantizer, multibit)
Image components due to path mismatch
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Continuous-Time Architectures I
DAC s( ) fnH s( )
fs
x1 t( )
E z( ) 0=
yn y t( ) x1 n,
X1 z( )
Y z( )-------------- Z L
1–DAC s( )H s( )[ ]
t nT s=Z DAC τ( )h t τ–( ) τd
∞–
∞
∫
t nTs=
= =
Equivalent discrete-time system
Continuous-Time BandPass Σ∆ Modulators
Speed enhancement
Implicit anti-alias filter
Sensitive to clock jitter
Excess modulator loop delay
+
-
x yn
DAC s( )
fnH s( )
fs
x1 t( ) x1 nTs( )
Internal sampling
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Continuous-Time Architectures II
Synthesis process
Select an appropriate DT architecture
Apply a DT-to-CT transformation
Impulse invariant transformation
DAC s( ) esp1Ts–
esp2Ts–
–s
-------------------------------------------=DAC t( )1 , p1Ts t p2Ts≤ ≤
0 , otherwise
=
Equivalent CT and DT loop filter transfer function for a BPΣ∆M.
Non-Return-to-Zero (NRZ),
Return-to-Zero (RZ),
Half-delay Return-to-Zero (HRZ),
2nd order–
DAC t( ) H z( ) H s( )
p1 0 p2, 1= =z 1– 1 z 1––( )
1 z 2–+------------------------------
ωos
s2 ωo2+
-------------------p1 0 p2, 1 2⁄= =1
22
-------– z 1– 2
2------- z 2––
1 z 2–+----------------------------------------------------
p1 1 2⁄ p2, 0= =
22
------- z 1– 12
2-------–
z 2––
1 z 2–+----------------------------------------------------
[Gao, 1998]
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Main Limitations of (LDI) Resonators
φ2 φ1
φ1
2Ibias Ibias
φ1 φ2
φ2
2Ibias 2Ibias Ibias
φ1
1 : 1 1 1 : 1 -2 1: :
ii io
:
φ1
io1 -2io
Current mirror mismatching
Finite Output/Input Conductance ratio
Charge injection
Settling error
Non-linearities
Switched-Current
+
− φ1
φ1 φ2
C1
C2+
−
vin +
−
C2
φ2
φ1
φ1
φ2
2C1 φ2
φ1
-1
+
−
vout
Capacitor mismatchingFinite opamp DC gain
Settling error
Clock jitter Thermal Noise
Non-linearities
φ1
C1 φ2φ1
φ2
Switched-Capacitor
Circuit Errors
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f. A
ngel
Ro
drig
uez-
Váz
quezFinite Av in SC; εg and εq in SI - I
φ2 φ1
φ1
go goid1 id2
go2
2Ibias Ibias
ii io
+
−φ2φ2
φ1
C2
+
−
vin
C1
φ1φ2+
−
vout
+
−
vaAvva
+
-vout
SC LDI integrator with finite opamp DC gain (Av)
SI LDI integrator with:
and charge injection error (εq) finite output-input conductance ratio error (εg)
+
-
φs
Ms
M
COLCOL
∆q ∆q
CgsVgs
H int z( ) 1 δ–( )z 1 2⁄–
1 1 γ–( )– z 1–-------------------------------≅
δ 1Av------- 1
C1C2-------+
≅ γ 1Av-------
C1C2-------≅
H int z( )1 εg– εq–( )z 1 2⁄––
1 1 2εg 2εq+( )–[ ]– z 1–-----------------------------------------------------------≅
εg2gogin----------≅
εq
∆VqoffξqVT–( )
Vgs· VT–( )
Q
----------------------------------------- 2ξq–≅
∆vq∆qin jCgs
--------------≡ ∆VqoffξqvgsM
–=
similar effect
Circuit Errors
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Pro
f. A
ngel
Ro
drig
uez-
Váz
quezFinite Av in SC; εg and εq in SI - II
ξ1
2εF 2εFB εgFεgFB
, for SI circuits+ + +–
2γ 4δ, for SC circuits–
=
ξ2
4εg 4εq εgFεgFB
for SI circuits,+ + +
2γ for SC circuits,
=
εF FB, rongoF FB,= εgF FB,goF FB, gm⁄( ) 1 εF FB,–( )=
Different effect at the resonator level
NTF z( ) 1 ξ1z 1– 1 ξ2–( )z 2–+ +[ ]2
≅
Noise transfer function of a 4th-order BP modulator
0.24 0.25 0.26-100
-80
-60
-40
-20NTF (dB)
Frequency/Sampling Freq.0.24 0.25 0.26-100
-80
-60
-40
-20
Frequency/Sampling Freq.
NTF (dB)
Hres z( )1 µ– 1( )z 1– µ2z 2–+
1 ξ1z 1– 1 ξ2–( )z 2–+ +----------------------------------------------------------≅
LDI reson. tran. function
0 0.1 0.2 0.3 0.4 0.5-120
-100-80
-60
-40
-200
IdealReal
PS
D(d
B)
Freq./Sampling Freq.
0 0.1 0.2 0.3 0.4 0.5-120-100-80-60
-40
-20
0IdealReal
Freq./Sampling Freq.
Effect on the resonant frequency
Effect on the Q-factor
PS
D(d
B)
Hres z( )1 µ– 1( )z 1– µ2z 2–+
1 ξ1z 1– 1 ξ2–( )z 2–+ +----------------------------------------------------------≅
Circuit Errors
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Finite Av in SC; εg and εq in SI - III
0.2 0.25 0.3-120
-100
-80
-60
-40
-20
0
0.2 0.25 0.3-120
-100
-80
-60
-40
-20
0
Model
Simulation
Model
Simulation
Av 60dB=Av 30dB=
Model
Simulation
0.2 0.25 0.3-120
-100
-80
-60
-40
-20
0
0.2 0.25 0.3-120
-100
-80
-60
-40
-20
0
Model
Simulation
εg 0,1%= εg 1%=
Normalized frequency to fs
Magnitude (dB) Magnitude (dB)
Normalized frequency to fs
Normalized frequency to fs
Magnitude (dB) Magnitude (dB)
Normalized frequency to fs
Circuit Errors
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Mismatch Gain Error
φ1
b1
iiioφ1 φ2
1 : k
Ibias kIbias
β2 V,T2
β1 V,T 1
+
−φ2φ2
φ1
C2
+
−
vin
C1
φ1φ2+
−
vout
εmis∆ββ
-------∆VT
vgs VT–( )Q
---------------------------------–≅
kC1C2-------= εmis
∆C1C1
-----------∆C2C2
-----------–=
Hres z( ) z 1–
1 εmis z 1– z 2–+ +---------------------------------------------≅
0.225 0.25 0.275
-50
0Magnitude (dB)
Normalized frequency to fs
δfn εmisMπ-----
BW2
--------- ≡
Notch frequency error
MonteCarlo Simulation
Gain factor mismatch are mapped into:
Capacitor ratio mismatch for SC circuits
Transistor ratio mismatch for SI circuits
In Lowpass Σ∆, mismatch error is criti-cal in cascade architectures
In Bandpass Σ∆, mismatch error affectsalso to the notch frequency position
Circuit Errors
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+
−φ2φ2
φ1
C2
+
−
vin
C1
φ1φ2+
−
vout
+
−
va
gmva+
−
voutCo go
SC LDI integrator with linear settling error
SI memory cell with linear settling error
Vbias Ibias
φ1 φ2
φ1M
ii io
gmQvgsgoQ
Cgs
+
−vgs
φ1
φ1 φ2
ii io
+
−
vds
+
−vgs
+
−
vds
ids
MB
Linear Settling I
H int z( ) gi1 εs–( )z 1 2⁄–
1 z 1––----------------------------------≅
εs eTs 2τ⁄–
= τ Ceq gm⁄=
Ceq C1 Co 1C1C2-------+
+=
εs eTs 2τ⁄–
= τ Cgs gmQ⁄=
H int z( )z 1 2⁄– 1 εs–( ) 1 εsz 1––( )
1 z 1––( ) 1 εs2 z 1––( )
--------------------------------------------------------------–≅
Circuit Errors
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Linear Settling II
LDI resonator transfer function
Notch frequency error
0.225 0.250 0.275-120
-100
-80
-60
-40
Normalized Frequency (Freq./fs)
εs=0.1%εs=0.5%εs=1.0%
Effect of εs on NTF in SI circuits
0.225 0.25 0.275-120
-100
-80
-60
-40
Normalized Frequency (Freq./fs)
εs=0.1%εs=0.5%εs=1.0%
Effect of εs on NTF in SC circuits
NTF (dB) NTF (dB)
δfn 4εsMπ-----
BW2
--------- ≡
ξ1 4εs, for both SC and SI circuits–{=
ξ24εs for SI circuits,
0 for SC circuits,
=Hres z( )
1 µ– 1( )z 1– µ2z 2–+
1 ξ1z 1– 1 ξ2–( )z 2–+ +----------------------------------------------------------≅
Circuit Errors
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Summary of Effect of Linear Errors on a 4th-Order Architecture I
φ2
LDIX
φ1 φ1 φ2
RSYLDI
2
+
−φ2
LDI
φ1
LDI
2
+
−
0.5
+−
Half Delay
io+
DACHalf Delay
NTF z( ) 1 ξ1z 1– 1 ξ2–( )z 2–+ +[ ]2
≅
loss of attenuation in the signal band
shifts of the Notch Frequency:
ξ2 0≠
ξ1 0≠ δfn ξ1Mπ-----
BW2
--------- ≡
Switched-Capacitor Switched-Current
Finite opamp DC gainIncomplete Settling error
Mismatch gain error
Mismatch gain errorIncomplete settling error
Finite opamp DC gain Incomplete settlingCharge injection error
Finite output-input conductance ratio error
ξ1 0≠
ξ2 0≠
Circuit Errors
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Quantization Noise Power (4th-order Modulator)
PSD signal
Summary of Effect of Linear Errors on a 4th-Order Architecture II
PQπ
4∆2
60M5-------------- 1 10
3------ 3ξ1
2 ξ22+
Mπ-----
25 ξ1
2 ξ22+
2 M
π-----
4+ +=
8 16 32 64 128 256 512102420
40
60
80
100
Hal
f-sca
le S
NR
(dB
)M
εmax=0.1%εmax=0.5%εmax=1%
εmax(%)0.01 0.1 1
40
60
80
100Half-scale SNR (dB)
M=256M=128M=64
Theory
Simulations
Assuming all errors to be below an error bound εmax
Circuit Errors
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Non-linear Behaviour: Harmonic Distortion I
Main non-linear error mechanisms in SC circuits:
Capacitor non-linearity
+
−C v( ) Cnom 1 αv βv2 …+ + +( )=v
Non-linear opamp DC-gain Av v( ) A0 1 γ1v γ2v2 …+ + +( )=
+
−φ2φ2
φ1
C2
+
−
vi
C1
φ1φ2+
−
vout
vo n, vo n 1–,C1C2------- vi n,
vi n, vo n,+
A0---------------------------- 1 γ1vo n, γ2– vo n,
2–( )–+≅
vo n, vo n 1–,C1nomC2nom----------------- vi n 1–, 1 α
2---vi n 1–,+
α2--- vo n 1–,
2 vo n,2–( )+ +≅
Circuit Errors
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Non-linear Behaviour: Harmonic Distortion II
Ibias
ioφ2
φ1
φ1
+
−
ii
vgs
io n, Ioff 1 ξ1–( )– ii n 1 2⁄–, ξkk 2=
∞
∑– ii n 1 2⁄–,k
=
Non-linear (static) model of the memory cell
io n, 1 2ξ1–( )io n 1–,
1 ξ1–( )– ii n 1 2⁄–,
ξ31 ξ1–( )
-------------------- io n 1–,3
io n,3
+ –≅
Fully-differential integrators
EXAMPLE: εg
ξ1gout Vgs VT–( )
QIbias
-------------------------------------------
ξ2
gout Vgs VT–( )Q
2 Ibias2
-------------------------------------------
ξ3
3– gout Vgs VT–( )Q
8 Ibias3
-------------------------------------------------
Main non-linear errors in SI circuits:
Source of non-linearity:
Output-input conductance ratio error (εg(%) chargeinjection error (εq(%) settling error (εs(%) mismatch error
gm i in( ) gmQ
1iin
Ibias------------+=
Circuit Errors
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φ2
LDIX
φ1 φ1 φ2
RSYLDI
2
+
−φ2
LDI
φ1
LDI
2
+
−
0.5
+−
Half Delay
+
AH 3,
DACHalf Delay
0.22 0.23 0.24 0.25 0.26 0.27 0.28-140
-120
-100
-80
-60
-40
-20
0Magnitude (dB)
Frequency/Sampling Frequency
Reson 1 non-linear
Reson 2 non-linear HD3
fi fs 4⁄ fi'–=( )
fi
fs 4 3fi'+⁄
Analysis of the effect of nonlinearity on the resonator is required
Non-linear Behaviour: Harmonic Distortion III
Approaches to analyse distortion:
HD3 at the modulator input is
equal to HD3 at the modulator output
The contribution of Resonator 2 is attenuated bythe gain of Resonator 1 in the signal bandwidth
Typical figures:
STF z( ) 1=
HD3AH 3,
X-------------≡ IM3 3HD3≡
Circuit Errors
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IM3 3HD3 12ξ3 X 2 1 16ξ1–( ) 1 12πfi'Ts+( )≅=
HD3 4ξ3 X 2 1 16ξ1–( ) 1 12πfi'Ts+( )≅ c
AH 3,ξ3 X 3
2 1 2ξ1–( )-------------------------- 1 12πfi'Ts+( )≅
EXAMPLE, effect of non-linear errors on fully-differential SI BP Σ∆Ms
0.22 0.23 0.24 0.25 0.26 0.27 0.28-100
-80
-60
-40
-20
0
Frequency/Sampling Frequency
IM3 =-43 dB
Magnitude (dB)
IM3 =-54 dB
0.1 1-80
-70
-60
-50
-40
ξ3 ppm µA( )⁄2
IM3 dB( )CalculatedSimulated,Simulated,
IDAC 50µA=IDAC 25µA=
Non-linear Behaviour: Harmonic Distortion IV
Circuit Errors
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Thermal Noise
φ2
X
φ1 φ1
Y
2
+
−φ2φ1
2
+
−
0.5
+−
Half Delay
+
DACHalf Delay
vn1 vn2 vn3 vn4
P th PSDin f( ) fd
fs 4 Bw 2⁄–⁄
fs 4 Bw 2⁄+⁄
∫=
vin
0.23 0.24 0.25 0.26 0.28-100
-80
-60
-40
-20
0Magnitude (dB)
Normalized frequency to fs
Considering vn2
Considering vn1Considerations for Analysis:Contributions of 3rd and 4th integrators to theinput noise are attenuated by the first resonator
Second integrator contributes to the input equiva-lent noise as:
vin2 vn1
2 1 z 1––2vn2
2+≅
fn fs 4⁄= ⇒ 1 z 1––2
2≅
Circuit Errors
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Uncertainties in the sampling time can be modelled asa (white) noise, jitter noise, with in-band noise power,
In BP Σ∆Ms, is a substantial fraction of
(Typically )
PJ f( ) A2
2-------
2πfiσt( )2
M------------------------=
fi fs
fi fs 4⁄=
Increase with the sampling frequency
clkx (t) x (nTs)
clk
δ
x nTs δ+( ) x nTs( ) 2πfiAδ 2πfinTs( )cos≅–
Sinusoidal inputs
Clock Jitter
[Tao, 1999]
Continuous-time bandpass Σ∆ modulators:More sensible to clock jitter
DAC’s clock jitter-induce errors with the input signal,
NRZ DAC
RZ DAC
PJ f( )α σ tfs( )2
M---------------------- ∆2
c πfi fs⁄( )sin( )2----------------------------------------= 0 α 4≤ ≤
PJ f( )8 σtfs( )2
M--------------------- ∆2
c πfi fs⁄( )sin( )2----------------------------------------=
State-of-the-Art
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State-of-the-Art on CMOS BP Σ∆ Ms I
Author DR (bit)fs
(MHz)fn (MHz) Bw (kHz)
Power Cons.(mW)
Process Architecture
Switched-Capacitor[Jant93] 10.2 1.825 0.455 8 210 3mm DP / 5V 4th, Optim. NTF[Long93] 15 7.2 1.8 30 -- 1mm DP / 5V 4th, LP-to-BP[Song95] 9 8 2 30 0.8 2mm DP / 3.3V 4th, LP-to-BP[Hair96] 11.7 13 3.25 200 14.4 0.8mm DP / 3V 4-2, LP-to-BP[Andr96] 8 8 2 64 8 0.5mm DP / 3.3V 6th, LP-to-BP[Liu97] 11.8 0.827 0.413 2 -- 2mm DP / 5V 4th, Optim. NTF[Corm97] 9.5 1.25 0.25-.375 6.25 -- 2mm DP / 5V 4th, LP-to-BP[Ong97] 12.2 80 20 200 72 0.6mm SP 3.3V 4th, LP-to-BP[Jant97] 10.8 10 3.75 200 130 0.8mm SP / 5V 4th, Quadrature[Andr98] 9.2 4 1 200 19 0.5mm DP / 3V 3th-3bit, Optim. NTF[Baza98] 6.7 40 20 1250 65 0.5mm DP / 5V 2nd, LP-to-BP[Chua98] 13 0.5 0.125 0.5 -- 2mm DP / 5V 6th, Optim.NTF[Park99] 12.2 20 5 200 180 0.65mm SP / 4V 4th, LP-to-BP[Taba99] 13 80 20 1250 90 0.25mm DP / 2.5V 6th, LP-to-BP[Toni99] 12.7 42.8 10.7 200 80 0.35mm SP / 3.3V 6th,Optim. NTF[Baza99] 9.4 68 17 1250 48 0.6mm DP / 3V 4-4, LP-to-BP[Taba00] 12 64 16 2000 110 0.25mm SP / 2.5V 6th, 2-path, IF-to-BB[Cusi00] 12 37.05 10.7 200 116 0.35mm SP/ 3.3V 6th, Optim. NTF[Cheu01] 6.7 42.8 10.7 200 12 0.35mm SP/ 1V 2nd, LP-to-BP[Burg01] 8.6 184.32 138.24 3840 13.5 0.25mm SP/ 2.5V 3rd, IF-to-BB
14 104 78 200 11.5Continuous Time
[Enge99] 11.7 40 9.15 200 60 0.5mm DP / 5V 6th, Optim. NTF10.8 80 10.7 200
[Tao99] 8 400 100 200 330 0.35mm SP/ 3.3V 2nd, IF-to-BB[Bree00] 13 13 13 100 1.8 0.35mm SP/2.5V 2nd, IF-to-BB[Zwan00] 16 21.07 10.7 9 8 0.25mm SP/2.5V 5th, IF-to-BB
13.3 200 11
State-of-the-Art
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State-of-the-Art on CMOS BP Σ∆ Ms II
• Statistics of the State-of-the-Art CMOS BPΣ∆Ms
♦ Synthesis method: (~50%)
♦ Passband location: (~80%)
♦ Circuit technique: Switched-Capacitor (~80%)
♦ Technology: CMOS (double-poly) (~54%)
z 1– z 2––→
fn fs 4⁄=
• Comparison figure
♦ of LowPass Σ∆ modulators,
is not appropriate ( is missing)
FOM
FOM Power W( )
2Resolution bit( ) fd Samples s⁄( )×---------------------------------------------------------------------------------------- 1012×=
fn
4
6
8
10
12
14
16
18
1 10 100 1000 10000
Bw (kHz)
DR
(b
its)
SC LP-to-BP
SC OPTIM. NTF
SC IF-to-BB
SC Quadrature
CT OPTIM. NTF
CT IF-to-BB
0
50
100
150
200
250
300
350
1 10 100 1000 10000
Bw (kHz)
Po
wer
Co
ns.
(m
W)
SC LP-to-BP
SC OPTIM. NTF
SC IF-to-BB
SC Quadrature
CT OPTIM. NTF
CT IF-to-BB
State-of-the-Art
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1,E-06
1,E-05
1,E-04
1,E-03
1,E-02
1,E-01
1,E+00
1 10 100 1000 10000
Bw (kHz)
FOM
BP
SC LP-to-BPSC OPTIM. NTFSC IF-to-BBSC QuadratureCT OPTIM. NTFCT IF-to-BB
AM, IS-54 FM, GSM, PCS
UMTSIS-95BLUETOOTH
FOMBPPower (mW)
2DR bits( )
fn MHz( )×----------------------------------------------------------=
State-of-the-Art on CMOS BP Σ∆ Ms III
State-of-the-Art
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1,00
10,00
100,00
1000,00
10000,00
0,0001 0,01 1 100
DOR (MS/s)
FO
M1(
pJ) SC
SI
SI lowpass Σ∆ modulators obtain worse performance than SC ones
SI Σ∆Ms vs. State-of-the-Art Σ∆Ms I
State-of-the-Art
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SI Σ∆Ms vs. State-of-the-Art Σ∆Ms II
1,E-04
1,E-03
1,E-02
1,E-01
1,E+001 10 100 1000 10000
Bw (kHz)
FO
MB
P
SC LP-to-BPSC OPTIM. NTF
SC QuadratureCT OPTIM. NTFSI
Best comparison is obtained in the bandpass case
[de la Rosa, 2002]
State-of-the-Art
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References I
[Andr96] E. André, D. Morche, F. Balestro and P. Senn: “A 2-path Σ∆ Modulator for Bandpass Application”, Proc. of IEEE-CASWorkshop on Analog and Mixed IC Design, pp. 87-91, September 1996.
[Andr98] E. André, G. Martel, D. Morche, and P. Senn: “A Bandpass A/D Converter and its I/Q Demodulator for IntegratedReceivers”, Proceedings of the 24th European Solid-Stated Circuits Conference, ESSCIRC’98, pp. 416-419, Sep-tember 1998.
[Baza98] S. Bazarjani, W.M. Snelgrove: “A 160MHz Fourth-Order Double-Sampled SC Bandpass Sigma-Delta Modulator”,IEEE Trans. Circuits and Systems-II, Vol. 45, pp. 547-555, May 1998.
[Baza99] S. Bazarjani, S. Younis, J. Goldblatt, D. Butterfield, G. McAllister, S. Ciccarelli: “An 85MHz IF Bandpass Sigma-DeltaModulator for CDMA Receivers”, Proceedings of the 25th European Solid-Stated Circuits Conference, ESSCIRC’99,pp. 266-269, September 1999.
[Burg01] T. Burger and Q. Huang: “A 13.5-mW 185-Msample/s DS Modulator for UMTS/GSM Dual-Standard IF Reception”,IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1868-1878, December 2001.
[Bree00] L. J. Breems, E. J. van der Zwan and J.H. Huijsing: “A 1.8-mW CMOS Σ∆ Modulator with Integrated Mixer for A/DConversion of IF Signals”, IEEE Journal of Solid-State Circuits, Vol. 35 pp. 468-475, April 2000.
[Cheu01] V. S. L. Cheung, H.C. Luong and W.H. Ki: “A 1V 10.7MHz Switched-Opamp Bandpass Σ∆ Modulator Using Double-Sampling Finite-Gain Compensation Technique”, 2001 IEEE Int. Solid-State Circuit Conference, pp. 52-53, Feb.2001.
[Chua98] S. Chuang, H. Liu, X. Yu, T.L. Sculley, R. H. Bamberger: “Design and Implementation of Bandpass Delta-SigmaModulators Using Half-Delay Integrators”, IEEE Trans. Circuits and Systems-II, Vol. 45, pp. 535-546, May 1998.
[Corm97] R. F. Cormier, T. L. Sculley, and R. H. Bamberger: “A Fourth Order Bandpass Delta-Sigma Modulator with DigitallyProgrammable Passband Frequency”, Int. Journal of Analog Integrated Circuits and Signal Processing, pp. 217-229,1997.
[Cusi00] P. Cusitano, F. Stefani and A. Baschirotto, “A 73dB SFDR 10.7MHz 3.3V CMOS Bandpass Σ∆ Modulator sampled at37.05MHz", Proc. of the 26th European Solid-State Cicuits Conference, pp. 80-83, September 2000.
[Enge99] J. van Engelen, R. van de Plasshe, E. Stikvoort, A. Venes: “A Sixth-Order Continuous-Time Bandpass Sigma-DeltaModulator For Digital Radio IF”, IEEE Journal of Solid-State Circuits, Vol. 34, pp. 1753-1764, December 1999.
[Hair96] A. Hairapetian: “An 81-MHz IF Receiver in CMOS”, IEEE Journal of Solid-State Circuits, pp. 1981-1986, December1996.
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Design of Embeddable Data Converters: Sigma-Delta Converters Slide BPSDM 56 of 56 IMSE-Σ∆ Design Group
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References II
[Jant93] S.A. Jantzi, M. Snelgrove and P.F. Ferguson: “A fourth-order Bandpass sigma-delta Modulator”, IEEE J. Solid-StateCircuits, Vol. 28, pp. 282-291, March 1993.
[Jant97] S.A. Jantzi, K. W. Martin, and A. S. Sedra: “Quadrature Bandpass Σ∆ Modulation for Digital Radio”, IEEE J. Solid-StateCircuits, Vol. 32, pp. 1935-1949, December 1997.
[Long93]L. Longo and H. Bor-Rong: “A 15b 30kHz Bandpass Sigma-Delta Modulator”, Proceeding 1993 IEEE Int. Solid-StateCircuit Conference, pp. 226-227, March 1993.
[Liu97] H. Liu, X. Yu, T. Sculley and R. H. Bamberger: “A Fourth Order Bandpass Delta-Sigma A/D Converter with Input Mod-ulation Network and Digitally Programmable Passband”, Proc. 1997 IEEE Int. Symp. Circuits and System, pp. 385-388,May 1997.
[Ong97] A.K. Ong and B.A. Wooley: “A Two-Path Bandpass Σ∆ Modulator for Digital IF Extraction at 20MHz”, IEEE Journal ofSolid-State Circuit, Vol. 32, pp. 1920-1933, December 1997.
[Park99] J. Park, E. Joe, M. Choe, B. Song: “A 5-MHz IF Digital FM Demodulator”, IEEE Journal of Solid-State Circuit, Vol. 34,pp. 3-11, January 1999.
[Song95]B.S. Song: “A Fourth-Order Bandpass Delta-Sigma Modulator with Reduced Number of Op Amps”, IEEE Journal ofSolid-Stated Circuits, Vol. 25, pp. 1309-1315, December 1995.
[Taba99]A. Tabatabaei, B. Wooley: “A Wideband Bandpass Sigma-Delta Modulator for Wireless Applications”, IEEE Int. Symp.on VLSI Circuits, pp. 91-92, 1999.
[Taba00]A. Tabatabaei and B. Wooley: “A Two-path Bandpass Sigma-Delta Modulator with Extended Noise Shaping”, IEEE J.Solid State Circuits, Vol. 35, pp. 1799-1809, December 2000.
[Tao99] H. Tao, J.M. Khoury: “A 400-MS/s Frequency Translating Bandpass Sigma-Delta Modulator”, IEEE J. Solid State Cir-cuits, Vol. 34, pp. 1741-1752, December 1999.
[Toni99] D. Tonietto, P. Cusinato, F. Stefani, A. Baschirotto: “A 3.3V CMOS 10.7MHz 6th-order bandpass Σ∆ Modulator with78dB Dynamic Range”, Proceedings of the 25th European Solid-Stated Circuits Conference, ESSCIRC’99, pp. 78-81,September 1999.
[Zwan00]E.J. van der Zwan, K. Philips and C. A.A. Bastiannsen: “A 10.7-MHz IF-to-Baseband Σ∆ A/D Conversion System forAM/FM Radio Receivers”, IEEE Journal of Solid-State Circuits, Vol. 35, pp. 1810-1819, December 2000.