Automated TFT Noise Characterization

Platform Kendell Clark (EE), Stephen Marshall (EE), Kendell Clark (EE), Stephen Marshall (EE), Carmen Parisi (EE), James Spoth (CE), Ryan Carmen Parisi (EE), James Spoth (CE), Ryan

Vaughan (ME)Vaughan (ME)Rochester Institute of TechnologyRochester Institute of Technology

Analog Devices Integrated Microsystems LaboratoryAnalog Devices Integrated Microsystems Laboratory

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AgendaAgenda Project OverviewProject Overview Customer NeedsCustomer Needs SpecificationsSpecifications Functionality so farFunctionality so far System DesignSystem Design ScheduleSchedule BudgetBudget Current StatusCurrent Status

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Project OverviewProject Overview Noise Measurements of Thin-Film Devices on Glass is Noise Measurements of Thin-Film Devices on Glass is

necessary for understanding their operation and necessary for understanding their operation and modeling their behaviormodeling their behavior

Many noise measurements are required to accurately Many noise measurements are required to accurately model any new technologymodel any new technology

1/f Noise measurements take a long time due to 1/f Noise measurements take a long time due to extremely low frequencies (1 mHz)extremely low frequencies (1 mHz)

Devices under test must be accurately biased for the Devices under test must be accurately biased for the entire durationentire duration

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Project OverviewProject Overview Design & build an automated low noise measurement Design & build an automated low noise measurement

environmentenvironment Computer-Controlled Low noise biasingComputer-Controlled Low noise biasing Low noise signal amplificationLow noise signal amplification Interface with and unify operation of laboratory measurement apparatusInterface with and unify operation of laboratory measurement apparatus

Lower budget than competing commercial solutionsLower budget than competing commercial solutions Cascade Microtech EDGE 1/f Noise Management System:Cascade Microtech EDGE 1/f Noise Management System:

$1.2 million, but has more functionality$1.2 million, but has more functionality Thermal Chuck, Automated Probers, Automated Data Analysis, Higher Bandwidth, etc.Thermal Chuck, Automated Probers, Automated Data Analysis, Higher Bandwidth, etc. Aimed at commercial foundries improving process for marketing high-performance siliconAimed at commercial foundries improving process for marketing high-performance silicon

ADIML VIKING PlatformADIML VIKING Platform Approximately $1,000Approximately $1,000

““Bare bones” automated noise measurementsBare bones” automated noise measurements Aimed at low budget research groups for characterization, rather than production testingAimed at low budget research groups for characterization, rather than production testing

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Customer NeedsCustomer Needs EMI/RFI Shielded EnvironmentEMI/RFI Shielded Environment Localized, low noise amplification of DUT noise signalLocalized, low noise amplification of DUT noise signal Low noise, programmable DC biasing of DUTLow noise, programmable DC biasing of DUT Immunity from 60Hz AC power interferenceImmunity from 60Hz AC power interference Full noise measurement cycle is software-controllableFull noise measurement cycle is software-controllable

IV Sweep IV Sweep Device Bias Device Bias Noise Measurement Noise Measurement Data Data AcquisitionAcquisition

Interface with existing wafer probe stationInterface with existing wafer probe station Maintain full movement of wafer chuck and microscope gantryMaintain full movement of wafer chuck and microscope gantry Maintain view of wafer during measurement; RF shielding must remainMaintain view of wafer during measurement; RF shielding must remain

System must operate for several hours at a timeSystem must operate for several hours at a time No clocks or oscillators inside shielded environmentNo clocks or oscillators inside shielded environment

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SpecificationsSpecificationsSpec Name

Specification (description)

Unit of Measure Min Value Nominal ValueMax

ValueAchieved

Overall System Gain Range Max system gain (adjustable) dB 40   180 180 Amplifier BW Max system BW Hz 10k 100k 1M  100k

Contributed Noise at DUT Gate

Switches must not add significant noise to the system, either through 4kTR, or through contact R modulation during measurement.

nV/rt(Hz)   1 20  3.2

Minimum Measureable FrequencyKeep 1/f noise corners of system components far enough below this value to be able to measure accurately at low frequencies

Hz 0.1 1 10 1

Input Referred Noise of LNA@ 10Hz pA/rt(Hz)   100 500  32

@ 10kHz pA/rt(Hz)   20 50 25

Drain Current Source Noise Performance 

pA/rt(Hz) 0.001   500 300 

Amplifier DC Bias Source Noise Performance 

nV/rt(Hz)     50 3.2 

Bias Settling Time Bias network settling time (seperately, not in total)

s 0 0.5 10  

Gate Bias Range   V -10   10 [-10,10] Amplifier DC Bias Range   V -10   10 [-10,10] Drain Current Resolution   A     2n  

Drain Current Range   A 1n   100u  Battery Life   Hours 3 5    

RF ShieldingEMI-shielded box for analog circuitry (attenuation of ambient noise)

BOOL T  

Ground Isolation From Analog CircuitryAnalog GND must be quiet; therefore must avoid ground loops through isolation.

BOOL T      

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Specifications - ProblemsSpecifications - Problems

Issue with current bias circuit prevents circuit from Issue with current bias circuit prevents circuit from settling.settling. Recent simulations show this can be fixed easilyRecent simulations show this can be fixed easily

Drain bias current resolution not yet measurable:Drain bias current resolution not yet measurable: Nano- or pico-ammeter not available, still developing a Nano- or pico-ammeter not available, still developing a

measurement circuit using LNA to amplify currentmeasurement circuit using LNA to amplify current LNA has an offset voltage that affects results at high gain settingsLNA has an offset voltage that affects results at high gain settings

Battery life untested.Battery life untested. 9V batteries purchased could not output enough current for the 9V batteries purchased could not output enough current for the

circuitcircuit Need to purchase new batteriesNeed to purchase new batteries

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Project OverviewProject Overview

PCWith LabVIEW

Digital Control Circuit

DUTSignal

Conditioning(Amplification)

Measurement(DSA, B1500)

Biasing Circuit

NI USB Development

Board

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Analog Circuitry – Block Analog Circuitry – Block DiagramDiagram

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Analog Circuitry – Voltage Bias Analog Circuitry – Voltage Bias CircuitryCircuitry

Control Voltage

LPF

C

RChargeCharging

Relay

RFilter

DUT Gate or LNA (-)

Terminal

Control Voltage comes Control Voltage comes from a DAC located on from a DAC located on the PCB.the PCB.

RRFilterFilter & C form a LPF & C form a LPF

with corner frequency with corner frequency of 1mHz.of 1mHz. >60dB attenuation of >60dB attenuation of

noise in the noise in the measurement frequency measurement frequency range, 1Hz to 100kHzrange, 1Hz to 100kHz

RRChargeCharge allows for capacitor to allows for capacitor to

reach desired voltage levels reach desired voltage levels quickly.quickly.

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Resistor-Based Current Bias Resistor-Based Current Bias GenerationGeneration

Uses battery and resistor, Uses battery and resistor, or op-amp biasing or op-amp biasing scheme to produce a fixed scheme to produce a fixed voltage across a resistorvoltage across a resistor

Fundamentally limited in Fundamentally limited in noise performancenoise performance Resistor thermal noise Resistor thermal noise

floor of Rfloor of RDD

Image: Kwok K. Hung, et. Al. A Physics Based MOSFET Noise Model for Circuit

Simulators. IEEE Trans. On Electron Devices. Vol. 37. May 1990.

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Analog Circuitry – Current Bias Analog Circuitry – Current Bias CircuitryCircuitry

Control Voltage

IoutLPF

C

C

LPF

DUT

VDDSensitiveMeasurement

Node

Noise Injection

Rs

Uses a JFET-based current Uses a JFET-based current sourcesource Permits isolation of resistors Permits isolation of resistors

from output currentfrom output current Allows resistors to be filtered Allows resistors to be filtered

without attenuating noise at without attenuating noise at higher frequencieshigher frequencies

Circuit topology offers Circuit topology offers output impedance enhanced output impedance enhanced by amplifier gainby amplifier gain

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Analog Circuitry – Current Bias Analog Circuitry – Current Bias Circuitry Equivalent Noise ModelCircuitry Equivalent Noise Model

Iout

LPF

Cf

CLPF

DUT

VDD

RsVn2

Vn1

Inr

RfIn,ch

In1

Vg

Use superposition to find Use superposition to find contribution of each noise contribution of each noise source to output noise currentsource to output noise current Choose Cs to attenuate all noise Choose Cs to attenuate all noise

sources appropriatelysources appropriately Assuming large Cs, Assuming large Cs, iin1n1, , vvn1n1, , iinrnr are are

made negligiblemade negligible

Amplifier with low Amplifier with low vvn2n2 was was

chosenchosen JFETs have naturally low JFETs have naturally low iin,chn,ch

System achieves total output noise current on the

order of 100 pA/√Hz

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Analog Circuitry – LNA Noise Analog Circuitry – LNA Noise ContributionContribution

Noise Analysis of LNA dictates Noise Analysis of LNA dictates that an amp with a low input that an amp with a low input voltage noise is chosenvoltage noise is chosen

Total noise contribution found to Total noise contribution found to be 25 pV/√Hz with AD797 ampbe 25 pV/√Hz with AD797 amp

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EMI/RFI EnclosureEMI/RFI Enclosure

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EMI/RFI EnclosureEMI/RFI Enclosure

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Digital HardwareDigital Hardware Xilinx Coolrunner II CPLDXilinx Coolrunner II CPLD

No internal oscillatorsNo internal oscillators Flexible I/O (Voltage levels, current drive, 33 I/O pins)Flexible I/O (Voltage levels, current drive, 33 I/O pins) Low Cost (< $3)Low Cost (< $3) Familiarity with design environmentFamiliarity with design environment

Chose Peripherals with Serial InterfaceChose Peripherals with Serial Interface Kept CPLD resource usage low (risk of running out of logic)Kept CPLD resource usage low (risk of running out of logic) Allowed communication protocols to be implemented in softwareAllowed communication protocols to be implemented in software AD5754BREZ DACAD5754BREZ DAC Maxim MAX1248 ADCMaxim MAX1248 ADC On-Semi AMIS 39101 Relay DriversOn-Semi AMIS 39101 Relay Drivers Used a CPLD register for power control linesUsed a CPLD register for power control lines

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CPLD DesignCPLD Design

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Control SoftwareControl Software Developed using LabVIEWDeveloped using LabVIEW

Initial effort at learning the language difficultInitial effort at learning the language difficult Reaping the benefits now (easy maintenance)Reaping the benefits now (easy maintenance)

Developed highly modular codeDeveloped highly modular code Large hierarchy of Virtual Instruments makes high-level Large hierarchy of Virtual Instruments makes high-level

modifications easymodifications easy Implements peripheral-specific protocols in LabVIEW codeImplements peripheral-specific protocols in LabVIEW code

Should make adding additional functionality easier than modifying CPLD Should make adding additional functionality easier than modifying CPLD hardware or microcontroller firmwarehardware or microcontroller firmware

Each register, whether located in the CPLD or a peripheral has Each register, whether located in the CPLD or a peripheral has a VI which makes setting parameters easy (top level module a VI which makes setting parameters easy (top level module performs no protocol or bit setting operations)performs no protocol or bit setting operations)

Easy interface with Dynamic Signal Analyzer and 6501 USB Easy interface with Dynamic Signal Analyzer and 6501 USB DAQDAQ

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Hardware/Software TestingHardware/Software Testing

Initial testing performed without any hardwareInitial testing performed without any hardware Oscilloscope to verify softwareOscilloscope to verify software Simulations to verify CPLD designSimulations to verify CPLD design

Once PCB arrived and was assembled hardware Once PCB arrived and was assembled hardware testing begantesting began Experienced typical hiccupsExperienced typical hiccups Verified functionality of CPLD communication and control Verified functionality of CPLD communication and control

of power bitsof power bits Only design error was an incorrect pinout of JTAG headerOnly design error was an incorrect pinout of JTAG header

Fixed using Xilinx flying leads connectorFixed using Xilinx flying leads connector

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ScheduleSchedule PCB build was delayed several weeks due to several issues:PCB build was delayed several weeks due to several issues:

Soldering was extra work due to lack of solder mask and high Soldering was extra work due to lack of solder mask and high component densitycomponent density

Circuit bugs due to schematic entry error (ExpressPCB has no Circuit bugs due to schematic entry error (ExpressPCB has no simulator)simulator)

Circuit bugs due to design errorsCircuit bugs due to design errors PCB reworksPCB reworks

Full functional/specification testing delayed due to circuit Full functional/specification testing delayed due to circuit board bugsboard bugs

Mechanical design delayed due to extracurricular Mechanical design delayed due to extracurricular circumstancescircumstances On track to be finished very soonOn track to be finished very soon

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BudgetBudget EMI Enclosure MaterialsEMI Enclosure Materials

Metal: $150Metal: $150 RF Glass and Gasket: $30RF Glass and Gasket: $30 JB Weld: $5JB Weld: $5

NI6501A USB DAQ: $100NI6501A USB DAQ: $100 Electrical Components: $340Electrical Components: $340 PC Board: $60, +$100 for final versionPC Board: $60, +$100 for final version Batteries and Charging Solution: $70Batteries and Charging Solution: $70 Total: $855Total: $855 Not accounted for:Not accounted for:

NI LabView LicenseNI LabView License Xilinx CPLD Programming Cable: $295Xilinx CPLD Programming Cable: $295 Probe Card: $500 ~ $1000, depending on applicationProbe Card: $500 ~ $1000, depending on application

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Current StatusCurrent Status

Mechanical design fits on probe station and meets all Mechanical design fits on probe station and meets all specificationsspecifications Scheduled for completionScheduled for completion

Still finding bugs in the circuitStill finding bugs in the circuit Pin-compatible, rail-to-rail amps are availablePin-compatible, rail-to-rail amps are available If that allows the circuit to work, the final PCB can be orderedIf that allows the circuit to work, the final PCB can be ordered Simulations indicate that this was the problemSimulations indicate that this was the problem

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Digital Hardware / Software Digital Hardware / Software StatusStatus

CPLD modifications for new relay drivers completeCPLD modifications for new relay drivers complete Including SimulationsIncluding Simulations

Control Software needs updating for new relay driversControl Software needs updating for new relay drivers Was pending completion of PCB v2 layoutWas pending completion of PCB v2 layout

Need to perform hardware validation of DAC controlNeed to perform hardware validation of DAC control DAC has never been soldered to boardDAC has never been soldered to board Oscilloscope measurements at the right CPLD pins looked Oscilloscope measurements at the right CPLD pins looked

correctcorrect

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ReferencesReferences [1] Johns, David A. and Ken Martin. [1] Johns, David A. and Ken Martin. Analog Integrated Circuit Analog Integrated Circuit

DesignDesign. John Wiley and Sons. 1997.. John Wiley and Sons. 1997. [2] Stanford Research Systems. [2] Stanford Research Systems. Model SR570 – Low Noise Current Model SR570 – Low Noise Current

PreampliferPreamplifer. SRS, Inc. 1997.. SRS, Inc. 1997. [3][3] Kwok K. Hung, et. Al. Kwok K. Hung, et. Al. A Physics Based MOSFET Noise Model A Physics Based MOSFET Noise Model

for Circuit Simulators. for Circuit Simulators. IEEE Trans. On Electron Devices. Vol. 37. IEEE Trans. On Electron Devices. Vol. 37. May 1990.May 1990.

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AcknowledgementsAcknowledgements

Dr. Robert J. Bowman, Faculty Advisor and Principal InvestigatorDr. Robert J. Bowman, Faculty Advisor and Principal Investigator

Professor George Slack, Faculty Mentor and GuideProfessor George Slack, Faculty Mentor and Guide