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Application Note 47

AN47-1

August 1991

High Speed Amplifier TechniquesA Designer’s Companion for Wideband Circuitry

Jim Williams

PREFACE

This publication represents the largest LTC commitmentto an application note to date. No other application noteabsorbed as much effort, took so long or cost so much.This level of activity is justified by our belief that high speedmonolithic amplifiers greatly interest users.

Historically, monolithic amplifiers have represented pack-ets of inexpensive, precise and controllable gain. Theyhave partially freed engineers from the constraints andfrustrations of device level design. Monolithic operationalamplifiers have been the key to practical implementationof high level analog functions. As good as they are, onemissing element in these devices has been speed.

Devices presently coming to market are addressing mono-lithic amplifiers’ lack of speed. They bring with them theease of use and inherent flexibility of op amps. When

Philbrick Researches introduced the first mass producedop amp in the 1950’s (K2-W) they knew it would be used.What they couldn’t possibly know was just how widely,and how many different types of applications there were.As good a deal as the K2-W was (I paid $24.00 for mine -or rather, my father did), monolithic devices are far better.The combination of ease of use, economy, precision andversatility makes modern op amps just too good to bebelieved.

Considering all this, adding speed to op amps’ attractionsseems almost certain to open up new application areas.We intend to supply useful high speed products and thelevel of support necessary for their successful application(such high minded community spirit is, of course,capitalism’s deputy). We hope you are pleased with ourinitial efforts and look forward to working together.

Application Note 47

AN47-2

PREFACE .......................................................................................................................................................... AN47-1

INTRODUCTION................................................................................................................................................ AN47-5

PERSPECTIVES ON HIGH SPEED DESIGN ....................................................................................................... AN47-5

MR. MURPHY’S GALLERY OF HIGH SPEED AMPLIFIER PROBLEMSUnterminated Pulse Generator ..................................................................................................................... AN47-7Poorly Terminated Line ................................................................................................................................ AN47-8Poor Probe Grounding ................................................................................................................................. AN47-8Undercompensated Probe ............................................................................................................................ AN47-8Overcompensated Probe .............................................................................................................................. AN47-9Mismatched Delay in Probes ........................................................................................................................ AN47-9Overdriven FET Probe ................................................................................................................................... AN47-9Probe at Amplifier Summing Point ............................................................................................................. AN47-10Poor Quality Probe ..................................................................................................................................... AN47-10Oscilloscope Overdriven ............................................................................................................................. AN47-10Poor or No Ground Plane ........................................................................................................................... AN47-11No Bypass Capacitors, Heavy Load ............................................................................................................ AN47-11No Bypass Capacitors, No Load ................................................................................................................. AN47-11Poor Quality Bypass Capacitors.................................................................................................................. AN47-12Paralleled Bypass Capacitors Ring ............................................................................................................. AN47-12Almost Good Enough Bypass Capacitors ................................................................................................... AN47-122pF at Amplifier Summing Junction ........................................................................................................... AN47-12Noise Due to Coupling Into Critical Nodes .................................................................................................. AN47-131pF Coupling Path’s Effects ........................................................................................................................ AN47-13Decompensated Amplifier at Too Low a Gain ............................................................................................. AN47-13Excessive Capacitive Load .......................................................................................................................... AN47-13Common Mode Overdrive........................................................................................................................... AN47-14Booster Stage with Local Oscillations......................................................................................................... AN47-14Booster Stage with Loop Oscillations ......................................................................................................... AN47-14Excessive Source Impedance ..................................................................................................................... AN47-14

TUTORIAL SECTIONAbout Cables, Connectors and Terminations .............................................................................................. AN47-15About Probes and Probing Techniques ...................................................................................................... AN47-16About Oscilloscopes ................................................................................................................................... AN47-20About Ground Planes ................................................................................................................................. AN47-24About Bypass Capacitors ............................................................................................................................ AN47-25Breadboarding Techniques ......................................................................................................................... AN47-26Oscillation .................................................................................................................................................. AN47-29

TABLE OF CONTENTS

Application Note 47

AN47-3

APPLICATIONS SECTION I - AMPLIFIERSFast 12-Bit DAC Amplifier ........................................................................................................................... AN47-322-Channel Video Amplifier .......................................................................................................................... AN47-32Simple Video Amplifier ............................................................................................................................... AN47-32Loop Through Cable Receivers ................................................................................................................... AN47-32DC Stabilization – Summing Point Technique ............................................................................................ AN47-33DC Stabilization – Differentially Sensed Technique ..................................................................................... AN47-34DC Stabilization – Servo Controlled FET Input Stage .................................................................................. AN47-34DC Stabilization – Full Differential Inputs with Parallel Paths ..................................................................... AN47-35DC Stabilization – Full Differential Inputs, Gain-of-1000 with Parallel Paths............................................... AN47-35High Speed Differential Line Receiver......................................................................................................... AN47-37Transformer Coupled Amplifier .................................................................................................................. AN47-38Differential Comparator Amplifier with Adjustable Offset ............................................................................ AN47-39Differential Comparator Amplifier with Settable Automatic Limiting and Offset .......................................... AN47-40Photodiode Amplifier .................................................................................................................................. AN47-41Fast Photo Integrator .................................................................................................................................. AN47-41Fiber Optic Receiver ................................................................................................................................... AN47-4340MHz Fiber Optic Receiver with Adaptive Trigger ..................................................................................... AN47-4350MHz High Accuracy Analog Multiplier .................................................................................................... AN47-44Power Booster Stage .................................................................................................................................. AN47-45High Power Booster Stage ......................................................................................................................... AN47-47Ceramic Bandpass Filters ........................................................................................................................... AN47-48Crystal Filter ............................................................................................................................................... AN47-48

APPLICATIONS SECTION II - OSCILLATORSSine Wave Output Quartz Stabilized Oscillator............................................................................................ AN47-48Sine Wave Output Quartz Stabilized Oscillator with Electronic Gain Control ............................................... AN47-49DC Tuned 1MHz-10MHz Wien Bridge Oscillator ......................................................................................... AN47-49Complete AM Radio Station ....................................................................................................................... AN47-50

APPLICATIONS SECTION III - DATA CONVERSION1Hz-1MHz Voltage-Controlled Sine Wave Oscillator ................................................................................... AN47-511Hz-10MHz V → F Converter ..................................................................................................................... AN47-548-Bit, 100ns Sample-Hold .......................................................................................................................... AN47-5615ns Current Summing Comparator .......................................................................................................... AN47-5750MHz Adaptive Threshold Trigger Circuit ................................................................................................. AN47-58Fast Time-to-Height (Pulsewidth-to-Voltage) Converter ............................................................................. AN47-58True RMS Wideband Voltmeter .................................................................................................................. AN47-61

APPLICATIONS SECTION IV - MISCELLANEOUS CIRCUITSRF Leveling Loop ........................................................................................................................................ AN47-63Voltage Controlled Current Source ............................................................................................................. AN47-63High Power Voltage Controlled Current Source .......................................................................................... AN47-6318ns Circuit Breaker ................................................................................................................................... AN47-63

Application Note 47

AN47-4

REFERENCES.................................................................................................................................................. AN47-67

APPENDICESA. ABC’s of Probes – Contributed by Tektronix, Inc. ................................................................................. AN47-69B. Measuring Amplifier Settling Time ........................................................................................................ AN47-82C. The Oscillation Problem – Frequency Compensation Without Tears ..................................................... AN47-86D. Measuring Probe-Oscilloscope Response ............................................................................................. AN47-93E. An Ultra Fast High Impedance Probe .................................................................................................... AN47-96F. Additional Comments on Breadboarding ............................................................................................... AN47-98G. FCC Licensing and Construction Permit Applications for Commercial AM Broadcasting Stations ...... AN47-123H. About Current Mode Feedback ............................................................................................................ AN47-124I. High Frequency Amplifier Evaluation Board ........................................................................................ AN47-127J. The Contributions of Edsel Murphy to the Understanding of the Behavior of Inanimate Objects,

D.L. Klipstein (with permission of Cahners Publishing Co.) ................................................................ AN47-130

Application Note 47

AN47-5

INTRODUCTION

Most monolithic amplifiers have been relatively slowdevices. Wideband operation has been the province ofdiscrete and hybrid technologies. Some fast monolithicamplifiers have been available, but the exotic and expensiveprocessing required has inflated costs, precludingwidespread acceptance. Additionally, many of the previousmonolithic designs were incapable of high precision andprone to oscillation or untoward dynamics, making themunattractive.

Recent processing and design advances have made inex-pensive, precision wideband amplifiers practical. Figure 1lists some amplifiers, along with a summary of theircharacteristics. Reviewing this information reveals ex-traordinarily wideband devices, with surprisingly good DCcharacteristics. All of these amplifiers utilize standard opamp architecture, except the LT1223 and LT1228, whichare so-called current mode feedback types (see AppendixH, “About Current Mode Feedback”). It is clear that the rawspeed capabilities of these devices, combined with theirinherent flexibility as op amps, permit a wide range ofapplications. What is required of the user is a familiaritywith the devices and respect for the requirements of highspeed circuitry.

This effort’s initial sections are devoted to familiarizing thereader with the realities and difficulties of high speedcircuit work. The mechanics and subtleties of achievingprecision circuit operation at DC and low frequency havebeen well documented. Relatively little has appeared whichdiscusses, in practical terms, how to get fast circuitry towork. In developing such circuits, even veteran designerssometimes feel that nature is conspiring against them. Insome measure this is true. Like all engineering endeavors,high speed circuits can only work if negotiated compro-mises with nature are arranged. Ignorance of, or contemptfor, physical law is a direct route to frustration. MotherNature laughs at dilettantism and crushes arrogance with-out even knowing she did it. Even without Einstein’srevelations, the world of high speed is full of surprises.Working with events measured in nanoseconds requiresthe greatest caution, prudence and respect for MotherNature. Absolutely nothing should be taken for granted,because nothing is. Circuit design is very much the art ofcompromise with parasitic effects. The “hidden

schematic” (this descriptive was originated by CharlyGullett of Intel Corporation) usually dominates the circuit’sform, particularly at high speed.

In this regard, much of the text and appendices aredirected at developing awareness of, and respect for,circuit parasitics and fundamental limitations. This ap-proach is maintained in the applications section, where thenotion of negotiated compromises is expressed in termsof resistor values and compensation techniques. Many ofthe application circuits use the amplifier’s speed to im-prove on a standard circuit. Some utilize the speed toimplement a traditional function in a non-traditional way,with attendant advantages. A (very) few operate at or nearthe state-of-the-art for a given circuit type, regardless ofapproach. Substantial effort has been expended in devel-oping these examples and documenting their operation.The resultant level of detail is justified in the hope that it willbe catalytic. The circuits should stimulate new ideas to suitparticular needs, while demonstrating fast amplifiers’capabilities in an instructive manner.

PERSPECTIVES ON HIGH SPEED DESIGN

A substantial amount of design effort has made Figure 1’samplifiers relatively easy to use. They are less prone tooscillation and other vagaries than some much sloweramplifiers. Unfortunately, laws of physics dictate that thecircuit’s environment must be properly prepared. Theperformance limits of high speed circuitry are oftendetermined by parasitics such as stray capacitance, groundimpedance and layout. Some of these considerations arepresent in digital systems where designers are comfortabledescribing bit patterns, delays and memory access timesin terms of nanoseconds. Figure 2’s test circuit providesvaluable perspective on just how fast these amplifiers are.Here, the pulse generator (Trace A, Figure 3) drives a74S04 Schottky TTL inverter (Trace B), an LT1223 op ampconnected as an inverter (Trace C), and a 74HC04 highspeed CMOS inverter (Trace D). The LT1223 doesn’t faretoo badly. Its delay and fall times are about 2ns slower thanthe 74S04, but significantly faster than the 74HC04. Infact, the LT1223 has completely finished its transitionbefore the 74HC04 even begins to move! Linear circuitsoperating with this kind of speed make many engineersjustifiably wary. Nanosecond domain linear circuits arewidely associated with oscillations, mysterious shifts in

Application Note 47

AN47-6

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Application Note 47

AN47-7

LTAN47 • TA02

PULSEGENERATOR OUTPUT

74S04 OUTPUT

LT1223 OUTPUT

74HC04 OUTPUT

PULSEGENERATOR

1k

74S04

74HC04

+

–

50Ω

Z = 50ΩO

1k

LT1223

HORIZ = 2ns/DIV

D= 5V/DIV

LTAN47 • TA03

A = 5V/DIV(INVERTED)

B = 5V/DIV

C = 5V/DIV

Figure 3. The Amplifier (Trace C) is 3ns Slower than 74S Logic(Trace B), but 5ns Faster than High Speed HCMOS (Trace D)!

Figure 2. A Race Between the LT1223 Amplifier and Some FastLogic Inverters

circuit characteristics, unintended modes of operationand outright failure to function.

Other common problems include different measurementresults using various pieces of test equipment, inability tomake measurement connections to the circuit withoutinducing spurious responses, and dissimilar operationbetween two identical circuits. If the components used inthe circuit are good and the design is sound, all of theabove problems can usually be traced to failure to providea proper circuit environment. To learn how to do this

requires studying the causes of the aforementioneddifficulties.

The following segments, “Mr. Murphy’s Gallery of HighSpeed Amplifier Problems” and the “Tutorial Section”,address this. The “Problems” section alerts the reader totrouble areas, while the “Tutorial” highlights theory andtechniques which may be applied towards solving theproblems shown. The tutorials are arranged in roughly thesame order as the problems are presented.

MR. MURPHY’S GALLERY OF HIGH SPEEDAMPLIFIER PROBLEMS

It sometimes seems that Murphy’s Law dominates allphysical law. For a complete treatise on Murphy’s Law, seeAppendix J, “The Contributions of Edsel Murphy to theUnderstanding of the Behavior of Inanimate Objects”, byD.L. Klipstein. The law’s consequences weigh heavily inhigh speed design. As such, a number of examples aregiven in the following discussion. The average number ofphone calls we receive per month due to each “Murphy”example appears at the end of each figure caption.Problems can start even before power is applied to theamplifier. Figure 4 shows severe ringing on the pulseedges at the output of an unterminated pulse generatorcable. This is due to reflections and may be eliminated byterminating the cable. Always terminate the source in itscharacteristic impedance when looking into cable or longPC traces. Any path over 1 inch long is suspect.

HORIZ = 100ns/DIVLTAN47 • TA04

A = 1V/DIV

Figure 4. An Unterminated Pulse Generator Cable ProducesRinging Due to Reflections – 3

In Figure 5 the cable is terminated, but ripple and aberrationare still noticeable following the high speed edge transitions.In this instance the terminating resistor’s leads are lengthy(≈3/4”), preventing a high integrity wideband termination.

Application Note 47

AN47-8


A = 0.5V/DIV

Figure 5. Poor Quality Termination Resultsin Pulse Corner Aberrations – 1


A = 2V/DIV

Figure 7. Improper Probe Compensation Causes SeeminglyUnexplainable Amplitude Error – 12

Figure 6. Poor Probe Grounding Badly Corrupts theObserved Waveform – 53


A = 0.5V/DIV

The best termination for 50Ω cable is the BNC coaxial type.These devices should not simply be resistors in anenclosure. Good grade 50Ω terminators maintain truecoaxial form. They use a carefully designed 50Ω resistorwith significant effort devoted to connections to the actualresistive element. In particular, the largest possibleconnection surface area is utilized to minimize high speedlosses. While these type terminators are practical on thetest bench, they are rarely used as board level components.In general, the best termination resistors for PC board useare carbon or metal film types with the shortest possiblelead lengths. These resistor’s end-cap connections providebetter high speed characteristics than the rod-connectedcomposition types. Wirewound resistors, because of theirinherent and pronounced inductive characteristics, arecompletely unsuitable for high speed work. This includesso-called non-inductive types.

Another termination consideration is disposal of the cur-rent flowing through the terminator. The terminatingresistor’s grounded end should be placed so that the highspeed currents flowing from it do not disrupt circuitoperation. For example, it would be unwise to returnterminator current to ground near the grounded positiveinput of an inverting op amp. The high speed, high density(5V pulses through a 50Ω termination generates 100mAcurrent spikes) current flow could cause serious corrup-tion of the desired zero volt op amp reference. This isanother reason why, for bench testing, the coaxial BNCterminators are far preferable to discrete, breadboardmounted resistors. With BNC types in use the terminationcurrent returns directly to the source generator and neverflows in the breadboard. (For more information see theTutorial section.) Select terminations carefully and evalu-ate the effects of their placement in the test set-up.

Figure 6 shows an amplifier output which rings anddistorts badly after rapid movement. In this case, theprobe ground lead is too long. For general purpose work,most probes come with ground leads about 6 inches long.At low frequencies this is fine. At high speed, the longground lead looks inductive, causing the ringing shown.High quality probes are always supplied with some shortground straps to deal with this problem. Some come withvery short spring clips which fix directly to the probe tip tofacilitate a low impedance ground connection. For fastwork, the ground connection to the probe should notexceed 1 inch in length. (Probes are covered in the Tutorialsection; also see Appendix A, “ABC’s of Probes”, guestwritten by the engineering staff of Tektronix, Inc.). Keepthe probe ground connection as short as possible. Theideal probe ground connection is purely coaxial. This iswhy probes mated directly to board mounted coaxialconnectors give the best results.

In Figure 7 the probe is properly grounded, but a newproblem pops up. This photo shows an amplifier output

Application Note 47

AN47-9

HORIZ = 10ns/DIV

A = 0.5V/DIV

LTAN47 • TA09

B = 0.5V/DIV

Figure 9. Probes with Mismatched Delays Produce ApparentTime Skewing in the Display – 4

HORIZ = 5 s/DIVLTAN47 • TA10

A = 200mV/DIV

µ

Figure 10. Overdriven FET Probe Produces Excessive WaveformDistortion and Tailing. Saturation Effects can Also CauseDelayed Response – 1

excursion of 11V — quite a trick from an amplifier runningfrom ±5V rails. This is a commonly reported problem inhigh speed circuits and can be quite confusing. It is notdue to suspension of natural law, but is traceable to agrossly miscompensated or improperly selected oscillo-scope probe. Use probes which match your oscilloscope’sinput characteristics and compensate them properly. (Fordiscussions on probes, see Appendix A, “ABC’s of Probes”,guest written by the engineering staff of Tektronix, Inc.and the Tutorial section.) Figure 8 shows another probe-induced problem. Here the amplitude seems correct butthe amplifier appears slow with pronounced edge round-ing. In this case, the probe used is too heavily compen-sated or slow for the oscilloscope. Never use 1X or straightprobes. Their bandwidth is 20MHz or less and capacitiveloading is high. Check probe bandwidth to ensure it isadequate for the measurement. Similarly, use an oscillo-scope with adequate bandwidth.


A = 0.5V/DIV

Figure 8. Overcompensated or Slow Probes Make Edges LookToo Slow – 2

Mismatched probes account for the apparent excessiveamplifier delay in Figure 9. Delay of almost 12ns (Trace Ais the input, Trace B the output) is displayed for anamplifier specified at 6ns. Always keep in mind thatvarious types of probes have different signal transit delaytimes. At high sweep speeds, this effect shows up in multi-trace displays as time skewing between individual chan-nels. Using similar probes will eliminate this problem, butmeasurement requirements often dictate dissimilar probes.In such cases the differential delay should be measuredand then mentally factored in to reduce error when inter-preting the display. It is worth noting that active probes,

such as FET and current probes, have signal transit timesas long as 25ns. A fast 10X or 50Ω probe delay can beinside 3ns. Account for probe delays in interpreting oscil-loscope displays.

The difficulty shown in Figure 10 is a wildly distortedamplifier output. The output slews quickly, but the pulsetop and bottom recoveries have lengthy, tailing responses.Additionally, the amplifier output seems to clip well belowits nominal rated output swing. A common oversight isresponsible for these conditions. A FET probe monitorsthe amplifier output in this example. The probe’s com-mon-mode input range has been exceeded, causing it tooverload, clip and distort badly. When the pulse rises, theprobe is driven deeply into saturation, forcing internalcircuitry away from normal operating points. Under theseconditions the displayed pulse top is illegitimate. Whenthe output falls, the probe’s overload recovery is lengthyand uneven, causing the tailing. More subtle forms of FET

Application Note 47

AN47-10


A = 1mV/DIV

µ

Figure 13. Overdriven Oscilloscope Display Says More About theOscilloscope than the Circuit it’s Connected to – 6


A = 10mV/DIV

Figure 12. Poor Quality 10X Probe Introduces Tailing – 2

probe overdrive may show up as extended delays with noobvious signal distortion. Know your FET probe. Accountfor the delay of its active circuitry. Avoid saturation effectsdue to common-mode input limitations (typically ±1V).Use 10X and 100X attenuator heads when required.

Figure 11’s probe-caused problem results in amplifieroutput peaking and ringing. In other respects the displayis acceptable. This output peaking characteristic is causedby a second 10X probe connected to the amplifier’ssumming junction. Because the summing point is socentral to analyzing op amp operation, it is often moni-tored. At high speed the 10pF probe input capacitancecauses a significant lag in feedback action, forcing theamplifier to overshoot and hunt as it seeks the null point.Minimizing this effect calls for the lowest possible probeinput capacitance, mandating FET types or special passiveprobes. (Probes are covered in the Tutorial section; alsosee Appendix A, “ABC’s of Probes”, guest written by theengineering staff of Tektronix, Inc.). Account for theeffects of probe capacitance, which often dominates itsimpedance characteristics at high speeds. A standard10pF 10X probe forms a 10ns lag with a 1KΩ sourceresistance.


A = 0.5V/DIV

Figure 11. Effect of a 10X, 10pF ‘Scope Probe at theSumming Point – 2

A peaked, tailing response is Figure 12’s characteristic.The photo shows the final 40mV of a 2.5V amplifierexcursion. Instead of a sharp corner which settles cleanly,peaking occurs, followed by a lengthy tailing decay. Thiswaveform was recorded with an inexpensive off-brand10X probe. Such probes are often poorly designed, andconstructed from materials inappropriate for high speedwork. The selection and integration of materials forwideband probes is a specialized and difficult art. Sub-

stantial design effort is required to get good fidelity at highspeeds. Never use probes unless they are fully specifiedfor wideband operation. Obtain probes from a vendor youtrust.

Figure 13 shows the final movements of an amplifieroutput excursion. At only 1mV per division the objective isto view the settling residue to high resolution. This re-sponse is characterized by multiple time constants, non-linear slew recovery and tailing. Note also the high speedevent just before the waveform begins its negative goingtransition. What is actually being seen is the oscilloscoperecovering from excessive overdrive. Any observation thatrequires off-screen positioning of parts of the waveformshould be approached with the greatest caution. Oscillo-scopes vary widely in their response to overdrive, bringingdisplayed results into question. Complete treatment ofhigh resolution settling time measurements and oscillo-scope overload characteristics is given in the Tutorialsection, “About Oscilloscopes” and Appendix B “Measur-ing Amplifier Settling Time”. Approach all oscilloscope

Application Note 47

AN47-11


A = 1V/DIV

Figure 14. Instabilities Due to No Ground Plane Produce aDisplay Similar to a Poorly Grounded Probe – 62


A = 0.5V/DIV

Figure 16. An Unbypassed Amplifier Driving No Load isSurprisingly Stable...at the Moment – 49


A = 2V/DIV

Figure 15. Output of an Unbypassed Amplifier Driving a 100ΩLoad Without Bypass Capacitors – 58

measurements which require off-screen activity with cau-tion. Know your instrument’s capabilities and limitations.

Sharp eyed readers will observe that Figure 14 is a dupli-cate of Figure 6. Such lazy authorship is excusable be-cause almost precisely the same waveform results whenno ground plane is in use. A ground plane is formed byusing a continuous conductive plane over the surface ofthe circuit board. (The theory behind ground planes isdiscussed in the Tutorial section). The only breaks in thisplane are for the circuit’s necessary current paths. Theground plane serves two functions. Because it is flat (ACcurrents travel along the surface of a conductor) andcovers the entire area of the board, it provides a way toaccess a low inductance ground from anywhere on theboard. Also, it minimizes the effects of stray capacitancein the circuit by referring them to ground. This breaks uppotential unintended and harmful feedback paths. Alwaysuse a ground plane with high speed circuitry.

By far the most common error involves power supplybypassing. Bypassing is necessary to maintain low supplyimpedance. DC resistance and inductance in supply wiresand PC traces can quickly build up to unacceptable levels.This allows the supply line to move as internal currentlevels of the devices connected to it change. This willalmost always cause unruly operation. In addition, severaldevices connected to an unbypassed supply can “commu-nicate” through the finite supply impedances, causingerratic modes. Bypass capacitors furnish a simple way toeliminate this problem by providing a local reservoir ofenergy at the device. The bypass capacitor acts as anelectrical flywheel to keep supply impedance low at high

frequencies. The choice of what type of capacitors to usefor bypassing is a critical issue and should be approachedcarefully (see Tutorial, “About Bypass Capacitors”). Anunbypassed amplifier with a 100Ω load is shown in Figure15. The power supply the amplifier sees at its terminalshas high impedance at high frequency. This impedanceforms a voltage divider with the amplifier and its load,allowing the supply to move as internal conditions in thecomparator change. This causes local feedback and oscil-lation occurs. Always use bypass capacitors.In Figure 16 the 100Ω load is removed, and a pulse outputis displayed. The unbypassed amplifier responds surpris-ingly well, but overshoot and ringing dominate. Alwaysuse bypass capacitors.Figure 17’s settling is noticeably better, but some ringingremains. This response is typical of lossy bypass capaci-tors, or good ones placed too far away from the amplifier.Use good quality, low loss bypass capacitors, and placethem as close to the amplifier as possible.

Application Note 47

AN47-12


A = 10mV/DIV

Figure 19. A More Subtle Bypassing Problem. Not-Quite-Good-Enough Bypassing Causes a Few Millivolts of Peaking – 1

HORIZ = 100ns/DIV

A = 0.5V/DIV

LTAN47 • TA20

Figure 20. 2pF Stray Capacitance at the Summing PointIntroduces Peaking – 4

The problem shown in Figure 20, peaking on the leadingand trailing corners, is typical of poor layout practice (seeTutorial section on “Breadboarding Techniques”). Thisunity gain inverter suffers from excessive trace area at thesumming point. Only 2pF of stray capacitance caused thepeaking and ring shown. Minimize trace area and straycapacitance at critical nodes. Consider layout as an inte-gral part of the circuit and plan it accordingly.

Figure 21’s low level square wave output appears to sufferfrom some form of parasitic oscillation. In actuality, thedisturbance is typical of that caused by fast digital clockingor switching regulator originated noise getting into criticalcircuit nodes. Plan for parasitic radiative or conductivepaths and eliminate them with appropriate layout andshielding.

Figure 22 underscores the previous statement. This out-put was taken from a gain-of-ten inverter with 1kΩ input

The multiple time constant ringing in Figure 18 oftenindicates poor grade paralleled bypassing capacitors orexcessive trace length between the capacitors. Whileparalleling capacitors of different characteristics is a goodway to get wideband bypassing, it should be carefullyconsidered. Resonant interaction between the capacitorscan cause a waveform like this after a step.

This type response is often aggravated by heavy amplifierloading. When paralleling bypass capacitors, plan thelayout and breadboard with the units you plan to use inproduction.


A = 0.5V/DIV

Figure 17. Poor Quality Bypass Capacitor Allows SomeRinging – 28


A = 0.5V/DIV

Figure 18. Paralleled Bypass Capacitors Form a ResonantNetwork and Ring – 2

Figure 19 addresses a more subtle bypassing problem.The trace shows the last 40mV excursion of a 5V stepalmost settling cleanly in 300ns. The slight overshoot isdue to a loaded (500Ω) amplifier without quite enoughbypassing. Increasing the total supply bypassing from0.1µF to 1µF cured this problem. Use large value paral-leled bypass capacitors when very fast settling is required,particularly if the amplifier is heavily loaded or sees fastload steps.

Application Note 47

AN47-13

HORIZ = 10 s/DIV

A = 0.05V/DIV

LTAN47 • TA21

µ

Figure 21. Clock or Switching Regulator Noise Corrupts OutputDue to Poor Layout – 3


A = 200mV/DIV

Figure 22. Output of an X10 Amplifier with 1pF Coupling from theSumming Point to the Input. Careful Shielding of the InputResistor Will Eliminate the Peaked Edges and Ringing – 2

Figure 24. Excessive Capacitive Load Upsets theAmplifier – 165

HORIZ = 100ns/DIV

A = 0.1V/DIV

LTAN47 • TA23

Figure 23. Decompensated Amplifier Running at Too Lowa Gain – 22


A = 0.5V/DIV

µ

resistance. It shows severe peaking induced by only 1pF ofparasitic capacitance across the 1k resistor. The 50Ωterminated input source provides only 20mV of drive via adivider, but that’s more than enough to cause problems,even with only 1pF stray coupling. In this case the solutionwas a ground referred shield at a right angle to, andencircling, the 1kΩ resistor. Plan for parasitic radiativepaths and eliminate them with appropriate shielding.A decompensated amplifier running at too low a gainproduced Figure 23’s trace. The price for decompensatedamplifiers’ increased speed is restrictions on minimumallowable gain. Decompensated amplifiers are simply notstable below some (specified) minimum gain, and noamount of ignorance or wishing will change this. This is a

common applications oversight with these devices, al-though the amplifier never fails to remind the user. Observegain restrictions when using decompensated amplifiers.

Oscillation is also the problem in Figure 24, and it is due toexcessive capacitive loading (see Tutorial section on“Oscillation”). Capacitive loading to ground introduces lagin the feedback signal’s return to the input. If enough lagis introduced (e.g., a large capacitive load) the amplifiermay oscillate. Even if a capacitively loaded amplifier doesn’toscillate, it’s always a good idea to check its response withstep testing. It’s amazing how close to the edge of the cliffyou can get without falling off, except when you build10,000 production units. Avoid capacitive loading. If suchloading is necessary, check performance margins andisolate or buffer the load if necessary.

Figure 25 appears to contain one cycle of oscillation. Theoutput waveform initially responds, but abruptly reversesdirection, overshoots and then heads positive again. Some

Application Note 47

AN47-14


A = 1V/DIV

Figure 25. Input Common Mode Overdrive GeneratesOdd Outputs – 3


A = 5V/DIV

µ

B = 5V/DIV

Figure 26. Local Oscillations in a Booster Stage. Frequency isTypically High – 12


A = 0.5V/DIV

Figure 28. Excessive Source Impedance Gives Serene ButUndesired Response – 6

HORIZ = 1µs/DIVLTAN47 • TA27

A = 5V/DIV

B = 5V/DIV

Figure 27. Loop Oscillations in a Booster Stage. Note LowerFrequency than Local Oscillations in Previous Example – 28

overshoot again occurs, with a long tail and a small dipwell before a non-linear slew returns the waveform to zero.Ugly overshoot and tailing completes the cycle. This iscertainly strange behavior. What is going on here? Theinput pulse is responsible for all these anomalies. Itsamplitude takes the amplifier outside its common-modelimits, inducing the bizarre effects shown. Keep inputsinside specified common-mode limits at all times.

Figure 26 shows an oscillation laden output (Trace B)trying to unity gain invert the input (Trace A). The input’sform is distinguishable in the output, but corrupted withvery high frequency oscillation and overshoot. In this casethe amplifier includes a booster within its loop to provideincreased output current. The disturbances noted aretraceable to local instabilities within the booster circuit.(See Appendix C, “The Oscillation Problem — FrequencyCompensation Without Tears”). When using output boosterstages, insure they are inherently stable before placingthem inside an amplifier’s feedback loop. Wideband boosterstages are particularly prone to device level parasitic highfrequency oscillation.

Figure 27’s booster augmented unity gain inverting opamp also oscillates, but at a much lower frequency.Additionally, overshoot and non-linear recovery dominatethe waveform’s envelope. Unlike the previous example,this behavior is not due to local oscillations within thebooster stage. Instead, the booster is simply too slow tobe included in the op amp’s feedback loop. It introducesenough lag to force oscillation, even as it hopelessly triesto maintain loop closure. Insure booster stages are fastenough to maintain stability when placed in the amplifier’sfeedback loop.

The serene rise and fall of Figure 28’s pulse is a welcomerelief from the oscillatory screaming of the previous pho-tos. Unfortunately, such tranquilized behavior is simplytoo slow. This waveform, reminiscent of Figure 8’sbandlimited response, is due to excessive source imped-ance. The high source impedance combines with amplifierinput capacitance to band limit the input and the outputreflects this action. Minimize source impedance to levels

Application Note 47

AN47-15

Note 1: The ability to generate such a pulse proves useful for a variety of tasks,including testing terminators, cables, probes and oscilloscopes for response.The requirements for this pulse generator are surprisingly convenient andinexpensive. For a discussion and construction details see Appendix D“Measuring Probe - Oscilloscope Response”.

HORIZ = 200ps/DIV

A = 2V/DIV

LTAN47 • TA29

Figure 29. 350ps Rise and Fall Times are Preserved by a GoodQuality Termination

HORIZ = 500ps/DIV

A = 2V/DIV

LTAN47 • TA30

Figure 30. Poor Grade Termination Produces PronouncedRinging and Tailing in the GHz Range

which maintain desired bandwidth. Keep stray capaci-tance at inputs down.

TUTORIAL SECTION

An implied responsibility in raising the aforementionedissues is their solution or elimination. What good is all therabble-rousing without suggestions for fixes? It is in thisspirit that this tutorial section is presented. Theory, tech-niques, prejudice and just plain gossip are offered as toolswhich may help avoid or deal with difficulties. As previ-ously mentioned, the tutorials appear in roughly the sameorder as the problems were presented.

About Cables, Connectors and Terminations

Routing of high speed signals to and from the circuit boardshould always be done with good quality coaxial cable. Thecable should be driven and terminated in the system’scharacteristic impedance at the drive and load points. Thedriven end is usually an instrument (e.g., pulse or signalgenerator), presumably endowed with proper characteris-tics by its manufacturer. It is the cable and its termination,selected by the experimenter, that often cause problems.

All coaxial cable is not the same. Use cable appropriate tothe system’s characteristic impedance and of good qual-ity. Poorly chosen cable materials or construction meth-ods can introduce odd effects at very high speeds, result-ing in observed waveform distortion. A poor cable choicecan adversely effect 0.01% settling in the 100ns-200nsregion. Similarly, poor cable can preclude maintenance ofeven the cleanest pulse generator’s 1ns rise time or purity.Typically, inappropriate cable can introduce tailing, risetime degradation, aberrations following transitions, non-linear impedance and other undesirable characteristics.

Termination choice is equally important. Good qualityBNC coaxial type terminators are usually the best choicefor breadboarding. Their impedance vs frequency is flatinto the GHz range. Additionally, their construction insuresthat the (often substantial) drive current returns directly tothe source, instead of being dumped into the breadboard’s

ground system. As previously discussed, BNC coaxialterminators are not simply resistors in a can. Specialconstruction techniques insure optimum widebandresponse. Figures 29 and 30 demonstrate this nicely. InFigure 29 a 1ns pulse with 350ps rise and fall times1 ismonitored on a 1GHz sampling ‘scope (Tektronix 556 with1S1 sampling plug-in and P6032 probe). The waveform isclean, with only a slight hint of ring after the falling edge.This photo was taken with a high grade BNC coaxial typeterminator in use. Figure 30 does not share these attributes.Here, the generator is terminated with a 50Ω carboncomposition resistor with lead lengths of about 1/8 inch.The waveform rings and tails badly on turn-off beforefinally settling. Note that the sweep speed required a 2.5Xreduction to capture these unwanted events.

Application Note 47

AN47-16

Note 2: Almost no one believes any of this until they see it for themselves. Ididn’t. Photos of the network analyzer’s display aren’t included in the textbecause no one would believe them. I wouldn’t.

Connectors, such as BNC barrel extensions and tee-typeadaptors, are convenient and frequently employed. Re-member that these devices represent a discontinuity in thecable, and can introduce small but undesirable effects. Ingeneral it is best to employ them as close as possible to aterminated point in the system. Use in the middle of a cablerun provides minimal absorption of their mismatch andreflections. The worst offenders among connectors areadapters. This is unfortunate, as these devices are neces-sitated by the lack of connection standardization inwideband instrumentation. The mismatch caused by aBNC-to-GR874 adaptor transition at the input of a widebandsampling ‘scope is small, but clearly discernible in thedisplay. Similarly, mismatches in almost all adaptors, andeven in “identical” adaptors of different manufacture, arereadily measured on a high-frequency network analyzersuch as the Hewlett-Packard 4195A2 (for additional wis-dom and terror along these lines see Reference 1).

BNC connections are easily the most common, but notnecessarily the most desirable, wideband connectionmechanism. The ingenious GR874 connector has notablysuperior high frequency characteristics, as does the typeN. Unfortunately, it’s a BNC world out there.

About Probes and Probing Techniques

The choice of which oscilloscope probe to use in a mea-surement is absolutely crucial. The probe must be consid-ered as an inherent part of the circuit under test. Rise time,bandwidth, resistive and capacitive loading, delay andother limitations must be kept in mind.

Sometimes, the best probe is no probe at all. In somecircumstances it is possible and preferable to connectcritical breadboard points directly to the oscilloscope (seeFigure 31). This arrangement provides the highest pos-sible grounding integrity, eliminates probe attenuation,and maintains bandwidth. In most cases this is mechani-cally inconvenient, and often the oscilloscope’s electricalcharacteristics (particularly input capacitance) will notpermit it. This is why oscilloscope probes were developed,and why so much effort has been put into their develop-ment (Reference 42 is excellent). In addition to the mate-

rial presented here, an in-depth treatment of probes ap-pears in Appendix A, “ABC’s of Probes”, guest written bythe engineering staff of Tektronix, Inc.

Probes are the most overlooked cause of oscilloscopemismeasurement. All probes have some effect on thepoint they are measuring. The most obvious is inputresistance, but input capacitance usually dominates in ahigh speed measurement. Much time can be lost chasingcircuit events which are actually due to improperly se-lected or applied probes. An 8pF probe looking at a 1kΩsource impedance forms an 8ns lag — substantiallylonger than a fast amplifier’s delay time! Pay particularattention to the probe’s input capacitance. Standard 10MΩ,10X probes typically have 8pF-10pF of input capacitance,with 1X types being much higher. In general, 1X probesare not suitable for fast work because their bandwidth islimited to about 20MHz. Remember that all 10X probescannot be used with all oscilloscopes; the probe’s com-pensation range must match the oscilloscope’s inputcapacitance. Low impedance probes (with 500Ω to 1kΩresistance), designed for 50Ω inputs, usually have inputcapacitance of 1pF or 2pF. They are a very good choice ifyou can stand the low resistance. FET probes maintainhigh input resistance and keep capacitance at the 1pF levelbut have substantially more delay than passive probes.FET probes also have limitations on input common-moderange which must be adhered to or serious measurementerrors will result. Contrary to popular belief, FET probes donot have extremely high input resistance — some typesare as low as 100kΩ. It is possible to construct a widebandFET probe with very high input impedance, although inputcapacitance is somewhat higher than standard FET probes.For measurements requiring these characteristics, such aprobe is useful. See Appendix E, “An Ultra Fast HighImpedance Probe”.

Regardless of which type probe is selected remember thatthey all have bandwidth and rise time restrictions. Thedisplayed rise time on the oscilloscope is the vector sumof source, probe and ‘scope rise times.

tRISE = √(tRISE Source)2 + (tRISE Probe)2 + (tRISE Oscilloscope)2

This equation warns that some rise time degradation mustoccur in a cascaded system. In particular, if probe andoscilloscope are rated at the same rise time, the systemresponse will be slower than either.

Application Note 47

AN47-17

LTAN47 • TA31

Note 3: A more thorough discussion of current probes is given in LTCApplication Note 35, “Step Down Switching Regulators”. See Reference 2.

Figure 31. Sometimes the Best Probe is No Probe. Direct Connection to the Oscilloscope Eliminates a 10X Probe’s Attenuation andPossible Grounding Problems in a Sample-Hold (Figure 124) Settling Time Measurement

Current probes are useful and convenient.3 The passivetransformer-based types are fast and have less delay thanthe Hall effect-based versions. The Hall types, however,respond at DC and low frequency and the transformertypes typically roll off around 100Hz to 1kHz. Both typeshave saturation limitations which, when exceeded, causeodd results on the CRT which will confuse the unwary. TheTektronix type CT-1 current probe, although not nearly asversatile as the clip-on probes, bears mention. Althoughthis is not a clip-on device, it may be the least electricallyintrusive way of extracting wideband signal information.Rated at 1GHz bandwidth, it produces 5mV/mA outputwith only 0.6pF loading. Decay time constant of this ACcurrent probe is ≈1%/50ns, resulting in a low frequencylimit of 35kHz.

A very special probe is the differential probe. A differentialprobe may be thought of as two matched FET probescontained within a common probe housing. This probeliterally brings the advantage of a differential input oscillo-scope to the circuit board. The probes matched, activecircuitry provides greatly improved high frequency com-mon mode rejection over single ended probing or evenmatched passive probes used with a differential amplifier.The resultant ability to reject common-mode signals andground noise at high frequency allows this probe to deliverexceptionally clean results when monitoring small, fastsignals. Figure 32 shows a differential probe being used toverify the waveshape of a 2.5mV input to a wideband, highgain amplifier (Figure 76 of the Applications section).

When using different probes, remember that they all havedifferent delay times, meaning that apparent timing errors

Application Note 47

AN47-18

LTAN47 • TA32

Figure 32. Using a Differential Probe to Verify the Integrity of a 2.5mV High Speed Input Pulse (Figure 76's X1000 Amplifier)

will occur on the CRT. Know what the individual probedelays are and account for them in interpreting the CRTdisplay.

By far the greatest source of error in probe use is grounding.Poor probe grounding can cause ripples and discontinuitiesin the waveform observed. In some cases the choice andplacement of a probe’s ground strap will affect waveformson another channel. In the worst case, connecting theprobe’s ground wire will virtually disable the circuit beingmeasured. The cause of these problems is due to parasiticinductance in the probe’s ground connection. In mostoscilloscope measurements this is not a problem, but atnanosecond speeds it becomes critical. Fast probes arealways supplied with a variety of spring clips andaccessories designed to aid in making the lowest possibleinductive connection to ground. Most of these attachments

assume a ground plane is in use, which it should be.Always try to make the shortest possible connection toground – anything longer than 1 inch may cause trouble.Sometimes it’s difficult to determine if probe grounding isthe cause of observed waveform aberrations. One goodtest is to disturb the grounding set-up and see if changesoccur. Nominally, touching the ground plane or jigglingprobe ground connectors or wires should have no effect.If a ground strap wire is in use try changing its orientationor simply squeezing it together to change and minimize itsloop area. If any waveform change occurs while doing thisthe probe grounding is unacceptable, rendering theoscilloscope display unreliable.

The simple network of Figure 33 shows just how easy itis for poorly chosen or used probes to cause bad results.A 9pF input capacitance probe with a 4 inch long ground

Application Note 47

AN47-19

A final form of probe is the human finger. Probing thecircuit with a finger can accentuate desired or undesiredeffects, giving clues that may be useful. The finger can beused to introduce stray capacitance to a suspected circuitnode while observing results on the CRT. Two fingers,lightly moistened, can be used to provide an experimentalresistance path. Some high speed engineers are particu-larly adept at these techniques and can estimate thecapacitive and resistive effects created with surprisingaccuracy.

Examples of some of the probes discussed, along withdifferent forms of grounding implements, are shown inFigure 37. Probes A, B, E, and F are standard typesequipped with various forms of low impedance groundingattachments. The conventional ground lead used on G ismore convenient to work with but will cause ringing and

Figure 36. Test Circuit Output with FET Probe

Figure 37. Various Probe-Ground Strap Configurations

strap monitors the output (Trace B, Figure 34). Althoughthe input (Trace A) is clean, the output contains ringing.Using the same probe with a 1/4 inch spring tip groundconnection accessory seemingly cleans up everything(Figure 35). However, substituting a 1pf FET probe (Fig-ure 36) reveals a 50% output amplitude error in Figure35! The FET probe’s low input capacitance allows a moreaccurate version of circuit action. The FET probe does,however, contribute its own form of error. Note that theprobe’s response is tardy by 5ns due to delay in its activecircuitry. Hence, separate measurements with each probeare required to determine the output’s amplitude andtiming parameters.

Figure 35. Test Circuit Output with 9pF Probe and 0.25 InchGround Strap

Figure 34. Test Circuit Output with 9pF Probe and 4 InchGround Strap

Figure 33. Probe Test Circuit

LTAN47 • TA34

A = 5V/DIV

B = 1V/DIV

HORIZ = 10ns/DIV

LTAN47 • TA35

A = 5V/DIV

B = 1V/DIV

HORIZ = 10ns/DIV

LTAN47 • TA36

A = 5V/DIV

B = 1V/DIV

HORIZ = 10ns/DIV

OUTPUTPULSE INPUT

10pF

50Ω 1k

AN47 F33

A B C D E F

J I H GLTAN47 • TA37

Application Note 47

AN47-20

Note 4: In particular, the marine chronometer received ferocious and abundantamounts of attention. See References 4, 5, and 6. For an enjoyable strollthrough the history of oscilloscope vertical amplifiers, see Reference 3. Seealso Reference 41.Note 5: See Appendix D, “Measuring Probe - Oscilloscope Response”, forcomplete details on this pulse generator.Note 6: This sequence of photos was shot in my home lab. I’m sorry, but 1GHzis the fastest ‘scope in my house.

other effects at high frequencies, rendering it useless. Hhas a very short ground lead. This is better, but can stillcause trouble at high speeds. D is a FET probe. The activecircuitry in the probe and a very short ground connectorensure low parasitic capacitance and inductance. C is aseparated FET probe attenuator head. Such heads allowthe probe to be used at higher voltage levels (e.g., ±10V or±100V). The miniature coaxial connector shown can bemounted on the circuit board and the probe mated with it.This technique provides the lowest possible parasiticinductance in the ground path and is especially recom-mended. I is a current probe. A ground connection is notusually required. However, at high speeds the groundconnection may result in a cleaner CRT presentation.Because no current flows in the ground lead of theseprobes, a long strap is usually permissible. J is typical ofthe finger probes described in the text. Note the groundstrap on the third finger.

The low inductance ground connectors shown are avail-able from probe manufacturers and are always suppliedwith good quality, high frequency probes. Because mostoscilloscope measurements do not require them, theyinvariably become lost. There is no substitute for thesedevices when they are needed, so it is prudent to take careof them. This is especially applicable to the ground strapon the finger probe.

About Oscilloscopes

The modern oscilloscope is one of the most remarkableinstruments ever constructed. The protracted and intensedevelopment effort put toward these machines is perhapsequaled only by the fanaticism devoted to timekeeping.4 Itis a tribute to oscilloscope designers that instrumentsmanufactured over 25 years ago still suffice for over 90%of today’s measurements. The oscilloscope-probe combi-nation used in high speed work is the most importantequipment decision the designer must make. Ideally, theoscilloscope should have at least 150MHz bandwidth, but

slower instruments are acceptable if their limitations arewell understood. Be certain of the characteristics of theprobe-oscilloscope combination. Rise time, bandwidth,resistive and capacitive loading, delay, noise, channel-to-channel feedthrough, overdrive recovery, sweep nonlin-earity, triggering, accuracy and other limitations must bekept in mind. High speed linear circuitry demands a greatdeal from test equipment and countless hours can besaved if the characteristics of the instruments used arewell known. Obscene amounts of time have been lostpursuing “circuit problems” which in reality are caused bymisunderstood, misapplied or out-of-spec equipment.Intimate familiarity with your oscilloscope is invaluable ingetting the best possible results with it. In fact, it ispossible to use seemingly inadequate equipment to getgood results if the equipment’s limitations are well knownand respected. All of the circuits in the Applicationssection involve rise times and delays well above the100MHz-200MHz region, but 90% of the developmentwork was done with a 50MHz oscilloscope. Familiaritywith equipment and thoughtful measurement techniquepermit useful measurements seemingly beyond instru-ment specifications. A 50MHz oscilloscope cannot track a5ns rise time pulse, but it can measure a 2ns delaybetween two such events. Using such techniques, it isoften possible to deduce the desired information. Thereare situations where no amount of cleverness will workand the right equipment (e.g., a faster oscilloscope) mustbe used. Sometimes, “sanity-checking” a limited band-width instrument with a higher bandwidth oscilloscope isall that is required. For high speed work, brute forcebandwidth is indispensable when needed, and no amountof features or computational sophistication will substitute.Most high speed circuitry does not require more than twotraces to get where you are going. Versatility and manychannels are desirable, but if the budget is limited, spendfor bandwidth!

Dramatic differences in displayed results are produced byprobe-oscilloscope combinations of varying bandwidths.Figure 38 shows the output of a very fast pulse5 monitoredwith a 1GHz sampling ‘scope (Tektronix 556 with 1S1sampling plug-in). At this bandwidth the 10V amplitudeappears clean, with just a small hint of ringing after thefalling edge. The rise and fall times of 350ps are suspi-cious, as the sampling oscilloscope’s rise time is alsospecified at 350ps.6

Application Note 47

AN47-21

HORIZ = 200ps/DIV

VERT = 2V/DIV

LTAN47 • TA38

Figure 38. A 350ps Rise/Fall Time 10V Pulse Monitored on 1GHzSampling Oscilloscope. Direct 50Ω Input Connection is Used


VERT = 2V/DIV

Figure 39. The Test Pulse Appears Smaller and Slower On a350MHz Instrument (tRISE = 1ns). Deliberate Poor GroundingCreates Rippling After the Pulse Falls. Direct 50Ω Connectionis Used


VERT = 2V/DIV

Figure 40. Test Pulse on the Same 350MHz Oscilloscope Using a3GHz 10X Probe. Deliberate Poor Grounding MaintainsRippling Residue


VERT = 2V/DIV

Figure 41. Test Pulse Measures Only 3V High on a 250MHz‘Scope with Significant Waveform Distortion. 250MHz 10XProbe Used

Figure 39 shows the same pulse observed on a 350MHzinstrument with a direct connection to the input (Tektronix485/50Ω input). Indicated rise time balloons to 1ns, whiledisplayed amplitude shrinks to 6V, reflecting thisinstrument’s lesser bandwidth. To underscore earlier dis-cussion, poor grounding technique (1 1/2” of ground leadto the ground plane) created the prolonged rippling afterthe pulse fall.

Figure 40 shows the same 350MHz (50Ω input) oscillo-scope with a 3GHz 10X probe (Tektronix P6056). Dis-played results are nearly identical, as the probe’s highbandwidth contributes no degradation. Again, deliberatepoor grounding causes overshoot and rippling on thepulse fall.

Figure 41 equips the same oscilloscope with a 10X probespecified at 290MHz bandwidth (Tektronix P6047). Addi-tionally, the oscilloscope has been switched to its 1MΩinput mode, reducing bandwidth to a specified 250MHz.Amplitude degrades to less than 4V and edge timessimilarly increase. The deliberate poor grounding contrib-utes the undershoot and underdamped recovery on pulsefall.

In Figure 42 a 100MHz 10X probe (Hewlett-Packard Model10040A) has been substituted for the 290MHz unit. Theoscilloscope and its set-up remain the same. Amplitudeshrinks below 2V, with commensurate rise and fall times.Cleaned up grounding eliminates aberrations.

Application Note 47

AN47-22

Figure 42. Test Pulse Measures Under 2V High Using 250MHz‘Scope and a 100MHz Probe


VERT = 2V/DIV


VERT = 2V/DIV

Figure 43. 150MHz Oscilloscope (tRISE = 2.4ns) with DirectConnection Responds to the Test Pulse

HORIZ = 10ns/DIV

VERT = 2V/DIV

LTAN47 • TA44

Figure 44. A 50MHz Instrument Barely Grunts. 10V, 350ps TestPulse Measures Only 0.5V High with 7ns Rise and Fall Times!

A Tektronix 454A (150MHz) produced Figure 43’s trace.The pulse generator was directly connected to the input.Displayed amplitude is about 2V, with appropriate 2nsedges. Finally, a 50MHz instrument (Tektronix 556 with1A4 plug-in) just barely grunts in response to the pulse(Figure 44). Indicated amplitude is 0.5V, with edges read-ing about 7ns. That’s a long way from the 10V and 350psthat’s really there!

A final oscilloscope characteristic is overload perfor-mance. It is often desirable to view a small amplitudeportion of a large waveform. In many cases the oscillo-scope is required to supply an accurate waveform after thedisplay has been driven off screen. How long must onewait after an overload before the display can be takenseriously? The answer to this question is quite complex.Factors involved include the degree of overload, its dutycycle, its magnitude in time and amplitude, and otherconsiderations. Oscilloscope response to overload varieswidely between types and markedly different behavior canbe observed in any individual instrument. For example, therecovery time for a 100X overload at 0.005V/division maybe very different than at 0.1V/division. The recovery char-acteristic may also vary with waveform shape, DC contentand repetition rate. With so many variables, it is clear thatmeasurements involving oscilloscope overload must beapproached with caution. Nevertheless, a simple test canindicate when the oscilloscope is being deleteriously af-fected by overdrive.

The waveform to be expanded is placed on the screen at avertical sensitivity which eliminates all off-screen activity.Figure 45 shows the display. The lower right hand portionis to be expanded. Increasing the vertical sensitivity by afactor of two (Figure 46) drives the waveform off-screen,but the remaining display appears reasonable. Amplitudehas doubled and waveshape is consistent with the originaldisplay. Looking carefully, it is possible to see smallamplitude information presented as a dip in the waveformat about the third vertical division. Some small disturb-ances are also visible. This observed expansion of theoriginal waveform is believable. In Figure 47, gain hasbeen further increased and all the features of Figure 46 areamplified accordingly. The basic waveshape appears clearerand the dip and small disturbances are also easier to see.No new waveform characteristics are observed. Figure 48brings some unpleasant surprises. This increase in gain

Application Note 47

AN47-23

Figure 47 Figure 50LTAN47 • TA47

100ns/DIV

0.2V/DIV

LTAN47 • TA50

100ns/DIV

0.1V/DIV

Figures 45-50. The Overdrive Limit is Determined by Progressively Increasing Oscilloscope Gain and Watchingfor Waveform Aberrations

Figure 46LTAN47 • TA46

100ns/DIV

0.5V/DIV

Figure 49 LTAN47 • TA49

100ns/DIV

0.1V/DIV


100ns/DIV

0.1V/DIV


1V/DIV

100ns/DIV

causes definite distortion. The initial negative-going peak,although larger, has a different shape. Its bottom appearsless broad than in Figure 47. Additionally, the peak’spositive recovery is shaped slightly differently. A newrippling disturbance is visible in the center of the screen.This kind of change indicates that the oscilloscope ishaving trouble. A further test can confirm that this wave-form is being influenced by overloading. In Figure 49 thegain remains the same, but the vertical position knob has

been used to reposition the display at the screen’s bottom.This shifts the oscilloscope’s DC operating point which,under normal circumstances, should not affect the dis-played waveform. Instead, a marked shift in waveformamplitude and outline occurs. Repositioning the wave-form to the screen’s top produces a differently distortedwaveform (Figure 50). It is obvious that for this particularwaveform, accurate results cannot be obtained at thisgain.

Application Note 47

AN47-24

Note 7: Additional discourse on oscilloscopes will be found in References 1and 7 through 11.

FIELD RADII

Figure 51. Single Wire Case

Figure 52. Two Wire Case

I

I

I

D

Differential plug-ins can address some of the issuesassociated with excessive overdrive, although they cannotsolve all problems. Two differential plug-in types meritspecial mention. At low level, a high sensitivity differentialplug-in is indispensable. The Tektronix 1A7, 1A7A and7A22 feature 10µV sensitivity, although bandwidth islimited to 1MHz. The units also have selectable high andlow pass filters and good high frequency common-moderejection. Tektronix type 1A5, W and 7A13 are differentialcomparators. They have calibrated DC nulling (slideback)sources, allowing observation of small, slowly movingevents on top of common-mode DC or fast events ridingon a waveform.

A special case is the sampling oscilloscope. By nature ofits operation, a sampling ‘scope in proper working orderis inherently immune to input overload, providing essen-tially instantaneous recovery between samples. AppendixB, “Measuring Amplifier Settling Time”, utilizes this capa-bility. See Reference 8 for additional details.

The best approach to measuring small portions of largewaveforms, however, is to eliminate the large signal swingseen by the oscilloscope. Appendix B, “Measuring Ampli-fier Settling Time” shows ways to do this when measuringDAC-amplifier settling time to very high accuracy at highspeed.

In summary, while the oscilloscope provides remarkablecapability, its limitations must be well understood wheninterpreting results.7

About Ground Planes

Many times in high frequency circuit layout, the term“ground plane” is used, most often as a mystical and ill-defined cure to spurious circuit operation. In fact, there islittle mystery to the usefulness and operation of groundplanes, and like many phenomena, their fundamentaloperating principle is surprisingly simple.

Ground planes are primarily useful for minimizing circuitinductance. They do this by utilizing basic magnetic theory.Current flowing in a wire produces an associated magneticfield. The field’s strength is proportional to the current andinversely related to the distance from the conductor. Thus,

we can visualize a wire carrying current (Figure 51) sur-rounded by radii of magnetic field. The unbounded fieldbecomes smaller with distance. A wire’s inductance isdefined as the energy stored in the field set up by the wire’scurrent. To compute the wire’s inductance requires inte-grating the field over the wire’s length and the total radialarea of the field. This implies integrating on the radius fromR = RW to infinity, a very large number. However, considerthe case where we have two wires in space carrying thesame current in either direction (Figure 52). The fieldsproduced cancel.

In this case, the inductance is much smaller than in thesimple wire case and can be made arbitrarily smaller byreducing the distance between the two wires. This reduc-tion of inductance between current carrying conductors isthe underlying reason for ground planes. In a normalcircuit, the current path from the signal source through itsconductor and back to ground includes a large loop area.This produces a large inductance for this conductor whichcan cause ringing due to LRC effects. It is worth noting that10nH at 100MHz has an impedance of 6Ω. At 10mA a60mV drop results.

A ground plane provides a return path directly under thesignal carrying conductor through which return currentcan flow. The conductor’s small physical separation meansthe inductance is low. Return current has a direct path toground, regardless of the number of branches associatedwith the conductor. Currents will always flow through thereturn path of lowest impedance. In a properly designed

Application Note 47

AN47-25

–

+DAC

R2

R3

R L L R

LEAKAGE

CAPACITOR USERTERMINALS

DIELECTRICABSORPTIONTERMS

AN47 F53/54

C1

D1

Figure 53. Typical Grounding Scheme Figure 54. Parasitic Terms of a Capacitor

D2 LT1016

R1

6

+V VIN

1

2 3

4 5

∞

VREF

ground plane, this path is directly under the signal conduc-tor. In a practical circuit, it is desirable to ground plane onewhole side of the PC card (usually the component side forwave solder considerations) and run the signal conduc-tors on the other side. This will give a low inductance pathfor all the return currents.

Aside from minimizing parasitic inductance, ground planeshave additional benefits. Their flat surface minimizesresistive losses due to AC skin effect (AC currents travelalong a conductor’s surface). Additionally, they aid thecircuit’s high frequency stability by referring stray capaci-tances to ground.

Some practical hints for ground planes are:

1. Ground plane as much area as possible on the compo-nent side of the board, especially under traces thatoperate at high frequency.

2. Mount components that conduct substantial fast risecurrents (termination resistors, ICs, transistors,decoupling capacitors) as close to the board as possible.

3. Where common ground potential is important (i.e., atcomparator inputs), try to single point the criticalcomponents into the ground plane to avoid voltagedrops.

For example, in Figure 53’s common A/D circuit, goodpractice would dictate that grounds 2, 3, 4 and 6 be asclose to single point as possible. Fast, large currentsmust flow through R1, R2, D1 and D2 during the DACsettle time. Therefore, D1, D2, R1 and R2 should bemounted close to the ground plane to minimize theirinductance. R3 and C1 don’t carry any current, so theirinductance is less important; they could be vertically

inserted to save space and to allow point 4 to be singlepoint common with 2, 3 and 6. In critical circuits, thedesigner must often trade off the beneficial effects oflowered inductance versus the loss of single pointground.

4. Keep trace length short. Inductance varies directly withlength and no ground plane will achieve perfectcancellation.

About Bypass Capacitors

Bypass capacitors are used to maintain low power supplyimpedance at the point of load. Parasitic resistance andinductance in supply lines mean that the power supplyimpedance can be quite high. As frequency goes up, theinductive parasitic becomes particularly troublesome. Evenif these parasitic terms did not exist, or if local regulationis used, bypassing is still necessary because no powersupply or regulator has zero output impedance at 100MHz.What type of bypass capacitor to use is determined by theapplication, frequency domain of the circuit, cost, boardspace and many other considerations. Some useful gen-eralizations can be made.

All capacitors contain parasitic terms, some of whichappear in Figure 54. In bypass applications, leakage anddielectric absorption are second order terms but series Rand L are not. These latter terms limit the capacitor’s abilityto damp transients and maintain low supply impedance.Bypass capacitors must often be large values so they canabsorb long transients, necessitating electrolytic typeswhich have large series R and L.

Application Note 47

AN47-26

Different types of electrolytics and electrolytic-non-polarcombinations have markedly different characteristics.Which type(s) to use is a matter of passionate debate insome circles and the test circuit (Figure 55) and accom-panying photos are useful. The photos show the responseof 5 bypassing methods to the transient generated by thetest circuit. Figure 56 shows an unbypassed line whichsags and ripples badly at large amplitudes. Figure 57 usesan aluminum 10µF electrolytic to considerably cut thedisturbance, but there is still plenty of potential trouble. Atantalum 10µF unit offers cleaner response in Figure 58and the 10µF aluminum combined with a 0.01µF ceramictype is even better in Figure 59. Combining electrolyticswith non-polarized capacitors is a popular way to getgood response but beware of picking the wrong duo. Theright (wrong) combination of supply line parasitics andparalleled dissimilar capacitors can produce a resonant,ringing response, as in Figure 60. Caveat!

Breadboarding Techniques

The breadboard is both the designer’s playground andproving ground. It is there that Reality resides, and paper(or computer) designs meet their ruler. More than any-thing else, breadboarding is an iterative procedure, an oddamalgam of experience guiding an innocent, ignorant,

LTAN47 • TA57

HORIZ = 100ns/DIV

A = 5V/DIV

B = 0.1V/DIV

Figure 57. Response of 10µF Aluminum Capacitor

LTAN47 • TA58

HORIZ = 100ns/DIV

A = 5V/DIV

B = 0.1V/DIV

Figure 58. Response of 10µF Tantalum Capacitor

LTAN47 • TA59

HORIZ = 100ns/DIV

A = 5V/DIV

B = 0.1V/DIV

Figure 59. Response of 10µF Aluminum Paralleledby 0.01µF Ceramic

LTAN47 • TA60

HORIZ = 100ns/DIV

A = 5V/DIV

B = 0.1V/DIV

Figure 60. Some Paralleled Combinations can Ring.Try before Specifying!

LTAN47 • TA55

560Ω

50Ω

100ΩCARBON

50ΩCARBON

TESTBYPASS

“A” WAVEFORM +5V “B” WAVEFORM

± 2.5VFROM PULSE GENERATOR

2N2369OV

Figure 55. Bypass Capacitor Test Circuit

LTAN47 • TA56

HORIZ = 100ns/DIV

A = 5V/DIV

B = 1V/DIV

Figure 56. Response of Unbypassed Line

Application Note 47

AN47-27

Figure 61. The Stabilized FET Input Amplifier (Applications Figure 73) to be Breadboarded

Note 8: A much more eloquently stated version of this approach is found inReference 12.

+

–

LTAN47 • TA61

900

1000.1

10k

A1LT1223

Ω

Ω10M

0.01

3k

10M

300pF

+

–

A2LT1097

–15V

330Ω

Q22N3904

Q12N5486

+15V

INPUT

OUTPUT

0.1

explorative spirit. A key is to be willing to try things out,sometimes for not very good reasons. Invent problemsand solutions, guess carefully and wildly, throw rocks andsee what comes loose. Invent and design experiments,and follow them wherever they lead. Reticence to trythings is probably the number one cause of breadboardsthat “don’t work”.8 Implementing the above approach tolife begins with the physical construction methods used tobuild the breadboard.

A high speed breadboard must start with a ground plane.Additionally, bypassing, component layout and connec-tions should be consistent with high speed operations.Because of these considerations there is a common mis-conception that breadboarding high speed circuits is timeconsuming and difficult. This is simply not true. For highspeed circuits of moderate complexity a complete andelectrically correct breadboard can be assembled in 10minutes if all necessary components are on hand. The keyto rapid breadboarding is to identify critical circuit nodesand design the layout to suit them. This permits most ofthe breadboard’s construction to be fairly sloppy, savingtime and effort. Additionally, use all degrees of freedom inmaking connections and mounting components. Don’t bebashful about bending I.C. pins to suit desired low capaci-tance connections, or air wiring components to achieverapid or electrically optimum layout. Save time by usingcomponents, such as bypass capacitors, as mechanical

supports for other components, such as amplifiers. It istrue that eventual printed circuit construction is required,but when initially breadboarding forget about PC andproduction constraints. Later, when the circuit works, andis well understood, PC adaptations can be taken care of.

Figure 61’s amplifier circuit is a good working example.This circuit, excerpted from the Applications section (whereits electrical operation is more fully explained) is a highimpedance, wideband amplifier with low input capaci-tance. Q1 and A1 form the high frequency path, with the900Ω-100Ω feedback divider setting gain. A2 and Q2close a DC stabilization loop, minimizing DC offset be-tween the circuit’s input and output. Critical nodes in thiscircuit include Q1’s gate (because of the desired low inputcapacitance) and A1’s input related connections (becauseof their high speed operation). Note that the connectionsassociated with A2 serve at DC and are much less sensitiveto layout. These determinations dominate the breadboard’sconstruction.

Figure 62 shows initial breadboard construction. Thecopper clad board is equipped with banana type connec-tors. The connector’s mounting nuts are simply solderedto the clad board, securing the connectors. Figure 63 addsA1 and the bypass capacitors. Observe that A1’s leadshave been bent out, permitting the amplifier to sit down onthe ground plane, minimizing parasitic capacitance. Also,the bypass capacitors are soldered to the amplifier powerpins right at the capacitor’s body. The capacitor’s leadlengths are returned to the banana power jacks. Thisconnection method provides good amplifier bypassing

Application Note 47

AN47-28

Figure 62. The Banana Jacks are Soldered to the Copper Clad BoardLTAN47 • TA62

while mechanically supporting the amplifier. It also elimi-nates separate wire runs to the power pins.

Figure 64 adds the discrete components in the high speedpath. Q1’s gate is connected directly to the input BNC, asis the 10MΩ resistor associated with A2’s negative input.Note that the end of this resistor that sees high frequencyis cut very short, while the other end is left uncut. The900Ω-100Ω divider is installed at A1, with very shortconnections to A1’s negative input. A1’s 10MΩ resistorreceives similar treatment to the BNC connected 10MΩunit; the high frequency end is cut short, while the enddestined for connection to A2 remains uncut. Q2’s collec-tor and Q1’s source, high speed points, are tied closelytogether with A1’s positive input.

Finally, DC amplifier A2 and its associated components areair wired into the breadboard (Figure 65). Their DC opera-

tion permits this, while the construction technique makesconnections to the previously wired nodes easy. Thepreviously uncommitted ends of the 10MΩ resistors maybe bent in any way necessary to make connections. Allother components associated with A2 receive similartreatment and the circuit is ready for experimentation.

Despite the breadboard’s seemingly haphazard construc-tion, the circuit worked well. Input capacitance measureda few pF (including BNC connector) with bias current ofabout 100pA. Slew rate was 1000V/µs, with bandwidthapproaching 100MHz. Output, even with 50mA loading,was clean, with no sign of oscillation or other instabilities.Full details on this circuit appear in the Applicationssection. Additional examples of breadboard constructiontechniques appear in Appendix F, “Additional Commentson Breadboarding”.

Application Note 47

AN47-29

LTAN47 • TA63

Figure 63. High Speed Amplifier A1 is Connected to Power. Bypass Capacitors Provide Support. Bending Amplifier Pins EasesConnections and Minimizes Distance to the Ground Plane

Once the breadboard seems to work, it’s useful to beginthinking about PC layout and component choice for pro-duction. Experiment with the existing layout to determinejust how sensitive nominally critical points are. Add con-trolled parasitic terms (e.g., resistors, capacitors andphysical layout changes) to test for sensitivity. Gentletouching of suspect points with a finger can yield prelimi-nary indication of sensitivity, giving clues that can be quitevaluable.

In conclusion, when breadboarding, design the bread-board to be quick and easy to build, work with and modify.Observe the circuit and listen to what it is telling you beforetrying to get it to some desired state. Finally, don’t hesitateto try just about anything; that’s what the breadboard isfor. Almost anything you do will cause some result —

whether it’s good or bad is almost irrelevant. Anything youdo that enhances your ability to correlate events occurringon the breadboard can only be beneficial.

Oscillation

The forte of the operational amplifier is negative feedback.It is feedback which stabilizes the operating point and fixesthe gain. However, positive feedback or delayed negativefeedback can cause oscillation. Thus, a properly function-ing amplifier constantly lives in the shadow of oscillation.

When oscillation occurs, several major candidates forblame are present. Power supply impedance must be low.If the supply is unbypassed, the impedance the amplifiersees at its power terminals is high, particularly at high

Application Note 47

AN47-30

LTAN47 • TA64

Figure 64. Additional High Speed Discrete Components and Connectors are Added. Note Short Connections at Amplifier Input Pins(Left Side of Package). 10M Resistors Uncommitted Ends are Just Visible

frequency. This impedance forms a voltage divider withthe amplifier, allowing the supply to move as internalconditions in the amplifier change. This can cause localfeedback and oscillation occurs. The obvious cure is tobypass the amplifier.

A second common cause of oscillation is positive feed-back. In most amplifier circuits feedback is negative,although controlled amounts of positive feedback may beused. In a circuit that nominally has only negative feedbackunintended positive feedback may occur with poor layout.Check for possible parasitic feedback paths and unwantedor overlooked feedback action. Always minimize (to theextent possible) impedances seen by amplifier inputs.This helps attenuate the effects of parasitic feedback pathsto the inputs. Similarly, minimize exposed input trace area.Route amplifier outputs and other signals well away from

sensitive nodes. Sometimes no amount of layout finessewill work and shielding is required. Use shielding onlywhen required — extensive shielding is a sloppy substi-tute for good layout practice.

A final cause of oscillation is negative feedback arrivingwell delayed in time. Under these conditions the amplifierhopelessly tries to servo a feedback signal which consis-tently arrives too late. The servo action takes the form ofan electronic tail chase, with oscillation centered aroundthe ideal servo point. The most common causes of thisproblem are reactive loading of the amplifier (most notablycapacitive loads such as cable) and circuitry, such aspower amplifiers, placed within the amplifier’s feedbackpath. Reactive loads should be isolated from the amplifier’soutput (and feedback path) with a resistor or poweramplifier. Sometimes rolling off the amplifier’s frequency

Application Note 47

AN47-31

LTAN47 • TA65

Figure 65. DC Servo Amplifier is Wired In and Connections to 10M Resistors Completed. This Part of the Circuitis Not Layout Sensitive

Note 9: Further exposition and kvetching on this point is given inReference 13.

response will fix the problem, but in high speed circuitsthis may not be an option.

Placing power gain or other type stages within theamplifier’s feedback path adds time delay to the stabilizingfeedback. If the delay is significant, oscillation commences.Stages operating within the amplifier’s loop must contrib-ute minimum time lag compared to the amplifier’s speedcapability. At lower speeds this is not too difficult, butsomething destined for operation within a 100MHzamplifier’s loop must be fast. As mentioned before, rollingoff the amplifier’s frequency response eases the job, but isusually undesirable in a wideband circuit. Every effortshould be expended to maximize the added stages band-width before resorting to roll-off of the amplifier. In thisway the fastest overall bandwidth is achieved while main-taining stability. Appendix C, “The Oscillation Problem –

Frequency Compensation Without Tears”, discusses con-siderations surrounding operating power gain and othertype stages within amplifier loops.

This completes the tutorial section. Hopefully, severalnotions have been imparted. First, in any measurementsituation, test equipment characteristics are an integralpart of the circuit. At high speed and high precision this isparticularly the case. As such, it is imperative to know yourequipment and how it works. There is no substitute forintimate familiarity with your tool’s capabilities andlimitations.9

In general, use equipment you trust and measurementtechniques you understand. Keep asking questions and

Application Note 47

AN47-32

Note 10: A truth table in an op amp circuit! Et tu, LTC!!

LTAN47 • TA66

+

–0V-10VOUTPUT

≈5k

LT1220

5pF

AD565A

INPUTS

INPUTS

LSB

MSB

Figure 66. Typical Output Amplifier Configuration for a12-Bit D-to-A Converter

LTAN47 • TA67

HORIZ = 100ns/DIV

A = 5V/DIV

B = 4mV/DIV

Figure 67. Settling Residue (Trace B) for All Bits Switched On(Trace A). Output is Fully Settled in 280ns

don’t be satisfied until everything you see on the oscillo-scope is accounted for and makes sense.

Fast monolithic amplifiers, combined with the precaution-ary notes listed above, permit fast linear circuit functionswhich are difficult or impractical using other approaches.Some of the applications presented represent the state-of-the-art for a particular circuit function. Others showsimplified and/or improved ways to implement standardfunctions by utilizing the amplifier’s easily accessed speed.All have been carefully (and painfully) worked out andshould serve as good idea sources for potential users ofthe device. Have fun. I did.

APPLICATIONS SECTION I - AMPLIFIERS

Fast 12-Bit Digital-to-Analog Converter (DAC)Amplifier

One of the most common applications for a high speedamplifier, transforming a 12-bit DAC’s current output intoa voltage, is also one of the most difficult. Although an opamp can easily do this, care is required to obtain gooddynamic performance. A fast DAC can settle to 0.01% in200ns or less, but its output also includes a parasiticcapacitance term, making the amplifier’s job more diffi-cult. Normally, the DAC’s current output is unloadeddirectly into the amplifier’s summing junction, placing theparasitic capacitance from ground to the amplifier’s in-put. The capacitance introduces feedback phase shift athigh frequencies, forcing the amplifier to hunt and ringabout the final value before settling. Different DACs havedifferent values of output capacitance. CMOS DACs havethe highest output capacitance, in the 100pF-150pF range,and it varies with code. Bipolar DACs typically have 20pF-30pF of capacitance, stable over all codes. As such,bipolar DACs are almost always used where high speed isrequired. Figure 66 shows the popular AD565A 12-bitDAC with an LT1220 output op amp. Figure 67 showsclean 0.01% settling in 280ns (Trace B) to an all-bits-oninput step (Trace A). The requirements for obtainingTrace B’s display are not trivial, and are fully detailed inAppendix B, “Measuring Amplifier Settling Time”.

2-Channel Video Amplifier

Figure 68 shows a simple way to multiplex two videoamplifiers onto a single 75Ω cable. The appropriate ampli-

fier is activated in accordance with the truth table in thefigure10. Amplifier performance includes 0.02% differen-tial gain error and 0.1° differential phase error. The 75Ωback termination looking into the cable means the ampli-fiers must swing 2Vp-p to produce 1Vp-p at the cableoutput, but this is easily handled.

Simple Video Amplifier

Figure 69 is a simpler version of Figure 68. This is a singlechannel video amplifier, arranged (in this case) for a gainof ten. The double cable termination is retained and thecircuit delivers a bandwidth of 55MHz.

Loop Through Cable Receivers

Figure 70 is another cable related circuit. Here, the LT1193differential amplifier simply hangs across a distributioncable, extracting the signal. The amplifier’s true differentialinputs reject common-mode signals. As in the previous

Application Note 47

AN47-33

LTAN47 • TA69

CABLE

2

+

–

+5V

7

LT1192

–5V

4

3

6

910Ω100Ω

75Ω

–3dB BANDWIDTH = 55MHz

75ΩVIN

Ω

LTAN47 • TA68

1k

Ω1k

+

–

INV

+5V

7

6

5

A1LT1190

S/D

–5V

4

3

2

1

Ω75

CABLE74HC04 74HC04

+

–

INV

+5V

76

5

LT1190

S/D

–5V

4

3

2

2

Ω1k Ω1k

–5V

Ω1k

Ω1k

CMOS INCH. SELECT

Ω75

INPUT SELECT

5V

0V

A1 OUTPUT

ACTIVE

INACTIVE

A2 OUTPUT

INACTIVE

ACTIVE

TRUTH TABLE

Figure 68. 2-Channel Multiplexed Video Amplifier

LTAN47 • TA70

Ω75CABLE

DCV

+5V

7

6LT1193

–5V

4

+

+

3

1

75

–

–

2

8

Ω300

Ω300

Ω

OUTV

INV

4.7k

1k1k

OUTPUT

LTAN47 • TA71

0.01

220Ω

100k

INPUT

–

+A1

LT1097

–

+A2

LT1191

Figure 69. Double Terminated Cable Driver

Figure 70. Cable Sense Amplifier for Loop Through Connectionswith DC Adjust

Figure 71. A1 DC Stabilizes A2 by Forcing the SummingPoint to Zero

circuit, differential gain and phase errors measure 0.2%and 0.1°, respectively. A separate input permits DC leveladjustment.

DC Stabilization – Summing Point Technique

Often it is desirable to obtain the precision offset of a DCamplifier with the bandwidth of a fast device. There are avariety of techniques for doing this. Which method is bestis heavily application dependent, so several configura-tions are presented.

Figure 71 shows a composite made up of an LT1097 lowdrift device and an LT1191 high speed amplifier. Theoverall circuit is a unity gain inverter with the summingnode located at the junction of the two 1k resistors. TheLT1097 monitors this summing node, compares it toground and drives the LT1191’s positive input, complet-ing a DC stabilizing loop around the LT1191. The 100kΩ-0.01µF time constant at the LT1097 limits its response to

low frequency signals. The LT1191 handles high fre-quency inputs while the LT1097 stabilizes the DC operat-ing point. The 4.7k-220Ω divider at the LT1191 preventsexcessive input overdrive during start-up. This circuitcombines the LT1097’s 35µV offset and 1.5V/°C drift withthe LT1191’s 450V/µs slew rate and 90MHz bandwidth.Bias current, dominated by the LT1191, is about 500nA.

Application Note 47

AN47-34

Ω

LTAN47 • TA72

+

–

+ INPUT

– INPUT

A2LT1220

A1LT1097

0.01

100k

100k

0.01

100k

270

+15V

OUTPUT

9k

1k

8+

–

Figure 72. A1 DC Stabilizes A2 by Forcing the Offset Pins toProduce a 0V Difference at A2’s Inputs

Figure 73. A1 DC Stabilizes the Circuit by Controlling Q1’s Channel Current

+

–

LTAN47 • TA73

900

1000.1

10k

0.1

A2LT1223

Ω

Ω10M

0.01

3k

10M

300pF

+

–

A1LT1097

–15V

330Ω

Q22N3904

Q12N5486

+15VINPUT

OUTPUT

DC Stabilization – Differentially Sensed Technique

Figure 72 is similar to Figure 71, except that the sensing isdone differentially, preserving access to both fast ampli-fier inputs. The LT1097 measures the DC error at theLT1220’s input terminals and biases its offset pins to forceoffset within 50µV. The offset pin biasing at the LT1220 isarranged so the LT1097 will always be able to find theservo point. The 0.01µF capacitor rolls off the LT1097 atlow frequency and the LT1220 handles high frequencysignals. The combined characteristics of these amplifiersyield the following performance:

Offset Voltage .......... 50µV

Offset Drift ............... 1µV/°C

Slew Rate ................ 250V/µs

Gain-Bandwidth ....... 45MHz

DC Stabilization – Servo Controlled FET Input Stage

Figure 73 shows a wideband, highly stable gain-of-tenwith high input impedance. Input capacitance is about3pF. Q1 and Q2 constitute a simple, high speed FET inputbuffer. Q1 functions as a source follower, with the Q2current source load setting the drain-source channel cur-rent. The LT1223 provides a 100MHz bandwidth gain often. Normally, this open loop configuration would be quitedrifty because there is no DC feedback. The LT1097contributes this function to stabilize the circuit. It does thisby comparing the filtered circuit output to a similarly

filtered version of the input signal. The amplified differ-ence between these signals is used to set Q2’s bias, andhence Q1’s channel current. This forces Q1’s VGS towhatever voltage is required to match the circuit’s inputand output potentials. The capacitor at A1 provides stableloop compensation. The RC network in A1’s output pre-vents it from seeing high speed edges coupled throughQ2’s collector-base junction.

This circuit constitutes an extremely wideband (Q1 doesnot degrade A2’s 100MHz performance), high input im-pedance amplifier. With an input capacitance of 3pF and

Application Note 47

AN47-35

bias current of 100pA, it is well suited for probing or as anATE pin amplifier. As shown, gain is ten, but other gainsare possible by varying the feedback ratio.

DC Stabilization – Full Differential Inputs withParallel Paths

Figure 74 shows a way to get full differential inputs with DCstabilized operation. This circuit combines the output oftwo differential input amplifiers for overall DC correctedwideband operation. A1 and A2 both differentially sensethe input at gains of ten. Wideband A1 feeds outputamplifier A3 via a highpass network, while the slower A2contributes DC and low frequency information to A3. A2does not see high frequency inputs, because they arefiltered by the 2k-200pF lowpass networks at its inputs. Ifthe gain and bandwidth of the high and low frequencypaths complement each other, A3’s output should be anundistorted, amplified version (in this case × 10) of theinput. Figure 75 shows this to be the case. Trace A is oneside of a differential input applied to the circuit. Trace B isA1’s output taken at the 500Ω potentiometer - 0.001µFjunction. Trace C is A2’s output. With the AC gain and DCgain match trims properly adjusted, the two paths’ contri-butions match up and Trace D is singularly clean, with noresidue. The adjustments are optimized by trimming theAC gain for the squarest corners and the DC gain match fora flat top. Bandwidth for this circuit exceeds 35MHz, slewrate is 450V/µs and DC offset about 200µV.

Figure 74. A Parallel Path DC Stabilized Differential Amplifier. High Frequency Signals Go through A1, while A2 Handles DCand Low Frequency. A3 Sums Both Paths

Note 11: For assistance in following circuit signal flow, the schematic of thisdevice is included in the figure.

DC Stabilization – Full Differential Inputs, Gain-of-1000 with Parallel Paths

Figure 76 is a very powerful extension of the previouscircuit. Operation is similar, but gain is increased to 1000.Bandwidth is about 35MHz, rise time equals 7ns and delayis inside 7.5ns. Full power response is available to 10MHz,with input noise about 15µV broadband. This kind ofspeed, coupled with full differential inputs, the gain of1000, DC stability, and low cost make the circuit broadlyapplicable in wideband instrumentation. As before, twodifferential amplifiers, A1 and A2, simultaneously sensethe inputs. In this case A1 is the popular and economical592-733 type, operating at a gain of 100.11 A1’s differen-tial outputs feed output amplifier A3 via 1µF-1kΩ highpass networks which strip off A1’s DC content. A2, aprecision DC differential type, operates in similar fashionto the previous circuit, supplying DC and low frequency

LTAN47 • TA75

HORIZ = 1 s/DIV

A = 0.2V/DIV

B = 2V/DIV

µ

C = 2V/DIV

D = 2V/DIV

Figure 75. Waveforms for the Parallel Path DifferentialAmplifier. Trace A is the Input; B, C and D are the High Pass,Low Pass and Output Nodes, Respectively

+

–

A1LT1193

+

– FB

A2LT1102A = 10

+

–

A3LT1191

1k

0.001 F

909Ω*

250 DC GAIN MATCH

Ω

200pF

2k

200pF

2kOUTPUT

INPUT

AC GAIN500 Ω

LTAN47 • TA74

* = 1% FILM RESISTOR

µ+

–

Application Note 47

AN47-36

Figure 76. A Full Differential, Parallel Path Amplifier. Gain is 1000, with 38MHz Bandwidth. Delay is Inside 7.5ns andRise Time Under 7ns

LTAN47 • TA76

Ω

+

–

––

–

+

+ +

+

9.09k*SELECTTYP. 240kLOW FREQUENCY GAIN(SEE TEXT)

1k*100k

OUTPUT

10pF

1.5M

1k1k

A4LT1056

A3LT1194

1µF

A1NE592µA733

A2LT1102A = 100

7pF-45pFPEAKING

250

2k2k

200pF200pF

INPUT

411 8

7

14

1

HIGH FREQUENCY GAIN(SEE TEXT)

* = 1% FILM RESISTOR

+

1µF

R12.4k

R22.4k

R810k

R350

R550

R7300

INPUT 22(1)

4(4)G1A

R4590

R6590

3(3)G2B

1(14)

9(11)

10(12)G2A

G1BGAIN SELECT

1.4k

Q8

R91.1k

R101.1k

Q4

R117k

R127k

OUTPUT 1

OUTPUT 2

7(8)

6(7)

Q9 Q10Q11

300 R13400

R14400

V5(5)

–

V8(10)

+

NUMBERS IN PARENTHESES SHOW DIP CONNECTIONS

GAINSELECT

INPUT 1

Q5

Q6

Q3

Q1 Q2

Q7

information to A3 at a trimmed gain of 100. In this caseoutput amplifier A3 is a differential gain block with anominal committed gain of 10. This change is necessi-tated by A1’s differential output, which must be single-ended to obtain the circuit’s output. As such A2 does notdirectly apply its low frequency information to A3 as it didbefore. Instead, A4 measures the difference between A2’soutput and a divided down portion of A3’s output. A4’soutput, biasing A3’s positive input via the 1kΩ resistor,closes a loop around the circuit’s DC-low frequency path.The divider feeding A4’s negative input is adjusted so thatthe circuit’s DC gain is known and equal to its AC gain.

Figure 77 shows the circuit’s response to a 60ns, 2.5mVamplitude pulse (Trace A). The X1000 output (Trace B)responds cleanly, with delay and rise time in the 5ns-7nsrange. Some small amount of peaking is evident, althoughit may be trimmed with the peaking adjustment at A1. Figure78 plots the circuit’s gain vs frequency. Gain is flat within 1/2dB to 20MHz, with the –3dB point at 38MHz. Figure 77’sedge peaking shows up here as a very slight gain increasestarting around 1MHz and continuing out to about 15MHz.The peaking trim will eliminate this effect.

To use this circuit, put in a low frequency or DC signal ofknown amplitude and adjust the low frequency gain for a

Application Note 47

AN47-37

X1000 output after the output has settled. Next, adjust thehigh frequency gain so that the signal’s front and rearcorners have amplitudes identical to the settled portion.Finally, trim the peaking adjustment for best settling of theoutput pulse’s front and rear corners.

Figure 79 shows input (Trace A) and output (Trace B)waveforms with all adjustments properly set. Fidelity isexcellent, with no aberrations or other artifacts of theparallel path operation evident. Figure 80 shows the ef-fects of too much AC gain; excessive peaking on the edgeswith proper amplitude indicated only after the AC channeltransitions through its highpass cut off. Similarly, exces-sive DC gain produces Figure 81’s traces. The AC gain path

LTAN47 • TA77

HORIZ = 10ns/DIV

A = 500 V/DIVB = 0.5V/DIV

µ

Figure 77. Pulse Response for the X1000 Differential Amplifier.Fidelity is Quite Good, with Only Slight Output Peaking (Trace B)

Figure 78. Gain vs Bandwidth for the X1000 DifferentialAmplifier. Peaking Noted in Figure 77 Shows up as 0.25dB Peakat 5MHz, Which Could be Trimmed Out

LTAN47 • TA79

HORIZ = 100 s/DIV

A = 0.002V/DIV

B = 2V/DIV

µ

Figure 79. Response of X1000 Amplifier with BandwidthCrossover Points Properly Adjusted. A = Input; B = Output

LTAN47 • TA80

HORIZ = 100 s/DIV

A = 0.002V/DIV

B = 2V/DIV

µ

Figure 80. Response of X1000 Amplifier with Excessive AC Gain.A = Input; B = Output

LTAN47 • TA81

HORIZ = 100 s/DIV

A = 0.002V/DIV

B = 2V/DIV

µ

Figure 81. Response of X1000 Amplifier with Too Much DC Gain.A = Input; B = Output

provides proper initial response, but too much DC gainforces a long, tailing response to an incorrect amplitude.

High Speed Differential Line Receiver

High speed analog signals transmitted on a line often pickup substantial common-mode noise. Figure 82 shows asimple, fast differential line receiver using the LT1194

Application Note 47

AN47-38

Figure 82. Simple, Full Differential Line Receiver

LTAN47 • TA83

HORIZ = 1 s/DIV

A = 0.5V/DIV

B = 0.5V/DIV

µ

C = 0.5V/DIV

D = 5V/DIV

Figure 83. Differential Line Receiver Easily Pulls Out a SignalBuried in Common-Mode Noise. Output is Clean, Despite 100:1Noise-to-Signal Ratio

–

+

LTAN47 • TA82

A1LT1194

DIFFERENTIALSIGNAL INPUT

= HP 5082-2810

1k

1k

–5V

–5V

LINE

+5V

+5V

OUTPUT

10k

SINEWAVE OSCILLATOR

ZO = 5050Ω

NOISE GENERATOR(GENERAL

RADIO 1390B)

A

B

TO DIFFERENTIALLINE INPUTS

Ω

T1

TEST CIRCUIT

10k

gain-of-ten differential amplifier. The differential line is fedto A1. The resistor-diode networks prevent overload andinsure input bias for A1 under all conditions. A1’s outputrepresents the difference of the two line input times a gainof ten. In theory, all common-mode noise should berejected. The test circuit shown in the figure confirms this.The sinewave oscillator drives T1 (Trace A, Figure 83),producing a differential line output at its secondary. T1’ssecondary is returned to ground through a broadbandnoise generator, flooding the line inputs with common-mode noise (traces B and C are A1’s inputs). Trace D, A1’sX10 version of the differential signal at its inputs, is cleanwith no visible noise or disturbances. This circuit willeasily provide a clean output with DC-5MHz noise domi-nating signal by a 100:1 ratio.

Transformer Coupled Amplifier

Figure 84 shows another way to achieve high common-mode rejection. Additionally, this circuit has the advantageof true 3 port isolation. The input, gain stage, and outputare all galvanically isolated from each other. As such, this

configuration is useful where large common-mode differ-ences are encountered or where ground integrity isuncertain. A1 is set up in a simple gain of 11. T1 feeds itsinput, and the output is taken from T2. Figure 85 showsresults for a 4MHz input, with all “•” designated trans-former leads referred to ground. The input (Trace A, Figure85) is applied to T1, whose output (Trace B) feeds A1. A1takes gain, and its output (Trace C) feeds T2. T2’s output

Application Note 47

AN47-39

Differential Comparator Amplifier with AdjustableOffset

It is often desirable to examine or amplify one particularportion of a signal while rejecting all other portions. At highspeed this can be difficult, because the amplifier may seefast, large common-mode swings. Recovery from suchactivity usually is dominated by saturation effects, makingthe amplifier’s output questionable. The LT1193’s differ-ential amplifier’s fast overload recovery permits thisfunction, maintaining output fidelity to the input signal.Additionally, the input level amplitude at which amplifica-tion begins is settable, allowing any amplitude definedpoint to be selected. In Figure 86, A1, the LT1019 referenceand associated components form an adjustable, bipolarvoltage source which is coupled to differential amplifierA2’s negative input. The input signal biases A2’s positiveinput with A2’s gain set by R1 and R2, in accordance withthe equation given.

Input signals below A2’s negative input levels maintainA2’s output in saturation, and no signal is seen at theoutput. When the positive input rises above the negativeinput’s bias point A2 becomes active, providing an ampli-fied version of the instantaneous difference between itsinputs. Figure 87 shows what happens when the output ofa triangle wave generator (Trace A) is applied to the circuit.Setting the bias level just below the triangle peak permitshigh gain, detailed operation of the turnaround at the peak.Switching residue in the generator’s output is clearlyobservable in Trace B. Appropriate variations in the volt-age source setting would permit more of the triangle

(Trace D) is the circuit’s output. Phase shift is evident,although tolerable. T1 and T2 are very wideband devices,with low phase shift. Note the negligible phase differencebetween the A-B and C-D trace pairs. A1 contributesessentially the entire phase error. Using the transformersspecified, the circuit’s low frequency cut-off is about 10kHz.

Figure 86. Fast Differential Comparator Amplifier with Settable Offset

R1*

A2LT1193

+

– FB

A1LT1006

+

–

R2*

100Ω

1k

10k*

INPUT

*1% FILM RESISTOR

0.1 Fµ

LT10192.5V

OUTPUT

+5V

A = +1R2R1

LTAN47 • TA86

10k*+–

IN OUTGND

+

–Ω

LTAN47 • TA84T1, T2 = MINI CIRCUITS LAB # T1-6

A1LT1191

100

1k

T2T1

INPUT OUTPUT

Figure 84. Transformer Coupled Amplifier. Note That A1 isGalvanically Isolated From Input and Output Nodes

LTAN47 • TA85

HORIZ = 50ns/DIV

A = 0.2V/DIVB = 0.2V/DIV

C = 2V/DIVD = 2V/DIV

Figure 85. Transformer Coupled Amplifier Responds to an Input(Trace A) with A Slightly Phase Shifted Output (Trace D). TracesB and C are T1 Secondary and T2 Primary, Respectively

Application Note 47

AN47-40

A HORIZ = 20 s/DIVB HORIZ = 2 s/DIV

A = 5V/DIV

LTAN47 • TA87

B = 0.1V/DIV

µµ

Figure 87. The Differential Comparator Amplifier ExtractingSignal Detail From a Triangle Waveform’s Peak. TriangleGenerator’s Switching Artifacts are Clearly Evident

Figure 88. Differential Comparator Amplifier with Settable Automatic Limiting and Offset

LTAN47 • TA88

–

–

+

+

1k

OUTPUTA2LT1194

A1LT1016

INPUT

1

8

–5V

2kVCLAMP

2k

+5V 1kVCOMPARE+

–5V

+5V

1kVCOMPARE–

2k

240

240

240

Q12N5771

1k

Q22N2369

+5V

Q52N3904

Q62N3906

Q32N2369

Q42N5771

–5V

–5V

240

Ω

Ω

Ω

Ω

D TO ACONVERTER ALTERNATE

VSOURCE

COMPARE+

A = 10


VSOURCE

COMPARE–


VSOURCE

CLAMP

slopes to be observed, with attendant loss of resolutiondue to oscilloscope overload limitations. Similarly, in-creasing A2’s gain allows more amplitude detail whileplacing restrictions on how much of the waveform can bedisplayed. It is worth noting that this circuit performs thesame function as differential plug-in units for oscillo-scopes. This circuit’s output is accurate and settled to0.1% 100ns after it enters its linear region.

Differential Comparator Amplifier with SettableAutomatic Limiting and Offset

Figure 88 extends the previous circuit’s operation, allow-ing amplified observation of information between twosettable, amplitude defined points. The amplitude setpointsare settable in both magnitude and sign. In this circuit thepolarity of the offset applied to A2’s negative input is

Application Note 47

AN47-41

+

–

LTAN47 • TA90

3pF

29k

A1LT1122

IPHOTO

–15V

OUTPUT

= HEWLETT-PACKARD HP5082-4204

2pFC DIODE

LIGHT (900nM)

1mW

100µW

10µW

1µW

100nW

DIODE CURRENT

350µA

35µA

3.5µA

350nA

35nA

CIRCUIT OUTPUT

10.0V

1V

0.1V

0.01V

0.001V

RESPONSE DATA

Figure 90. A Simple Photodiode Amplifier

determined by comparator A1’s output state. A1 com-pares the circuit’s input to ground, generating polarityinformation at its outputs. Level shifters Q1-Q3 and Q2-Q4bias followers Q5 and Q6. Positive circuit inputs result inQ5 supplying the “VCOMPARE+” potential to A2, whilenegative inputs route “VCOMPARE–” to A2. This eliminatesthe previous circuit’s manual polarity switch, permittingautomatic selection of the differencing polarity and ampli-tude. Additionally, this circuit takes advantage of A2’sinput clamp feature. This feature (See LT1194 Data Sheet)limits the dynamic range of the input, clamping theamplifier’s input operating range. Signals inside the clamplimit are processed normally, while signals outside thelimit are precluded from influencing the amplifier. Thiscombination of circuit controls allows very tightly definedwindows on a waveform to be selected for accurateamplification without overload restrictions.

Figure 89 shows the circuit output for a sine input (TraceA) from the same function generator used to test theprevious circuit. The V+ and V– compare voltages are setjust below the sinewave peaks, with “Vclamp” programmedto restrict amplification to the peak’s excursion. Trace B,the circuit’s output, simultaneously shows amplitude de-tail of both sine peaks. The observed distortion is directlytraceable to this generator’s imperfect internal trianglewaveform (see Figure 87), as well as its sine shapercharacteristics.

LTAN47 • TA89

HORIZ = 5 s/DIV

A = 2V/DIV

B = 0.1V/DIV

µ

Figure 89. The Automatic Differential Comparator AmplifierFinds Triangle Wave and Switching Residuals (Trace B)in Trace A’s Peaks

Photodiode Amplifier

Amplification of fast photodiode signals over a wide rangeof intensity is a common requirement. Figure 90’s fast FETamplifier serves well, giving wideband operation with 5

decades of photocurrent. The photodiode is set up in theconventional manner. Photocurrent is fed directly to A1’ssumming point, causing A1’s output to move to the levelrequired to maintain virtual ground at the negative input.The –15V diode bias aids diode response. The table in thefigure details circuit operating characteristics with thediode specified.

Some care in frequency compensating this configurationis required. The diode has about 2pF of parasitic capaci-tance, forming a significant lag at A1’s summing point. Ifno feedback capacitor is used, high speed dynamics arepoor. Figure 91 shows circuit response to a photo input(Trace A) with the indicated 3pF feedback capacitor re-moved. A1’s output overshoots and saturates beforefinally ringing down to final value. In contrast, replacingthe 3pf capacitor provides Figure 92’s results. The sameinput pulse (Trace A, Figure 92) produces a cleanly dampedoutput (Trace B). The capacitor imposes a 50% speedpenalty (note faster horizontal scale for Figure 92). This isunavoidable because suppressing the parasitic ringing’srelatively low frequency mandates significant roll-off.

Fast Photo Integrator

A related circuit to the photodiode amplifier is Figure 93’sphoto integrator. Here, the output represents the integralof the diode’s photocurrent over some period of time. This

Application Note 47

AN47-42

HORIZ = 500ns/DIV

A = 175µA/DIV

LTAN47 • TA91

B = 10V/DIV

Figure 91. Response of Figure 90 Without a Feedback Capacitor

HORIZ = 200ns/DIV

A = 175µA/DIV

LTAN47 • TA92

B = 5V/DIV

Figure 92. Figure 90 Responding with a Feedback Capacitor

+

–

LTAN47 • TA93

30k 7pF-45pF

S21/4 LTC201

OUTPUT

S11/4 LTC201

10 11

RUNRESET0V

5V

CONTROLINPUT 9

LIGHT INPUT

–15V

IPHOTO

10pF

7 6

8

10pF

2pFCDIODE

A1LT1122

= HEWLETT PACKARD HP5082-420410pF CAPACITOR = POLYSTYRENE

DO NOT ALTER LTC201 SWITCH CONNECTIONS

Figure 93. A Very Fast Photo Integrator. S2 Compensates ResetSwitch S1’s Small Charge Injection

HORIZ = 200ns/DIV

A = 2V/DIV

LTAN47 • TA94

B = 5V/DIV

C = 5V/DIV

Figure 94. The Photo Integrator Acquires (Trace C) an InputLight Pulse (Trace B) with the Control Line (Trace A) in the RunMode. Charge Cancellation Action is Evident at Trace C’s 400nsPoint

circuit is particularly applicable in situations where thetotal energy in a light pulse (or pulses) must be measured.The circuit is a very fast integrator, with S1 used as a resetswitch. S2, switched simultaneously with S1, compen-sates S1’s charge injection error. With the control input(Trace A, Figure 94) low and no photocurrent, S1 is closedand A1 looks like a grounded follower. Under these condi-tions A1’s output (Trace C) sits at 0V. When the controlinput goes high, A1 becomes an integrator as soon as S1opens. Due to switch delay, this occurs about 150ns afterthe control input goes high. When S1 opens it deliverssome parasitic charge to A1’s summing point. S2 providesa compensatory charge based pulse at A1’s positiveterminal to cancel the effects of S1’s charge error. Thisaction shows up as a fast, small amplitude event in A1’soutput which settles rapidly back to 0V.

Application Note 47

AN47-43

+

–

LTAN47 • TA95

I 2.5 A-350 AµPHOTO µ≈

500ΩTHRESHOLD ADJUST

A1LT1220 A2

LT1016

5.1k

10k

OUTPUT

= HP5082-40240.1

+5V

+

–

Figure 95. A Simple Fiber Optic Receiver

LTAN47 • TA96

HORIZ = 20ns/DIV

A = 5V/DIV

B = 0.2V/DIV

C = 2V/DIV

Figure 96. Waveforms for the Simple Fiber Optic Receiver. A1(Trace B) Lags the Input (Trace A), but Output (Trace C) is Clean

At this point in time the integrator is ready to receive andrecord a photo pulse. When light falls on the photodiode(Trace B triggers a light pulse seen by the photodiode) A1responds by integrating. In this case A1’s output integratesrapidly until the light pulse ceases. A1’s voltage after thelight event is over is related to the total energy seen by thediode during the event. A monitoring A-D converter canacquire A1’s output. In typical operation the control linereturns low, resetting A1 until the next event is to beintegrated.

With only 10pF of integration capacitor, the circuit has anoutput droop rate of about 0.2V/µs. This can be increased,although integration speed will suffer accordingly. Inte-gration times of nanoseconds to milliseconds andphotocurrents ranging from nanoamperes to hundreds ofmicroamperes are accommodated by the circuit as shown.Thus, light intensities spanning microwatts to milliwattsover wide ranges of duration are practical inputs. Theprimary accuracy restrictions are A1’s 75pA bias current,its 12V output swing and the effectiveness of the chargecancellation network. Typically, full-scale accuracy of sev-eral percent is achievable if the charge cancellation networkis trimmed. To do this, assure that the diode sees no lightwhile repetitively pulsing the control line. Adjust the trim-mer capacitor for 0V output at A1 immediately after thedisturbance associated with the S1-S2 switching settles.

Fiber Optic Receiver

A simple high speed fiber optic receiver appears in Figure95. A1, a photocurrent-to-voltage converter similar toFigure 90, feeds comparator A2. A2 compares A1’s output

to a DC level established by the threshold adjust setting,producing a logic compatible output. Figure 96 showstypical waveforms. Trace A is a pulse associated with aphoto input. Trace B is A1’s response and Trace C is A2’soutput. The phase shift between the photo input and A2’soutput is due to A1’s delay in reaching the threshold level.Reducing the threshold level will help, but moves opera-tion closer to the noise floor. Additionally, the fixed thresh-old level cannot account for response changes in theemitter and detector diodes and fiber optic line over timeand temperature.

40MHz Fiber Optic Receiver with Adaptive Trigger

Receiving high speed fiber optic data with wide inputamplitude variations is not easy. The high speed data anduncertain intensity of the light level can cause erroneousresults unless the receiver is carefully designed. Figure 97addresses the previous circuit’s limitations, offering sig-nificant performance advantages. This receiver will reli-ably condition fiber optic inputs of up to 40MHz with inputamplitude varying by >40dB. Its digital output features anadaptive threshold trigger which accommodates varyingsignal intensities due to component aging and othercauses. An analog output is also available to monitor thedetector output. The optical signal is detected by the PINphotodiode and amplified by A1. A second stage, A2, givesfurther amplification. The output of this stage biases a 2-way peak detector (Q1-Q4). The maximum peak is storedin Q2’s emitter capacitor, while the minimum excursion isretained in Q4’s emitter capacitor. The DC value of A2’soutput signal’s mid-point appears at the junction of the500pF capacitor and the 22MΩ units. This point willalways sit midway between the signal’s excursions, re-

Application Note 47

AN47-44

Figure 97. Adaptively Triggered 40MHz Fiber Optic Receiver is Immune to Shifts in Operating Point

LTAN47 • TA98

HORIZ = 20ns/DIV

A = 5V/DIV

B = 2V/DIV

C = 2V/DIV

Figure 98. Adaptively Triggered Fiber Optic Receiver’sWaveforms at 20MHz with 5µA Diode Current

LTAN47 • TA97

+

–0.005 500pF

0.005

22M

22M

330Ω

A3LT1097

+

–

A4LT1016

0.1

+

–

A2LT1223

1k

50Ω

+

–A1

LT1220

10k

PULSE GENERATOR

+

–50Ω

10kTEST CIRCUIT

HP-HEMT-6000

FIBRE OPTIC CABLE

Q3 Q4

Q1 Q2

+5V

–5V

3k

3k

HP5082-4207

I = 500nA-350 APHOTO µ

PNP = 2N3906NPN = 2N3904

ANALOG OUTPUT — 0.2V/µA PHOTOCURRENT

OUTPUT

gardless of absolute amplitude. This signal-adaptive volt-age is buffered by the low bias LT1097 to set the triggervoltage at the LT1016’s positive input. The LT1016’snegative input is biased directly from A2’s output. Figure98 shows the results using the test circuit indicated inFigure 97. The pulse generator’s output is Trace A, whileA2’s output (analog output monitor) appears in Trace B.The LT1016 output is Trace C. The waveforms wererecorded with a 5µA photocurrent at about 20MHz. Notethat A4’s output transitions correspond with the midpointof A2’s output (plus A4’s 10ns propagation delay) inaccordance with the adaptive trigger’s operation.

50MHz High Accuracy Analog Multiplier

Although highly accurate, very wideband analog multipli-ers are available, their output takes a differential form.These differential outputs, which have substantial com-mon mode content, are frequently inconvenient to workwith. RF transformers can be used to single end theoutputs, but DC and low frequency information is lost.

Figure 99 uses the LT1193 differential amplifier to accom-plish the differential-to-single ended transition. The AD834is set up in the recommended configuration (see AnalogDevices AD834 Data Sheet, Reference 26). The LT1193takes the differential signal from the AD834’s 50Ω termi-nated output and provides a single ended output. The gainof two yields a ±1V output at full-scale.

Application Note 47

AN47-45

Figure 99. Analog Multiplier with 2% Accuracy Over DC to 50MHz Has a Single Ended Output

LTAN47 • TA100

HORIZ = 40ns/DIV

A = 0.5V/DIV

B = 0.5V/DIV

Figure 100. The Multiplier Produces a Modulated Sine Output(Trace B) in Accordance with Trace A’s Envelope

LTAN47 • TA99

X1

X2

Y1Y2

+VS

–VS

W1

W2

1 Fµ+

0.01

XIN

YIN

INPUT = ±1VFS

+

–LT1193

1 Fµ+0.01

AD834

50Ω

–7.5V

+7.5V

FB

500 *Ω1pF-5pF

500 * Ω

OUTPUT = ±1VFS

OUTPUT = (X1 – X2)(Y1 – Y2)

= 1N4148 = 0.1% METAL FILM RESISTOR = FERRITE BEAD, FERRONICS #21-110J

*

50Ω

The AD834 outputs come out riding on a common-modelevel very close to the devices positive supply. This common-mode level falls outside the LT1193’s input common-moderange. The diodes in the 7.5V supply rails drop the supplyat the AD834, biasing its outputs within the LT1193’s inputrange. This scheme avoids the attenuation and matchingproblems presented by placing a level shift between themultiplier and amplifier. The ferrite beads combine withthe diode’s impedance to ensure adequate bypassing forthe multiplier, a very wideband device.

Performance for this circuit is quite impressive. Errorremains within 2% over DC-50MHz, with feedthroughbelow –50dB. Trimming the circuit involves adjusting thevariable capacitor at the amplifier for minimal outputsquare wave peaking. Figure 100 shows performancewhen a 20MHz sine input is multiplied by Trace A’swaveform. The output (Trace B) is a singularly cleaninstantaneous representation of the X•Y input products,with strict fidelity to their components.

Power Booster Stage

Occasionally, it is necessary to supply larger output cur-rents than an amplifier is capable of delivering. The powergain stage, sometimes called a booster, is usually placedwithin the monolithic amplifier’s feedback loop, preserv-ing the IC’s low drift and stable gain characteristics.

Because the output stage resides in the amplifier’s feed-back path, loop stability is a concern. This is particularlythe case with high speed amplifiers. The output stage’sgain and AC characteristics must be considered if gooddynamic performance is to be achieved. Overall circuitphase shift, frequency response and dynamic load han-dling capabilities are issues that cannot be ignored whendesigning a power gain stage for a monolithic amplifier.The output stage’s added gain and phase shift can causepoor AC response or outright oscillation. Judicious appli-cation of frequency compensation methods is needed forgood results (see Appendix C, “The Oscillation Problem –Frequency Compensation Without Tears”, for discussionand details on compensation methods).

Application Note 47

AN47-46

HORIZ = 10ns/DIV

A = 2V/DIV

LTAN47 • TA102

B = 2V/DIV

Figure 102. Response of Figure 101’s Booster Stage

HORIZ = 20ns/DIV

A = 2V/DIV

LTAN47 • TA103

B = 2V/DIV(INVERTED)

Figure 103. The Booster’s Response When Inside anAmplifier’s Loop

Figure 101. A 200mA Output Wideband Booster Stage

1k

LTAN47 • TA101

+

–Ω

1k

LT1220

BOOSTER INPUT

100

–15V

+15V

1k

3pF

Q1 Q31k

2Ω

Q41k

2Ω

Q6

1k

+15V

–15V

OUTPUT

INPUT

======

FERRITE BEAD, FERRONICS #21-110J2N39062N39042N38662N51601N4148

Q1,Q4Q2,Q3

Q5Q6

Q2

Q5

Figure 101 shows a 200mA power booster used with anLT1220 amplifier. Complementary emitter followers Q1-Q5 provide current gain for positive signals, with Q2 andQ6 handling negative excursions. Q3 and Q4 are VBE basedcurrent limits, coming on and robbing drive from theappropriate output transistor when current exceeds about300mA. The diodes prevent Q1 and Q2 from seeingreverse VBE during current limit. The 100Ω resistor andferrite beads prevent the low impedance amplifier outputfrom causing oscillation in Q1 and Q2 (see Appendix C).

To be effective, the booster must be exceptionally fast. Aslow design will obviate the AC performance of the ampli-fier controlling it, or in the worst case, cause oscillation(again, see Appendix C). Figure 102 shows booster perfor-mance with the LT1220 removed from the circuit. Theinput pulse (Trace A) is applied to the booster input, withthe output (Trace B) taken at the indicated spot. Evaluationof the photograph shows that booster rise and fall timesare limited by the input pulse generator. Additionally, delayis in the 1ns range. This kind of speed makes the circuit agood candidate for acceptable AC performance within afast amplifier’s loop.

Figure 103 shows pulse response with the LT1220 in-stalled in the circuit with a 50Ω load. The booster’s highspeed contributes negligible delay and overall response isclean and predictable. The local 3pF roll-off at the LT1220optimizes response, but is not absolutely necessary in thiscircuit. The input (Trace A) produces a nicely shapedLT1220 slew-limited output (Trace B).

Application Note 47

AN47-47

Figure 104. Fast, 1A Booster Stage

HORIZ = 20ns/DIV

C = 2V/DIV

LTAN47 • TA105

A = 2V/DIVB = 2V/DIV

Figure 105. The Boosted Op Amp Drives a 1A Load to 10Vin 50ns

+

+

+

–LT1220

1k

1k

100Ω

1k100Ω

1k100Ω

0.5Ω

1k

–15V

+15V

–15V

+15VOUTPUT

1k

1k

5pF-30pF

1k

INPUT

Q3

Q1

Q2

Q7

Q8

Q4

Q6

3pF

2pF

22

22

0.5Ω

Q5

= 1N4148= 2N3906= 2N3904= 2N3375= 2N3866= 2N5160= FERRITE BEADS FERRONICS #21-110J

Q1,Q8Q2,Q7Q4,Q6

Q3Q5

AN47 F104

High Power Booster Stage

In theory, higher power booster stages should be achiev-able by utilizing bigger devices. This is partly the case, butlack of availability of wideband PNP power transistors isan issue. Figure 104 shows a way around this problem.

The circuit is essentially a 1A output version of Figure 101,with several differences. In the positive signal path outputtransistor Q4 is an RF power type, driven by Darlingtonconnected Q3. The diode in Q1’s emitter compensates theadditional VBE introduced by Q3, preventing crossoverdistortion.

The negative signal path substitutes the Q5-Q6 connectionto simulate a fast PNP power transistor. Although thisconfiguration acts like a fast PNP follower, it has voltagegain and tends to oscillate. The local 2pF feedback capaci-tor suppresses these parasitic oscillations and the com-posite transistor is stable.

This circuit also includes a feedback capacitor trim tooptimize AC response. This difference from the previouscircuit is necessitated by this circuit’s slightly slowercharacteristics and much heavier loading. Current limitoperation and other characteristics are similar to the lowerpower circuit.

Figure 105 shows waveforms for a 10V negative input step(Trace A) with a 10Ω load. The amplifier responds (TraceB), driving the booster to the voltage required to close theloop. For this positive step, the amplifier provides about1.5V overdrive to overcome Q3 and Q4’s VBE drops. Thebooster output, lagging by a few nanoseconds (Trace C),drives the load cleanly, with only minor peaking. Thispeaking may be minimized with the feedback capacitancetrimmer.

Application Note 47

AN47-48

A1LT1190

+

–

*CERAMIC RESONATOR MURATA-ERIE CORP LTAN47 • TA108

1k100Ω

OUTPUT

INPUT

400kHz*

CPARASITIC

620pF 1k

Figure 108. Differential Network Nulls Parasitic Capacitance ofCeramic Element

LT1221

+

–

LTAN47 • TA109

1k

100Ω

OUTPUT

INPUT3.57MHz

5pF

Figure 109. Crystal Filter

A1LT1190

+

–

*CERAMIC RESONATOR MURATA-ERIE CORP LTAN47 • TA106

1k

100Ω

OUTPUT

INPUT

400kHz*

CPARASITIC

Figure 106. A Piezo-Ceramic Based Filter

FREQUENCY (kHz)

250–40dB

AMPL

ITUD

E IN

RM

S VO

LTS

AND

dB

–20dB

0.6

0.8

1.2

1.6

0dB 1.8

300 400 500 600

LTAN47 • TA107

350 450 550

0.4

1.0

1.4FIGURE 106

V = 1.77 V (5Vp-p)

OUT RMS

FIGURE 108

Figure 107. Response of Both Piezo-Ceramic Filters. DifferentialNetwork’s Activity is Evident in Figure 108’s Performance

Ceramic Bandpass Filters

Figure 106 is a highly selective bandpass filter using aresonant ceramic element and a single amplifier. Theceramic element nominally looks like a high impedance offits resonant frequency, in this case 400kHz. For off reso-nance inputs, A1 acts like a grounded follower, producingno output. At resonance, the ceramic element has a lowimpedance and A1 responds as an inverter with gain. The100Ω resistor isolates the ceramic element’s capacitancefrom A1’s summing point. This capacitance is quite sub-stantial and limits the circuits out of band rejection capa-bility. Figure 107 shows this. This plot shows very steeprejection, with A1’s output down almost 20dB at 300kHzand 40dB at 425kHz. The device’s stray parasitic capaci-tance causes the gentle rise in output at higher frequenciesand also sets the –20dB floor at 300kHz.

Figure 108 partially corrects this problem with a nullingtechnique. This circuit is similar to the previous one,except that a portion of the input is fed to A1’s positiveinput. The RC network at this input is scaled to look like theceramic resonator’s off null impedance. As such, A1’sinputs see similar signals for out of band components,

resulting in attenuation via A1’s common-mode rejection.At resonance, the added RC network appears as a muchhigher impedance than the ceramic element and filterresponse is similar to Figure 106’s circuit. Figure 107shows that this circuit has much better out of bandrejection than Figure 106. The high frequency roll-off issmooth, and over 20dB deeper than Figure 106 at 475kHz.The low frequency side of resonance has similar charac-teristics at 375kHz and below.

Crystal Filter

Quartz crystals can also be used to make even higherselectivity filters at higher frequencies. Figure 109 replacesFigure 106’s ceramic element with a 3.57MHz quartzcrystal. Figure 110 shows almost 30dB attenuation only afew kHz on either side of resonance! The differentialnulling technique used with the ceramic elements is lesseffective with quartz crystals. Crystals have significantlylower parasitic terms, making the cancellation less effective.

APPLICATIONS SECTION II - OSCILLATORS

Sine Wave Output Quartz Stabilized Oscillator

Figure 111 places a crystal within the amplifier’s feedbackpath, creating an oscillator. With the crystal removed, the

Application Note 47

AN47-49

Figure 110. The Crystal Filter’s Response

LTAN47 • TA111

100Ω

1k

A1LT1191

+

–

#345 LAMP

10MHz

10MHzSINE OUT

Figure 111. 10MHz Quartz Stabilized Sine Wave Oscillator

Note 12: See Reference 20, as well as References 19 and 21 for supplementalinformation.

circuit is a familiar non-inverting amplifier with a groundedinput. Gain is set by the impedance ratio of the elementsassociated with A1’s negative input. Inserting the crystalcloses a positive feedback path at the crystal’s resonantfrequency and oscillations commence.

In any oscillator it is necessary to control the gain as wellas the phase shift at the frequency of interest. If gain is toolow, oscillation will not occur. Conversely, too much gainproduces saturation limiting. Here, gain control comesfrom the positive temperature coefficient of the lamp atA1’s negative input. When power is applied, the lamp is ata low resistance value, gain is high and oscillation ampli-tude builds. As amplitude builds, lamp current increases,heating occurs, and the lamp’s resistance goes up. Thiscauses a reduction in amplifier gain and the circuit finds a

stable operating point. This circuit’s sine wave output hasall the stability advantages associated with quartz crystals.Although shown at 10MHz, it works well with a widevariety of crystal types over a 100kHz-20MHz range. Theuse of the lamp to control amplifier gain is a classictechnique, first described by Meacham in 1938.12 Elec-tronic gain control, while more complex, offers moreprecise control of amplitude.

Sine Wave Output Quartz Stabilized Oscillator withElectronic Gain Control

Figure 112’s quartz stabilized oscillator replaces the lampwith an electronic amplitude stabilization loop. A2 com-pares the A1 oscillator’s positive output peaks with a DCreference. The diode in the DC reference path temperaturecompensates the rectifier diode. A2 biases Q1, controllingits channel resistance. This influences loop gain, which isreflected in oscillator output amplitude. Loop closurearound A1 occurs, stabilizing oscillator amplitude. The1µF capacitor compensates the gain control loop.

The DC reference network is set up to provide optimumtemperature compensation for the rectifier diode, whichsees a 2Vp-p 20MHz waveform out of A1. A1’s smallamplitude swing minimizes distortion introduced by chan-nel resistance modulation in Q1. To use this circuit, adjustthe 50Ω trimmer until 2Vp-p oscillations appear at A1’soutput.

Figure 113 is a spectrum analysis of the oscillator’soutput. The fundamental sits at 20MHz, with the secondharmonic 47dB down at 40MHz. A third harmonic, 50dBdown, occurs at 60MHz. Resolution bandwidth for thespectrum analysis is 1kHz.

DC Tuned 1MHz-10MHz Wien Bridge Oscillator

In Figure 114 the quartz crystal is replaced with a Wiennetwork at A2’s positive input. A1 controls Q1 to amplitudestabilize A2’s oscillations in identical fashion to the previ-ous figure. Although the Wien network is not nearly asstable as a quartz crystal, it has the advantage of a variablefrequency output. Normally, this is facilitated by varyingeither R, C, or both. Usually, manually adjustable elementssuch as dual potentiometers and two section variable

Application Note 47

AN47-50

LTAN47 • TA112

A2LT1006

5k (SELECT)

50 Ω

+

–

1 F

LT10041.2V

1N4148MOUNT CLOSE

1.5k

–5V10k

A1LT1191

+

–10k

Q12N4393

1k

µ

20MHz

10k

1k

1k

OUTPUT2Vp-p

Figure 112. 20MHz Quartz Stabilized Sine Wave Oscillator with Electronic AGC

Figure 113. Spectrum Analysis of the 20MHz Quartz Oscillator.Harmonic Content is at Least 47dB Down

Note 13: The construction and operation of this apparatus may requireFederal Communications Commission review and/or licensing. See AppendixG for FCC licensing and application information.

capacitors are used. Here, the Wien network resistors arefixed at 360Ω, while the capacitive elements are realizedwith varactor diodes. The varactor diodes voltage-vari-able-capacitance characteristic allows DC tuning of theoscillator. DC inputs of 0V-10V to the varactors result in a1MHz to 10MHz shift in oscillation frequency. The 0.1µFcapacitor blocks the DC bias from A2’s positive input whilepermitting the Wien network to function normally. A2’s2Vp-p output minimizes the varactor’s junction effects,aiding distortion.

This ±5V powered circuit requires voltage step-up todevelop adequate varactor drive. A3 and the LT1172switching regulator form a simple voltage step-up regula-tor. A3 controls the LT1172 to produce the output voltagerequired to close a loop at A3’s negative input. L1’s highvoltage inductive flyback events, rectified by the diode andzener connected Q2, are stored in the 22µF output capaci-tor. The 7.5k-2.5k divider provides a sample of the output’svalue to A3’s negative input, closing the loop. The 0.1µFcapacitor stabilizes this feedback action. Q2’s zener dropallows the circuit to produce controlled outputs all the waydown to 0V. This arrangement permits a 0V-2.5V input atA3 to produce a corresponding 0V-10V varactor bias.Figure 115, a spectral plot of the circuit running at 7.6MHz,shows the second harmonic down 35dB, with the thirdharmonic down almost 60dB. Resolution bandwidth is3kHz.

Complete AM Radio Station

A complete microphone-to-antenna AM radio station ap-pears in Figure 116.13 The carrier is generated by A1, setup as a quartz stabilized oscillator similar to the onedescribed in Figure 111. A1’s output feeds A2, functioningas a modulated RF power output stage. A2’s input signalrange is restricted by the bias applied to offset pins 1 and

Application Note 47

AN47-51

Note 14: Operating frequency subject to FCC approval and assignment. SeeFootnote 13 and Appendix G.Note 15: Seasoned readers of LTC literature, a hardened corps, mayrecognize this and other circuits in this publication as updated versions ofprevious LTC applications. The partial repetition is justified based on improvedspecifications and/or simplification of the original circuit.

Figure 114. Varactor Tuned 1MHz-10MHz Wien Bridge Oscillator

Figure 115. Spectrum Analysis for the Varactor Tuned WienBridge. Harmonics are at Least 34dB Down From Fundamental

LTAN47 • TA114

Ω100

0.1 F

+

1 Fµ

A1LT1006

+

–

µ

Ω

AGC

1N4148MOUNT CLOSE

1.5k

1k

3.8k(SELECT)

1k

–5V250Ω

10k

10k

10k

Q12N4393

360

Ω360

100kMV-1405

VARACTOR BIAS

≈ 0V-10V

OSCILLATOR

2Vp-pOUTPUT

0V-2.5V = 1MHz 10MHz OUT

2.5kA3

LT1006

+

–

1N4148

NC

LT1172

GND V FB

E1

E2

VSWVIN NC

L1150 Hµ

+5V

Q22N3904

22 F

1N4148

7.5k

VARACTORBOOST

A2LT1191

+

–

L1 = TOKO#262LYF0095K

MV-1405

C

µ

LT10041.2V

→

THIS SECTION MAY BE DELETED IF 10V SUPPLY IS AVAILABLE≥

0.1µF

100k

8 (see LT1194 data sheet for details). A3, a microphoneamplifier, supplies bias to these pins, resulting in anamplitude modulated RF carrier at A2’s output. The DCterm summed with the microphone biases A3’s output tothe appropriate level for good quality modulation charac-teristics. Calibration of this circuit involves trimming the

100Ω potentiometer in the oscillator for a stable 1Vp-p1MHz A1 output.14

Figure 117 shows typical AM carrier output at the antenna.In this case the modulation is supplied by Mr. Chuck Berry,singing “Johnny Be Goode”.

APPLICATIONS SECTION III - DATA CONVERSION

1Hz-1MHz Voltage-Controlled Sine Wave Oscillator

The oscillators presented to this point have limited fre-quency tuning range. Although Figure 118 is not a trueoscillator, it produces a synthesized sine wave output overa wide dynamic range. Many applications such as audio,shaker table driving and automatic test equipment requirevoltage-controlled oscillators (VCO) with a sine waveoutput. This circuit meets this need, spanning a 1Hz-1MHzrange (120dB or 6 decades) for a 0V to 10V input. Itmaintains 0.25% frequency linearity and 0.40% distortionspecifications.15 To understand the circuit, assume Q5 is

Application Note 47

AN47-52

LTAN47 • TA116

50Ω

1k

A1LT1190

+

–#345 LAMP

1MHz

A2LT1194

+

–

9k

A3LT1007

+

–

200Ω

1

10k

MODULATION AMPLIFIER

MICROPHONE

FINAL

OSCILLATOR

1k8

–5V

75k

1k

ANTENNA

Figure 116. A Complete AM Radio Station. Don’t Forget Your Advertisers and FCC License (See Appendix G)

LTAN47 • TA117

HORIZ = 5ms/DIV

A = 2V/DIV

Figure 117. Chuck Berry Lays a Little Modulation on the1MHz Carrier

on and its collector (Trace A, Figure 119) is at –15V,cutting off Q1. The positive input voltage is inverted by A3,which biases the summing node of integrator A1 throughthe 3.6k resistor and the self-biased FETs. A current, –I, ispulled from the summing point. A2, a precision op amp,DC stabilizes A1. A1’s output (Trace B, Figure 119) inte-grates positive until C1’s input (Trace C) crosses 0V. Whenthis happens, C1’s inverting output goes negative, the Q4-Q5 level shifter turns off, and Q5’s collector goes to +15V.This allows Q1 to come on. The resistors in Q1’s path arescaled to produce a current, +2I, exactly twice the absolutemagnitude of the current, –I, being removed from the

summing node. As a result, the net current into thejunction becomes +I and A1 integrates negatively at thesame rate as its positive excursion.

When A1 integrates far enough in the negative direction,C1’s “+” input crosses zero and its outputs reverse. Thisswitches the Q4-Q5 level shifter’s state. Q1 goes off andthe entire cycle repeats. The result is a triangle waveformat A1’s output. The frequency of this triangle is dependenton the circuit’s input voltage and varies from 1Hz to 1MHzwith a 0V-10V input. The LT1009 diode bridge and theseries-parallel diodes provide a stable bipolar referencewhich always opposes the sign of A1’s output ramp. TheSchottky diodes bound C1’s “+” input, assuring it cleanrecovery from overdrive.

The AD639 trigonometric function generator, biasedvia A4, converts A1’s triangle output into a sine wave(Trace D).

The AD639 must be supplied with a triangle wave whichdoes not vary in amplitude or output distortion will result.At higher frequencies, delays in the A1 integrator switch-ing loop result in late turn on and turn off of Q1. If thesedelays are not minimized, triangle amplitude will increasewith frequency, causing distortion level to also increasewith frequency. The total delay generated by the LT1016,

Application Note 47

AN47-53

Figure 118. 1Hz-1MHz Sine Wave Output VCO Has 0.25% Linearity and 0.4% Distortion

HORIZ = 500ns/DIV

A = 50V/DIV

LTAN47 • TA119

B = 5V/DIV

C = 1V/DIV

D = 5V/DIV

E = 0.5V/DIV

Figure 119. Sine Wave VCO Waveforms

LTAN47 • TA118

X1X2U1U2COM

AD639VRY1Y2

+VCCWZ1Z2

GTUP–V

68k

68k

–15V

+15V

A4LT1122

2

34

7

6

3.48k*

5.36k*

–15V

+15V

–15V

+15V

OUTPUT 1Hz-1MHzSINE WAVE

10kDISTORTION

TRIM

+

–

1kFREQUENCY TRIM

3.65k*C1

LT1016 +15V

–15V

2.2k

4.7k

4.7k

LT10092.5V

1000pF

–15V

+15V

Q5

820

4.7k

820

0.1

820

430

Q42N2907

22pF

4.2k

240pF(POLYSTYRENE)

A1LT1122

8pF

Q2 Q3A3LT1097

10k*

LOW FREQUENCYSYMMETRY

6M

1.74k* 100 HIGHFREQUENCYSYMMETRY

Ω

3.6k*

+15V

–15V

10k*

6.8pF

10k

EIN0V-10V Q1

+

–

+

–

100k

+

–10k

A2LT1150

+

–

300pFOPTIONAL OFFSET SERVO(SEE TEXT)

* 1% FILM RESISTOR

FET = 2N4391

= 1N4148

NPN = 2N2369

= HP5082-2810

1kDISTORTION

TRIM

+2I

–I

the Q4-Q5 level shifter, and Q1 is 14ns. This small delay,combined with the 22pF feedforward network at theLT1016’s input, keeps distortion to just 0.40% over theentire 1MHz range. At 100kHz, distortion is typically inside0.2%. The effects of gate-source charge transfer, whichhappens whenever Q1 switches, are minimized by the 8pFunit in Q1’s source line. Without this capacitor, a sharpspike would occur at the triangle peaks, increasingdistortion. The Q2-Q3 FETs compensate the temperature-dependent on-resistance of Q1, keeping the +2I/–Irelationship constant with temperature.

This circuit features extremely fast response to inputchanges, something most sine wave circuits cannot do.

Application Note 47

AN47-54

Figure 121. 1Hz-10MHz V-to-F Converter. Linearity is 0.03% with 50ppm/°C Drift

HORIZ = 10µs/DIV

A = 5V/DIV

LTAN47 • TA120

B = 5V/DIV

C = 5V/DIV

Figure 120. Sine Wave Output VCO Step Response isQuick and Clean

+5V

8

1.2k

+15V

Ω100

150pF

5pFCOMPARATOR

C1LT1016

A1LT1122

–5V

1k

+

15pF(POLYSTYRENE)

Q1

Q2

68pF

+

–+

–10k*

2k6MHzTRIM

INPUT0V–10V

10k

–5V

+5V0.02

36kA2LTC1050

–

+ 10 Fµ

START-UP1k 10M

–5V

4.7 Fµ

0.1 F

+15V +15V

A4LT1010

100k*

A3LT1006

–

+

100k*

6.8Ω

470Ω

–15V

LM134

LT1034-1.2V

LT1034-2.5V

Q3

Q4

2.2M*

20k10MHz

TRIM

OUTPUT1Hz–10MHz

LTAN47 • TA121

2N2369

74HC14

=

=

µ

µ

+V

+

INTEGRATOR

C1

+5VREFREFERENCE

LT137

OUT IN

ADJ

300

1002 Fµ Ω

Ω

–5V –15V

∑

DCSTABILIZATION

(OPTIONALSEE TEXT)

REFERENCESWITCH

+

* = 1% METAL FILM/10ppm/°C

BYPASS ALL IC’s WITH 2.2 F ON EACH SUPPLY DIRECTLY AT PINS

Figure 120 shows what happens when the input switchesbetween two levels (Trace A). A1’s triangle output (TraceB) shifts frequency immediately, with no glitching or poordynamics. The sine output (Trace C), reflecting this action,is similarly clean. To adjust this circuit, put in 10.00V andtrim the 100Ω pot for a symmetrical triangle output at A1.

Next, put in 100µV and trim the 100k pot for trianglesymmetry. Then, put in 10.00V again and trim the 1kfrequency trim adjustment for a 1MHz output frequency.Finally, adjust the distortion trim potentiometers for mini-mum distortion as measured on a distortion analyzer(Trace E, Figure 119). Slight readjustment of the otherpotentiometers may be required to get lowest possibledistortion. If operation below 100Hz is not required, the A2based DC stabilization stage may be deleted. If this is done,A1’s positive input should be grounded.

1Hz-10MHz V → → → → → F Converter

The LT1016 and the LT1122 high speed FET amplifiercombine to form a high speed V → F converter in Figure121. A variety of circuit techniques are used to achieve a1Hz to 10MHz output. Overrange to 12MHz (VIN = 12) isprovided. This circuit has a wider dynamic range (140dBor 7 decades) than any commercially available unit. The10MHz full-scale frequency is 10 times faster than cur-rently available monolithic V → Fs. The theory of operationis based on the identity Q = CV.

Application Note 47

AN47-55

LTAN47 • TA122

HORIZ = 100ns/DIV

A = 0.5V/DIV

B = 5V/DIV

C = 20mA/DIV

D = 1V/DIV

Figure 122. 10MHz V-to-F’s Operating Waveforms. LT1122Integrator is Completely Reset in 60ns

Each time the circuit produces an output pulse, it feedsback a fixed quantity of charge (Q) to a summing node (∑).The circuit’s input furnishes a comparison current at thesumming node. The difference signal at the node isintegrated in a monitoring amplifier’s feedback capacitor.The amplifier controls the circuit’s output pulse generator,completing a feedback loop around the integrating ampli-fier. To maintain the summing node at zero, the pulsegenerator runs at a frequency which permits enoughcharge pumping to offset the input signal. Thus, the outputfrequency will be linearly related to the input voltage. A1 isthe integrating amplifier.

0.05µV/°C offset drift performance is obtained by stabiliz-ing A1 with A2, a chopper stabilized op amp. A2 measuresthe DC value of the negative input, compares it to ground,and forces the positive input to maintain offset balance inA1. Note that A2 is configured as an integrator and cannotsee high frequency signals. It functions only at DC and lowfrequency.

A1 is arranged as an integrator with a 68pF feedbackcapacitor. When a positive voltage is applied to the input,A1’s output integrates in a negative direction (Trace A,Figure 122). During this period, C1’s inverting output islow. The paralleled HCMOS inverters form a referencevoltage switch. The reference voltage is established by theLM134 current source driven LT1034’s and the Q3-Q4combination. Additionally, a small input voltage relatedterm is summed into the reference, improving overallcircuit linearity. A3-A4 provides low drift buffering, pre-senting a low impedance reference to the paralleledinverter’s supply pin. The HCMOS outputs give low resis-tance, essentially errorless switching. The referenceswitch’s output charges the 15pF capacitor via Q1’s path.

When A1’s output crosses zero, C1’s inverting outputgoes high and the reference switch (Trace B) goes toground. This causes the 15pF unit to dispense charge intothe summing node via Q2’s VBE. The amount of chargedispensed is a direct function of the voltage the 15pF unitwas charged to (Q = CV). Q1 and Q2 are temperaturecompensated by Q3 and Q4 in the reference string. Thecurrent through the 15pF unit (Trace C) reflects the chargepumping action. The removal of current from A1’s sum-ming junction (Trace D) causes the junction to be drivenvery quickly negative. The initial negative-going 15ns

transient at A1’s output is due to amplifier delay. The inputsignal feeds directly through the feedback capacitor andappears at the output. When the amplifier finally responds,its output (Trace A) slew limits as it attempts to regaincontrol of the summing node. The class A 1.2kΩ pull-upand the RC damper at A1’s output minimizes erroneousoutput movement, enhancing this slew recovery. Theamount of time the reference switch remains at grounddepends on how long it takes A1 to recover and the 5pF-1000Ω hysteresis network at C1. This 60ns interval is longenough for the 15pF unit to fully discharge. After this, C1changes state, the reference switch swings positive, thecapacitor is recharged and the entire cycle repeats. Thefrequency at which this oscillation occurs is directly re-lated to the voltage-input-derived current into the sum-ming junction. Any input current will require a corre-sponding oscillation frequency to hold the summing pointat an average value of 0V.

Maintaining this relationship at megahertz frequenciesplaces severe restrictions on circuit timing. The key toachieving 10MHz full-scale operating frequency is theability to transmit information around the loop as quicklyas possible. The discharge-reset sequence is particularlycritical and is detailed in Figure 123. Trace A is the A1integrator output. Its ramp output crosses 0V at the firstleft vertical graticule division. A few nanoseconds later,C1’s inverting output begins to rise (Trace B), switchingthe reference switch to ground (Trace C). The referenceswitch begins to head towards ground about 16ns afterA1’s output crosses 0V. 2ns later, the summing point(Trace D) begins to go negative as current is pulled fromit through the 15pF capacitor. At 25ns, C1’s inverting

Application Note 47

AN47-56

LTAN47 • TA123

HORIZ = 10ns/DIV

A = 0.2V/DIV(UNCALIBRATED)

B = 2V/DIV

C = 5V/DIV

D = 0.5V/DIV

Figure 123. Detail of 60ns Reset Sequence (Whoosh!)

Note 16: See References 7, 8 and 28.

output is fully up, the reference switch is at ground, and thesumming point has been pulled to its negative extreme.Now, A1 begins to take control. Its output (Trace A) slewsrapidly in the positive direction, restoring the summingpoint. At 60ns, A1 is in control of the summing node andthe integration ramp begins again.

Start-up and overdrive conditions could force A1’s outputto go to the negative rail and stay there. The AC-couplednature of the charge dispensing loop can preclude normaloperation and the circuit may latch. The remaining HCMOSinverter provides a watchdog function for this condition. IfA1’s output rails negative the reference switch tries to stayat ground. The remaining inverter goes high, lifting A1’spositive input. This causes A1’s output to slew positive,initiating normal circuit action. The 1k-10µF combinationand the 10M-inverter input capacitance limit start-up loopbandwidth, preventing unwanted outputs.

The LM134 current source driving the reference string hasa built in 0.33%/°C thermal coefficient, causing slightvoltage modulation in the Q3-Q4 pair over temperature.This small change (≈ +120 ppm/°C) opposes the –120ppm/°C drift in the 15pF polystyrene capacitor, aiding overallcircuit tempco.

To trim this circuit, apply exactly 6V at the input and adjustthe 2kΩ potentiometer for 6.000MHz output. Next, put inexactly 10V and trim the 20k unit for 10.000MHz output.Repeat these adjustments until both points are fixed. A2’slow drift eliminates a zero adjustment. If operation below600Hz is not required, A2 and its associated componentsmay be deleted.

Linearity of this circuit is 0.03% with full-scale drift of50ppm/°C. Zero point error, controlled by A2, is 0.05Hz/°C.

8-Bit, 100ns Sample-Hold

Figure 124 shows a simple, very fast sample-hold circuit.This circuit will acquire a ±5V input to 8-bit accuracy in100ns. Hold step is inside 1/4 LSB with hold settling inside25ns. Aperture time is 4ns and droop rate about 1/2 LSB/µs.

The input is fed to a Schottky switching bridge via invertingbuffer A1. The Schottky bridge, similar to types used insampling oscilloscopes16, gives 1ns switching and elimi-nates the charge pump-through that a FET switch wouldcontribute. The switching bridge’s output feeds outputamplifier A2. A2, configured as an integrator, is the actualhold amplifier. Its output is fed back to the switchingbridge’s input, forming a summing point with A1’s outputresistor. This feedback loop places the bridge within aloop, enhancing accuracy.

The bridge is switched by driving the sample-hold inputline. Q1 and Q2 drive L1’s primary. L1’s secondariesprovide complementary drive to the bridge with almost notime skewing.

Figure 125 shows the circuit acquiring a full scale step.Trace A is the input command while Trace B is A2’s output.The aberration visible in A2’s output when switching intohold (hold step) is due to minute residual AC imbalancesin the bridge. Figure 126 studies this effect in high resolu-tion detail, with the hold step trim deliberately discon-nected. After A2’s output nominally settles at final value,the circuit is switched into hold. The bridge imbalanceallows a small parasitic charge to be displaced into A2’ssumming point, causing A2 to step 10mV higher (in thiscase). If the trim is connected and properly adjusted, itsupplies a small compensatory charge during switching.Figure 127 shows the effect of this on the output. Thesettled hold output is the same as the acquired value. Totrim this circuit, ground the input while pulsing the sample-hold control line. Next, adjust the trim for minimal ampli-tude step between the sample and hold states.

In contrast to low frequency sample-hold circuits thisdesign cannot pass signal if left in the sample mode. Thetransformer’s inherent AC coupling precludes such opera-tion. Similarly, extended sample mode duration (e.g.,>500ns) will cause transformer saturation, resulting inerroneous outputs and excessive Q1-Q2 dissipation. If

Application Note 47

AN47-57

10

470 *Ω

A2LT1220

+

–

1k

2pFHOLD STEP

TRIM

20pF

1k 20pF

500Ω

A1LT1220

+

–

1k*

1k*INPUT5V

100Ω

Ω

+15V

10Ω

–15V

0VHOLD

SAMPLE5V

Q12N3904

Q22N3906

20pF(POLYSTYRENE)

= 1N5711, MATCHED 20mV

L1 = PULSE ENGINEERING PE-2229X 1:1:1 *= 0.1% FILM RESISTOR

OUTPUT±5V

±

3

4

1

2

5

6

470 *Ω

LTAN47 • TA124

L1

Figure 124. 8-Bit, 100ns Sample-Hold

HORIZ = 50ns/DIV

A = 2V/DIV

LTAN47 • TA125

B = 1V/DIV

Figure 125. Fast Sample-Hold Acquiring a Full-Scale Input

extended logic high durations are possible at the controlinput, it should be AC coupled.

15ns Current Summing Comparator

Figure 128 shows a way to build a high speed currentcomparator with resolution in the 12-bit range. Currentcomparison, the fastest way to compare D→A outputs andanalog values, is commonly used in high speed A→Dconverters and instrumentation. A1 is set up as a Schottkybounded amplifier. The bound diodes prevent A1 from

HORIZ = 50ns/DIV

A = 10mV/DIV(ON 5V LEVEL)

LTAN47 • TA126

Figure 126. Hold Step with Mis-Adjusted Compensation

saturating due to excessive summing point overdrive,aiding response time. The 3pF capacitor, a typical value,compensates DAC output capacitance and is selected forbest amplifier damping. The 10k feedback resistor, alsotypical, is chosen for best gain-bandwidth performance.Voltage gains of 4 to 10 are common. Figure 129 showsperformance. Trace A, a test input, causes A1’s output(Trace B) to slew through zero (screen center horizontalline). When A1 crosses zero, C1’s input biases negative andit responds (C1’s output is Trace C) 10ns later with a TTL

Application Note 47

AN47-58

HORIZ = 10ns/DIV

A = 5V/DIV

LTAN47 • TA129

B = 0.5V/DIV

C = 2V/DIV

Figure 129. Fast Summing Comparator’s Waveforms.Total Delay is 15ns

HORIZ = 50ns/DIV

A = 10mV/DIV(ON 5V LEVEL)

LTAN47 • TA127

Figure 127. Hold Step with Properly Adjusted Compensation

LTAN47 • TA128

+

–+

–

2k

EIN

I

TYPICALISOURCE

A1LT1191

10k

3pF

C1LT1016

OUTPUT

= HP5082-2810

DAC

Figure 128. Fast Summing Comparator

Note 17: This technique is borrowed from oscilloscope trigger circuitry. SeeReference 29.

output. Total elapsed time from the test input arriving at aTTL high until the comparator output achieves a TTL highis inside 15ns.

50MHz Adaptive Threshold Trigger Circuit

Figure 130 is an extremely versatile trigger circuit. Design-ing a fast, stable trigger is not easy and often entails aconsiderable amount of discrete circuitry. This circuitreliably triggers from DC-50MHz over a 2mV-300mV inputrange with no level adjustment required.

A1, a gain of ten preamplifier, feeds an adaptive triggerconfiguration identical to the one described in Figure 97’sfiber optic receiver. The adaptive trigger maintains the A3output comparator’s trip point at 1/2 input signal ampli-tude, regardless of its magnitude. This insures reliableautomatic triggering over a wide input amplitude range,even for very low level inputs. As an option, the network

shown in dashed lines permits changing the trip thresh-old. This allows any point on the input waveform edge tobe selected as the actual trigger point.17

Figure 131 shows performance for a 40MHz input sinewave (Trace A). A1’s output (Trace B) takes gain and theA3 comparator gives a clean logic output (Trace C). At thehighest frequencies, any bandwidth limiting in A1 is irrel-evant; the adaptive trigger threshold will simply varyratiometrically to maintain circuit output.

Fast Time-to-Height (Pulsewidth-to-Voltage)Converter

The circuit of Figure 132 allows very short pulsewidths (inthis case 250ns full-scale) to be determined to a typicalaccuracy of 1%. Digital methods of achieving similarresults dictate clock speeds of 1GHz, which is cumber-some. In addition, processor based approaches usingaveraging techniques require repetitive pulses which thiscircuit does not. Circuits of this type are frequently re-quired in automatic test equipment and nuclear and highenergy physics work where determination of shortpulsewidths is a common requirement.

The circuit functions by charging a capacitor during theperiod of a pulsewidth. When the pulse ends, chargingceases and the voltage across the capacitor is proportionalto the width of the pulse.

Application Note 47

AN47-59

Figure 130. 50MHz Trigger with Adaptive Threshold

HORIZ = 50ns/DIV

A = 0.1V/DIV

LTAN47 • TA131

B = 0.1V/DIV

C = 5V/DIV

Figure 131. The Trigger Responds to a 40MHz Input. InputAmplitude Variations from 2mV-300mV Have No Effect

Note 18: See Reference 45.

–

+

A1LT1222

–

+

A2LT1097

–

+A3

LT1016

TO Q3 EMITTER

TO Q4 EMITTER

TO A2+INPUT

500pF

22M

0.005

3k

3kPNP = 2N3906NPN = 2N3904

0.005

Q3Q1

INPUT

900Ω

100Ω

3pF

+5V

–5V

Q4Q2

500pF

300Ω22M

0.1

OUTPUT

OPTIONALSEE TEXT

AN47 F130

The input pulse to be measured (Trace A, Figure 133)simultaneously biases the 74C221 dual one shot and Q3.Q3, aided by Baker18 clamping, capacitive feedforwardand optimized DC base biasing, turns off in a few nanosec-onds. Current source Q2’s emitter forward biases and Q2

supplies constant current to the 100pF integrating capaci-tor. Q1 supplies temperature compensation for Q2, withthe 2.5V LT1009 referencing the current source. Q2’scollector (e.g., the 100pF capacitor) charges in rampfashion (Trace B). A1 supplies a buffered output (Trace C).When the input pulse ends, Q3 rapidly turns on, reversebiasing Q2’s emitter and turning off the current source.A1’s voltage is directly proportional to the input pulsewidth. A monitoring A → D converter can acquire thisdata.

After a time set by the 74C221’s RC programmed delay, apulse appears at its Q2 output (Trace D). This pulse turnson Q4, discharging the 100pF capacitor to zero andreadying the circuit for the next input pulse.

This circuit’s accuracy and resolution are crucially depen-dent on minimizing delay in switching the Q1-Q2 currentsource. Figure 134 provides amplitude and time expandedversions of critical circuit waveforms. Trace A is the inputpulse and Trace B is A1’s input, showing the beginning ofthe ramp’s ascent. Trace C, A1’s output, shows about 13nsdelay from A1’s input. Traces D and E, A1’s input and

Application Note 47

AN47-60

Figure 132. Fast Time-to-Height Converter

HORIZ = 20ns/DIV

A = 5V/DIV(UNCALIBRATED)

LTAN47 • TA134

B = 0.2V/DIVC = 0.2V/DIV

D = 0.5V/DIVE = 0.5V/DIV

Figure 134. Detail of Time-to-Height Converter’sRamp Switching

HORIZ = 200ns/DIV

A = 20V/DIV

LTAN47 • TA133

B = 10V/DIV

C = 10V/DIV

D = 20V/DIV

Figure 133. Time-to-Height Converter Acquires a 250ns Pulse

–

+

A1LT1220

LT10092.5V

1kSCALE FACTOR

+15V

+15V

+15V

+15V

OUTPUT0V–10V

INPUT0ns–250ns AN47 F132

15V

0V

–15V

1k

20pF

20pF2k

2k

2kR1 C1 Q1 A2

B2A1

C2Q2 74C221= 1N4148

= HP 5082-2810= POLSTYRENE= 2N5771= 2N2369= 2N2222

PNPQ3 NPNQ4 NPN

B1R2

10k

3k100pF† 100pF

4.7k

Q3

Q4

Q1

†

Q2

output respectively, record similar A1 delays for rampturn-off. The photo reflects the extremely fast currentsource switching; the vast majority of delay is due to A1’sdelay. A1’s delay is far less critical than current sourceswitching delays; A1 will always settle to the correct valuewell before the one shot resets the circuit. In practice, amonitoring A → D converter should not be triggered untilabout 50ns after the circuit’s input pulse has ceased. Thisgives A1 plenty of time to catch up to the 100pF capacitor’ssettled value.

As mentioned, current source switching speed is essentialfor good results. Figure 135 details current source turn off.Trace A is the circuit’s input pulse rising edge and Trace Bshows the top of the ramp. Turn off occurs in a fewnanoseconds. Similar speed is characteristic of the input’sfalling edge (current source turn on). Additionally, it isnoteworthy that circuit accuracy and resolution limits areset by the difference in current source turn on and offdelays. As such, the effective overall delay is extremelysmall.

Application Note 47

AN47-61

HORIZ = 10ns/DIV

A = 2V/DIV(UNCALIBRATED)

LTAN47 • TA135

B = 0.2V/DIV

Figure 135. Current Source Turn-Off Detail for the Time-to-Height Converter

Note 19: Complete details on this device and a discussion on thermalconversion considerations are found in Reference 40.

HEATER

INPUT

HEATER

THERMALINSULATION

DC OUTPUT

AN47 F136

DC AMPLIFIER

TEMPERATURESENSOR

TEMPERATURESENSOR

To calibrate this circuit, put in a 250ns width pulse and trimthe 1kΩ potentiometer for 10V output. The circuit willconvert pulse widths from 20ns to 250ns to a typicalaccuracy of 1%. The 20ns minimum measurable width isdue to inability to fully discharge the 100pF capacitor. Ifthis is objectionable, Q4 can be replaced with a lowersaturation device or A1’s output can be offset.

True RMS Wideband Voltmeter

Most AC RMS measurements use logarithmic techniquesto compute the waveform’s RMS value. This method limitsbandwidth to below 1MHz and crest factor performance toabout 10:1. Practically speaking, a waveform’s RMS valueis defined as its heating value in the load. Specializedinstruments employ thermally based assemblies that com-pute the RMS value of the input. The thermal methodprovides substantially improved bandwidth and crest fac-tor capability compared to logarithmically based converters.

Thermal RMS-DC converters are direct acting, thermo-electronic analog computers. The thermal technique isexplicit, relying on first principles. The simple operationpermits wideband performance unattainable with implicit,indirect methods based on logarithmic computing.

Figure 136 shows a classic scheme for implementing athermally based RMS-DC converter. Here, the DC ampli-fier forces a second, identical, heater-sensor pair to thesame thermal conditions as the input driven pair. Thisdifferentially sensed, feedback enforced loop makes am-bient temperature shifts a common-mode term, eliminat-ing their effect. Also, although the voltage and thermal

interaction is non-linear, the input-output voltage relation-ship is linear with unity gain. The ability of this arrange-ment to reject ambient temperature shifts depends on theheater-sensor pairs being isothermal. This is achievableby thermally insulating them with a time constant wellbelow that of ambient shifts. If the time constants to theheater-sensor pairs are matched, ambient temperatureterms will affect the pairs equally in phase and amplitude.The DC amplifier will reject this common-mode term. Notethat, although the pairs are isothermal, they are insulatedfrom each other. Any thermal interaction between thepairs reduces the system’s thermally based gain terms.This would cause unfavorable signal-to-noise performance,limiting dynamic operating range. Figure 136’s output islinear because the matched thermal pair’s non-linearvoltage-temperature relationships cancel each other.

Figure 136. Conceptual Thermal RMS-DC Converter

The advantages of this approach have made its use popu-lar in thermally based RMS-DC measurements. Typically,the assembly is composed of matched heater resistors,sensors and thermal insulation. These assemblies arerelatively large and expensive to produce. Figure 137’seconomical wideband thermally based voltmeter is basedon a monolithic thermal converter. The LT1223 providesgain, and drives the LT1088 RMS-DC thermal converter.19

The LT1088’s temperature sensing diodes are biased fromthe supply. A1, set up as a differential servo amplifier witha gain of 9000, extracts the diode’s difference signal andbiases Q1. Q1 drives one of the LT1088’s heaters, com-pleting a loop. The 3300pF capacitor gives a stable roll-off.

Application Note 47

AN47-62

Figure 137. Wideband True RMS Voltmeter

0.1 F

50 *(120 FOR 50 INPUT)

LTAN47 • TA137

+

–

A3LT1223

µ

Ω900

INPUT

ΩΩ

Ω2503

2 Ω50

7

14

1Ω

–15V

LT1088

Ω250

Ω50

13 6 8

12 5

0.01 Fµ

10

9

1k*

9.09M*0.01 Fµ

15V

+

–A1

1/2 LT1013

500Ω

2.7k*

1k Q12N2219

1k*

1.5M0.022 Fµ

1k

9.09M*

3300pF

2.7k*

15V

ZERO TRIM(TRIM AT 10%

OF FULL-SCALE)

3k

+

–

A21/2 LT1013

10k*

VOUT

10k*

10k FULL-SCALE

TRIM

*1% FILM RESISTORV FULL-SCALE = 0.5V FOR 250 RANGE 0.5V FOR 50 RANGE

ΩΩ

IN

LT10041.2V

The 1.5M-0.022µF combination improves settling by re-ducing gain during output slew. The LT1088’s square-lawthermal gain means overall loop gain is lower for smallinputs. Normally, this would result in slow settling forvalues below about 10%-20% of scale. The LT1004 1k-3knetwork is a simple breakpoint, boosting amplifier gain inthis region to improve settling. A2, a gain trimmableoutput stage, serves to compensate for gain variations inthe two sides of the LT1088. To trim the circuit, put inabout a 10% scale DC signal (e.g., 0.05V). Adjust the zerotrim so that VOUT = VIN. Next, apply a full-scale DC inputand set the full-scale trim to that value at the output.Repeat the trims until both are fixed well within 1% of full-scale. An alternate trim scheme involves applying noinput, grounding Q1’s base and setting the zero trim untilA1’s output is active. Then, unground Q1’s base, apply afull-scale input and trim the full-scale adjustment for thatvalue at the output.

Figure 138 is a plot of error vs input frequency. TheLT1088 is specified at 2% to 100MHz (50Ω heater) or 1%to 20MHz (250Ω heater). As such, most of the errorshown is due to bandwidth restrictions in A3, but perfor-mance is still impressive. The plots include data taken atvarious input levels into both heaters. A 500mV input into250Ω dips to 1% at 8MHz and 2.5% at 14MHz beforepeaking badly beyond 17MHz. This input level forces a 9.5VRMS output at A3, introducing large signal bandwidthlimitations. The 400mV input to the 250Ω heater showsessentially flat results to 20MHz, the LT1088’s 250Ωheater specification limit.

The 50Ω heater provides significantly wider bandwidth,although A3’s 50mA output limits maximum input toabout 100mVRMS (1.76VRMS at the LT1088).

Application Note 47

AN47-63

FREQUENCY (MHz)

0–10

OUTP

UT E

RROR

(%)

–6

0

2

6

10

5 15 25 35

LTAN47 • TA138

–8

–4

–2

4

8

10 20 30

V = 200mV 50 HEATER

IN RMSΩ

V = 500mV 250 HEATER

IN RMSΩ

VIN = 100mVRMS50Ω HEATER

V = 400mV 250 HEATER

IN RMSΩ

V = 50mV 50 HEATER

IN RMSΩ

Figure 138. Accuracy Plot for the RMS Voltmeter

APPLICATIONS SECTION IV - MISCELLANEOUSCIRCUITS

RF Leveling Loop

Figure 137’s wideband AC conversion can be applied inother areas. A common RF requirement is to stabilize theamplitude of a waveform against variations in input, timeand temperature. Instruments and transmitters frequentlyrequire this function, which is not easy if waveform puritymust be maintained. Figure 139A shows a 25MHz RFleveling loop. The RF input is applied to the AD539wideband multiplier. The multiplier’s output drives A1.A1’s output is converted to DC by the LT1088 based RMS-DC converter (see previous circuit). A servo amplifiercompares this output with a settable DC reference andbiases the multiplier’s control channel, completing a loop.The 0.33µF capacitor provides frequency compensationby rolling off gain at a frequency well below the responseof the LT1088 servo. The loop maintains the output’s25MHz RMS amplitude at the DC reference’s value. Changesin load, input, power supply and other variables arerejected.

Figure 139B, a similar circuit, offers significantly lowercost although performance is not quite as good. The RFinput is applied to LT1228 A1, an operational transcon-ductance amplifier. A1’s output feeds LT1228 A2, a cur-rent feedback amplifier. A2’s output, the circuit’s output,is sampled by the A3 based gain control configuration.This arrangement, similar to the gain control loops de-scribed in Figures 112 and 114, closes a gain control loopback at A1. The 4pF capacitor compensates rectifier diode

capacitance, enhancing output flatness vs frequency. A1’sISET input current controls its gain, allowing overall outputlevel control. This approach to RF leveling is simple andinexpensive, although output drift, distortion and regula-tion are somewhat higher than in the previous circuit.

Voltage Controlled Current Source

Figure 140 shows a voltage controlled current source withload and control voltage referred to ground. This simple,powerful circuit produces output current in accordancewith the sign and magnitude of the control voltage. Thecircuit’s scale factor is set by resistor R. A1, biased by VIN,drives current through R (in this case 10Ω) and the load.A2, sensing differentially across R, closes a loop back toA1. The load current is constant because A1’s loop forcesa fixed voltage across R. The 2k-100pF combination setsroll off and the configuration is stable. Figure 141 showsdynamic response. Trace A is the voltage control inputwhile Trace B is the output current. Response is quick andclean, with delay of 5ns and no slew residue or aberration.

High Power Voltage Controlled Current Source

Figure 142 is identical to the basic current source, exceptthat it adds a 1A booster stage (adapted from Figure 104)for increased output power. Including the booster insideA1’s feedback loop eliminates its DC errors. Note that thebooster’s current limiting features have been removed,because of this circuit’s inherent current limiting nature ofoperation. Figure 143 shows this circuit’s response to beas clean as the lower power version, although delay isabout 20ns slower. It is worth mentioning that the loopstability considerations involved in placing A2 and thebooster in A1’s feedback path are significant. This circuitreceives treatment in Appendix C, “The Oscillation Prob-lem - Frequency Compensation Without Tears”.

18ns Circuit Breaker

Figure 144 shows a simple circuit which will turn offcurrent in a load 18ns after it exceeds a preset value. Thiscircuit has been used to protect integrated circuits duringdevelopmental probing and is also useful for protectingexpensive loads during trimming and calibration. Thecircuit’s versatility is enhanced because one side of theload is grounded. Under normal conditions, Q1’s emitter(Trace A, Figure 145, is Q1’s current, and Trace C is its

Application Note 47

AN47-64

Figure 139A. RF Leveling Loop

Figure 139B. Simple RF Leveling Loop

+

–A3

LT1006

LTAN47 • TA139B

+

–

A2CFA

1/2 LT1228

100Ω

10kRF INPUT0.6VRMS-1.3VRMS

25MHz

300Ω

–15V

+15V

+

–

A1OTA

1/2 LT1228

470Ω

10Ω

0.01

10k

0.01

+15V

–15V

4pF

10k

100k

AMPLITUDEADJUST

10k 4.7k–15V

LT10041.2V

10k

OUTPUT2Vp-p

1N4148’s COUPLE THERMALLY

1k Ω

LTAN47 • TA139A

3

2

1

8

7

6

+

–

RF INPUT0.6VRMS-1.3V 25MHz

RMS

0.1CONTROL

HF COMPCH1INPUT

CH2INPUTINPUTCOMMONOUTPUTCOMMON

14

11

12

13

CH1OUTPUT

CH2OUTPUT

BASE COMMON

AD539

+

–

A1LT1223

20 Ω0.33

A2LT1006

15V

SERVO AMPLIFIER

330Ω

100k LT1088(SEE FIGURE 137)

10kLT10341.2V

1k15V

25MHzLEVELLED OUTPUT1VRMS

MULTIPLIER

1N914

RMS-DC CONVERTER

50Ω INPUT

AMPLITUDEADJUST

Application Note 47

AN47-65

Ω

LTAN47 • TA140

+

–

A1LT1190

100pF

+

–

A2LT1194A =10

R10

LOAD

2k

E R 10

INI =×

EIN0V TO ±3V

LTAN47 • TA141

HORIZ = 10ns/DIV

A = 0.5V/DIVB = 5mA/DIV

Figure 142. High Power, Wideband Voltage Controlled Current Source

Figure 140. Fast, Precise, Voltage Controlled Current Sourcewith Grounded Load

Figure 141. Dynamic Response of the Current Source. Delay is4ns, with Clean Settling

LTAN47 • TA142

–5V

+5V

Q2

Ω0.5

Ω0.5

Q6

2pF

1k

Q4

1k

22+

–5V

+5V

====

2N51602N38662N3375FERRITE BEADS FERRONICS #21-110J

Q1,Q5Q2,Q3Q4,Q6

1N4148

Ω

+

–

A1LT1190

100pF

+

–

A2LT1194A =10

R0.33

LOAD

2k

E R 10

INI =×

100Ω

EIN0V TO ±3V

Q3

Q1

22 +

Q5

Application Note 47

AN47-66

LTAN47 • TA143

HORIZ = 20ns/DIV

A = 0.5V/DIV

B = 0.2A/DIV

Ω

LTAN47 • TA144

+

–

D TO A CONVERTER

TYPICAL TRIP SET SOURCES

LOAD

TRIP SET 0mA-250mA = 0V-2.5V

200CALIBRATE

9001k*

10 METAL FILM5W (10 1001/2W IN PARALLEL)

Ω

Ω

1k*

9k*

9k*A1

LT1193

FB

A2LT1016

L

1k

RESET(NORMALLY OPEN)

300Ω33pF

2.4k–5V

Q22N2369

330

Q12N3866

+28V

* 1% FILM RESISTORA1, A2 USE 5V SUPPLIES±

+

–

Figure 145. Operating Waveforms for the 18ns Circuit Breaker.Circuit Output (Trace C) is Shut Down 18ns After Output Current(Trace A) Begins to Rise

LTAN47 • TA145

HORIZ = 10ns/DIV

A = 0.1A/DIV

B = 1V/DIV

C = 10V/DIV

D = 2V/DIV

Figure 144. 18ns Circuit Breaker with Voltage Programmable Trip Point

Figure 143. 1A Pulse Response of the High Power CurrentSource

voltage) is biased on, supplying power to the load via the10Ω current shunt. Differential amplifier A1’s output re-sides below comparator A2’s voltage programmed trippoint and Q2 is off. When an overload occurs, Q1’s emittercurrent begins to increase (Trace A, just prior to the thirdvertical division). A1’s output (Trace B) begins to rise as ittracks the increase in the 10Ω shunt’s voltage. The 9k-1kdividers keep A1 inputs inside their common-mode range.Simultaneously, Q1’s emitter voltage (Trace C) begins todrop as it beta limits. When A1’s version of the load currentexceeds A2’s trip point, A2 (Trace D) goes high, turning onQ2. Q2’s turn on steals Q1’s base drive, turning off the load

current. Local positive feedback at A2’s latch pin causes itto latch in this off state. When the load fault has beencleared, the pushbutton can be used to reset the circuit.The delay from the onset of excessive load current tocomplete shutdown is inside 18ns. The 4ns delay of TraceA’s current probe should be factored in when interpretingwaveforms. To calibrate this circuit, ground Q2’s base andinstall a 250mA load. Adjust the 200Ω trim for a 2.5Voutput at A1. Next, remove the load, unground Q2’s baseand press the reset button. Finally, put in the desired tripset voltage and the circuit is ready for use.

Application Note 47

AN47-67

REFERENCES

1. Orwiler, Bob, “Oscilloscope Vertical Amplifiers”,Tektronix, Inc., Concept Series. (1969)

2. Williams, Jim, “Techniques and Equipment for Cur-rent Measurement”, Appendix C, in “Step Down Switch-ing Regulators”, Linear Technology Corporation, Ap-plication Note 35. (August 1989)

3. Addis, John, “Fast Vertical Amplifiers and Good Engi-neering”, in Analog Circuit Design; Art, Science andPersonalities, Butterworths. (1991)

4. Brown, Lloyd A., “The Story of Maps” pp. 226-240.Little, Brown. Boston, Massachusetts. (1949)

5. Willsberger, Johann, “Clocks and Watches”, Dial Press.(1975)

6. Mercer, Vaudrey, “John Arnold and Son – Chronom-eter Makers 1762-1843”, Antiquarian HorologicalSociety, London. (1972)

7. Tektronix, Inc., “Type 1S1 Sampling Plug-In Operat-ing and Service Manual”, Tektronix, Inc. (1965)

8. Mulvey, J., “Sampling Oscilloscope Circuits”,Tektronix, Inc., Concept Series. (1970)

9. Williams, Jim, “About Probes and Oscilloscopes”,Appendix B, in “High Speed Comparator Techniques”,Linear Technology Corporation, Application Note 13.(April 1985)

10. Williams, Jim, “Evaluating Oscilloscope Overload Per-formance”, Box Section A, in “Methods for MeasuringOp Amp Settling Time”, Linear Technology Corpora-tion, Application Note 10. (July 1985)

11. Williams, Jim and Huffman, Brian, “Instrumentationfor Converter Design”, Appendix F, in “Some Thoughtson DC-DC Converters”, Linear Technology Corpora-tion, Application Note 29. (October 1988)

12. Gilbert, Barrie, “Where Do Little Circuits Come From”in Analog Circuit Design; Art, Science and Personali-ties, Butterworths. (1991)

13. Williams, Jim, “Should Ohm’s Law Be Repealed?”, inAnalog Circuit Design; Art, Science and Personalities,Butterworths. (1991)

14. Williams, Jim, “Methods for Measuring Op Amp Set-tling Time”, Linear Technology Corporation, Applica-tion Note 10. (July 1985)

15. Demerow, R., “Settling Time of Operational Amplifi-ers”, Analog Dialogue, Volume 4-1, Analog Devices,Inc. (1970)

16. Pease, R.A., “The Subtleties of Settling Time”, TheNew Lightning Empiricist, Teledyne Philbrick. (June1971)

17. Harvey, Barry, “Take the Guesswork Out of SettlingTime Measurements”, EDN. (September 19, 1985)

18. Addis, John, “Sampling Oscilloscopes”, Private Com-munication. (February, 1991)

19. Williams, Jim, “Bridge Circuits – Marrying Gain andBalance”, Linear Technology Corporation, ApplicationNote 43. (June 1990)

20. Meacham, L.A., “The Bridge Stabilized Oscillator”,Bell System Technical Journal, Vol. 17, p. 574. (Octo-ber 1938)

21. Hewlett, William R., “A New Type Resistance-CapacityOscillator”, M.S. Thesis, Stanford University, PaloAlto, California. (1939)

22. Hewlett, William R., U.S. Patent No. 2,768,872. (Janu-ary 6, 1942)

23. Bauer, Brunton, “Design Notes on the Resistance-Capacity Oscillator Circuit”, Parts I and II, Hewlett-Packard Journal, Hewlett-Packard. (November, De-cember 1949)

24. Black, H.S., “Stabilized Feedback Amplifier”, Bell Sys-tem Technical Journal, Vol. 13, p. 1. (January 1934)

25. Tektronix, Inc., Type 111 Pretrigger Pulse GeneratorOperating and Service Manual, Tektronix, Inc. (1960)

26. Analog Devices, Inc., “Linear Products Databook”,AD834 Datasheet, pp. 6-43 to 6-48. (1988)

27. Analog Devices, Inc., “Multiplier Application Guide”,Analog Devices, Inc. (1978)

Application Note 47

AN47-68

Note: This application note was derived from a manuscriptoriginally prepared for publication in EDN Magazine.

28. Hewlett-Packard, “Schottky Diodes for High-Volume,Low Cost Applications”, Application Note 942, Hewlett-Packard Company. (1973)

29. Tektronix, Inc., “Trigger Circuit – Peak-Peak Auto-matic Operation”, Model 2235 Oscilloscope ServiceManual, Tektronix, Inc. (1983)

30. Wien, Max, “Measung der induction constanten mitdern Optischen Telephon”, Ann. der Phys., Vol. 44, pp.704-707. (1891)

31. Dostal, J., “Operational Amplifiers”, Elsevier. (1981)

32. Philbrick Researches, “Applications Manual for Op-erational Amplifiers”, Philbrick Researches. (1965)

33. Sheingold, D.H., “Analog-Digital Conversion Hand-book”, Prentice-Hall. (1986)

34. Bunze, V., “Matching Oscilloscope and Probe forBetter Measurements”, Electronics, pp. 88-93. (March1, 1973)

35. Williams, Jim, “High Speed Comparator Techniques”,Linear Technology Corporation, Application Note 13.(April 1985)

36. Morrison, Ralph, “Grounding and Shielding Tech-niques in Instrumentation”, 2nd Edition, WileyInterscience. (1977)

37. Hewlett-Packard, “Threshold Detection of Visible andInfra-Red Radiation with PIN Photodiodes”, Applica-tion Note 915, Hewlett-Packard Company.

38. Roberge, J.K., “Operational Amplifiers: Theory andPractice”, Wiley Interscience. (1975)

39. Ott, Henry W., “Noise Reduction Techniques in Elec-tronic Systems”, Wiley Interscience. (1976)

40. Williams, Jim, “A Monolithic IC for 100MHz RMS-DCConversion”. Linear Technology Corporation, Appli-cation Note 22. (September 1987)

41. Lee, Marshall M., “Winning With People: The First 40Years of Tektronix”, Tektronix, Inc. (1986)

42. Weber, Joe, “Oscilloscope Probe Circuits”, Tektronix,Inc., Concept Series. (1969)

43. Chessman, M. and Sokol, N., “Prevent Emitter-Fol-lower Oscillation”, Electronic Design 13, pp. 110-113.(21 June 1976)

44. DeBella, G.B., “Stability of Capacitively-Loaded Emit-ter Followers – a Simplified Approach”, Hewlett-Packard Journal 17, pp. 15-16. (April 1966)

45. Baker, R.H., “Boosting Transistor Switching Speed”,Electronics, Vol. 31, pp. 190-193. (1957)

46. Williams, Jim, “Max Wien, Mr. Hewlett and a RainySunday Afternoon”, in Analog Circuit Design: Art,Science and Personalities, Butterworths. (1991)

AN47-69

Application Note 47

Application Note 47

AN47-70

AN47-71

Application Note 47

Application Note 47

AN47-72

AN47-73

Application Note 47

Application Note 47

AN47-74

AN47-75

Application Note 47

Application Note 47

AN47-76

AN47-77

Application Note 47

Application Note 47

AN47-78

AN47-79

Application Note 47

Application Note 47

AN47-80

AN47-81

Application Note 47

Application Note 47

AN47-82

Note 1: See Reference 3 for history and wisdom about vertical amplifiers.

Figure B1. One (Not Very Good) Way to Measure DAC-Op Amp Settling Time

APPENDIX B

Measuring Amplifier Settling Time

High resolution measurement of amplifier settling at highspeed is often necessary. Frequently, the amplifier isdriven from a digital-to-analog converter (DAC). In par-ticular, the time required for the DAC-amplifier combina-tion to settle to final value after an input step is especiallyimportant. This specification allows setting a circuit’stiming margins with confidence that the data produced isaccurate. The settling time is the total length of time frominput step application until the amplifier output remainswithin a specified error band around the final value.

Figure B1 shows one way to measure DAC amplifiersettling time. The circuit uses the false sum node tech-nique. The resistors and amplifier form a summing net-work. The amplifier output will step positive when the DACmoves. During slew, the oscilloscope probe is bounded bythe diodes, limiting voltage excursion. When settling oc-curs, the summing node is arranged so the oscilloscopeprobe voltage should be zero. Note that the resistordivider’s attenuation means the probe’s output will be one-half the actual settled voltage.

In theory, this circuit allows settling to be observed tosmall amplitudes. In practice, it cannot be relied upon toproduce useful measurements. Several flaws exist. Theoscilloscope connection presents problems. As probecapacitance rises, AC loading of the resistor junction willinfluence observed settling waveforms. The 20pF probeshown alleviates this problem but its 10X attenuation

sacrifices oscilloscope gain. 1X probes are not suitablebecause of their excessive input capacitance. An active 1XFET probe might work, but another issue remains.

The clamp diodes at the probe point are intended to reduceswing during amplifier slewing, preventing excessive os-cilloscope overdrive. Unfortunately, oscilloscope over-drive recovery characteristics vary widely among differenttypes and are not usually specified. The diodes’ 600mVdrop means the oscilloscope may see an unacceptableoverload, bringing displayed results into question (for adiscussion of oscilloscope overdrive considerations, seethe Tutorial Section on Oscilloscopes). With the oscillo-scope set at 1mV per division, the diode bound allows a600:1 overdrive. Schottky diodes can cut this in half, butthis is still much more than any real-time vertical amplifieris designed to accommodate.1 The oscilloscope’s over-load recovery will completely dominate the observedwaveform and all measurements will be meaningless.

One way to achieve reliable settling time measurements isto clip the incoming waveform in time, as well as ampli-tude. If the oscilloscope is prevented from seeing thewaveform until settling is nearly complete, overload isavoided. Doing this requires placing a switch at the settlecircuit’s output and controlling it with an input-triggered,variable delay. FET switches are not suitable because oftheir gate-source capacitance. This capacitance will allowgate drive artifacts to corrupt the oscilloscope display,

+

LTAN47 • TAB1

–

2k

2k

SCOPE PROBE — 20pF OR LESSTO SCOPE 2mV/DIV≤

AUT

CCOMP

DAC

50ΩPULSE

GENERATOR

VOUT

FALSE SUM NODE

–V SETTLED

OUT

INPUT STEPTO SCOPE

AN47-83

Application Note 47

Note 2: The Q1-Q4 bridge switching scheme, a variant of one described inReference 14, was developed at LTC by George Feliz.Note 3: See References 7, 8 and 18.Note 4: See Reference 17.Note 5: Construction details of the settling time fixture discussed hereappear (literally) in Appendix F, “Additional Comments on Breadboarding”.Also see the Tutorial Section on Breadboarding Techniques.Note 6: See Reference 17.

producing confusing readings. In the worst case, gatedrive transients will be large enough to induce overload,defeating the switch’s purpose.

Figure B2 shows a way to implement the switch whichlargely eliminates these problems. This circuit allowssettling within 1mV to be observed. The Schottky sam-pling bridge is the actual switch. The bridge’s inherentbalance, combined with matched diodes and very highspeed complementary bridge switching, yields a cleanswitched output. An output buffer stage unloads the settlenode and drives the diode bridge.

The operation of the DAC-amplifier is as before. Theadditional circuitry provides the delayed switching func-tion, eliminating oscilloscope overdrive. The settle node isbuffered by A1, a unity gain broadband FET input bufferwith 3pF input capacitance and 350MHz bandwidth. A1drives the Schottky bridge. The pulse generator’s outputfires the 74123 one shot. The one shot is arranged toproduce a delayed (controllable by the 20k potentiometer)pulse whose width (controllable by the 5k potentiometer)sets diode bridge on-time. If the delay is set appropriately,the oscilloscope will not see any input until settling isnearly complete, eliminating overdrive. The sample win-dow width is adjusted so that all remaining settling activityis observable. In this way the oscilloscope’s output isreliable and meaningful data may be taken. The one shot’soutput is level shifted by the Q1-Q4 transistors, providingcomplementary switching drive to the bridge. The actualswitching transistors, Q1-Q2, are UHF types, permittingtrue differential bridge switching with less than 1ns of timeskew.2 The bridge’s output may be observed directly (byoscilloscopes with adequate sensitivity) or A2 provides atimes 10 amplified version. A2’s gain of 20 (and the directoutput’s ÷ 2 scaling) derives from the 2k-2k settle nodedividers attenuation. A third output, taken directly fromA1, is also available. This output, which bypasses theentire switching circuitry, is designed to be monitored bya sampling oscilloscope. Sampling oscilloscopes are in-herently immune to overload.3 As such, a good test of thissettling time test fixture (and the above statement) is tocompare the signals displayed by the sampling ‘scope andthe Schottky-bridge-aided real time ‘scope. As an addi-tional test, a completely different method of measuringsettling time (albeit considerably more complex) describedby Harvey4 was also employed. If all three approaches

represent good measurement technique and are con-structed properly, results should be identical.5 If this is thecase, the identical data produced by the three methods hasa high probability of being valid. Figures B3, B4 and B5show settling time details of an AD565A DAC and anLT1220 op amp. The photos represent the samplingbridge, sampling ‘scope and Harvey methods, respec-tively. Photos B3 and B5 display the input step for conve-nience in ascertaining elapsed time. Photo B4, taken witha single trace sampling oscilloscope (Tektronix 1S1 withP6032 cathode follower probe in a 556 mainframe) usesthe leftmost vertical graticule line as its zero time refer-ence. All methods agree on 280ns to 0.01% settling (1mVon a 10V step). Note that Harvey’s method inherently adds30ns, which must be subtracted from the displayed 310nsto get the real number.6 Additionally, the shape of thesettling waveform, in every detail, is identical in all threephotographs. This kind of agreement provides a highdegree of credibility to the measured results.

Some poorly designed amplifiers exhibit a substantialthermal tail after responding to an input step. This phe-nomenon, due to die heating, can cause the output towander outside desired limits long after settling has ap-parently occurred. After checking settling at high speed, itis always a good idea to slow the oscilloscope sweep downand look for thermal tails. Often the thermal tail’s effect canbe accentuated by loading the amplifier’s output. Such atail can make an amplifier appear to have settled in a muchshorter time than it actually has.

To get the best possible settling time from any amplifier,the feedback capacitor, CF, should be carefully chosen.CF’s purpose is to roll-off amplifier gain at the frequencywhich permits best dynamic response. The optimumvalue for CF will depend on the feedback resistor’s valueand the characteristics of the source. DAC’s are one of themost common sources and also one of the most difficult.DAC’s current outputs must often be converted to a

Application Note 47

AN47-84

LTAN47 • TAB2

+

–

+15V

–15V

AD565A

5pF

AUTLT1220

+15V

–15V

2k**

2k**

D8 D9

A1EL2004

+15V

–15V

PULSEGENERATOR

INPUT

1.1k

1.1k

2.2kD5

D6

820Ω

Q1 Q2

D7470

0.1 10+560

–5V

Q3 Q4

51Ω 51Ω 680Ω

0.1 10+

–5V

500OFFSET

Ω

0.110

LT1021-10IN OUT

GND

NC

–15V

+

–

A2LT1222

68 *Ω

1.3k*

SETTLE NODE 10×

SETTLE NODE 2÷

500Ω

VCC RC1 C1 Q1 Q2 CLR2 B2 A2

5.1k

5k

4.7k

+5V

A1 B1 CLR1 Q1 Q2 C2 RC2 GND

74123

30pF

20kDELAY

5.1k

+5V

+5V

4.7k

V = SETTLE NODE2

***

D1-D4D5-D9Q3, Q4Q1, Q2

======

TRIM RATIO FOR DAC-ALL BITS HIGH = 0V AT SETTLE NODE1% FILM RESISTOR1N57121N57112N3904MRF501

BYPASS ALL ACTIVE DEVICES

50Ω

OUTPUT TO SAMPLING OSCILLOSCOPE

+

+5V

+5V1000pF

SETTLENODE

10k

SAMPLE WINDOW WIDTH

OUTPUTS TO REAL TIME OSCILLOSCOPE

2.2k

Figure B2. Settling Time Test Circuit Using a Sampling Bridge Eliminates Oscilloscope Overdrive

AN47-85

Application Note 47

LTAN47 • TAB3

HORIZ = 100ns/DIV

A = 5V/DIV

B = 4mV/DIV

Figure B3. 280ns Settling Time as Measured by Figure B2’sCircuit. Sampling Switch Closes Just Before Third VerticalDivision, Allowing Settling Detail to be Observed WithoutOverdriving the Oscilloscope

HORIZ = 100ns/DIV

A = 4mV/DIV

LTAN47 • TAB4

Figure B4. 280ns Settling Time as Measured at Figure B2’sSampling Oscilloscope Output by a Sampling ‘Scope. SettlingTime and Waveform Shape is Identical to Figure B3

LTAN47 • TAB5

HORIZ = 100ns/DIV

A = 5V/DIV

B = 4mV/DIV

Figure B5. 280ns Settling Time as Measured by Harvey’sMethod. After Subtraction of this Method’s Inherent 30ns Delay,Settling Time and Waveform Shape are Identical toFigures B3 and B4

amplifier’s input. The capacitance introduces feedbackphase shift at high frequencies, forcing the amplifier tohunt and ring about the final value before settling. DifferentDACs have different values of output capacitance. CMOSDACs have the highest output capacitance and it varieswith code. Bipolar DACs typically have 20pF-30pF ofcapacitance, stable over all codes. Because of their outputcapacitance, DAC’s furnish an instructive example in am-plifier compensation. Figure B6 shows the response of anindustry standard DAC-80 type and a relatively slow (forthis publication) op amp. Trace A is the input, while TracesB and C are the amplifier and settle outputs, respectively.In this example no compensation capacitor is used and theamplifier rings badly before settling. In Figure B7, an 82pFunit stops the ringing and settling time goes down to 4µs.The overdamped response means that CF dominates thecapacitance at the AUT’s input and stability is assured. Iffastest response is desired, CF must be reduced. Figure B8shows critically damped behavior obtained with a 22pFunit. The settling time of 2µs is the best obtainable for thisDAC-amplifier combination. Higher speed is possible withfaster amplifiers and DACs but the compensation issuesremain the same.

voltage. Although an op amp can easily do this, care isrequired to obtain good dynamic performance. A fast DACcan settle to 0.01% in 200ns or less but its output alsoincludes a parasitic capacitance term, making the amplifier’sjob more difficult. Normally, the DAC’s current output isunloaded directly into the amplifier’s summing junction,placing the parasitic capacitance from ground to the

Application Note 47

AN47-86

LTAN47 • TAB6

HORIZ = 1 s/DIV

A = 5V/DIV

B = 5V/DIV

C = 0.01V/DIV

µ

Figure B6. No Feedback Capacitor

LTAN47 • TAB7

HORIZ = 2µs/DIV

A = 5V/DIV

B = 5V/DIV

C = 0.01V/DIV

Figure B7. Relatively Large Feedback Capacitor

LTAN47 • TAB8

HORIZ = 1 s/DIV

A = 5V/DIV

B = 5V/DIV

C = 0.01V/DIV

µ

Figure B8. Reduced Feedback Capacitor Gives Fastest Settling

Figures B6-B8. Effects of Different Feedback Capacitors on a DAC-Op Amp Combination

APPENDIX C

The Oscillation Problem – Frequency CompensationWithout Tears

All feedback systems have the propensity to oscillate.Basic theory tells us that gain and phase shift are requiredto build an oscillator. Unfortunately, feedback systems,such as operational amplifiers, have gain and phase shift.The close relationship between oscillators and feedbackamplifiers requires careful attention when an op amp isdesigned. In particular, excessive input-to-output phaseshift can cause the amplifier to oscillate when feedback isapplied. Further, any time delay placed in the amplifier’sfeedback path introduces additional phase shift, increas-ing the likelihood of oscillation. This is why feedback loopenclosed stages can cause oscillation.

A large body of complex mathematics is available whichdescribes stability criteria and can be used to predictstability characteristics of feedback amplifiers. For themost sophisticated applications, this approach is requiredto achieve optimum performance.

However, little has appeared which discusses, in practicalterms, how to understand and address the issues ofcompensating feedback amplifiers. Specifically, a practi-cal approach to stabilizing amplifier-power gain stagecombinations is discussed here, although the consider-ations can be generalized to other feedback systems.

Oscillation problems in amplifier-power booster stagecombinations fall into two broad categories; local and loop

AN47-87

Application Note 47

oscillations. Local oscillations can occur in the booststage, but should not appear in the IC op amp, whichpresumably was debugged prior to sale. These oscilla-tions are due to transistor parasitics, layout and circuitconfiguration-caused instabilities. They are usually rela-tively high in frequency, typically in the 0.5MHz to 100MHzrange. Usually, local booster stage oscillations do notcause loop disruption. The major loop continues to func-tion, but contains artifacts of the local oscillation. TextFigure 101, repeated here as Figure C1 for reader conve-nience, furnishes an instructive example. The Q1, Q2emitter follower pair has reasonably high ft. These deviceswill oscillate if driven from a low impedance source (seeinsert, Figure C1 and References 43 and 44). The 100Ωresistor and the ferrite beads are included to make the opamps output look like a higher impedance to preventproblems. Q5 and Q6, also followers, have even higher ft,but are driven from 330Ω sources, eliminating theproblem.The photo in Figure C2 shows Figure C1 follow-ing an input with the 100Ω resistor and ferrite beadsremoved. Trace A is the input, while Trace B is the output.The resultant high frequency oscillation is typical of locallycaused disturbances. Note that the major loop is func-tional, but the local oscillation corrupts the waveform.

Eliminating such local oscillations starts with device se-lection. Avoid high ft transistors unless they are needed.When high frequency devices are in use, plan layoutcarefully. In very stubborn cases, it may be necessary to

lightly bypass transistor junctions with small capacitors orRC networks. Circuits which use local feedback can some-times require careful transistor selection and use. Forexample, transistors operating in a local loop may requiredifferent fts to achieve stability. Emitter followers arenotorious sources of oscillation and should never bedirectly driven from low impedance sources (again, seeReferences 43 and 44).

Loop oscillations are caused when the added gain stagesupplies enough delay to force substantial phase shift.This causes the control amplifier to run too far out of phasewith the gain stage. The control amplifier’s gain combinedwith the added delay causes oscillation. Loop oscillationsare usually relatively low in frequency, typically 10Hz-1MHz.

Figure C1. Figure 101’s Booster Circuit with a Few Components Removed Begins Our Study of Loop Stability

LTAN47 • TAC1

INPUT1k

1k 3pF

100ΩBOOSTERINPUT

1k

1k

Q1 Q3

Q4Q2

–15V+15V

330Ω

330Ω

2Ω

2Ω

Q6

Q5

–15V

+15V

OUTPUT

330Ω50

+V

Ω

TYPICAL EMITTER FOLLOWER OSCILLATOR

= FERRITE BEAD, FERRONICS #21-110JQ1, Q4 = 2N3906Q2, Q3 = 2N3904

Q5 = 2N3866Q6 = 2N5160

THESE COMPONENTS REMOVED F0R FIGURE C2†

†

†

†

+

–LT1220

ACGROUND

LTAN47 • TAC2

HORIZ = 1 s/DIV

A = 5V/DIV

B = 5V/DIV

µ

Figure C2. Local Oscillations Due to Booster Stage Instabilities

Application Note 47

AN47-88

1MHz gain-bandwidth. The LT1010’s 20MHz gain-band-width introduces negligible loop delay, and dynamics areclean. In this case, the LT1006’s internal roll-off is wellbelow that of the output stage and stability is achieved withno external compensation components. Figure C5 uses a100MHz bandwidth LT1223 as the control amplifier. Theassociated photo (Figure C6) shows the results. Here, thecontrol amplifier’s roll-off is well beyond the output stage’s,causing problems. The phase shift through the LT1010 isnow appreciable and oscillations occur. Stabilizing thiscircuit requires degenerating the control amplifier’s gain-bandwidth.

Ω

LTAN47 • TAC5

LT1223

1kINPUT

Ω1k

OUTPUTLT1010

+

–

Figure C5. A Fast Op Amp and a Medium Speed Booster

LTAN47 • TAC6

HORIZ = 1µs/DIV

A = 5V/DIV

B = 5V/DIV

Figure C6. Loop Oscillation is “Free” When the Op Amp is MuchFaster than the Booster

The fact that the slower op amp circuit doesn’t oscillate isa key to understanding how to compensate booster loops.With the slow device, compensation is free. The fasteramplifier makes the AC characteristics of the output stagebecome significant and requires roll-off components forstability. Practically, the LT1223’s speed is simply toomuch for the LT1010. A somewhat slower amplifier is theway to go. Alternately, a faster booster may be employed.Figure C7 attempts this, but doesn’t quite make it. PhotoC8 is less corrupted, but 100MHz oscillation indicates thebooster stage (borrowed from text Figure 101) is still tooslow for the LT1223. Attempts to use another boosterdesign in Figure C9 (similarly purloined from text Figure

A good way to eliminate loop-caused oscillations is to limitthe gain-bandwidth of the control amplifier. If the boosterstage has higher gain-bandwidth than the control ampli-fier, its phase delay is easily accommodated in the loop.When control amplifier gain-bandwidth dominates, oscil-lation is assured. Under these conditions, the controlamplifier hopelessly tries to servo a feedback signal whichconsistently arrives too late. The servo action takes theform of an electronic tail chase with oscillation centeredaround the ideal servo point.

Frequency response roll-off of the control amplifier willalmost always cure loop oscillations. In many situations itis preferable to brute force compensation using largecapacitors in the major feedback loop. As a general rule, itis wise to stabilize the loop by rolling off control amplifiergain-bandwidth. The feedback capacitor serves only totrim step response and should not be relied on to stopoutright oscillation.

Figures C3 and C4 illustrate these issues. The LT1006amplifier used with the LT1010 current buffer producesthe output shown in Figure C4. As before, Trace A is theinput and Trace B the output. The LT1006 has less than

Ω

LTAN47 • TAC3

LT1006

1kINPUT

Ω1k

OUTPUTLT1010

+

–

Figure C3. A Slow Op Amp and a Medium Speed Booster

LTAN47 • TAC4

HORIZ = 20 s/DIV

A = 10V/DIV(INVERTED)

B = 10V/DIV

µ

Figure C4. Loop Stability is “Free” When the Op Amp is MuchSlower than the Booster

AN47-89

Application Note 47

current source, reproduced here as Figure C13, is aninteresting variation. There is no power booster in theloop, but rather a 40MHz differential amplifier with a gainof 10. To stabilize the circuit the slowest amplifier in the1190 family, the 50MHz LT1190, is chosen. The local100pF feedback slows it down a bit more and the loop isfast and stable (Figure C14). What happens if we removethe 100pF feedback path? Figure C15 shows that the loopis no longer stable under this condition because theLT1190 control amplifier cannot servo the phase shiftedfeedback at higher frequency. Put that 100pF capacitorback in!

It’s worth mentioning that similar results to those obtainedback in Figure C3 are obtainable by substituting a veryslow control amplifier (e.g., an LT1006 which has lessthan 1MHz gain-bandwidth). The slower amplifier wouldgive “free” compensation, eliminating the necessity forthe 100pF unit. However, the circuit’s frequency responsewould be severely degraded.

Text Figure 142’s high power current source furnishesfurther instruction. This loop contains the differentialamplifier and a booster, seemingly making things evenmore difficult. Figure C16, recognizable as text Figure142’s high power current source with the 100pF localcompensation removed, oscillates above 10MHz. Replac-ing the compensation restores proper response. Figure

Figure C7. A Very Fast Amplifier with a Fast Booster

104) fail for the same reason. Figure C10 shows 40MHzoscillation, indicative of this high power booster’s slowerspeed.

Figure C11 has much more pleasant results. Here a 45MHzgain-bandwidth LT1220 has been substituted for the100MHz LT1223 in Figure C7’s circuit. The slower ampli-fier, combined with light local compensation, works wellwith the booster stage in its loop. Figure C12 shows a wellcontrolled high speed output, nicely damped, with no signof oscillations.

Power boosters are not the only things that can be placedwithin an amplifier’s feedback loop. Text Figure 140’s

LTAN47 • TAC8

HORIZ = 100ns/DIV

A = 5V/DIV

B = 5V/DIV

Figure C8. Figure C7’s Booster is Not Quite Quick Enough toPrevent Loop Oscillation

–

+LT1223

1k

–15V

+15V

–15V

+15V

1k

1kINPUT

1k

100ΩBOOSTER

INPUT

1kΩ

1kΩ

2Ω

2Ω

Q1 Q3

Q2

OUTPUT

Q6

Q4

Q5

= FERRITE BEAD, FERRONICS #21-110J= 2N3906= 2N3904= 2N3866= 2N5160

Q1,Q4Q2,Q3

Q5Q6

LTAN47 • TAC7

Application Note 47

AN47-90

Figure C9. A Very Fast Amplifier with a Fast High Power Booster

LTAN47 • TAC10

HORIZ = 200ns/DIV

A = 5V/DIV

B = 5V/DIV

Figure C10. C9’s High Power Booster is Fast But Causes LoopOscillations

C17 shows the loop has no oscillations. What this tells usis that the control amplifier doesn’t care just what gener-ates the causal feedback between its input and output, solong as there isn’t excessive delay. This circuit has a fairlybusy feedback loop, but the control amplifier is obliviousto its bustling nature....unless you leave that 100pF feed-back capacitor out!

When compensating loops like these, remember to inves-tigate the effects of various loads and operating condi-tions. Sometimes a compensation scheme which appearsfine gives bad results for some conditions. For this reason,check the completed circuit over as wide a variety ofoperating conditions as possible.

LTAN47 • TAC9

+

–1k

LT1223

INPUTΩ100

–15V

+15V

Q2

1k

1k

0.5Ω

0.5Ω

Q5 Q6

2pF

1k

Q3

Q4

1k

22+

22+

–15V

+15V

1k

OUTPUT

=======

1N41482N39062N39042N33752N38662N5160FERRITE BEAD, FERRONICS #21-110J

Q1,Q8Q2,Q7Q4,Q6

Q3Q5

Q8

Q7Q1

AN47-91

Application Note 47

Figure C11. Figure 101 (Again) with 100Ω Resistor and Beads Reinstalled

LTAN47 • TAC12

HORIZ = 20ns/DIV

A = 2V/DIVB = 2V/DIV

(INVERTED)

Figure C12. Lovely!

Ω

LTAN47 • TAC13

+

–LT1190

100pF

+

–

LT1194A =10

R10

LOAD

2k

EIN 0V TO ±3V

E R 10

INI =×

Figure C13. Figure 140’s Current Source. What Do the RCComponents Do?

LTAN47 • TAC14

HORIZ = 10ns/DIV

A = 0.5V/DIVB = 5mA/DIV

Figure C14. Response of the Current Source with the RCComponents in Place

HORIZ = 500ns/DIV

B = 20mA/DIV

LTAN47 • TAC15

A = 2V/DIV

Figure C15. Removing the 100pF Capacitor Allows the Op Amp toSee Phase Shifted Feedback, Causing Oscillation. Put that100pF Back In!

–

+LT1220

1k

–15V

+15V

–15V

+15V

1k

1kINPUT

1k

3pF

100ΩBOOSTER

INPUT

1kΩ

1kΩ

2Ω

2Ω

Q1 Q3

Q2

OUTPUT

Q6

Q4

Q5

= FERRITE BEAD, FERRONICS #21-110J= 2N3906= 2N3904= 2N3866= 2N5160

Q1,Q4Q2,Q3

Q5Q6

LTAN47 • TAC11

Application Note 47

AN47-92

LTAN47 • TAC16

–5V

+5V

Q1

Q2

0.5Ω

0.5Ω

2pF

1k

Q3

Q4

1k

22+

22+

–5V

+5V

====

2N51602N38662N3375FERRITE BEAD, FERRONICS #21-110J

Q1,Q5Q2,Q3Q4,Q6

1N4148

+

–LT1190

+

–

LT1194A =10

R0.33Ω

LOAD

2k

EIN0V TO ±3V

E R 10

INI =×

100Ω

REMOVED FORSTABILITY TEST

100pF

Q5 Q6

Figure C16. Text Figure 142’s High Power Current Source. When the 100pF Capacitor is Removed, 10MHz Loop Oscillations Result

LTAN47 • TAC17

HORIZ = 20ns/DIV

A = 0.5V/DIV

B = 200mA/DIV

Figure C17. Much Better. Leave that 100pF Capacitor in There!

AN47-93

Application Note 47

APPENDIX D

Measuring Probe-Oscilloscope Response

Verifying the rise time limit of wideband test equipmentset-ups is a difficult task. In particular, the end-to-end risetime of oscilloscope-probe combinations is often requiredto assure measurement integrity. Conceptually, a pulsegenerator with rise times substantially faster than theoscilloscope-probe combination can provide this infor-mation. Figure D1’s circuit does this, providing a 1ns pulsewith rise and fall times inside 350ps. Pulse amplitude is10V with a 50Ω source impedance. This circuit, built intoa small box and powered by a 1.5V battery, provides asimple, convenient way to verify the rise time capability ofalmost any oscilloscope-probe combination.

The LT1073 switching regulator and associated compo-nents supply the necessary high voltage. The LT1073forms a flyback voltage boost regulator. Further voltagestep-up is obtained from a diode-capacitor voltage step-up network. L1 periodically receives charge and its flybackdischarge delivers high voltage events to the step-upnetwork. A portion of the step-up network’s DC output isfed back to the LT1073 via the 10M, 24k divider, closing acontrol loop.

The regulator’s 90V output is applied to Q1 via the 1M- 2pFcombination. Q1, a 40V breakdown device, non-destruc-tively avalanches when C1 charges high enough. Theresult is a quickly rising, very fast pulse across R4. C1

LTAN47 • TAD1

LT1073

VIN

SW1

FB

GND SW2

IL

1.5V TO 90V CONVERTER

1.5VAACELL

220Ω

0.47

0.47 0.47

L1150µH

10M*

24k*

+90VDCAVALANCHE BIAS

1M

10k R450Ω

Q12N2369SEE TEXT

OUTPUT

C12pF

AVALANCHE PULSE GENERATORL1

*

= TOKO 262-LYF-0095K

= MUR120

= 1% FILM RESISTORQ1 AND ASSOCIATED COMPONENTS LAYOUT SENSITIVE—SEE TEXT

discharges, Q1’s collector voltage falls and breakdownceases. C1 then recharges until breakdown again occurs.This action causes free running oscillation at about200kHz.1,2 Figure D2 shows the output pulse. A 1GHzsampling oscilloscope (Tektronix 556 with 1S1 samplingplug-in) measures the pulse at 10V high with about a 1nsbase. Rise time is 350ps, with fall time also indicating350ps. There is a slight hint of ring after the falling edge,but it is well controlled. The figures may actually be faster,as the 1S1 is specified with a 350ps limit.3

Figure D1. 350ps Rise/Fall Time Avalanche Pulse Generator

Note 1: This method of generating fast pulses borrows heavily from theTektronix type 111 Pretrigger Pulse Generator. See References 8 and 25.Note 2: This circuit replaces the tunnel diode based arrangement shown inAN13, Appendix D. While AN13’s circuit works well, it generates a smaller,more irregularly shaped pulse and the tunnel diodes have become quiteexpensive.Note 3: Just before going to press the pulse was measured at Hewlett-Packard Laboratories with a HP-54120B 12GHz sampling oscilloscope.Rise and fall times were 216ps and 232ps, respectively. Photo availableon request.

Q1 may require selection to get avalanche behavior. Suchbehavior, while characteristic of the device specified, is notguaranteed by the manufacturer. A sample of 50 Motorola2N2369s, spread over a 12 year date code span, yielded82%. All good devices switched in less than 650ps. C1 isselected for a 10V amplitude output. Value spread istypically 2pF-4pF. Ground plane type construction with

Application Note 47

AN47-94

LTAN47 • TAD3

Figure D3. Details of the Avalanche Pulse Generator’s Head. 90VDC Enters at Lower Right BNC, Pulse Exits at Top Left BNC.Note Short Lead Lengths Associated with Output

high speed layout techniques are essential for good re-sults from this circuit. Current drain from the 1.5V batteryis about 5mA.

Figure D3 shows the physical construction of the actualgenerator. Power, supplied from a separate box, is fed intothe generator’s enclosure via a BNC connector. Q1 ismounted directly at the output BNC connector, with ground-ing and layout appropriate for wideband operation. Leadlengths, particularly Q1’s and C1’s, should be experi-mented with to get best output pulse purity. Figure D4 isthe complete unit.HORIZ = 200ps/DIV

LTAN47 • TAD2

A = 2V/DIV

Figure D2. The Avalanche Pulse Generator’s Output Monitoredon a 1GHz Sampling Oscilloscope

AN47-95

Application Note 47

LTAN47 • TAD4

Figure D4. The Packaged Avalanche Pulser. 1.5V-90V Converter is in the Black Box. Avalanche Head is at Left

Application Note 47

AN47-96

APPENDIX E

An Ultra-Fast High Impedance Probe

Under most circumstances the 1pF-2pF input capacitanceand 10MΩ resistance of FET probes is more than adequatefor difficult probing situations. Occasionally, however,very high input resistance with high speed is needed. Atsome sacrifice in speed and input capacitance comparedto commercial probes, it is possible to construct such aprobe. Figure E1 shows schematic details. A1, a 350MHzhybrid FET buffer, forms the electrical core of the probe.This device is a low input capacitance, wideband FETsource follower driving a fast bipolar output stage. Theinput of the probe goes to this device via a 51Ω resistor,reducing the possibility of oscillations in the follower inputstage when the probe sees low AC impedance. A1’s outputdrives a guard shield around the probe’s input line, reduc-ing effective input capacitance to about 4pF. A groundreferred shield encircles the guard shield, reducing pickupand making high quality ground connections to the circuitunder test easy. A1 drives the output BNC cable to feed theoscilloscope. Normally, it is undesirable to back terminatethe cable at A1 because the oscilloscope will see only halfof A1’s output. While a back termination provides the bestsignal dynamics, the resulting attenuation is a heavypenalty. The RC damper shown can be trimmed for bestedge response while maintaining an unattenuated output.

What can’t be seen in the schematic is the probe’s physicalconstruction. Very careful construction is required to

maintain low input capacitance, low bias current and widebandwidth. The probe head is particularly critical. Everyeffort should be made to minimize the length of wirebetween A1’s input and the probe tip. In our lab, we havefound that discarded pieces of broken 10X probes, par-ticularly attenuator boxes and probe heads, provide anexcellent packaging basis for this probe.1 Figure E2 showsthe probe head. Note the compact packaging. Additionally,A1’s package is arranged so that it’s (not insubstantial)dissipated heat is transferred to the probe case body whenthe snap-on cover (shown in photo) is in place. Thisreduces A1’s substrate temperature, keeping bias currentdown. A1’s input is directly connected to the probe headto minimize parasitic capacitance. The power supply forA1, located in a separate enclosure, is fed in throughseparate wires. A1’s output is delivered to the oscilloscopevia conventional BNC hardware.

Figure E3 shows the probe output (Trace B) responding toan input (Trace A) as monitored on a 350MHz oscilloscope(Tektronix 485). Measured specifications for our versionof this probe include a rise time of 6ns, 6ns delay and58MHz bandwidth. The delay time contribution is aboutevenly split between the amplifier and cable. Input capaci-tance is about 4pF without the probe hook tip and 7pF withthe hook tip. Input bias current measured 400pA and gainerror about 5%. (A1 is an open loop device.)

Note 1: This is not to encourage or even accept the breakage of probes.The author regards the breakage of oscilloscope probes as the lowestpossible human activity. The sole exception to this condemnation is poorquality probes, which should be destroyed as soon as their deficienciesare discovered.

LTAN47 • TAE1

A1EL2004

51Ω

+15V

–15V

OUTIN

500Ω

75pF

50Ω

1 INCH

INPUT

50Ω3 FT CABLEBNC

OSCILLOSCOPEZIN

OPTIONALBACK TERMINATION

SEE TEXT

Figure E1. Ultra Fast Buffer Probe Schematic

AN47-97

Application Note 47

LTAN47 • TAE2

Figure E2. Physical Layout of Ultra Fast Buffer Probe

LTAN47 • TAE3

HORIZ = 2ns/DIV

A = 1V/DIV

B = 1V/DIV

Figure E3. Probe Response (Trace B) to Input Pulse (Trace A)

Application Note 47

AN47-98

LTA

N47

• T

AF

1

APPENDIX F

Additional Comments on Breadboarding

This section contains, in visual form, commentary onsome of the breadboards of the circuits described in thetext. The breadboards appear in roughly corresponding

order to their text presentation and comments are brief buthopefully helpful. The bit pushers have commented soft-ware; why not commented hardware?

Figu

re F

1. N

o

AN47-99

Application Note 47

LTA

N47

• T

AF

2

Figu

re F

2. N

o

Application Note 47

AN47-100

LTA

N47

• T

AF

3

Figu

re F

3. N

o

AN47-101

Application Note 47

LTA

N47

• T

AF

4

Figu

re F

4. P

roto

type

Ava

lanc

he P

ulse

r Und

er T

est.

Dire

ct C

onne

ctio

n to

Osc

illos

cope

Elim

inat

es C

able

or P

robe

Effe

cts

Application Note 47

AN47-102

LTA

N47

• T

AF

5

Figu

re F

5. C

lose

-Up

of P

roto

type

Ava

lanc

he P

ulse

Gen

erat

or. D

C Bi

as G

ener

ator

(Rig

ht S

ide

of B

oard

) is

Care

less

ly W

ired,

but

Pul

seFo

rmin

g Ci

rcui

try (L

eft S

ide

of B

oard

, by

BNC

Conn

ecto

r) is

Car

eful

ly a

nd T

ight

ly W

ired

AN47-103

Application Note 47

LTA

N47

• T

AF

6

Figu

re F

6. T

he S

ettli

ng T

ime

Test

Fix

ture

Des

crib

ed in

App

endi

x B.

DAC

and

Am

plifi

er a

re in

Cen

ter R

ight

of P

hoto

. Not

e Br

eak

in C

lad

Sepa

ratin

g An

alog

and

Dig

ital G

roun

ds a

nd A

ttent

ion

to L

ayou

t in

Switc

hing

Brid

ge (L

ower

Lef

t). S

witc

hing

Brid

ge is

Ret

urne

dSe

para

tely

to G

roun

d —

Its

Boar

d is

Mec

hani

cally

Sto

od-O

ff Fr

om M

ain

Boar

d by

10M

Ω R

esis

tors

. Out

put S

ectio

n, D

rivin

g th

e La

rge

P603

2 Fo

llow

er P

robe

, is

at L

ower

Rig

ht

Application Note 47

AN47-104

LTA

N47

• T

AF

7

Figu

re F

7. T

he X

1000

38M

Hz D

iffer

entia

l Am

plifi

er. D

C an

d Lo

w F

requ

ency

Ele

ctro

nics

use

Soc

kets

(For

egro

und)

and

Air W

ire T

echn

ique

s (C

ente

r Rig

ht) f

or E

asy

and

Fast

Bre

adbo

ardi

ng. W

ideb

and

Circ

uitry

Hug

s th

e Gr

ound

Plan

e, a

nd is

Clu

ster

ed N

ear t

he In

put B

NC

AN47-105

Application Note 47

LTA

N47

• T

AF

8

Figu

re F

8. In

put D

etai

l of X

1000

Diff

eren

tial A

mpl

ifier

. Cla

d Sh

ield

(Cen

ter R

ight

) Pre

vent

s BN

C Ra

diat

ion

from

Cor

rupt

ing

Low

Leve

l Circ

uitry

. Diff

eren

tial P

robe

Ver

ifies

Fid

elity

of 2

.5m

V Pu

lse

Out o

f the

X10

0 At

tenu

ator

Sta

cked

Sec

tions

. Not

e DI

P Pa

ckag

esHu

ggin

g Gr

ound

Pla

ne, W

hile

Can

s Op

erat

ing

at L

ow F

requ

ency

are

Car

eles

sly

Wire

d

Application Note 47

AN47-106

LTA

N47

• T

AF

9

Figu

re F

9. T

he D

iffer

entia

l Pro

be a

nd It

s 10

X At

tenu

ator

. Offs

et P

robe

Tip

s ar

e Co

nven

ient

for M

akin

g Di

ffere

ntia

l Con

nect

ions

, but

Sock

ets

Mai

ntai

n a

True

Coa

xial

Env

ironm

ent a

nd a

re P

refe

rred

AN47-107

Application Note 47

LTA

N47

• T

AF

10

Figu

re F

10. T

he P

hoto

diod

e Am

plifi

er L

ayou

t Em

phas

izes

Low

Cap

acita

nce

at A

mpl

ifier

(Loc

ated

Bel

ow T

rimm

erCa

paci

tor,

Pho

to C

ente

r Upp

er L

eft).

Ver

tical

Gua

rd S

hiel

d Br

eaks

Up

BNC

Radi

atio

n; w

as U

sed

Whe

n Ph

oto

Inpu

t was

Sim

ulat

ed w

ith a

Pul

se G

ener

ator

Application Note 47

AN47-108

Figu

re F

11. F

ast P

hoto

Inte

grat

or U

nder

Tes

t with

Pul

se G

ener

ator

Sim

ulat

ing

a Ph

oto

Inpu

t. BN

C Ra

diat

ion

isCo

ntro

lled

with

Ext

ensi

ve S

hiel

ding

at I

nteg

rato

r Inp

ut (J

ust V

isib

le U

pper

Cen

ter)

. Con

trol I

nput

(Cab

leCo

nnec

ted

BNC)

is L

ess

Criti

cal;

Does

Not

Req

uire

Shi

eldi

ng

LTA

N47

• T

AF

11

AN47-109

Application Note 47

LTA

N47

• T

AF

12

Figu

re F

12. P

hoto

Inte

grat

or D

etai

ls. I

nteg

rato

r Inp

ut B

NC is

Ful

ly S

hiel

ded

From

Inte

grat

or A

mp

— 1

pF C

oupl

ing

From

BNC

Out

put

to S

umm

ing

Poin

t will

Cau

se E

xces

sive

Pea

king

. Am

plifi

er a

nd S

witc

h IC

s ar

e Ju

st V

isib

le

Application Note 47

AN47-110

LTA

N47

• T

AF

13

Figu

re F

13. T

he A

dapt

ive

Trig

ger F

iber

Opt

ic R

ecei

ver.

BNC

Pho

to-S

imul

atio

n In

put a

nd F

iber

Opt

ic L

ine

Both

Con

nect

ed.

Low

Fre

quen

cy W

iring

is H

apha

zard

ly C

onst

ruct

ed W

hile

Hig

h Fr

eque

ncy

Sect

ions

are

Tig

ht a

nd H

ug th

e Gr

ound

Pla

ne.

Note

Ver

tical

Shi

eld

at P

hoto

-Sim

ulat

ion

Inpu

t BNC

AN47-111

Application Note 47

Figu

re F

14. D

etai

l of t

he F

iber

Opt

ic R

ecei

ver’s

Pho

to-S

imul

atio

n BN

C In

put.

Resi

stor

Fro

m B

NC is

Rou

ted

Thro

ugh

aSm

all H

ole

in V

ertic

al S

hiel

d, M

inim

izin

g Ca

paci

tanc

e. A

noth

er R

esis

tor o

n th

e Sh

ield

’s O

ther

Sid

e Di

vide

s Ef

fect

s of

Resi

dual

Cap

acita

nce

to K

eep

Sum

min

g Po

int C

lean

LTA

N47

• T

AF

14

Application Note 47

AN47-112

Figu

re F

15. T

he 1

A Bo

oste

r. N

ote

Heav

y By

pass

ing

Righ

t at t

he O

utpu

t Pow

er T

rans

isto

rs (B

oth

Stud

-Mou

nted

to C

lad)

. Loc

alCo

mpe

nsat

ion

Capa

cito

rs (R

ight

Sid

e Up

per a

nd L

ower

) Hav

e Sh

ort L

eads

LTA

N47

• T

AF

15

AN47-113

Application Note 47

LTA

N47

• T

AF

16

Figu

re F

16. 2

0MHz

Sin

e W

ave

Crys

tal O

scill

ator

. DC-

AGC

Sect

ion

is a

t Low

er L

eft,

Osci

llato

r is

in C

ente

r. C

ontro

l FET

is L

ocat

ed a

tOs

cilla

tor A

mpl

ifier

. Slo

w G

ate

Cont

rol S

igna

l Arr

ives

via

Lon

g-Le

aded

Res

isto

r, (P

hoto

Cen

ter U

pper

Lef

t)

Application Note 47

AN47-114

LTA

N47

• T

AF

17

Figu

re F

17. T

he V

arac

tor T

uned

Wie

n Br

idge

. DC-

AGC

Sect

ion

is o

n Ve

rtica

l Boa

rd —

Hig

h Fr

eque

ncy

Sect

ion

Hugs

the

Grou

ndPl

ane.

Con

trol F

ET (C

ente

r Lef

t), L

ocat

ed a

t Osc

illat

or, i

s Bi

ased

Fro

m a

Lon

g Li

ne O

rigin

atin

g on

AGC

Boa

rd. N

ote

FET

Gate

Resi

stor

is L

ocat

ed a

t FET

, Not

DC

Boar

d. O

scill

ator

Out

put R

ecei

ves

Reve

rse

Trea

tmen

t

AN47-115

Application Note 47

LTA

N47

• T

AF

18

Figu

re F

18. T

he 1

Hz-1

0MHz

V to

F B

read

boar

d w

ith P

robe

s At

tach

ed. D

C Se

rvo

Ampl

ifier

is S

ocke

ted,

with

Lon

g Le

ads.

Ref

eren

ceSe

ctio

n, S

tarti

ng a

t Bre

adbo

ard

(Upp

er R

ight

), W

orks

Tow

ard

Refe

renc

e Sw

itch

(Lar

ge D

IP a

t Boa

rd C

ente

r). N

ote

Very

Tig

ht L

ayou

t in

Ampl

ifier

-Com

para

tor R

egio

n (B

oard

Lef

t Cen

ter)

Application Note 47

AN47-116

LTA

N47

• T

AF

19

Figu

re F

19. D

etai

ls o

f 1Hz

-10M

hz V

to F

Hig

h Sp

eed

Sect

ion.

LT1

122

Inte

grat

or is

Jus

t Vis

ible

Und

er it

s As

soci

ated

Dis

cret

eCo

mpo

nent

s. S

umm

ing

Poin

t (Le

ft Si

de o

f Am

plifi

er) i

s La

yout

’s E

lect

rical

Cen

ter.

LT1

016

Wiri

ng is

Als

o Ve

ry T

ight

Exc

ept f

or it

sOu

tput

Whi

ch G

oes

to R

efer

ence

Sw

itch.

DC

Serv

o Am

plifi

er S

leep

s in

its

Sock

et. N

ote

Prob

e Ti

p Co

nnec

tors

AN47-117

Application Note 47

LTA

N47

• T

AF

20

Figu

re F

20. T

he T

ime-

to-H

eigh

t Con

verte

r. S

witc

hed

Curr

ent S

ourc

e, (B

oard

Cen

ter L

eft),

has

Ver

y Ti

ght L

ayou

t. Fo

llow

er A

mpl

ifier

isat

Boa

rd U

pper

Cen

ter.

Maj

or C

ompo

nent

s (in

Ord

er fr

om T

op to

Bot

tom

), In

clud

e Cu

rren

t Sou

rce

Switc

h Tr

ansi

stor

, Cur

rent

Sou

rce

Tran

sist

or (B

lack

Cas

e), I

nteg

rato

r Cap

acito

r (Si

lver

) and

Res

et T

rans

isto

r. N

ote

Shor

t Con

nect

ion

to A

mpl

ifier

Inpu

t Pin

Application Note 47

AN47-118

LTA

N47

• T

AF

21

Figu

re F

21. T

he A

utom

atic

Trig

ger.

Low

Fre

quen

cy A

utom

atic

Lev

el S

ectio

n is

Spr

ead

Out,

(Rig

ht S

ide

of B

oard

). W

ideb

and

Circ

uitry

Hugs

Gro

und

Plan

e an

d is

Loc

ated

Nea

r Inp

ut B

NC. A

mpl

ifier

’s L

ow Im

peda

nce,

Fas

t Out

put F

eeds

LT1

016

Outp

ut C

ompa

rato

r Ove

r aRe

lativ

ely

Long

Wire

Run

, Rou

ted

Thro

ugh

Inse

nsiti

ve S

ectio

n of

DC

Circ

uitry

AN47-119

Application Note 47

LTA

N47

• T

AF

22

Figu

re F

22. T

he R

F Le

velin

g Lo

op. T

he R

MS

to D

C Co

nver

ter (

Left

Boar

d) w

as B

uilt

Firs

t, Th

en th

e RF

Pre

-Am

p (C

ente

r Boa

rd) a

ndFi

nally

the

Mul

tiplie

r-Se

rvo

Boar

d. E

ach

Boar

d’s

Perfo

rman

ce w

as V

erifi

ed B

efor

e Jo

inin

g Th

em. N

ote

Copp

er T

ape

Mai

ntai

ning

Grou

nd P

lane

Inte

grity

Bet

wee

n Bo

ards

Application Note 47

AN47-120

Figu

re F

23. R

F Le

velin

g Lo

op A

ttach

ed D

irect

ly to

the

Test

Gen

erat

or. C

able

Unc

erta

intie

s ar

e El

imin

ated

Bec

ause

The

re is

No

Cabl

e

LTA

N47

• T

AF

23

AN47-121

Application Note 47

LTA

N47

• T

AF

24

Figu

re F

24. T

he V

olta

ge C

ontro

lled

Curr

ent S

ourc

e. V

ertic

al S

hiel

d (U

pper

Lef

t) Ab

sorb

s In

put B

NC R

adia

tion.

Am

plifi

er-L

oop

Com

pens

atio

n Co

mpo

nent

s ar

e Lo

cate

d Di

rect

ly a

t Am

plifi

er (B

ehin

d Sh

ield

)

Application Note 47

AN47-122

Figu

re F

25. T

he G

ood

Life

. The

Hig

h Fr

eque

ncy

Ampl

ifier

Dem

onst

ratio

n Bo

ard

Disc

usse

d in

App

endi

x I.

Sock

ets

are

a Co

mpr

omis

eBe

twee

n Be

st P

erfo

rman

ce a

nd F

lexi

bilit

y

LTA

N47

• T

AF

25

AN47-123

Application Note 47

APPENDIX G

FCC Licensing and Construction Permit Applicationsfor Commerical AM Broadcasting Stations

In accordance with the application for Figure 116’s circuit,and our law-abiding nature, find facsimiles of the appro-

priate FCC applications below. The complete forms areavailable by writing to:

Federal Communications CommissionWashington, D.C. 20554

Figure G1 Figure G2

Figure G1-G2. The FCC Forms Appropriate for Figure 116’s Circuit

Application Note 47

AN47-124

APPENDIX H

About Current Feedback

Contrary to some enthusiastic marketing claims, currentfeedback isn’t new. In fact, it is much older than “normal”voltage feedback, which has been so popularized by opamps. The current feedback connection is at least50 years old, and probably much older. William R. Hewlettused it in 1939 to construct his now famous sine waveoscillator.1 “Cathode feedback” was widely applied in RFand wideband instrument design throughout the 30’s,40’s and 50’s. It was a favorite form of feedback, if forno other reason than there wasn’t any place else left tofeed back to!

In the early 1950’s G.A. Philbrick Researches introducedthe K2-W, the first commercially available packaged op-erational amplifier. This device, with its high impedancedifferential inputs, permitted the voltage type feedback socommon today. Although low frequency instrumentationtypes were quick to utilize the increased utility afforded byhigh impedance feedback nodes, RF and widebanddesigners hardly noticed. They continued to use cathodefeedback, called (what else?) emitter feedback in the newtransistor form.

Numerous examples of the continued use of currentfeedback in RF and wideband instruments are found indesigns dating from the 1950’s to the present.2 Withostensibly easier to use voltage type feedback a realityduring this period, particularly as monolithic devicesbecame cheaper, why did discrete current feedback con-tinue to be used? The reason for the continued popularityof current techniques was (and is) bandwidth.Current feedback is simply much faster. Additionally,within limits, a current feedback based amplifier’s band-width does not degrade as closed loop gain is increased.This is a significant advantage over voltage feedbackamplifiers, where bandwidth falls as closed loop gain isincreased.

Relatively recently, current based designs have becomeavailable as general purpose, easy to use monolithic andhybrid devices. This brings high speed capability to amuch wider audience, hopefully opening up new applica-tions. So, while the technique is not new, marketing claimsnotwithstanding, the opportunity is. Although currentbased designs have poorer DC performance than voltageamplifiers, their bandwidth advantage is undeniable. What’sthe magic?

Current Feedback Basics

William H. Gross

The distinctions of how current feedback amplifiers differfrom voltage feedback amplifiers are not obvious at first,because, from the outside, the differences can be subtle.Both amplifier types use a similar symbol, and can beapplied on a first order basis using the same equations.However, their behavior in terms of gain bandwidth trade-offs and large signal response is another story.

Unlike voltage feedback amplifiers, small signal band-width in a current feedback amplifier isn’t a straightinverse function of closed loop gain, and large signalresponse is closer to ideal. Both benefits are because thefeedback resistors determine the amount of current driv-ing the amplifier’s internal compensation capacitor. Infact, the amplifier’s feedback resistor (Rf) from output toinverting input works with internal junction capacitancesto set the closed loop bandwidth. Even though the gain setresistor (Rg) from inverting input to ground works with theRf to set the voltage gain, just as in a voltage feedback opamp, the closed loop bandwidth does not change. Theexplanation of this is fairly straightforward. The equivalentgain bandwidth product of the CFA is set by the Theveninequivalent resistance at the inverting input and the internalcompensation capacitor. If Rf is held constant and gainchanged with Rg, the Thevenin resistance changes by thesame amount as the gain. From an overall loop standpoint,this change in feedback attenuation will produce a changein noise gain, and a proportionate reduction of open loopbandwidth (as in a conventional op amp). With currentfeedback, however, the key point is that changes inThevenin resistance also produce compensatory changes

Note 1: See Appendix C, “The Wien Bridge and Mr. Hewlett”, in Reference19. See also References 20 through 24 and 46.Note 2: See the “General Electric Transistor Manual”, published by G.E. in1964. See also operating and service manuals for the Hewlett-Packard 3400ARMS Voltmeter, 1120A FET probe, and the Tektronix P6042 current probe.

AN47-125

Application Note 47

in open loop bandwidth, unlike a conventional fixed gainbandwidth amplifier. As a result, the net closed loopbandwidth of a current-fed-back amplifier remains thesame for various closed loop gains.

Figure H1 shows the LT1223 voltage gain vs frequency forfive gain settings driving 100Ω. Shown for comparison isa plot of the fixed 100MHz gain bandwidth limitation thata voltage feedback amplifier would have. It is obvious thatfor gains greater than one, the LT1223 provides 3-20times more bandwidth.

FREQUENCY (Hz)

100k–20

VOLT

AGE

GAIN

(dB)

–10

10

20

50

60

10M 100M 1G

LTAN47 • TAH1

1M

0

30

40

100MHz GAIN BANDWIDTH

R = 10g

R = 33g

R = 110g

R = 470g

R = g ∞

1k

Rg

+

–

Figure H1. Voltage Gain vs Frequency for CurrentFeedback Amplifier (Family of Curves) and a ConventionalVoltage Amplifier (Straight Line)

Because the feedback resistor determines the compensa-tion of the LT1223, bandwidth and transient response canbe optimized for almost every application. When operatingon ±15V supplies, Rf should be 1kΩ or more for stability,but on ±5V, the minimum value is 680Ω, because thejunction capacitors increase with lower voltage. For eithercase, larger feedback resistors can also be used, but willslow down the LT1223 (which may be desirable in someapplications).

The LT1223 delivers excellent slew rate and bandwidthwith better DC performance than previous current feed-

back amplifiers (CFAs). On ±15V supplies with a 1kfeedback resistor, the small signal bandwidth is 100MHzinto a 400Ω load and 75MHz into 100Ω. The input willfollow slew rates of 250V/µs with the output generatingover 500V/µs, and output slew rate is well over 1000V/µsfor large input overdrive. Input offset voltage is 3mV(max), and input bias current is 3µA (max). A 10kΩ pot,connected to pins 1 and 5 with wiper to V+, providesoptional offset trimming. This trim shifts inverting inputcurrent about ±10µA, effectively producing input voltageoffset.

The LT1223 also has shutdown control, available at pin 8.Pulling more than 200µA from pin 8 drops the supplycurrent to less than 3mA, and puts the output into a highimpedance state. The easy way to force shutdown is toground pin 8 using an open collector (drain) logic stage.An internal resistor limits current, allowing direct interfac-ing with no additional parts. When pin 8 is open, theLT1223 operates normally.

The difference in operating characteristics between opamps and CFAs result in slight differences in commoncircuit configurations. Figure H2 summarizes some popu-lar circuit types, showing differences between op ampsand CFAs. Gain can be set with either RIN or Rf in an opamp, while a CFA’s feedback resistor (Rf) is fixed. Op ampbandwidth is controllable with a feedback capacitor; for aCFA, bandwidth must be limited at the input. A feedbackcapacitor is never used. In an integrator, the 1k resistormust be included in the CFA so its negative input sees theoptimal impedance. Finally, (not shown) there is no corre-lation between bias currents of a CFA’s inputs. Because ofthis, source impedance matching will not improve DCaccuracy. Matching input source impedances aids offsetperformance in op amps that do not have internal biascurrent cancellation.

Application Note 47

AN47-126

CIRCUIT TYPE VOLTAGE FEEDBACK CURRENT FEEDBACKOP AMP AMPLIFIER

SETTING GAIN

INPUT

RGAIN

Rf

–

+

LTAN47 • TAH2A

INPUT

RGAIN

Rf

–

+

LTAN47 • TAH2B

LIMITING BANDWIDTH

INPUT

RGAIN

Rf

–

+

LTAN47 • TAH2C

CBANDWIDTH

INPUT

RGAIN

Rf

–

+

LTAN47 • TAH2D

CBANDWIDTH

RBANDWIDTH

INTEGRATOR INPUTR

–

+

LTAN47 • TAH2E

C

INPUTR

1k

–

+

LTAN47 • TAH2F

C

Figure H2. Some Practical Differences in Applying Current and Voltage Amplifiers

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Application Note 47

APPENDIX I

High Frequency Amplifier Evaluation Board

LTC demo board 009 (photo, Figure I1, schematic, FigureI2) is designed to simplify the evaluation of high speedoperational amplifiers. It includes both an inverting andnon-inverting circuit, and extra holes are provided to allowthe use of board-mounted BNC or SMA connectors. Thetwo circuits are independent with the exception of sharedpower supply and ground connections.

Layout is a primary contributor to the performance of anyhigh speed amplifier. Poor layout techniques adverselyaffect the behavior of a finished circuit. Several importantlayout techniques, all used in demo board 009, are de-scribed below:

1. Top side ground plane. The primary task of a groundplane is to lower the impedance of ground connections.The inductance between any two points on a uniformsheet of copper is less than the inductance of a thin,straight trace of copper connecting the same two points.The ground plane approximates the characteristics of acopper sheet and lowers the impedance at key points inthe circuit, such as the grounds of connectors andsupply bypass capacitors.

2. Ground plane voids. Certain components and circuitnodes are very sensitive to stray capacitance. Two goodexamples are the summing node of the op amp and thefeedback resistor. Voids are put in the ground plane inthese areas to reduce stray ground capacitance.

3. Input/output matching. The width of the input andoutput traces is adjusted to a stripline impedance of50Ω. Note that the terminating resistors (R3 and R7)are connected to the end of the input lines, not at theconnector. While stripline techniques aren’t absolutelynecessary for the demo board, they are important onlarger layouts where line lengths are longer. The shortlines on the demo board can be terminated in 50Ω,75Ω, or 93Ω without adversely affecting performance.

4. Separation of input and output grounds. Even thoughthe ground plane exhibits a low impedance, input andoutput grounds are still separated. For example, thetermination resistors (R3 and R7) and the gain-settingresistor (R1) are grounded in the vicinity of the inputconnector. Supply bypass capacitors (C1, C2, C4, C5,C7, C8, C9 and C10) are returned to ground in thevicinity of the output connectors.

The circuit board is designed to accommodate standard 8-pin miniDIP, single operational amplifiers such as theLT1190 and LT1220 families. Both voltage and currentfeedback types can be used. Pins 1, 5 and 8 are outfittedwith extra holes for use in adjusting DC offsets, compen-sation, or, in the case of the LT1223 and LT1190/1/2, forshutting down the amplifier.

If a current feedback amplifier such as the LT1223 is beingevaluated, omit C3/C6. R4 and R6 are included for imped-ance matching when driving low impedance lines. If theamplifier is supposed to drive the line directly, or if the loadimpedance is high, R4 and R8 can be replaced by jumpers.Similarly R10 and R12 can be used to establish a load atthe output of the amplifier.

Low profile sockets may be used for the op amps tofacilitate changing parts, but performance may be affectedabove 100MHz.

High speed operational amplifiers work best when theirsupply pins are bypassed with Rf-quality capacitors. C1,C5, C8 and C10 should be 10nF disc ceramic or othercapacitors with a self-resonant frequency greater than10MHz. The polarized capacitors (C2, C4, C7, and C9)should be 1µF to 10µF tantalums. Most 10nF ceramics areself-resonant well above 10MHz and 4.7µF solid tantalums(axial leaded) are self-resonant at 1MHz or below. Leadlengths are critical; the self-resonant frequency of a 4.7µFtantalum drops by a factor of 2 when measured through 2"leads. Although a capacitor may become inductive at highfrequencies, it is still an effective bypass componentabove resonance because the impedance is low.

Application Note 47

AN47-128

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AN47-129

Application Note 47

LTAN47 • TAI2

–

+U1

1

76

4

5

3

2

+

C10.1µF

C24.7µF

C3SEE TEXT

R21k

R11k

C50.1µF

C44.7µF

R10SEE TEXT

J2NON-INVERTINGOUTPUTJ1

NON-INVERTINGINTPUT

R350Ω

–

+U2

1

76

4

5

3

2

+

C80.1µF

C74.7µF

C6SEE TEXT

R51k

C100.1µF

C94.7µF

R12SEE TEXT

J4INVERTINGOUTPUT

J3INVERTING

INTPUT

R750Ω

–V

+V

GND

R61k

+

+

Figure I2. High Frequency Amplifier Demonstration Board Schematic

Application Note 47

AN47-130

AN47-131

Application Note 47

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,no responsibility is assumed for its use. Linear Technology Corporation makes no representation thatthe interconnection of its circuits as described herein will not infringe on existing patent rights.

Application Note 47

AN47-132an47fa LT/LW/TP 0600 2K REV A • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1991

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear-tech.com

august 1991 high speed amplifier techniques · august 1991 high speed amplifier techniques a...

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