VERSION 1.0

AUGUST 04, 2014

1. Revision History Rev No Date Description

1.0 August 04, 2014 Initial Version

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Contents 1. Revision History .................................................................................................................................... 2

2. Introduction .......................................................................................................................................... 4

2.1 Key Specifications ......................................................................................................................... 4

2.2 Future Enhancement .................................................................................................................... 4

3. Code Generation approach ................................................................................................................... 5

3.1 User inputs .................................................................................................................................... 5

3.1.1 Configuration Inputs ............................................................................................................. 5

3.1.2 Mapping Specification ........................................................................................................... 6

3.2 Generate RTL and Test Bench ....................................................................................................... 7

3.2.1 Folder Structure generated by IQMAP ................................................................................. 7

4. IQ Mapper details ................................................................................................................................. 9

4.1 IQ MAPPER Interface Specification ............................................................................................... 9

4.2 IQ MAPPER Interface Timing ....................................................................................................... 10

4.2.1 IQ Mapper AxC Interface timing ......................................................................................... 11

4.2.2 IQ Mapper CPRI Interface timing ....................................................................................... 11

5. IQ De Mapper details .......................................................................................................................... 12

5.1 IQ De MAPPER Interface Specification ........................................................................................ 12

5.2 IQ De MAPPER Interface Timing ................................................................................................. 13

5.2.1 IQ Mapper CPRI Interface timing ....................................................................................... 14

5.2.2 IQ Mapper AxC Interface timing ......................................................................................... 14

6. Integrating with the CPRI IP Core........................................................................................................ 15

6.1 Latency Interface Timing ............................................................................................................. 15

7. Verification environment .................................................................................................................... 17

7.1 IQ Mapper Verification Environment Architecture .................................................................... 17

7.2 CPRI IQ De-Mapper Verification Environment Architecture ....................................................... 17

7.3 How to run the simulation of the IQMap with the CPRI IP Core ................................................ 18

8. IQ Mapper Integrated simulation with CPRI IP core V6 ...................................................................... 19

8.1 Configuration details ................................................................................................................... 19

9. Consecutive Samples from the same AxC ........................................................................................... 22

10. Example Reference Design .............................................................................................................. 23

10.1 Resource Usage ........................................................................................................................... 24

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2. Introduction The Altera IQ Mapper tool provides a simple and elegant way to specify the mapping of IQ samples to Antenna Carriers (AxC). The Altera IQ Mapper tool also generates a RTL design (based on the AxC mapping specified) that interfaces with the Altera CPRI V6 IP core. This avoids the need of manually developing RTL to map AxCs and interface the AxC Mapper to the Altera CPRI V6 core. The Altera IQMAP tool is developed using Microsoft Excel (Version 2013) and is developed based on the CPRI Specification V6.0 (2013-08-30)

2.1 Key Specifications The IQMapper Tool has the following features. 1. Mapping method 1: IQ sample based 2. Interleaved AxC format 3. Multiple IQ Sample Widths (Bits): 4 to 20. 4. Multiple Line rates (Mbps): 614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 9830.4, 10137.6. 5. Multiple Antenna Carriers: Minimum 1 and Maximum of 40. 6. Stuffing bits are supported.

2.2 Future Enhancement The following features are planned to be supported in the next release.

Latency counter

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3. Code Generation approach The IQ Mapper tools is Excel based and all inputs are provided in the excel spreadsheet. VBA Excel scripts

parse the user inputs and generate the RTL design in Verilog as well as a test bench in System Verilog. This

approach is illustrated in Figure 1.

Figure 1 Code Generation Methodology

3.1 User inputs The user has to provide types of inputs in the spreadsheet. 1. Configuration Inputs 2. Mapping Specification

3.1.1 Configuration Inputs

In the first stage, the configuration of the IQ Mapper is provided. 1. Line Rate 2. Symmetrical DL/UL

a. YES Both IQ Mapper and DeMapper have same configuration b. NO IQ Mapper and DeMapper have different configuration

Figure 2 details the configurations required.

Figure 2: Configuration Inputs

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Steps: 1. Open the IQMapper Excel Sheet 2. Click the Mapper Sheet 3. Select the Line Rate by using the Scroll button 4. Select Symmetrical DL/UL using Yes/No Scroll button

o YES Both downlink and uplink have the same configuration o NO Downlink and uplink have different configuration

5. Click “Prepare User Plane Area” Button 6. Fill the antenna carriers 7. Click the “Generate Code” button 8. If NO(Symmetrical DL/UL) option is selected, then Click the DeMap sheet 9. Repeat the Step 3 to 7

3.1.2 Mapping Specification

In the second stage, the mapping of the IQ samples to AxC has to be provided. Mention the AxC number

in each cell. Each cell represents a bit of the IQ sample. If the sample width of AxC0 is a 32 bit complex

number, then enter ‘AxC0’ in 32 successive cells. For stuffing bits, leave the cell blank. For consecutive

samples from the same AxC - split the AxC into 2 and place the odd samples in one AxC and the even

samples in the other.

Figure 3: Specifying the AxC mapping

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3.2 Generate RTL and Test Bench RTL and Test bench are generated by clicking the “Generate RTL and TB” button. Ensure the security mode

in Excel to allow macros and scripts to run. The RTL is generated in Verilog and the Test bench in System

Verilog.

3.2.1 Folder Structure generated by IQMAP

The folder structure for the generated RTL and test bench is highlighted in Figure 4. All the folders are generated by the IQMAP Automation tool

Figure 4 Directory Structure

design

lib

msim

iq_demapper

checkers

comp_lib

run

seq_lib

tb_top

test_lib

trn_lib

iq_mapper

checkers

comp_lib

run

seq_lib

tb_top

test_lib

trn_lib

lib

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Table 1: Folder Structure details

Folder Structure Description

designs\lib Generated IQ Mapper/DeMapper RTL files

msim\iq_demapper

msim\iq_demapper\Checkers IQ Demapper checker releated files

msim\iq_demapper\comb_lib Component used to generate CPRI basic frames and receive AxC data

msim\iq_demapper\run IQ Demapper test will be executed using run.do script

msim\iq_demapper\tb_top Top level Testbench files

msim\iq_demapper\test_lib Test cases files

msim\iq_demapper\trn_lib Transaction library contains packet structure

msim\iq_mapper

msim\iq_mapper\checkers IQ Mapper Checker releated files

msim\iq_mapper\comb_lib Component used to generate AxC data and receive CPRI basic frames

msim\iq_mapper\run IQ Mapper test will be executed using run.do script

msim\iq_mapper\tb_top Top level Testbench files

msim\iq_mapper\test_lib Test cases files

msim\iq_mapper\trn_lib Transaction library contains packet structure

lib Common simulaton library files

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4. IQ Mapper details The IQ Mapper operates on a Basic Frame. The IQ Mapper block accumulates IQ samples from different

AxCs streaming interface to form a Basic Frame and then starts transmitting on the CPRI interface. After

this initial latency, the IQ mapper continuously transmits. The entire Mapping logic is enabled only when

the map_ena is asserted.

The latency (in CPRI Clock cycles) through the IQ mapper is given by the following equation.

((number of bits in one cpri basic_structure /32) + 4

4.1 IQ MAPPER Interface Specification The interface signals of the IQ Mapper are detailed in Figure 5 and elaborated in Table 2. As can be seen,

the IQ Mapper is a single clock design and operates using the same clock as the Altera CPRI V6 Core.

IQ DEMAPPER

CPRI_RX_DATA[31:0]

CPRI_RX_READY [3:0]

CPRI_RX_SEQ [6:0]

DEMAP_ENA

CPRI_CLK

AXC0_DATA[39:0]

AXC0_VALID

AXC1_DATA[39:0]

AXC1_VALID

AXCn_DATA[39:0]

AXCn_VALID

RST_N

Figure 5 IQ Mapper Interface

Table 2: IQ Mapper Interface

Signal name Bit width Direction Description

cpri_clk 1 IN This frequency should match the Altera CPRI IP Core V6 Clock

rst_n 1 IN Synchronous reset Signal

axcn_data 40 IN AxC channel data. Each AxC has separate interface. All 40 bits are available on the interface port. If a particular AxC has only 32 bits, the remaining 8 bits are treated as ‘Don’t Care’

axcn_ready 1 OUT Ready Output for each AxC. Axcn_data is expected two clock cycles after axcn_ready signal is asserted.

cpri_tx_data 32 OUT CPRI IQ Tx data

cpri_tx_ready 4 OUT CPRI IQ Tx data Ready

aux_tx_seq 7 IN Index number of current 32 bit word in the current basic frame

map_ena 1 IN Global for all AxC to enable the mapper operation

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IQ mapper/Demapper operates at the CPRI Clock and the clock frequency to be used for various line rates

are detailed in Table 3.

Table 3: CPRI Line Rate and Clock Frequency

CPRI Line Rate(Gbps)

CPRI CLOCK (MHz)

0.6144 61.44

1.2288 61.44

2.4576 61.44

3.072 76.8

4.9512 122.88

6.144 153.6

9.8304 245.76

10.1376 253.44

4.2 IQ MAPPER Interface Timing To illustrate the timing relationships between various signals of the IQ Mapper interface, a reference design with the following configuration is chosen Line Rate : 2.457 Gbs Number of AxCs : 2 Sample Width : 32 bits Bandwidth : 10 MHz

Iq00 Iq10 Iq01 Iq11 Iq02 Iq12 Iq03 Iq13

[31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0]

D0 D1 D2 D3 D4 D5 D6 D7

Figure 6: Example AxC mapping to illustrate interface timing

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4.2.1 IQ Mapper AxC Interface timing

Figure 7 shows the AxC Interface timing of theIQ mapper. For every ready signal asserted by the controller, it expects the data to be stable after 2 clock cycle.

xxxx xxxxIq00 Iq03

CPRI_CLK

AXC0_READY

AXC0_DATA[39:0]

AXC1_READY

AXC1_DATA[39:0]

Iq01 Iq02

xxxx xxxxIq00 Iq03Iq01 Iq02

Figure 7 IQ Mapper Input Timing Diagram

4.2.2 IQ Mapper CPRI Interface timing

The timing interface at the CPRI interface is shown in Figure 8

xx 0xf

CPRI CLK

xxxx 0 D0 D1 D2 D3 D4 D5 D6

CPRI_TX_READY

CPRI_TX_DATA[31:0]

0X0

D7

Figure 8 IQ Mapper Output Timing Diagram

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5. IQ De Mapper details The IQ-DeMapper block receives one basic frame structure and demaps to individual antenna carriers.

The demapper waits for one basic frame structure before starting to transmit the individual antenna

carriers on the AxC interface. The entire De-mapping logic is enabled only when the demap_ena is asseted.

5.1 IQ De MAPPER Interface Specification

IQ DEMAPPER

CPRI_RX_DATA[31:0]

CPRI_RX_READY [3:0]

CPRI_RX_SEQ [6:0]

DEMAP_ENA

CPRI_CLK

AXC0_RX_DATA[39:0]

AXC0_RX_VALID

AXC1_RX_DATA[39:0]

AXC1_RX_VALID

AXCn_RX_DATA[39:0]

AXCn_RX_VALID

RST_N

Figure 9 IQ DeMapper Interface

Signal name Bit width Direction Remarks

cpri_clk 1 IN This frequency should match the Altera CPRI IP Core V6 Clock

rst_n 1 IN Synchronous Reset

cpri_rx_data 32 IN CPRI IQ RX data

cpri_rx_ready 4 IN CPRI IQ RX data ready

aux_rx_seq 7 IN Index number of current 32 bit word in the current basic frame

axcn_data 40 OUT AxC channel data. Each AxC has separate interface. All 40 bits are available on the interface port. If a particular AxC has only 32 bits, the remaining 8 bits are stuffed with “0”.

axcn_valid 1 OUT Valid signal for each antenna-carrier interface

demap_enb 1 IN Global for all AxC to enable the demapper operation

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5.2 IQ De MAPPER Interface Timing To illustrate the timing relationships between various signals of the IQ Mapper interface, a reference design with the following configuration is chosen Line Rate : 2.457 Gbs Number of AxCs : 2 Sample Width : 32 bits BW : 10 MHz

Iq00 Iq10 Iq01 Iq11 Iq02 Iq12 Iq03 Iq13

[31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0]

D0 D1 D2 D3 D4 D5 D6 D7

Figure 10 Example AxC demapping to illustrate interface timing

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5.2.1 IQ Mapper CPRI Interface timing

xx 0xf

CPRI CLK

CPRI_RX_READY[3:0]

CPRI_RX_DATA[31:0]

xxxx 0 D0 D1 D2 D3 D4 D5 D6

0X0

D7

Figure 11 IQ Demapper Input Timing Diagram

5.2.2 IQ Mapper AxC Interface timing

xxxxIq00 Iq3

CPRI CLK

AXC0_VALID

AXC0_DATA[39:0]

AXC1_VALID

AXC1_DATA[39:0]

Iq01 Iq02

xxxxIq10 Iq13Iq11 Iq12

Figure 12 IQ DeMapper Output Timing Diagram

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6. Integrating with the CPRI IP Core Integration of CRPI IP with the IQ mapper and Demapper module is shown in Figure 13 . A Asynchronous FIFO is implemented to enable the user interface to operate in a different clock domain. The IQ mapper and De mapper operates in the CPRI Clock Domain.

ASYNCHORNOUS FIFO

CPRI IP

AXC0_data

AXC0_vld

AXC1_data

AXC1_vld

AXC2_data

AXC_clk

IQ MAPPER

Iq0_tx_data

Iq0_tx_valid

Iq1_tx_valid

Iq1_tx_valid

Iq2_tx_data

Iq2_tx_valid

Cpri_clk

Cpri_tx_data

ASYNCHORNOUS FIFO

CPRI IPIQ DEMAPPER

Iq0_Rx_data

Iq0_Rx_valid

Iq1_Rx_valid

Iq1_Rx_valid

Iq2_Rx_data

Iq2_Rx_valid

Cpri_clk

Cpri_Rx_data

Cpri_clk

AXC0_data

Cpri_tx_valid

Cpri_Rx_ready

AXC_clk

AXC0_vld

AXC1_data

AXC1_vld

AXC2_data

Latency

cpri_clk

Iq_tx_data[31:0]

Iq_tx_valid

Iq_tx_ready

aux_tx_seq

aux_rx_seq

AXC2_vld

AXC2_vld

Figure 13 Integration with CPRI IP Core

6.1 Latency Interface Timing IQ Mapper starts sending control word when aux_tx_seq value is 0. Altera CPRI IP V6 Core expects iq_tx_data based on the aux_latency used when generating the CPRI V6 Core. So there is a need to delay the cpri_tx_data from IQ Mapper before sending it to the CPRI IP. Figure 14 shows the IQ mapper interface output and Figure 15and Figure 16 demonstrate the delay to be introduced by the “Latency” block for aux_latency = 0 and 1 respectively.

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CPRI CLK

xx 0xfCPRI_TX_READY[3:0]

CPRI_TX_DATA[31:0]xxxx 0 D0 D1 D2 D3 D4 D5 D6

0X0

D7

CPRI_TX_SEQ_CNT xxxx 0 1 2 3 4 5 6 7 8

Figure 14 IQ mapper output timing diagram

aux_latency = 0 CPRI TX Data from IQ Mapper is delayed by one clock cycle (IQ_TX_DATA)

xx 0xfIQ_TX_VALID[3:0]

IQ_TX_DATA[31:0]xxxx 0 D0 D1 D2 D3 D4 D5 D6

0X0

D7

CPRI_TX_SEQ_CNT xxxx 0 1 2 3 4 5 6 7 8

CPRI CLK

Figure 15 CPRI input timing diagram ( Aux_latency 0)

aux_latency = 1 CPRI_TX_DATA from IQ Mapper is delayed by 2 clock cycle (IQ_TX_DATA)

xx 0xfIQ_TX_VALID[3:0]

IQ_TX_DATA[31:0] xxxx 0 D0 D1 D2 D3 D4 D5 D6

0X0

D7

CPRI_TX_SEQ_CNTxxxx 0 1 2 3 4 5 6 7 8

CPRI CLK

Figure 16 CPRI input timing diagram (aux_latency 1)

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7. Verification environment

7.1 IQ Mapper Verification Environment Architecture The test bench is built in system Verilog. The test bench comprise of configuration manager, pattern

generator (GEN), TX Streaming monitor(TX_MON), RX Streaming monitor(RX_MON), mapper model and

mapper checker (CHECKER) as shown in the Figure 17.

Tx Streaming generator streams data continuously at the AxC interface. The streaming is controlled based

on the AxC configuration. As an example, Streaming generator will generate 8 valid data per basic frame

structure for a 20 Mhz AxC.

TX monitor collects data at the AxC input interface and sends it to the checker. RX monitor collects data

at the CPRI output interface and sends it to the checker. The checker implements the mapper model and

predicts the expected output at the CPRI interface. It reports error if there is any mismatch.

Rx MON

MAPPER

Tx MON

CHECKER SB

GEN

Tx MON

GEN

Figure 17 IQ Mapper Verification Environment

7.2 CPRI IQ De-Mapper Verification Environment Architecture The test bench is built in system Verilog. The test bench comprise of comprise of configuration manager,

pattern generator(GEN), TX CPRI Streaming monitor(Tx MON), RX AxC Streaming monitor (Rx MON) ,

demapper model and de mapper checker (CHECKER) as shown in the Figure 18.

Tx CPRI Streaming generator streams random data continuously at the demapper CPRI interface. Byte

valid is generated based on the data rate and AxC width

TX CPRI monitor collects data at the CPRI input interface and sends it to the demapper checker. RX AxC

monitor collects data at the AxC output interface and sends it to the demapper checker. DeMapper

checker has the demapper model and predicts the expected output at the AxC interface. It reports error

if there is any mismatch

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Rx MON

Rx MON

DEMAPPER Tx MON

CHECKERSB

GEN

Figure 18 IQ DeMapper Verification Environment

7.3 How to run the simulation of the IQMap with the CPRI IP Core Steps to run the Mapper simulation. 1. Set the environment variable "QUARTUS_INSTALL_DIR" to Quartus installation directory 2. Open Questasim 3. cd \dev\fpga\msim\iq_mapper\run directory 4. do run.do Steps to run the Mapper simulation. 1. Set the environment variable "QUARTUS_INSTALL_DIR" to Quartus installation directory 2. Open Questasim 3. cd \dev\fpga\msim\iq_demapper\run directory 4. do run.do

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8. IQ Mapper Integrated simulation with CPRI IP core V6

IQ Mapper/DeMapper Code generated from IQMAP tool is integrated and tested with CPRI IP

successfully. Figure 19 shows the integration diagram.

ASYNCHORNOUS FIFO

AXC0_data

AXC0_vld

AXC1_data

AXC1_vld

AXC2_data

AXC_clk

IQ MAPPER

Iq0_tx_data

Iq0_tx_valid

Iq1_tx_valid

Iq1_tx_valid

Iq2_tx_data

Iq2_tx_valid

Cpri_clk

Cpri_tx_data

ASYNCHORNOUS FIFO

CPRI IP

IQ DEMAPPER

Iq0_Rx_data

Iq0_Rx_valid

Iq1_Rx_valid

Iq1_Rx_valid

Iq2_Rx_data

Iq2_Rx_valid

Cpri_clk

Cpri_Rx_data

Cpri_clk

AXC0_data

Cpri_tx_valid

Cpri_Rx_ready

AXC_clk

AXC0_vld

AXC1_data

AXC1_vld

AXC2_data

Latency

cpri_clk

Iq_tx_data[31:0]

Iq_tx_valid

Iq_tx_ready

aux_tx_seq

aux_rx_seq

AXC2_vld

AXC2_vld

Figure 19 IQ Mapper Integration with CPRI IP Core (10G)

8.1 Configuration details Number of AxCs : 3

Sample IQ Width for all 3 AxCs : 32

Bandwidth : 20 MHz

CPRI Line Rate : 10G

Latency Value : 1

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9. Consecutive Samples from the same AxC An example for integration of Consecutive samples from the same AxC0 is shown below.

ASYNCHORNOUS FIFO

AXC0_data

AXC0_vld

AXC1_data

AXC1_vld

AXC2_data

AXC_clk

IQ MAPPER

Iq0_tx_data

Iq0_tx_valid

Iq1_tx_valid

Iq1_tx_valid

Iq2_tx_data

Iq2_tx_valid

Cpri_clk

Cpri_tx_data

ASYNCHORNOUS FIFO CPRI IP

IQ DEMAPPER

Iq0_Rx_data

Iq0_Rx_valid

Iq1_Rx_valid

Iq1_Rx_valid

Iq2_Rx_data

Iq2_Rx_valid

Cpri_clk

Cpri_Rx_data

Cpri_clk

AXC0_data

Cpri_tx_valid

Cpri_Rx_ready

AXC_clk

AXC0_vld

AXC1_data

AXC1_vld

AXC2_data

Latency

cpri_clk

Iq_tx_data[31:0]

Iq_tx_valid

Iq_tx_ready

aux_tx_seq

aux_rx_seq

AXC2_vld

AXC2_vld

SplitAxC

AXC0_data

AXC0_vld

MergeAxC

AXC0_data

AXC0_vld

Figure 20 Consecutive Samples from the same AxC

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10. Example Reference Design An Example reference design of 5AxC with 2.457 Gbps is shown below.

Figure 21 Example Reference Design

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10.1 Resource Usage The resource usage for Device 5ASTFD5K3F40I3ES based on Synthesis of the reference design is detailed below.

IQ mapper Resource Usage for Device 5ASTFD5K3F40I3ES

Resource Type IQ Mapper IQ De Mapper

ALM 206 248

Register 382 571

Memory Bits -

Variable Precision DSP -

Hard Memory Controllers -

PLL -

SERDES Transmitter -

SERDES Receiver -