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ATtiny406AVRreg Microcontroller with Core Independent Peripherals
and picoPowerreg Technology
Introduction
The ATtiny406 microcontrollers are using the high-performance low-power AVRreg RISC architecture andare capable of running at up to 20 MHz with up to 4 KB Flash 256 bytes of SRAM and 128 bytes ofEEPROM in a 20-pin packageThe series uses the latest technologies with a flexible and low-powerarchitecture including Event System and SleepWalking accurate analog features and advancedperipherals
Features
bull CPUndash AVRreg 8-bit CPUndash Running at up to 20 MHzndash Single cycle IO accessndash Two-level interrupt controllerndash Two-cycle hardware multiplier
bull Memoriesndash 4 KB In-system self-programmable Flash memoryndash 128B EEPROMndash 256B SRAMndash WriteErase Cycles 10000 Flash100000 EEPROMndash Data Retention 20 Years at 85degC
bull Systemndash Power-on Reset (POR)ndash Brown-out Detection (BOD)ndash Clock Options
bull 1620 MHz Low-Power Internal RC Oscillator withndash plusmn3 Accuracy over full temperature and voltage rangendash plusmn2 Drift over limited temperature and 18 36V voltage range
bull 32768 kHz Ultra Low-Power (ULP) Internal RC Oscillator with plusmn10 Accuracy plusmn2Calibration Step Size
bull External Clock Inputndash Single Pin Unified Program Debug Interface (UPDI)ndash Three Sleep Modes
bull Idle with all peripherals running and mode for immediate wake-up time
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bull Standbyndash Configurable operation of selected peripheralsndash SleepWalking peripherals
bull Power-down with wake-up functionalitybull Peripherals
ndash 3-channel Event Systemndash One 16-bit TimerCounter Type A with Dedicated Period Register Three Compare Channels
(TCA)ndash One 16-bit TimerCounter Type B with Input Capture (TCB)ndash One 16-bit Real-Time Counter (RTC) running from Internal RC Oscillatorndash One USART with fractional Baud Rate Generator Auto-baud and Start-of-frame Detectionndash MasterSlave Serial Peripheral Interface (SPI)ndash MasterSlave TWI with Dual Address Match
bull Standard mode (Sm 100 kHz)bull Fast mode (Fm 400 kHz)bull Fast mode Plus (Fm+ 1 MHz)
ndash Configurable Custom Logic (CCL) with Two Programmable Look-up Tables (LUT)ndash Analog Comparator (AC)ndash 10-bit 115 ksps Analog-to-Digital Converter (ADC)ndash Five selectable internal voltage references 055V 11V 15V 25V and 43Vndash Automated CRC memory scanndash Watchdog Timer (WDT) with Window mode with separate on-chip oscillatorndash External interrupt on all general purpose pins
bull IO and Packagesndash 18 Programmable IO linesndash 20-pin VQFN and SOIC300
bull Temperature Rangesndash -40degC to 105degCndash -40degC to 125degC Temperature graded device options available
bull Speed Gradesndash 0-5 MHz 18V ndash 55Vndash 0-10 MHz 27V ndash 55Vndash 0-20 MHz 45V ndash 55V
ATtiny406
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Table of Contents
Introduction1
Features 1
1 tinyAVRreg 0-Series Overview911 Configuration Summary9
2 Ordering Information1121 ATtiny40611
3 Block Diagram 12
4 Pinout 1341 20-Pin VQFN1342 20-Pin SOIC 13
5 IO Multiplexing and Considerations1551 Multiplexed Signals 15
6 Memories1661 Overview 1662 Memory Map 1663 In-System Reprogrammable Flash Program Memory1664 SRAM Data Memory 1765 EEPROM Data Memory 1766 User Row1867 Signature Bytes1868 Memory Section Access from CPU and UPDI on Locked Device1869 IO Memory19610 Configuration and User Fuses (FUSE)22
7 Peripherals and Architecture 4171 Peripheral Module Address Map4172 Interrupt Vector Mapping4273 System Configuration (SYSCFG)43
8 AVR CPU4681 Features 4682 Overview 4683 Architecture 4684 Arithmetic Logic Unit (ALU)4885 Functional Description4986 Register Summary - CPU5487 Register Description54
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9 Nonvolatile Memory Controller (NVMCTRL) 5991 Features 5992 Overview 5993 Functional Description6094 Register Summary - NVMCTRL6795 Register Description67
10 Clock Controller (CLKCTRL) 75101 Features 75102 Overview 75103 Functional Description77104 Register Summary - CLKCTRL82105 Register Description82
11 Sleep Controller (SLPCTRL) 91111 Features 91112 Overview 91113 Functional Description92114 Register Summary - SLPCTRL 95115 Register Description95
12 Reset Controller (RSTCTRL)97121 Features 97122 Overview 97123 Functional Description98124 Register Summary - RSTCTRL101125 Register Description101
13 CPU Interrupt Controller (CPUINT) 104131 Features 104132 Overview 104133 Functional Description106134 Register Summary - CPUINT 112135 Register Description 112
14 Event System (EVSYS) 117141 Features 117142 Overview117143 Functional Description120144 Register Summary - EVSYS 122145 Register Description122
15 Port Multiplexer (PORTMUX) 131151 Overview 131152 Register Summary - PORTMUX 132153 Register Description132
16 IO Pin Configuration (PORT)137
ATtiny406
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161 Features 137162 Overview 137163 Functional Description139164 Register Summary - PORT 143165 Register Description - Ports 143166 Register Summary - VPORT 155167 Register Description - Virtual Ports 155
17 Brown-Out Detector (BOD)160171 Features 160172 Overview 160173 Functional Description162174 Register Summary - BOD164175 Register Description164
18 Voltage Reference (VREF)171181 Features 171182 Overview 171183 Functional Description171184 Register Summary - VREF173185 Register Description173
19 Watchdog Timer (WDT)176191 Features 176192 Overview 176193 Functional Description178194 Register Summary - WDT 182195 Register Description182
20 16-bit TimerCounter Type A (TCA)186201 Features 186202 Overview 186203 Functional Description190204 Register Summary - TCA in Normal Mode (CTRLDSPLITM=0) 200205 Register Description - Normal Mode 201206 Register Summary - TCA in Split Mode (CTRLDSPLITM=1)221207 Register Description - Split Mode221
21 16-bit TimerCounter Type B (TCB)237211 Features 237212 Overview 237213 Functional Description240214 Register Summary - TCB 248215 Register Description248
22 Real-Time Counter (RTC)260221 Features 260222 Overview 260
ATtiny406
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223 RTC Functional Description 262224 PIT Functional Description 263225 Events 265226 Interrupts 266227 Sleep Mode Operation 266228 Synchronization267229 Configuration Change Protection 2672210 Register Summary - RTC2682211 Register Description268
23 Universal Synchronous and Asynchronous Receiver and Transmitter (USART)284231 Features 284232 Overview 284233 Functional Description288234 Register Summary - USART 303235 Register Description303
24 Serial Peripheral Interface (SPI)322241 Features 322242 Overview 322243 Functional Description325244 Register Summary - SPI333245 Register Description333
25 Two-Wire Interface (TWI) 342251 Features 342252 Overview 342253 Functional Description344254 Register Summary - TWI357255 Register Description357
26 Cyclic Redundancy Check Memory Scan (CRCSCAN) 377261 Features 377262 Overview 377263 Functional Description379264 Register Summary - CRCSCAN382265 Register Description382
27 Configurable Custom Logic (CCL)386271 Features 386272 Overview 386273 Functional Description388274 Register Summary - CCL 397275 Register Description397
28 Analog Comparator (AC)405281 Features 405282 Overview 405
ATtiny406
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283 Functional Description407284 Register Summary - AC 409285 Register Description409
29 Analog-to-Digital Converter (ADC) 414291 Features 414292 Overview 414293 Functional Description418294 Register Summary - ADCn426295 Register Description426
30 Unified Program and Debug Interface (UPDI)444301 Features 444302 Overview 444303 Functional Description447304 Register Summary - UPDI467305 Register Description467
31 Electrical Characteristics 478311 Disclaimer478312 Absolute Maximum Ratings 478313 General Operating Ratings 479314 Power Consumption for ATtiny406480315 Wake-Up Time481316 Power Consumption of Peripherals482317 BOD and POR Characteristics483318 External Reset Characteristics483319 Oscillators and Clocks4843110 IO Pin Characteristics 4853111 USART 4863112 SPI 4873113 TWI4883114 VREF4903115 ADC4923116 AC 4943117 UPDI Timing4953118 Programming Time495
32 Typical Characteristics496321 Power Consumption496322 GPIO 503323 VREF Characteristics 511324 BOD Characteristics513325 ADC Characteristics516326 AC Characteristics521327 OSC20M Characteristics524328 OSCULP32K Characteristics 526
ATtiny406
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33 Errata527331 Errata - ATtiny406 527
34 Package Drawings529341 20-Pin SOIC 529342 20-Pin VQFN530
35 Thermal Considerations 531351 Thermal Resistance Data531352 Junction Temperature531
36 Instruction Set Summary 532
37 Conventions537371 Numerical Notation537372 Memory Size and Type537373 Frequency and Time537374 Registers and Bits 538
38 Acronyms and Abbreviations539
39 Data Sheet Revision History542391 Revision History 542
The Microchip Web Site 543
Customer Change Notification Service543
Customer Support 543
Microchip Devices Code Protection Feature 543
Legal Notice544
Trademarks 544
Quality Management System Certified by DNV545
Worldwide Sales and Service546
ATtiny406
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1 tinyAVRreg 0-Series OverviewThe figure below shows the tinyAVR 0-series laying out pin count variants and memory sizes
bull Vertical migration can be done upwards without code modification since these devices are pincompatible and provide the same or additional features Downward migration may require codemodification due to fewer available instances of some peripherals
bull Horizontal migration to the left reduces the pin count and therefore the available features
Figure 1-1 Device Family Overview
2KB
8 14 20Pins
Flash
ATtiny406ATtiny404
ATtiny204ATtiny202
ATtiny4024KB
The fully compatible variants of the ATtiny devices that is the vertical migration option shown in the figureabove come with both smaller and larger Flash memories
Devices with different Flash memory size typically also have different SRAM and EEPROM
The name of a device of the ATtiny family contains information as depicted below (not all options areavailable)Figure 1-2 Device Designations
6=20 pins4=14 pins2= 8 pins
Carrier TypeAT tiny 406 - SFR
Flash size in KBFeature set
Pin count
Package up to 20 pins
Package TypeM=VQFNS=SOIC300SS=SOIC150
Temperature RangeN=-40degC to +105degCF=-40degC to +125degC
R=Tape amp Reel
11 Configuration Summary
111 Peripheral SummaryTable 1-1 Peripheral Summary
ATtin
y406
Pins 20
SRAM 256B
Flash 4 KB
ATtiny406tinyAVRreg 0-Series Overview
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ATtin
y406
EEPROM 128B
Max frequency (MHz) 20
16-bit TimerCounter type A (TCA) 1
16-bit TimerCounter type B (TCB) 1
12-bit TimerCounter type D (TCD) No
Real-Time Counter (RTC) 1
USART 1
SPI 1
TWI (I2C) 1
ADC 1
ADC channels 12
DAC No
AC 1
AC inputs 2p2n
Peripheral Touch Controller (PTC) No
Custom Logic 1
Window Watchdog 1
Event System channels 3
General purpose IO 18
External interrupts 18
CRCSCAN 1
ATtiny406tinyAVRreg 0-Series Overview
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2 Ordering Information
21 ATtiny406Table 2-1 ATtiny406 Ordering Codes
Ordering Code(1) Flash Package Type(GPC)
Leads Power Supply Operational Range Carrier Type
ATtiny406-MNR 4 KB VQFN (ZCL) 20 18V - 55V Industrial (-40degC +105degC) Tape amp Reel
ATtiny406-MFR 4 KB VQFN (ZCL) 20 18V - 55V Industrial (-40degC +125degC) Tape amp Reel
ATtiny406-SNR 4 KB SOIC300 (SRJ) 20 18V - 55V Industrial (-40degC +105degC) Tape amp Reel
ATtiny406-SFR 4 KB SOIC300 (SRJ) 20 18V - 55V Industrial (-40degC +125degC) Tape amp Reel
1 Pb-free packaging complies with the European Directive for Restriction of Hazardous Substances(RoHS directive) They are also Halide free and fully Green
ATtiny406Ordering Information
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3 Block DiagramFigure 3-1 Block Diagram
INOUT
DATABUS
Clock generation
BUS Matrix
CPU
USART0
SPI0
CCL
AC0
ADC0
TCA0
TCB0
AINP0AINN0
OUT
AIN[110]
WO[50]
RXDTXDXCK
XDIR
MISOMOSISCK
SS
PORTS
EVSYS
System management
SLPCTRL
RSTCTRL
CLKCTRL
EVENT
ROUTING
NETWORK
DATABUS
UPDICRC
SRAM
NVMCTRL
Flash
EEPROM
OSC20M
OSC32K
Detectorsreferences
BODVLM
POR
Bandgap
WDT
RTC
CPUINT
M M
S
MS
S
OCD
UPDI RESET
EVOUT[n0]
S
EXTCLK
LUTn-IN[20]LUTn-OUT
WO
CLKOUT
PA[70]PB[50]
GPIOR
TWI0SDASCL
RST12V
To detectors
PC[30]
ATtiny406Block Diagram
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4 Pinout
41 20-Pin VQFNNote For the most current package drawings see the Microchip Packaging Specification located at httpwwmicrochipcompackaging
1
2
3
4
5
6 7 8
20 19 18 179
13
14
15
1610
11
12
PA1
PA4
PA7
PA6
PB0
PB1
PB4
PB5
PC2
PC3
PA5
GND
VDD
PA2 PC0
PC1
PA0
RES
ETU
PDI
PB3
EXTCLK PA3
PB2
GPIO VDD power domain
Clock
Programming Debug ResetInput supply
Ground
Analog function
Digital function only
42 20-Pin SOICNote For the most current package drawings see the Microchip Packaging Specification located at httpwwmicrochipcompackaging
ATtiny406Pinout
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1
2
3
4
5
6
7
13
11
12
14
VDD GND
PA1
PA2
PA4
PA5
PA7
PA6
PB0
8
9
10
15
20
19
18
17
16
PB1
PB4
PB5
PC0
PC2
PC3
PC1
PA0RESETUPDI
PA3EXTCLK
PB3
PB2
GPIO VDD power domain
Clock
Programming Debug ResetInput supply
Ground
Analog function
Digital function only
ATtiny406Pinout
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5 IO Multiplexing and Considerations
51 Multiplexed SignalsTable 5-1 PORT Function Multiplexing
VQFN
20-
pin
SOIC
20-
pin Pin Name (12) OtherSpecial ADC0 AC0 USART0 SPI0 TWI0 TCA0 TCB0 CCL
19 16 PA0RESETUPDI
AIN0 LUT0-IN0
20 17 PA1 AIN1 TXD MOSI SDA LUT0-IN11 18 PA2 EVOUT0 AIN2 RxD MISO SCL LUT0-IN22 19 PA3 EXTCLK AIN3 XCK SCK WO33 20 GND4 1 VDD5 2 PA4 AIN4 XDIR SS WO4 LUT0-OUT6 3 PA5 AIN5 OUT WO5 WO7 4 PA6 AIN6 AINN0 MOSI8 5 PA7 AIN7 AINP0 MISO LUT1-OUT9 6 PB5 CLKOUT AIN8 AINP1 WO210 7 PB4 AIN9 AINN1 WO1 LUT0-OUT11 8 PB3 RxD WO012 9 PB2 EVOUT1 TxD WO213 10 PB1 AIN10 XCK SDA WO114 11 PB0 AIN11 XDIR SCL WO015 12 PC0 SCK W016 13 PC1 MISO LUT1-OUT17 14 PC2 EVOUT2 MOSI18 15 PC3 SS WO3 LUT1-IN0
Note 1 Pin names are of type Pxn with x being the PORT instance (A B) and n the pin number Notation
for signals is PORTx_PINn All pins can be used as event input2 All pins can be used for external interrupt where pins Px2 and Px6 of each port have full
asynchronous detection
Tip Signals on alternative pin locations are in typewriter fontSee PORTMUX chapter for selecting the altarnative pin locations
ATtiny406IO Multiplexing and Considerations
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6 Memories
61 OverviewThe main memories are SRAM data memory EEPROM data memory and Flash program memory Inaddition the peripheral registers are located in the IO memory space
Table 6-1 Physical Properties of Flash Memory
Property ATtiny406
Size 4 KB
Page size 64B
Number of pages 64
Start address 0x8000
Table 6-2 Physical Properties of SRAM
Property ATtiny406
Size 256B
Start address 0x3F00
Table 6-3 Physical Properties of EEPROM
Property ATtiny406
Size 128B
Page size 32B
Number of pages 4
Start address 0x1400
Related LinksIO Memory
62 Memory Map
63 In-System Reprogrammable Flash Program MemoryThe ATtiny406 contains 4 KB on-chip in-system reprogrammable Flash memory for program storageSince all AVR instructions are 16 or 32 bits wide the Flash is organized as 4K x 16 For write protectionthe Flash program memory space can be divided into three sections (see the illustration below)Bootloader section application code section and application data section with restricted access rightsamong them
ATtiny406Memories
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The Program Counter (PC) is 11-bits wide to address the whole program memory The procedure forwriting Flash memory is described in detail in the documentation of the Nonvolatile Memory Controller(NVMCTRL) peripheral
The entire Flash memory is mapped in the memory space and is accessible with normal LDSTinstructions as well as the LPM instruction For LDST instructions the Flash is mapped from address0x8000 For the LPM instruction the Flash start address is 0x0000
The ATtiny406 also has a CRC peripheral that is a master on the bus
Figure 6-1 Flash and the Three SectionsFLASHSTART 0x8000
BOOTENDgt0 0x8000+BOOTEND256
BO OT
APPENDgt0 0x8000+APPEND256
AP PL ICA TIO NCO DE
AP PLICA TIO NDA TA
FLASH
FLASHENDRelated LinksConfiguration SummaryNonvolatile Memory Controller (NVMCTRL)
64 SRAM Data MemoryThe 256B SRAM is used for data storage and stack
Related LinksAVR CPUStack and Stack Pointer
65 EEPROM Data MemoryThe ATtiny406 has 128 bytes of EEPROM data memory see Memory Map section The EEPROMmemory supports single byte read and write The EEPROM is controlled by the Nonvolatile MemoryController (NVMCTRL)
Related LinksMemory MapNonvolatile Memory Controller (NVMCTRL)
ATtiny406Memories
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66 User RowIn addition to the EEPROM the ATtiny406 has one extra page of EEPROM memory that can be used forfirmware settings the User Row (USERROW) This memory supports single byte read and write as thenormal EEPROM The CPU can write and read this memory as normal EEPROM and the UPDI can writeand read it as a normal EEPROM memory if the part is unlocked The User Row can be written by theUPDI when the part is locked USERROW is not affected by a chip erase
Related LinksMemory MapNonvolatile Memory Controller (NVMCTRL)Unified Program and Debug Interface (UPDI)
67 Signature BytesAll ATtiny microcontrollers have a 3-byte signature code that identifies the device This code can be readin both Serial and Parallel mode The three bytes reside in a separate address space For the device thesignature bytes are given in the following table
Note When the device is locked only the System Information Block (SIB) can be obtained
Table 6-4 Device ID
Device Name Signature Bytes Address
0x00 0x01 0x02
ATtiny406 0x1E 0x92 0x25
Related LinksSystem Information Block
68 Memory Section Access from CPU and UPDI on Locked DeviceThe device can be locked so that the memories cannot be read using the UPDI The locking protects boththe Flash (all BOOT APPCODE and APPDATA sections) SRAM and the EEPROM including the FUSEdata This prevents successful reading of application data or code using the debugger interface Regularmemory access from within the application still is enabled
The device is locked by writing any non-valid value to the LOCKBIT bit field in FUSELOCKBIT
Table 6-5 Memory Access in Unlocked Mode (FUSELOCKBIT Valid)(1)
Memory Section CPU Access UPDI Access
Read Write Read Write
SRAM Yes Yes Yes Yes
Registers Yes Yes Yes Yes
Flash Yes Yes Yes Yes
EEPROM Yes No Yes Yes
ATtiny406Memories
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Memory Section CPU Access UPDI Access
Read Write Read Write
USERROW Yes Yes Yes Yes
SIGROW Yes No Yes No
Other Fuses Yes No Yes Yes
Table 6-6 Memory Access in Locked Mode (FUSELOCKBIT Invalid)(1)
Memory Section CPU Access UPDI Access
Read Write Read Write
SRAM Yes Yes No No
Registers Yes Yes No No
Flash Yes Yes No No
EEPROM Yes No No No
USERROW Yes Yes No Yes(2)
SIGROW Yes No Yes No
Other Fuses Yes No No No
Note 1 Read operations marked No in the tables may appear to be successful but the data is corrupt
Hence any attempt of code validation through the UPDI will fail on these memory sections2 In Locked mode the USERROW can be written blindly using the fuse Write command but the
current USERROW values cannot be read out
Important The only way to unlock a device is a CHIPERASE which will erase all devicememories to factory default so that no application data is retained
Related LinksFuse Summary - FUSELOCKBITUnified Program and Debug Interface (UPDI)Enabling of KEY Protected Interfaces
69 IO MemoryAll ATtiny406 IOs and peripherals are located in the IO memory space The IO address range from0x00 to 0x3F can be accessed in a single cycle using IN and OUT instructions The extended IO memoryspace from 0x0040 - 0x0FFF can be accessed by the LDLDSLDD and STSTSSTD instructionstransferring data between the 32 general purpose working registers and the IO memory space
ATtiny406Memories
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IO registers within the address range 0x00 - 0x1F are directly bit accessible using the SBI and CBIinstructions In these registers the value of single bits can be checked by using the SBIS and SBICinstructions Refer to the Instruction Set section for more details
For compatibility with future devices reserved bits should be written to zero if accessed Reserved IOmemory addresses should never be written
Some of the interrupt flags are cleared by writing a 1 to them On ATtiny406 devices the CBI and SBIinstructions will only operate on the specified bit and can be used on registers containing such interruptflags The CBI and SBI instructions work with registers 0x00 - 0x1F only
General Purpose IO RegistersThe ATtiny406 devices provide four general purpose IO registers These registers can be used forstoring any information and they are particularly useful for storing global variables and interrupt flagsgeneral purpose IO registers which reside in the address range 0x1C - 0x1F are directly bit accessibleusing the SBI CBI SBIS and SBIC instructions
Related LinksMemory MapPeripheral Module Address MapInstruction Set Summary
ATtiny406Memories
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691 Register Summary - GPIOR
Offset Name Bit Pos
0x00 GPIOR0 70 GPIOR[70]
0x01 GPIOR1 70 GPIOR[70]
0x02 GPIOR2 70 GPIOR[70]
0x03 GPIOR3 70 GPIOR[70]
692 Register Description - GPIOR
ATtiny406Memories
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6921 General Purpose IO Register n
Name GPIOROffset 0x00 + n0x01 [n=03]Reset 0x00Property -
These are general purpose registers that can be used to store data such as global variables and flags inthe bit accessible IO memory space
Bit 7 6 5 4 3 2 1 0 GPIOR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash GPIOR[70] GPIO Register byte
610 Configuration and User Fuses (FUSE)Fuses are part of the nonvolatile memory and hold factory calibration data and device configuration Thefuses are available from device power-up The fuses can be read by the CPU or the UPDI but can onlybe programmed or cleared by the UPDI The configuration and calibration values stored in the fuses arewritten to their respective target registers at the end of the start-up sequence
The content of the Signature Row fuses (SIGROW) is pre-programmed and cannot be altered SIGROWholds information such as device ID serial number and calibration values
The fuses for peripheral configuration (FUSE) are pre-programmed but can be altered by the userAltered values in the configuration fuse will be effective only after a ResetNote When writing the fuses write all reserved bits to lsquo1rsquo
This device provides a User Row fuse area (USERROW) that can hold application data The USERROWcan be programmed on a locked device by the UPDI This can be used for final configuration withouthaving programming or debugging capabilities enabled
Related LinksSignature Row DescriptionFuse Description
ATtiny406Memories
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6101 Signature Row Summary - SIGROW
Offset Name Bit Pos
0x00 DEVICEID0 70 DEVICEID[70]
0x01 DEVICEID1 70 DEVICEID[70]
0x02 DEVICEID2 70 DEVICEID[70]
0x03 SERNUM0 70 SERNUM[70]
0x04 SERNUM1 70 SERNUM[70]
0x05 SERNUM2 70 SERNUM[70]
0x06 SERNUM3 70 SERNUM[70]
0x07 SERNUM4 70 SERNUM[70]
0x08 SERNUM5 70 SERNUM[70]
0x09 SERNUM6 70 SERNUM[70]
0x0A SERNUM7 70 SERNUM[70]
0x0B SERNUM8 70 SERNUM[70]
0x0C SERNUM9 70 SERNUM[70]
0x0D
0x1F
Reserved
0x20 TEMPSENSE0 70 TEMPSENSE[70]
0x21 TEMPSENSE1 70 TEMPSENSE[70]
0x22 OSC16ERR3V 70 OSC16ERR3V[70]
0x23 OSC16ERR5V 70 OSC16ERR5V[70]
0x24 OSC20ERR3V 70 OSC20ERR3V[70]
0x25 OSC20ERR5V 70 OSC20ERR5V[70]
6102 Signature Row Description
ATtiny406Memories
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61021 Device ID n
Name DEVICEIDnOffset 0x00 + n0x01 [n=02]Reset [Device ID]Property -
Each device has a device ID identifying the device and its properties such as memory sizes pin countand die revision This can be used to identify a device and hence the available features by software TheDevice ID consists of three bytes SIGROWDEVICEID[20]
Bit 7 6 5 4 3 2 1 0 DEVICEID[70]
Access R R R R R R R R Reset x x x x x x x x
Bits 70 ndash DEVICEID[70] Byte n of the Device ID
ATtiny406Memories
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61022 Serial Number Byte n
Name SERNUMnOffset 0x03 + n0x01 [n=09]Reset [device serial number]Property -
Each device has an individual serial number representing a unique ID This can be used to identify aspecific device in the field The serial number consists of ten bytes SIGROWSERNUM[90]
Bit 7 6 5 4 3 2 1 0 SERNUM[70]
Access R R R R R R R R Reset x x x x x x x x
Bits 70 ndash SERNUM[70] Serial Number Byte n
ATtiny406Memories
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61023 Temperature Sensor Calibration n
Name TEMPSENSEnOffset 0x20 + n0x01 [n=01]Reset [Temperature sensor calibration value]Property -
These registers contain correction factors for temperature measurements by the ADCSIGROWTEMPSENSE0 is a correction factor for the gainslope (unsigned) SIGROWTEMPSENSE1 isa correction factor for the offset (signed)
Bit 7 6 5 4 3 2 1 0 TEMPSENSE[70]
Access R R R R R R R R Reset x x x x x x x x
Bits 70 ndash TEMPSENSE[70] Temperature Sensor Calibration Byte nRefer to Temperature Measurement for how to use the values and to the Signature Row Descriptionsection for location of the values
ATtiny406Memories
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61024 OSC16 Error at 3V
Name OSC16ERR3VOffset 0x22Reset [Oscillator frequency error value]Property -
Bit 7 6 5 4 3 2 1 0 OSC16ERR3V[70]
Access R R R R R R R R Reset x x x x x x x x
Bits 70 ndash OSC16ERR3V[70] OSC16 Error at 3VThese registers contain the signed oscillator frequency error value when running at internal 16 MHz at 3Vas measured during production
ATtiny406Memories
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61025 OSC16 Error at 5V
Name OSC16ERR5VOffset 0x23Reset [Oscillator frequency error value]Property -
Bit 7 6 5 4 3 2 1 0 OSC16ERR5V[70]
Access R R R R R R R R Reset x x x x x x x x
Bits 70 ndash OSC16ERR5V[70] OSC16 Error at 5VThese registers contain the signed oscillator frequency error value when running at internal 16 MHz at 5Vas measured during production
ATtiny406Memories
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61026 OSC20 Error at 3V
Name OSC20ERR3VOffset 0x24Reset [Oscillator frequency error value]Property -
Bit 7 6 5 4 3 2 1 0 OSC20ERR3V[70]
Access R R R R R R R R Reset x x x x x x x x
Bits 70 ndash OSC20ERR3V[70] OSC20 Error at 3VThese registers contain the signed oscillator frequency error value when running at internal 20 MHz at 3Vas measured during production
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61027 OSC20 Error at 5V
Name OSC20ERR5VOffset 0x25Reset [Oscillator frequency error value]Property -
Bit 7 6 5 4 3 2 1 0 OSC20ERR5V[70]
Access R R R R R R R R Reset x x x x x x x x
Bits 70 ndash OSC20ERR5V[70] OSC20 Error at 5VThese registers contain the signed oscillator frequency error value when running at internal 20 MHz at 5Vas measured during production
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6103 Fuse Summary - FUSE
Offset Name Bit Pos
0x00 WDTCFG 70 WINDOW[30] PERIOD[30]
0x01 BODCFG 70 LVL[20] SAMPFREQ ACTIVE[10] SLEEP[10]
0x02 OSCCFG 70 OSCLOCK FREQSEL[10]
0x03
0x04
Reserved
0x05 SYSCFG0 70 CRCSRC[10] RSTPINCFG[10] EESAVE
0x06 SYSCFG1 70 SUT[20]
0x07 APPEND 70 APPEND[70]
0x08 BOOTEND 70 BOOTEND[70]
0x09 Reserved
0x0A LOCKBIT 70 LOCKBIT[70]
6104 Fuse Description
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61041 Watchdog Configuration
Name WDTCFGOffset 0x00Reset -Property -
Bit 7 6 5 4 3 2 1 0 WINDOW[30] PERIOD[30]
Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bits 74 ndash WINDOW[30] Watchdog Window Time-out PeriodThis value is loaded into the WINDOW bit field of the Watchdog Control A register (WDTCTRLA) duringReset
Bits 30 ndash PERIOD[30] Watchdog Time-out PeriodThis value is loaded into the PERIOD bit field of the Watchdog Control A register (WDTCTRLA) duringResetRelated LinksRegister Summary - WDTReset Controller (RSTCTRL)
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61042 BOD Configuration
Name BODCFGOffset 0x01Reset -Property -
The settings of the BOD will be reloaded from this Fuse after a Power-on Reset For all other Resets theBOD configuration remains unchanged
Bit 7 6 5 4 3 2 1 0 LVL[20] SAMPFREQ ACTIVE[10] SLEEP[10]
Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bits 75 ndash LVL[20] BOD LevelThis value is loaded into the LVL bit field of the BOD Control B register (BODCTRLB) during Reset
Value Name Description0x0 BODLEVEL0 18V0x1 BODLEVEL1 215V0x2 BODLEVEL2 260V0x3 BODLEVEL3 295V0x4 BODLEVEL4 330V0x5 BODLEVEL5 370V0x6 BODLEVEL6 400V0x7 BODLEVEL7 430V
Bit 4 ndash SAMPFREQ BOD Sample FrequencyThis value is loaded into the SAMPFREQ bit of the BOD Control A register (BODCTRLA) during Reset
Value Description0x0 Sample frequency is 1 kHz0x1 Sample frequency is 125 Hz
Bits 32 ndash ACTIVE[10] BOD Operation Mode in Active and IdleThis value is loaded into the ACTIVE bit field of the BOD Control A register (BODCTRLA) during Reset
Value Description0x0 Disabled0x1 Enabled0x2 Sampled0x3 Enabled with wake-up halted until BOD is ready
Bits 10 ndash SLEEP[10] BOD Operation Mode in SleepThis value is loaded into the SLEEP bit field of the BOD Control A register (BODCTRLA) during Reset
Value Description0x0 Disabled0x1 Enabled
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Value Description0x2 Sampled0x3 Reserved
Related LinksRegister Summary - BODReset Controller (RSTCTRL)
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61043 Oscillator Configuration
Name OSCCFGOffset 0x02Reset -Property -
Bit 7 6 5 4 3 2 1 0 OSCLOCK FREQSEL[10]
Access R R R Reset 0 1 0
Bit 7 ndash OSCLOCK Oscillator LockThis fuse bit is loaded to LOCK in CLKCTRLOSC20MCALIBB during Reset
Value Description0 Calibration registers of the 20 MHz oscillator are accessible1 Calibration registers of the 20 MHz oscillator are locked
Bits 10 ndash FREQSEL[10] Frequency SelectThese bits select the operation frequency of the 1620 MHz internal oscillator (OSC20M) and determinethe respective factory calibration values to be written to CAL20M in CLKCTRLOSC20MCALIBA andTEMPCAL20M in CLKCTRLOSC20MCALIBB
Value Description0x1 Run at 16 MHz with corresponding factory calibration0x2 Run at 20 MHz with corresponding factory calibrationOther Reserved
Related LinksRegister Summary - CLKCTRLReset Controller (RSTCTRL)
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61044 System Configuration 0
Name SYSCFG0Offset 0x05Reset 0xC4Property -
Bit 7 6 5 4 3 2 1 0 CRCSRC[10] RSTPINCFG[10] EESAVE
Access R R R R R Reset 1 1 0 1 0
Bits 76 ndash CRCSRC[10] CRC SourceSee CRC description for more information about the functionality
Value Name Description00 FLASH CRC of full Flash (boot application code and application data)01 BOOT CRC of boot section10 BOOTAPP CRC of application code and boot sections11 NOCRC No CRC
Bits 32 ndash RSTPINCFG[10] Reset Pin ConfigurationThese bits select the ResetUPDI pin configuration
Value Description0x0 GPIO0x1 UPDI0x2 RESET0x3 Reserved
Bit 0 ndash EESAVE EEPROM Save During Chip EraseIf the device is locked the EEPROM is always erased by a chip erase regardless of this bit
Value Description0 EEPROM erased during chip erase1 EEPROM not erased under chip erase
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61045 System Configuration 1
Name SYSCFG1Offset 0x06Reset -Property -
Bit 7 6 5 4 3 2 1 0 SUT[20]
Access R R R Reset 1 1 1
Bits 20 ndash SUT[20] Start-Up Time SettingThese bits select the start-up time between power-on and code execution
Value Description0x0 0 ms0x1 1 ms0x2 2 ms0x3 4 ms0x4 8 ms0x5 16 ms0x6 32 ms0x7 64 ms
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61046 Application Code End
Name APPENDOffset 0x07Reset -Property -
Bit 7 6 5 4 3 2 1 0 APPEND[70]
Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bits 70 ndash APPEND[70] Application Code Section EndThese bits set the end of the application code section in blocks of 256 bytes The end of the applicationcode section should be set as BOOT size plus application code size The remaining Flash will beapplication data A value of 0x00 defines the Flash from BOOTEND256 to end of Flash as applicationcode When both FUSEAPPEND and FUSEBOOTEND are 0x00 the entire Flash is BOOT sectionRelated LinksNonvolatile Memory Controller (NVMCTRL)Flash
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61047 Boot End
Name BOOTENDOffset 0x08Reset -Property -
Bit 7 6 5 4 3 2 1 0 BOOTEND[70]
Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bits 70 ndash BOOTEND[70] Boot Section EndThese bits set the end of the boot section in blocks of 256 bytes A value of 0x00 defines the whole Flashas BOOT section When both FUSEAPPEND and FUSEBOOTEND are 0x00 the entire Flash is BOOTsectionRelated LinksNonvolatile Memory Controller (NVMCTRL)Flash
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61048 Lockbits
Name LOCKBITOffset 0x0AReset -Property -
Bit 7 6 5 4 3 2 1 0 LOCKBIT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash LOCKBIT[70] LockbitsWhen the part is locked UPDI cannot access the system bus so it cannot read out anything but CS-space
Value Description0xC5 Valid key - the device is openother Invalid - The device is locked
Related LinksMemory Section Access from CPU and UPDI on Locked Device
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7 Peripherals and Architecture
71 Peripheral Module Address MapThe address map shows the base address for each peripheral For complete register description andsummary for each peripheral module refer to the respective module chapters
Table 7-1 Peripheral Module Address Map
Base Address Name Description
0x0000 VPORTA Virtual Port A
0x0004 VPORTB Virtual Port B
0x0008 VPORTC Virtual Port C
0x001C GPIO General Purpose IO registers
0x0030 CPU CPU
0x0040 RSTCTRL Reset Controller
0x0050 SLPCTRL Sleep Controller
0x0060 CLKCTRL Clock Controller
0x0080 BOD Brown-Out Detector
0x00A0 VREF Voltage Reference
0x0100 WDT Watchdog Timer
0x0110 CPUINT Interrupt Controller
0x0120 CRCSCAN Cyclic Redundancy Check Memory Scan
0x0140 RTC Real-Time Counter
0x0180 EVSYS Event System
0x01C0 CCL Configurable Custom Logic
0x0200 PORTMUX Port Multiplexer
0x0400 PORTA Port A Configuration
0x0420 PORTB Port B Configuration
0x0440 PORTC Port C Configuration
0x0600 ADC0 Analog-to-Digital ConverterPeripheral Touch Controller
0x0680 AC0 Analog Comparator 0
0x0800 USART0 Universal Synchronous Asynchronous Receiver Transmitter
0x0810 TWI0 Two-Wire Interface
0x0820 SPI0 Serial Peripheral Interface
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Base Address Name Description
0x0A00 TCA0 TimerCounter Type A instance 0
0x0A40 TCB0 TimerCounter Type B instance 0
0x0F00 SYSCFG System Configuration
0x1000 NVMCTRL Nonvolatile Memory Controller
0x1100 SIGROW Signature Row
0x1280 FUSES Device-specific fuses
0x1300 USERROW User Row
72 Interrupt Vector MappingEach of the interrupt vectors is connected to one peripheral instance as shown in the table below Aperipheral can have one or more interrupt sources see the Interrupt section in the Functional descriptionof the respective peripheral for more details on the available interrupt sources
When the interrupt condition occurs an Interrupt Flag (nameIF) is set in the Interrupt Flags register of theperipheral (peripheralINTFLAGS)
An interrupt is enabled or disabled by writing to the corresponding Interrupt Enable bit (nameIE) in theperipherals Interrupt Control register (peripheralINTCTRL)
The naming of the registers may vary slightly in some peripherals
An interrupt request is generated when the corresponding interrupt is enabled and the interrupt flag is setThe interrupt request remains active until the interrupt flag is cleared See the peripherals INTFLAGSregister for details on how to clear interrupt flags
Interrupts must be enabled globally for interrupt requests to be generated
Table 7-2 Interrupt Vector Mapping
Vector Number Peripheral Source Definition
0 RESET RESET
1 CRCSCAN_NMI NMI - Non-Maskable Interrupt from CRC
2 BOD_VLM VLM - Voltage Level Monitor
3 PORTA_PORT PORTA - Port A
4 PORTB_PORT PORTB - Port B
5 PORTC_PORT PORTC - Port C
6 RTC_CNT RTC - Real-Time Counter
7 RTC_PIT PIT - Periodic Interrupt Timer (in RTC peripheral)
8 TCA0_LUNFTCA0_OVF TCA0 - Timer Counter Type A LUNFOVF
9 TCA0_HUNF TCA0 HUNF
10 TCA0_LCMP0TCA0_CMP0 TCA0 LCMP0CMP0
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Vector Number Peripheral Source Definition
11 TCA0_LCMP1TCA0_CMP1 TCA0 LCMP1CMP1
12 TCA0_CMP2TCA0_LCMP2 TCA0 LCMP2CMP2
13 TCB0_INT TCB0 - Timer Counter Type B
16 - -
17 AC0_AC AC0 ndash Analog Comparator
18 - -
19 - -
20 ADC0_RESRDY ADC0 ndash Analog-to-Digital Converter RESRDY
21 ADC0_WCOMP ADC0 WCOMP
22 - -
23 - -
24 TWI0_TWIS TWI0 - Two-Wire InterfaceI2C TWIS
25 TWI0_TWIM TWI0 TWIM
26 SPI0_INT SPI0 - Serial Peripheral Interface
27 USART0_RXC USART0 - Universal Asynchronous Receiver-Transmitter RXC
28 USART0_DRE USART0 DRE
29 USART0_TXC USART0 TXC
30 NVMCTRL_EE NVM - Nonvolatile Memory
Related LinksNonvolatile Memory Controller (NVMCTRL)IO Pin Configuration (PORT)Real-Time Counter (RTC)Serial Peripheral Interface (SPI)Universal Synchronous and Asynchronous Receiver and Transmitter (USART)Two-Wire Interface (TWI)Cyclic Redundancy Check Memory Scan (CRCSCAN)16-bit TimerCounter Type A (TCA)16-bit TimerCounter Type B (TCB)Analog Comparator (AC)Analog-to-Digital Converter (ADC)
73 System Configuration (SYSCFG)The system configuration contains the revision ID of the part The revision ID is readable from the CPUmaking it useful for implementing application changes between part revisions
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731 Register Summary - SYSCFG
Offset Name Bit Pos
0x01 REVID 70 REVID[70]
732 Register Description - SYSCFG
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7321 Device Revision ID Register
Name REVIDOffset 0x01Reset [revision ID]Property -
This register is read-only and displays the device revision ID
Bit 7 6 5 4 3 2 1 0 REVID[70]
Access R R R R R R R R Reset
Bits 70 ndash REVID[70] Revision IDThese bits contain the device revision 0x00 = A 0x01 = B and so on
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8 AVR CPU
81 Featuresbull 8-Bit High-Performance AVR RISC CPU
ndash 135 instructionsndash Hardware multiplier
bull 32 8-Bit Registers Directly Connected to the Arithmetic Logic Unit (ALU)bull Stack in RAMbull Stack Pointer Accessible in IO Memory Spacebull Direct Addressing of up to 64 KB of Unified Memory
ndash Entire Flash accessible with all LDST instructionsbull True 16-Bit Access to 16-Bit IO Registersbull Efficient Support for 8- 16- and 32-Bit Arithmeticbull Configuration Change Protection for System Critical Features
82 OverviewAll AVR devices use the 8-bit AVR CPU The CPU is able to access memories perform calculationscontrol peripherals and execute instructions in the program memory Interrupt handling is described in aseparate section
Related LinksMemoriesNonvolatile Memory Controller (NVMCTRL)CPU Interrupt Controller (CPUINT)
83 ArchitectureIn order to maximize performance and parallelism the AVR CPU uses a Harvard architecture withseparate buses for program and data Instructions in the program memory are executed with single-levelpipelining While one instruction is being executed the next instruction is prefetched from the programmemory This enables instructions to be executed on every clock cycle
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Figure 8-1 AVR CPU Architecture
Register file
Flash Program Memory
Data Memory
ALU
R0R1R2R3R4R5R6R7R8R9R10R11R12R13R14R15R16R17R18R19R20R21R22R23R24R25
R26 (XL)R27 (XH)R28 (YL)R29 (YH)R30 (ZL)R31 (ZH)
Stack Pointer
Program Counter
Instruction Register
Instruction Decode
STATUS Register
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between aconstant and a register Also single-register operations can be executed in the ALU After an arithmeticoperation the STATUS register is updated to reflect information about the result of the operation
The ALU is directly connected to the fast-access register file The 32 8-bit general purpose workingregisters all have single clock cycle access time allowing single-cycle arithmetic logic unit operation
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between registers or between a register and an immediate Six of the 32 registers can be used as three16-bit Address Pointers for program and data space addressing enabling efficient address calculations
The program memory bus is connected to Flash and the first program memory Flash address is 0x0000
The data memory space is divided into IO registers SRAM EEPROM and Flash
All IO Status and Control registers reside in the lowest 4 KB addresses of the data memory This isreferred to as the IO memory space The lowest 64 addresses are accessed directly with single-cycleINOUT instructions or as the data space locations from 0x00 to 0x3F These addresses can be accessedusing load (LDLDSLDD) and store (STSTSSTD) instructions The lowest 32 addresses can even beaccessed with single-cycle SBICBI instructions and SBISSBIC instructions The rest is the extendedIO memory space ranging from 0x0040 to 0x0FFF The IO registers here must be accessed as dataspace locations using load and store instructions
Data addresses 0x1000 to 0x1800 are reserved for memory mapping of fuses the NVM controller andEEPROM The addresses from 0x1800 to 0x7FFF are reserved for other memories such as SRAM
The Flash is mapped in the data space from 0x8000 and above The Flash can be accessed with all loadand store instructions by using addresses above 0x8000 The LPM instruction accesses the Flash similarto the code space where the Flash starts at address 0x0000
For a summary of all AVR instructions refer to the Instruction Set Summary section For details of all AVRinstructions refer to httpwwwmicrochipcomdesign-centers8-bit
Related LinksNonvolatile Memory Controller (NVMCTRL)MemoriesInstruction Set Summary
84 Arithmetic Logic Unit (ALU)The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between aconstant and a register Also single-register operations can be executed
The ALU operates in direct connection with all 32 general purpose registers Arithmetic operationsbetween general purpose registers or between a register and an immediate are executed in a single clockcycle and the result is stored in the register file After an arithmetic or logic operation the Status register(CPUSREG) is updated to reflect information about the result of the operation
ALU operations are divided into three main categories ndash arithmetic logical and bit functions Both 8- and16-bit arithmetic are supported and the instruction set allows for efficient implementation of 32-bitarithmetic The hardware multiplier supports signed and unsigned multiplication and fractional format
841 Hardware MultiplierThe multiplier is capable of multiplying two 8-bit numbers into a 16-bit result The hardware multipliersupports different variations of signed and unsigned integer and fractional numbers
bull Multiplication of signedunsigned integersbull Multiplication of signedunsigned fractional numbersbull Multiplication of a signed integer with an unsigned integerbull Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles
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85 Functional Description
851 Program FlowAfter Reset the CPU will execute instructions from the lowest address in the Flash program memory0x0000 The Program Counter (PC) addresses the next instruction to be fetched
Program flow is supported by conditional and unconditional JUMP and CALL instructions capable ofaddressing the whole address space directly Most AVR instructions use a 16-bit word format and alimited number use a 32-bit format
During interrupts and subroutine calls the return address PC is stored on the stack as a Word PointerThe stack is allocated in the general data SRAM and consequently the stack size is only limited by thetotal SRAM size and the usage of the SRAM After Reset the Stack Pointer (SP) points to the highestaddress in the internal SRAM The SP is readwrite accessible in the IO memory space enabling easyimplementation of multiple stacks or stack areas The data SRAM can easily be accessed through thefive different addressing modes supported by the AVR CPU
852 Instruction Execution TimingThe AVR CPU is clocked by the CPU clock CLK_CPU No internal clock division is applied The figurebelow shows the parallel instruction fetches and instruction executions enabled by the Harvardarchitecture and the fast-access register file concept This is the basic pipelining concept enabling up to 1MIPSMHz performance with high efficiency
Figure 8-2 The Parallel Instruction Fetches and Instruction Executions
clk
1st Instruction Fetch1st Instruction Execute
2nd Instruction Fetch2nd Instruction Execute
3rd Instruction Fetch3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
The following figure shows the internal timing concept for the register file In a single clock cycle an ALUoperation using two register operands is executed and the result is stored in the destination register
Figure 8-3 Single Cycle ALU Operation
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU
853 Status RegisterThe Status register (CPUSREG) contains information about the result of the most recently executedarithmetic or logic instruction This information can be used for altering program flow in order to performconditional operations
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CPUSREG is updated after all ALU operations as specified in the Instruction Set Summary This will inmany cases remove the need for using the dedicated compare instructions resulting in faster and morecompact code CPUSREG is not automatically storedrestored when enteringreturning from an InterruptService Routine Maintaining the Status register between context switches must therefore be handled byuser-defined software CPUSREG is accessible in the IO memory space
Related LinksInstruction Set Summary
854 Stack and Stack PointerThe stack is used for storing return addresses after interrupts and subroutine calls Also it can be usedfor storing temporary data The Stack Pointer (SP) always points to the top of the stack The SP isdefined by the Stack Pointer bits in the Stack Pointer register (CPUSP) The CPUSP is implemented astwo 8-bit registers that are accessible in the IO memory space
Data is pushed and popped from the stack using the PUSH and POP instructions The stack grows fromhigher to lower memory locations This implies that pushing data onto the stack decreases the SP andpopping data off the stack increases the SP The Stack Pointer is automatically set to the highest addressof the internal SRAM after Reset If the stack is changed it must be set to point above address 0x2000and it must be defined before any subroutine calls are executed and before interrupts are enabled
During interrupts or subroutine calls the return address is automatically pushed on the stack as a WordPointer and the SP is decremented by 2 The return address consists of two bytes and the LeastSignificant Byte is pushed on the stack first (at the higher address) As an example a Byte Pointer returnaddress of 0x0006 is saved on the stack as 0x0003 (shifted one bit to the right) pointing to the fourth 16-bit instruction word in the program memory The return address is popped off the stack with RETI (whenreturning from interrupts) and RET (when returning from subroutine calls) and the SP is incremented bytwo
The SP is decremented by 1 when data is pushed on the stack with the PUSH instruction andincremented by 1 when data is popped off the stack using the POP instruction
To prevent corruption when updating the Stack Pointer from software a write to SPL will automaticallydisable interrupts for up to four instructions or until the next IO memory write
855 Register FileThe register file consists of 32 8-bit general purpose working registers with single clock cycle access timeThe register file supports the following inputoutput schemes
bull One 8-bit output operand and one 8-bit result inputbull Two 8-bit output operands and one 8-bit result inputbull Two 8-bit output operands and one 16-bit result inputbull One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit Address Register Pointers for data space addressingenabling efficient address calculations
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Figure 8-4 AVR CPU General Purpose Working Registers
7 0R0R1R2
R13R14R15R16R17
R26R27R28R29R30R31
Addr0x000x010x02
0x0D0x0E0x0F0x100x11
0x1A0x1B0x1C0x1D0x1E0x1F
X-register Low ByteX-register High ByteY-register Low ByteY-register High ByteZ-register Low ByteZ-register High Byte
The register file is located in a separate address space and is therefore not accessible throughinstructions operation on data memory
8551 The X- Y- and Z-RegistersRegisters R26R31 have added functions besides their general purpose usage
These registers can form 16-bit Address Pointers for addressing data memory These three addressregisters are called the X-register Y-register and Z-register Load and store instructions can use all X-Y- and Z-registers while the LPM instructions can only use the Z-register Indirect calls and jumps (ICALLand IJMP) also use the Z-register
Refer to the instruction set or Instruction Set Summary for more information about how the X- Y- and Z-registers are used
Figure 8-5 The X- Y- and Z-RegistersBit (individually)
X-register
Bit (X-register)
7 0 7 0
15 8 7 0
R27 R26
XH XL
Bit (individually)
Y-register
Bit (Y-register)
7 0 7 0
15 8 7 0
R29 R28
YH YL
Bit (individually)
Z-register
Bit (Z-register)
7 0 7 0
15 8 7 0
R31 R30
ZH ZL
The lowest register address holds the Least Significant Byte (LSB) and the highest register addressholds the Most Significant Byte (MSB) In the different addressing modes these address registersfunction as fixed displacement automatic increment and automatic decrement
Related LinksInstruction Set Summary
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856 Accessing 16-Bit RegistersThe AVR data bus is 8-bits wide and so accessing 16-bit registers requires atomic operations Theseregisters must be byte accessed using two read or write operations 16-bit registers are connected to the8-bit bus and a temporary register using a 16-bit bus
For a write operation the low byte of the 16-bit register must be written before the high byte The low byteis then written into the temporary register When the high byte of the 16-bit register is written thetemporary register is copied into the low byte of the 16-bit register in the same clock cycle
For a read operation the low byte of the 16-bit register must be read before the high byte When the lowbyte register is read by the CPU the high byte of the 16-bit register is copied into the temporary registerin the same clock cycle as the low byte is read When the high byte is read it is then read from thetemporary register
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously whenreading or writing the register
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bitregister during an atomic 16-bit readwrite operation To prevent this interrupts can be disabled whenwriting or reading 16-bit registers
The temporary registers can be read and written directly from user software
857 Configuration Change Protection (CCP)System critical IO register settings are protected from accidental modification Flash self-programming(via store to NVM controller) is protected from accidental execution This is handled globally by theConfiguration Change Protection (CCP) register
Changes to the protected IO registers or bits or execution of protected instructions are only possibleafter the CPU writes a signature to the CCP register The different signatures are listed in the descriptionof the CCP register (CPUCCP)
There are two modes of operation one for protected IO registers and one for the protected self-programming
Related LinksCCP
8571 Sequence for Write Operation to Configuration Change Protected IO RegistersIn order to write to registers protected by CCP these steps are required
1 The software writes the signature that enables change of protected IO registers to the CCP bit fieldin the CPUCCP register
2 Within four instructions the software must write the appropriate data to the protected registerMost protected registers also contain a write enablechange enablelock bit This bit must be writtento 1 in the same operation as the data are written
The protected change is immediately disabled if the CPU performs write operations to the IOregister or data memory if load or store accesses to Flash NVMCTRL EEPROM are conductedor if the SLEEP instruction is executed
8572 Sequence for Execution of Self-ProgrammingIn order to execute self-programming (the execution of writes to the NVM controllers command register)the following steps are required
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1 The software temporarily enables self-programming by writing the SPM signature to the CCPregister (CPUCCP)
2 Within four instructions the software must execute the appropriate instruction The protectedchange is immediately disabled if the CPU performs accesses to the Flash NVMCTRL orEEPROM or if the SLEEP instruction is executed
Once the correct signature is written by the CPU interrupts will be ignored for the duration of theconfiguration change enable period Any interrupt request (including non-maskable interrupts) during theCCP period will set the corresponding interrupt flag as normal and the request is kept pending After theCCP period is completed any pending interrupts are executed according to their level and priority
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86 Register Summary - CPU
Offset Name Bit Pos
0x04 CCP 70 CCP[70]
0x05
0x0C
Reserved
0x0D SP70 SP[70]
158 SP[158]
0x0F SREG 70 I T H S V N Z C
87 Register Description
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871 Configuration Change Protection
Name CCPOffset 0x04Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CCP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash CCP[70] Configuration Change ProtectionWriting the correct signature to this bit field allows changing protected IO registers or executing protectedinstructions within the next four CPU instructions executed
All interrupts are ignored during these cycles After these cycles interrupts will automatically be handledagain by the CPU and any pending interrupts will be executed according to their level and priority
When the protected IO register signature is written CCP[0] will read as 1 as long as the CCP feature isenabled
When the protected self-programming signature is written CCP[1] will read as 1 as long as the CCPfeature is enabled
CCP[72] will always read as zero
Value Name Description0x9D SPM Allow Self-Programming0xD8 IOREG Un-protect protected IO registers
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872 Stack Pointer
Name SPOffset 0x0DReset 0xxxxxProperty -
The CPUSP holds the Stack Pointer (SP) that points to the top of the stack After Reset the StackPointer points to the highest internal SRAM address
Only the number of bits required to address the available data memory including external memory (up to64 KB) is implemented for each device Unused bits will always read as zero
The CPUSPL and CPUSPH register pair represents the 16-bit value CPUSP The low byte [70] (suffixL) is accessible at the original offset The high byte [158] (suffix H) can be accessed at offset + 0x01 Formore details on reading and writing 16-bit registers refer to Accessing 16-Bit Registers
To prevent corruption when updating the SP from software a write to CPUSPL will automatically disableinterrupts for the next four instructions or until the next IO memory write
Bit 15 14 13 12 11 10 9 8 SP[158]
Access RW RW RW RW RW RW RW RW Reset x x x x x x x x
Bit 7 6 5 4 3 2 1 0 SP[70]
Access RW RW RW RW RW RW RW RW Reset x x x x x x x x
Bits 158 ndash SP[158] Stack Pointer High ByteThese bits hold the MSB of the 16-bit register
Bits 70 ndash SP[70] Stack Pointer Low ByteThese bits hold the LSB of the 16-bit register
ATtiny406AVR CPU
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873 STATUS Register
Name SREGOffset 0x0FReset 0x00Property -
The STATUS register contains information about the result of the most recently executed arithmetic orlogic instruction For details about the bits in this register and how they are affected by the differentinstructions see the Instruction Set Summary
Bit 7 6 5 4 3 2 1 0 I T H S V N Z C
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 ndash I Global Interrupt EnableWriting a 1 to this bit enables interrupts on the device
Writing a 0 to this bit disables interrupts on the device independent of the individual interrupt enablesettings of the peripherals
This bit is not cleared by hardware after an interrupt has occurred
This bit can be set and cleared by software with the SEI and CLI instructions
Changing the I flag through the IO register results in a one-cycle Wait state on the access
Bit 6 ndash T Bit Copy StorageThe bit copy instructions bit load (BLD) and bit store (BST) use the T bit as source or destination for theoperated bit
A bit from a register in the register file can be copied into this bit by the BST instruction and this bit canbe copied into a bit in a register in the register file by the BLD instruction
Bit 5 ndash H Half Carry FlagThis bit indicates a half carry in some arithmetic operations Half carry is useful in BCD arithmetic
Bit 4 ndash S Sign Bit S = N oplus VThe sign bit (S) is always an exclusive or (xor) between the negative flag (N) and the tworsquos complementoverflow flag (V)
Bit 3 ndash V Tworsquos Complement Overflow FlagThe tworsquos complement overflow flag (V) supports tworsquos complement arithmetic
Bit 2 ndash N Negative FlagThe negative flag (N) indicates a negative result in an arithmetic or logic operation
Bit 1 ndash Z Zero FlagThe zero flag (Z) indicates a zero result in an arithmetic or logic operation
ATtiny406AVR CPU
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Bit 0 ndash C Carry FlagThe carry flag (C) indicates a carry in an arithmetic or logic operation
ATtiny406AVR CPU
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9 Nonvolatile Memory Controller (NVMCTRL)
91 Featuresbull Unified Memorybull In-System Programmablebull Self-Programming and Boot Loader Supportbull Configurable Sections for Write Protection
ndash Boot section for boot loader code or application codendash Application code section for application codendash Application data section for application code or data storage
bull Signature Row for Factory-Programmed Datandash ID for each device typendash Serial number for each devicendash Calibration bytes for factory calibrated peripherals
bull User Row for Application Datandash 32 bytes in sizendash Can be read and written from softwarendash Can be written from UPDI on locked devicendash Content is kept after chip erase
92 OverviewThe NVM Controller (NVMCTRL) is the interface between the device the Flash and the EEPROM TheFlash and EEPROM are reprogrammable memory blocks that retain their values even when not poweredThe Flash is mainly used for program storage and can be used for data storage The EEPROM is usedfor data storage and can be programmed while the CPU is running the program from the Flash
921 Block DiagramFigure 9-1 NVMCTRL Block Diagram
Flash
EEPROM
NVM Block
Signature Row
User Row
NVMCTRL
Program Memory Bus
Data Memory Bus
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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922 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
Table 9-1 NVMCTRL System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections No -
Interrupts Yes CPUINT
Events No -
Debug Yes UPDI
Related LinksClocksDebug OperationInterrupts
9221 ClocksThis peripheral always runs on the CPU clock (CLK_CPU) It will request this clock also in sleep modes ifa writeerase is ongoing
Related LinksClock Controller (CLKCTRL)
9222 IO Lines and ConnectionsNot applicable
9223 InterruptsUsing the interrupts of this peripheral requires the interrupt controller to be configured first
9224 EventsNot applicable
9225 Debug OperationWhen run-time debugging this peripheral will continue normal operation Halting the CPU in Debuggingmode will halt normal operation of the peripheral
If the peripheral is configured to require periodical service by the CPU through interrupts or similarimproper operation or data loss may result during halted debugging
Related LinksUnified Program and Debug Interface (UPDI)
93 Functional Description
931 Memory Organization
9311 FlashThe Flash is divided into a set of pages A page is the basic unit addressed when programming the FlashIt is only possible to write or erase a whole page at a time One page consists of several words
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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The Flash can be divided into three sections in blocks of 256 bytes for different security The threedifferent sections are BOOT Application Code (APPCODE) and Application Data (APPDATA)
Figure 9-2 Flash SectionsFLASHSTART 0x8000
BOOTENDgt0 0x8000+BOOTEND256
BO OT
APPENDgt0 0x8000+APPEND256
AP PL ICA TIO NCO DE
AP PLICA TIO NDA TA
Section SizesThe sizes of these sections are set by the Boot Section End fuse (FUSEBOOTEND) and ApplicationCode Section End fuse (FUSEAPPEND)
The fuses select the section sizes in blocks of 256 bytes As shown in Figure 9-2 the BOOT sectionstretches from the start of the Flash until BOOTEND The APPCODE section runs from BOOTEND untilAPPEND The remaining area is the APPDATA section If APPEND is written to 0 the APPCODE sectionruns from BOOTEND to the end of Flash (removing the APPDATA section) If BOOTEND and APPENDare written to 0 the entire Flash is regarded as BOOT section APPEND should either be set to 0 or avalue greater or equal than BOOTEND
Table 9-2 Setting Up Flash Sections
BOOTEND APPEND BOOT Section APPCODE Section APPDATA Section
0 0 0 to FLASHEND - -
gt 0 0 0 to 256BOOTEND 256BOOTEND toFLASHEND
-
gt 0 ==BOOTEND
0 to 256BOOTEND - 256BOOTEND toFLASHEND
gt 0 gtBOOTEND
0 to 256BOOTEND 256BOOTEND to256APPEND
256APPEND toFLASHEND
Note bull See also the BOOTEND and APPEND descriptions
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bull Interrupt vectors are by default located after the BOOT section This can be changed in theinterrupt controller Refer to Interrupt Vector Locations
If FUSEBOOTEND is written to 0x04 and FUSEAPPEND is written to 0x08 the first4256 bytes will be BOOT the next 4256 bytes will be APPCODE and the remainingFlash will be APPDATA
Inter-Section Write ProtectionBetween the three Flash sections a directional write protection is implemented
bull Code in the BOOT section can write to APPCODE and APPDATAbull Code in APPCODE can write to APPDATAbull Code in APPDATA cannot write to Flash or EEPROM
Boot Section Lock and Application Code Section Write ProtectionThe two lockbits (APCWP and BOOTLOCK in NVMCTRLCTRLB) can be set to lock further updates ofthe respective APPCODE or BOOT section until the next Reset
The CPU can never write to the BOOT section NVMCTRL_CTRLBBOOTLOCK prevents reads andexecution of code from the BOOT section
9312 EEPROMThe EEPROM is divided into a set of pages where one page consists of multiple bytes The EEPROMhas byte granularity on erase write Within one page only the bytes marked to be updated will be erasedwritten The byte is marked by writing a new value to the page buffer for that address location
9313 User RowThe User Row is one extra page of EEPROM This page can be used to store various data such ascalibrationconfiguration data and serial numbers This page is not erased by a chip erase The User Rowis written as normal EEPROM but in addition it can be written through UPDI on a locked device
932 Memory Access
9321 ReadReading of the Flash and EEPROM is done by using load instructions with an address according to thememory map Reading any of the arrays while a write or erase is in progress will result in a bus wait andthe instruction will be suspended until the ongoing operation is complete
9322 Page Buffer LoadThe page buffer is loaded by writing directly to the memories as defined in the memory map FlashEEPROM and User Row share the same page buffer so only one section can be programmed at onetime The Least Significant bits (LSb) of the address are used to select where in the page buffer the datais written The resulting data will be a binary and operation between the new and the previous content ofthe page buffer The page buffer will automatically be erased (all bits set) after
bull A device Resetbull Any page write or erase operationbull A Clear Page Buffer commandbull The device wakes up from any sleep mode
9323 ProgrammingFor page programming filling the page buffer and writing the page buffer into Flash User Row andEEPROM are two separate operations
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Before programming a Flash page with the data in the page buffer the Flash page must be erased Thepage buffer is also erased when the device enters sleep mode Programming an unerased Flash pagewill corrupt its content
The Flash can either be written with the erase and write separately or one command handling both
Alternative 1bull Fill the page bufferbull Write the page buffer to Flash with the EraseWrite Page command
Alternative 2bull Write to a location in the page to set up the addressbull Perform a Erase Page commandbull Fill the page bufferbull Perform a Write Page command
The NVM command set supports both a single erase and write operation and split Page Erase and PageWrite commands This split commands enable shorter programming time for each command and theerase operations can be done during non-time-critical programming execution
The EEPROM programming is similar but only the bytes updated in the page buffer will be written orerased in the EEPROM
9324 CommandsReading of the FlashEEPROM and writing of the page buffer is handled with normal loadstoreinstructions Other operations such as writing and erasing the memory arrays are handled by commandsin the NVM
To execute a command in the NVM1 Confirm that any previous operation is completed by reading the Busy Flags (EEBUSY and
FBUSY) in the NVMCTRLSTATUS register2 Write the NVM command unlock to the Configuration Change Protection register in the CPU
(CPUCCP)3 Write the desired command value to the CMD bits in the Control A register (NVMCTRLCTRLA)
within the next four instructions
Write CommandThe Write command of the Flash controller writes the content of the page buffer to the Flash or EEPROM
If the write is to the Flash the CPU will stop executing code as long as the Flash is busy with the writeoperation If the write is to the EEPROM the CPU can continue executing code while the operation isongoing
The page buffer will be automatically cleared after the operation is finished
Erase CommandThe Erase command erases the current page There must be one byte written in the page buffer for theErase command to take effect
For erasing the Flash first write to one address in the desired page then execute the command Thewhole page in the Flash will then be erased The CPU will be halted while the erase is ongoing
For the EEPROM only the bytes written in the page buffer will be erased when the command isexecuted To erase a specific byte write to its corresponding address before executing the command To
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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erase a whole page all the bytes in the page buffer have to be updated before executing the commandThe CPU can continue running code while the operation is ongoing
The page buffer will be automatically cleared after the operation is finished
Erase-Write OperationThe EraseWrite command is a combination of the Erase and Write command but without clearing thepage buffer after the Erase command The erasewrite operation first erases the selected page then itwrites the content of the page buffer to the same page
When executed on the Flash the CPU will be halted when the operations are ongoing When executedon EEPROM the CPU can continue executing code
The page buffer will be automatically cleared after the operation is finished
Page Buffer Clear CommandThe Page Buffer Clear command clears the page buffer The contents of the page buffer will be all onesafter the operation The CPU will be halted when the operation executes (seven CPU cycles)
Chip Erase CommandThe Chip Erase command erases the Flash and the EEPROM The EEPROM is unaltered if theEEPROM Save During Chip Erase (EESAVE) fuse in FUSESYSCFG0 is set The Flash will not beprotected by Boot Section Lock (BOOTLOCK) or Application Code Section Write Protection (APCWP) inNVMCTRLCTRLB The memory will be all ones after the operation
EEPROM Erase CommandThe EEPROM Erase command erases the EEPROM The EEPROM will be all ones after the operationThe CPU will be halted while the EEPROM is being erased
Fuse Write CommandThe Fuse Write command writes the fuses It can only be used by the UPDI the CPU cannot start thiscommand
Follow this procedure to use this commandbull Write the address of the fuse to the Address register (NVMCTRLADDR)bull Write the data to be written to the fuse to the Data register (NVMCTRLDATA)bull Execute the Fuse Write commandbull After the fuse is written a Reset is required for the updated value to take effect
For reading fuses use a regular read on the memory location
933 Preventing FlashEEPROM CorruptionDuring periods of low VDD the Flash program or EEPROM data can be corrupted if the supply voltage istoo low for the CPU and the FlashEEPROM to operate properly These issues are the same as for boardlevel systems using FlashEEPROM and the same design solutions should be applied
A FlashEEPROM corruption can be caused by two situations when the voltage is too low First a regularwrite sequence to the Flash requires a minimum voltage to operate correctly Also the CPU itself canexecute instructions incorrectly when the supply voltage is too low See the Electrical Characteristicschapter for Maximum Frequency vs VDD
FlashEEPROM corruption can be avoided by these measures
Keep the device in Reset during periods of insufficient power supply voltage This can be done byenabling the internal Brown-Out Detector (BOD)
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The voltage level monitor in the BOD can be used to prevent starting a write to the EEPROM close to theBOD level
If the detection levels of the internal BOD does not match the required detection level an external lowVDD Reset protection circuit can be used If a Reset occurs while a write operation is ongoing the writeoperation will be aborted
Related LinksGeneral Operating RatingsBrown-Out Detector (BOD)
934 InterruptsTable 9-3 Available Interrupt Vectors and Sources
Offset Name Vector Description Conditions
0x00 EEREADY NVM The EEPROM is ready for new writeerase operations
When an interrupt condition occurs the corresponding interrupt flag is set in the Interrupt Flags register ofthe peripheral (NVMCTRLINTFLAGS)
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripherals InterruptEnable register (NVMCTRLINTEN)
An interrupt request is generated when the corresponding interrupt source is enabled and the interruptflag is set The interrupt request remains active until the interrupt flag is cleared See the peripheralsINTFLAGS register for details on how to clear interrupt flags
935 Sleep Mode OperationIf there is no ongoing write operation the NVMCTRL will enter sleep mode when the system enters sleepmode
If a write operation is ongoing when the system enters a sleep mode the NVM block the NVM Controllerand the system clock will remain on until the write is finished This is valid for all sleep modes includingPower-Down Sleep mode
The EEPROM Ready interrupt will wake-up the device only from Idle Sleep mode
The page buffer is cleared when waking up from Sleep
936 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) In order to write tothese a certain key must be written to the CPUCCP register first followed by a write access to theprotected bits within four CPU instructions
It is possible to try writing to these registers any time but the values are not altered
The following registers are under CCP
Table 9-4 NVMCTRL - Registers under Configuration Change Protection
Register Key
NVMCTRLCTRLA SPM
Related Links
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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Sequence for Execution of Self-Programming
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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94 Register Summary - NVMCTRL
Offset Name Bit Pos
0x00 CTRLA 70 CMD[20]
0x01 CTRLB 70 BOOTLOCK APCWP
0x02 STATUS 70 WRERROR EEBUSY FBUSY
0x03 INTCTRL 70 EEREADY
0x04 INTFLAGS 70 EEREADY
0x05 Reserved
0x06 DATA70 DATA[70]
158 DATA[158]
0x08 ADDR70 ADDR[70]
158 ADDR[158]
95 Register Description
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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951 Control A
Name CTRLAOffset 0x00Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 CMD[20]
Access RW RW RW Reset 0 0 0
Bits 20 ndash CMD[20] CommandWrite this bit field to issue a command The Configuration Change Protection key for self-programming(SPM) has to be written within four instructions before this write
Value Name Description0x0 - No command0x1 WP Write page buffer to memory (NVMCTRLADDR selects which memory)0x2 ER Erase page (NVMCTRLADDR selects which memory)0x3 ERWP Erase and write page (NVMCTRLADDR selects which memory)0x4 PBC Page buffer clear0x5 CHER Chip erase erase Flash and EEPROM (unless EESAVE in FUSESYSCFG is 1)0x6 EEER EEPROM Erase0x7 WFU Write fuse (only accessible through UPDI)
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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952 Control B
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 BOOTLOCK APCWP
Access RW RW Reset 0 0
Bit 1 ndash BOOTLOCK Boot Section LockWriting a 1 to this bit locks the boot section from read and instruction fetch
If this bit is 1 a read from the boot section will return 0 A fetch from the boot section will also return 0as instruction
This bit can be written from the boot section only It can only be cleared to 0 by a Reset
This bit will take effect only when the boot section is left the first time after the bit is written
Bit 0 ndash APCWP Application Code Section Write ProtectionWriting a 1 to this bit protects the application code section from further writes
This bit can only be written to 1 It is cleared to 0 only by Reset
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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953 Status
Name STATUSOffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 WRERROR EEBUSY FBUSY
Access R R R Reset 0 0 0
Bit 2 ndash WRERROR Write ErrorThis bit will read 1 when a write error has happened A write error could be writing to different sectionsbefore doing a page write or writing to a protected area This bit is valid for the last operation
Bit 1 ndash EEBUSY EEPROM BusyThis bit will read 1 when the EEPROM is busy with a command
Bit 0 ndash FBUSY Flash BusyThis bit will read 1 when the Flash is busy with a command
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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954 Interrupt Control
Name INTCTRLOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 EEREADY
Access RW Reset 0
Bit 0 ndash EEREADY EEPROM Ready InterruptWriting a 1 to this bit enables the interrupt which indicates that the EEPROM is ready for new writeerase operations
This is a level interrupt that will be triggered only when the EEREADY flag in the INTFLAGS register is setto zero Thus the interrupt should not be enabled before triggering an NVM command as the EEREADYflag will not be set before the NVM command issued The interrupt should be disabled in the interrupthandler
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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955 Interrupt Flags
Name INTFLAGSOffset 0x04Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 EEREADY
Access RW Reset 0
Bit 0 ndash EEREADY EEREADY Interrupt FlagInterrupt flag for the EEPROM interrupt This bit is cleared by writing a 1 to it When this interrupt isenabled it will immediately request an interrupt and it will continue to request interrupts - even if noEEPROM writes are initiated
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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956 Data
Name DATAOffset 0x06Reset 0x00Property -
The NVMCTRLDATAL and NVMCTRLDATAH register pair represents the 16-bit valueNVMCTRLDATA The low byte [70] (suffix L) is accessible at the original offset The high byte [158](suffix H) can be accessed at offset + 0x01 For more details on reading and writing 16-bit registers referto Accessing 16-Bit Registers
Bit 15 14 13 12 11 10 9 8 DATA[158]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 DATA[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 150 ndash DATA[150] Data RegisterThis register is used by the UPDI for fuse write operations
ATtiny406Nonvolatile Memory Controller (NVMCTRL)
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957 Address
Name ADDROffset 0x08Reset 0x00Property -
The NVMCTRLADDRL and NVMCTRLADDRH register pair represents the 16-bit valueNVMCTRLADDR The low byte [70] (suffix L) is accessible at the original offset The high byte [158](suffix H) can be accessed at offset + 0x01 For more details on reading and writing 16-bit registers referto Accessing 16-Bit Registers
Bit 15 14 13 12 11 10 9 8 ADDR[158]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 ADDR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 150 ndash ADDR[150] AddressThe Address register contains the address to the last memory location that has been updated
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10 Clock Controller (CLKCTRL)
101 Featuresbull All clocks and clock sources are automatically enabled when requested by peripheralsbull Internal Oscillators
ndash 1620 MHz Oscillator (OSC20M)ndash 32 KHz Ultra Low-Power Oscillator (OSCULP32K)
bull External Clock Optionsndash External clock
bull Main Clock Featuresndash Safe run-time switchingndash Prescaler with 1x to 64x division in 12 different settings
102 OverviewThe Clock Controller peripheral (CLKCTRL) controls distributes and prescales the clock signals from theavailable oscillators The CLKCTRL supports internal and external clock sources
The CLKCTRL is based on an automatic clock request system implemented in all peripherals on thedevice The peripherals will automatically request the clocks needed If multiple clock sources areavailable the request is routed to the correct clock source
The Main Clock (CLK_MAIN) is used by the CPU RAM and the IO bus The main clock source can beselected and prescaled Some peripherals can share the same clock source as the main clock or runasynchronously to the main clock domain
ATtiny406Clock Controller (CLKCTRL)
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1021 Block Diagram - CLKCTRLFigure 10-1 CLKCTRL Block Diagram
CPURAMNVM BODRTC
OSC20Mint Oscillator
WDT
DIV32
RTCCLKSEL
CLK_RTCCLK_PER
CLK_MAIN
CLK_WDT CLK_BOD
Main Clock Prescaler
Main Clock Switch
INT
PRESCALER
CLK_CPU
OtherPeripherals
CLKOUT
OSC20M
OSCULP32K
32 KHz ULPInt Oscillator
EXTCLK
The clock system consists of the main clock and other asynchronous clocksbull Main Clock
This clock is used by the CPU RAM Flash the IO bus and all peripherals connected to the IObus It is always running in Active and Idle Sleep mode and can be running in Standby Sleep modeif requested
The main clock CLK_MAIN is prescaled and distributed by the clock controllerbull CLK_CPU is used by the CPU SRAM and the NVMCTRL peripheral to access the
nonvolatile memorybull CLK_PER is used by all peripherals that are not listed under asynchronous clocks
bull Clocks running asynchronously to the main clock domainndash CLK_RTC is used by the RTCPIT It will be requested when the RTCPIT is enabled The
clock source for CLK_RTC should only be changed if the peripheral is disabledndash CLK_WDT is used by the WDT It will be requested when the WDT is enabled
ATtiny406Clock Controller (CLKCTRL)
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ndash CLK_BOD is used by the BOD It will be requested when the BOD is enabled in Sampledmode
The clock source for the for the main clock domain is configured by writing to the Clock Select bits(CLKSEL) in the Main Clock Control A register (CLKCTRLMCLKCTRLA) The asynchronous clocksources are configured by registers in the respective peripheral
1022 Signal Description
Signal Type Description
CLKOUT Digital output CLK_PER output
Related LinksIO Multiplexing and Considerations
103 Functional Description
1031 Sleep Mode OperationWhen a clock source is not usedrequested it will turn off It is possible to request a clock source directlyby writing a 1 to the Run Standby bit (RUNSTDBY) in the respective oscillators Control A register(CLKCTRL[osc]CTRLA) This will cause the oscillator to run constantly except for Power-Down Sleepmode Additionally when this bit is written to 1 the oscillator start-up time is eliminated when the clocksource is requested by a peripheral
The main clock will always run in Active and Idle Sleep mode In Standby Sleep mode the main clock willonly run if any peripheral is requesting it or the Run in Standby bit (RUNSTDBY) in the respectiveoscillators Control A register (CLKCTRL[osc]CTRLA) is written to 1
In Power-Down Sleep mode the main clock will stop after all NVM operations are completed
1032 Main Clock Selection and PrescalerAll internal oscillators can be used as the main clock source for CLK_MAIN The main clock source isselectable from software and can be safely changed during normal operation
Built-in hardware protection prevents unsafe clock switching
Upon selection of an external clock source a switch to the chosen clock source will only occur if edgesare detected indicating it is stable Until a sufficient number of clock edges are detected the switch willnot occur and it will not be possible to change to another clock source again without executing a Reset
An ongoing clock source switch is indicated by the System Oscillator Changing flag (SOSC) in the MainClock Status register (CLKCTRLMCLKSTATUS) The stability of the external clock sources is indicatedby the respective status flags (EXTS in CLKCTRLMCLKSTATUS)
CAUTION If an external clock source fails while used as CLK_MAIN source only the WDT can provide amechanism to switch back via System Reset
CLK_MAIN is fed into a prescaler before it is used by the peripherals (CLK_PER) in the device Theprescaler divide CLK_MAIN by a factor from 1 to 64
ATtiny406Clock Controller (CLKCTRL)
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Figure 10-2 Main Clock and Prescaler
(Div 1 2 4 8 16 32 64 6 10 24 48)
OSC20M
32kHz Osc
External clock
CLK_MAIN CLK_PERMain Clock Prescaler
The Main Clock and Prescaler configuration registers (CLKCTRLMCLKCTRLACLKCTRLMCLKCTRLB) are protected by the Configuration Change Protection Mechanism employing atimed write procedure for changing these registers
Related LinksConfiguration Change Protection (CCP)
1033 Main Clock After Reset
After any Reset CLK_MAIN is provided by the 1620 MHz Oscillator (OSC20M) and with a prescalerdivision factor of 6 Since the actual frequency of the OSC20M is determined by the Frequency Selectbits (FREQSEL) of the Oscillator Configuration fuse (FUSEOSCCFG) these frequencies are possibleafter ResetTable 10-1 Peripheral Clock Frequencies After Reset
CLK_MAINas Per FREQSEL in FUSEOSCCFG
Resulting CLK_PER
16 MHz 266 MHz
20 MHz 33 MHz
See the OSC20M description for further details
Related Links1620 MHz Oscillator (OSC20M)
1034 Clock SourcesAll internal clock sources are enabled automatically when they are requested by a peripheral
The respective Oscillator Status bits in the Main Clock Status register (CLKCTRLMCLKSTATUS) indicatewhether the clock source is running and stable
Related LinksConfiguration and User Fuses (FUSE)Configuration Change Protection (CCP)
10341 Internal OscillatorsThe internal oscillators do not require any external components to run See the related links for accuracyand electrical characteristics
Related LinksElectrical Characteristics
1620 MHz Oscillator (OSC20M)This oscillator can operate at multiple frequencies selected by the value of the Frequency Select bits(FREQSEL) in the Oscillator Configuration Fuse (FUSEOSCCFG) The center frequencies are
ATtiny406Clock Controller (CLKCTRL)
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bull 16 MHzbull 20 MHz
After a system Reset FUSEOSCCFG determines the initial frequency of CLK_MAIN
During Reset the calibration values for the OSC20M are loaded from fuses There are two differentcalibration bit fields The Calibration bit field (CAL20M) in the Calibration A register(CLKCTRLOSC20MCALIBA) enables calibration around the current center frequency The OscillatorTemperature Coefficient Calibration bit field (TEMPCAL20M) in the Calibration B register(CLKCTRLOSC20MCALIBB) enables adjustment of the slope of the temperature drift compensation
For applications requiring more fine-tuned frequency setting than the oscillator calibration providesfactory stored frequency error after calibrations are available
The oscillator calibration can be locked by the Oscillator Lock (OSCLOCK) Fuse (FUSEOSCCFG) Whenthis fuse is 1 it is not possible to change the calibration The calibration is locked if this oscillator is usedas main clock source and the Lock Enable bit (LOCKEN) in the Control B register(CLKCTRLOSC20MCALIBB) is 1
The calibration bits are protected by the Configuration Change Protection Mechanism requiring a timedwrite procedure for changing the main clock and prescaler settings
The start-up time of this oscillator is analog start-up time plus four oscillator cycles Refer to the ElectricalCharacteristics section for the start-up time
When changing the oscillator calibration value the frequency may overshoot If the oscillator is used asthe main clock (CLK_MAIN) it is recommended to change the main clock prescaler so that the main clockfrequency does not exceed frac14 of the maximum operation main clock frequency as described in theGeneral Operating Ratings section The system clock prescaler can be changed back after the oscillatorcalibration value has been updated
Related LinksElectrical CharacteristicsConfiguration and User Fuses (FUSE)Configuration Change ProtectionGeneral Operating RatingsMain Clock After ResetOscillators and Clocks
OSC20M Stored Frequency Error CompensationThis oscillator can operate at multiple frequencies selected by the value of the Frequency Select bits(FREQSEL) in the Oscillator Configuration fuse (FUSEOSCCFG) at Reset As previously mentionedappropriate calibration values are loaded to adjust to center frequency (OSC20M) and temperature driftcompensation (TEMPCAL20M) meeting the specifications defined in the internal oscillatorcharacteristics For applications requiring wider operating range the relative factory stored frequencyerror after calibrations can be used The four errors are measured at different settings and are available inthe signature row as signed byte values
bull SIGROWOSC16ERR3V is the frequency error from 16 MHz measured at 3Vbull SIGROWOSC16ERR5V is the frequency error from 16 MHz measured at 5Vbull SIGROWOSC20ERR3V is the frequency error from 20 MHz measured at 3Vbull SIGROWOSC20ERR5V is the frequency error from 20 MHz measured at 5V
ATtiny406Clock Controller (CLKCTRL)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 79
The error is stored as a compressed Q110 fixed point 8-bit value in order not to lose resolution wherethe MSB is the sign bit and the seven LSBs the lower bits of the Q10BAUDact = BAUD+ BAUD 1024The minimum legal BAUD register value is 0x40 the target BAUD register value should therefore not belower than 0x4A to ensure that the compensated BAUD value stays within the legal range even for partswith negative compensation values The example code below demonstrates how to apply this value formore accurate USART baud rate
include ltasserthgt Baud rate compensated with factory stored frequency error Asynchronous communication without Auto-baud (Sync Field) 16MHz Clock 3V and 600 BAUD
int8_t sigrow_val = SIGROWOSC16ERR3V read signed error int32_t baud_reg_val = 600 ideal BAUD register value assert (baud_reg_val gt= 0x4A) Verify legal min BAUD register value with max neg comp baud_reg_val = (1024 + sigrow_val) sum resolution + error baud_reg_val = 1024 divide by resolution USART0BAUD = (int16_t) baud_reg_val set adjusted baud rate
Related LinksOscillators and Clocks
32 KHz Oscillator (OSCULP32K)The 32 KHz oscillator is optimized for Ultra Low-Power (ULP) operation
This oscillator provides the 1 KHz signal for the Real-Time Counter (RTC) the Watchdog Timer (WDT)and the Brown-out Detector (BOD)
The start-up time of this oscillator is the oscillator start-up time plus four oscillator cycles Refer to theElectrical Characteristics chapter for the start-up time
Related LinksElectrical CharacteristicsBrown-Out Detector (BOD)Watchdog Timer (WDT)Real-Time Counter (RTC)
10342 External Clock SourcesThis external clock source is available
bull External Clock from pin (EXTCLK)
External Clock (EXTCLK)The EXTCLK is taken directly from the pin This GPIO pin is automatically configured for EXTCLK if anyperipheral is requesting this clock
This clock source has a start-up time of two cycles when first requested
1035 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) In order to write tothese a certain key must be written to the CPUCCP register first followed by a write access to theprotected bits within four CPU instructions
ATtiny406Clock Controller (CLKCTRL)
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It is possible to try writing to these registers any time but the values are not altered
The following registers are under CCP
Table 10-2 CLKCTRL - Registers Under Configuration Change Protection
Register Key
CLKCTRLMCLKCTRLB IOREG
CLKCTRLMCLKLOCK IOREG
CLKCTRLMCLKCTRLA IOREG
CLKCTRLOSC20MCTRLA IOREG
CLKCTRLOSC20MCALIBA IOREG
CLKCTRLOSC20MCALIBB IOREG
CLKCTRLOSC32KCTRLA IOREG
Related LinksSequence for Write Operation to Configuration Change Protected IO Registers
ATtiny406Clock Controller (CLKCTRL)
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104 Register Summary - CLKCTRL
Offset Name Bit Pos
0x00 MCLKCTRLA 70 CLKOUT CLKSEL[10]
0x01 MCLKCTRLB 70 PDIV[30] PEN
0x02 MCLKLOCK 70 LOCKEN
0x03 MCLKSTATUS 70 EXTS OSC32KS OSC20MS SOSC
0x04
0x0F
Reserved
0x10 OSC20MCTRLA 70 RUNSTDBY
0x11 OSC20MCALIBA 70 CAL20M[50]
0x12 OSC20MCALIBB 70 LOCK TEMPCAL20M[30]
0x13
0x17
Reserved
0x18 OSC32KCTRLA 70 RUNSTDBY
105 Register Description
ATtiny406Clock Controller (CLKCTRL)
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1051 Main Clock Control A
Name MCLKCTRLAOffset 0x00Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 CLKOUT CLKSEL[10]
Access RW R R R R R RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 ndash CLKOUT System Clock OutWhen this bit is written to 1 the system clock is output to CLKOUT pin
When the device is in a Sleep mode there is no clock output unless a peripheral is using the systemclock
Bits 10 ndash CLKSEL[10] Clock SelectThis bit field selects the source for the Main Clock (CLK_MAIN)
Value Name Description0x0 OSC20M 1620 MHz internal oscillator0x1 OSCULP32K 32 KHz internal ultra low-power oscillator0x2 Reserved Reserved0x3 EXTCLK External clock
ATtiny406Clock Controller (CLKCTRL)
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1052 Main Clock Control B
Name MCLKCTRLBOffset 0x01Reset 0x11Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 PDIV[30] PEN
Access R R R RW RW RW RW RW Reset 0 0 0 1 0 0 0 1
Bits 41 ndash PDIV[30] Prescaler DivisionIf the Prescaler Enable (PEN) bit is written to 1 these bits define the division ratio of the main clockprescaler
These bits can be written during run-time to vary the clock frequency of the system to suit the applicationrequirements
User software must ensure a correct configuration of input frequency (CLK_MAIN) and prescaler settingssuch that the resulting frequency of CLK_PER never exceeds the allowed maximum (see ElectricalCharacteristics)
Value DescriptionValue Division0x0 20x1 40x2 80x3 160x4 320x5 640x8 60x9 100xA 120xB 240xC 48other Reserved
Bit 0 ndash PEN Prescaler EnableThis bit must be written 1 to enable the prescaler When enabled the division ratio is selected by thePDIV bit field
When this bit is written to 0 the main clock will pass through undivided (CLK_PER=CLK_MAIN)regardless of the value of PDIV
ATtiny406Clock Controller (CLKCTRL)
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1053 Main Clock Lock
Name MCLKLOCKOffset 0x02Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 LOCKEN
Access R R R R R R R RW Reset 0 0 0 0 0 0 0 x
Bit 0 ndash LOCKEN Lock EnableWriting this bit to 1 will lock the CLKCTRLMCLKCTRLA and CLKCTRLMCLKCTRLB registers and ifapplicable the calibration settings for the current main clock source from further software updates Oncelocked the CLKCTRLMCLKLOCK registers cannot be accessed until the next hardware Reset
This provides protection for the CLKCTRLMCLKCTRLA and CLKCTRLMCLKCTRLB registers andcalibration settings for the main clock source from unintentional modification by software
Related LinksConfiguration and User Fuses (FUSE)
ATtiny406Clock Controller (CLKCTRL)
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1054 Main Clock Status
Name MCLKSTATUSOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 EXTS OSC32KS OSC20MS SOSC
Access R R R R R R R Reset 0 0 0 0 0 0 0
Bit 7 ndash EXTS External Clock Status
Value Description0 EXTCLK has not started1 EXTCLK has started
Bit 5 ndash OSC32KS OSCULP32K StatusThe Status bit will only be available if the source is requested as the main clock or by another module Ifthe oscillator RUNSTDBY bit is set but the oscillator is unusednot requested this bit will be 0
Value Description0 OSCULP32K is not stable1 OSCULP32K is stable
Bit 4 ndash OSC20MS OSC20M StatusThe Status bit will only be available if the source is requested as the main clock or by another module Ifthe oscillator RUNSTDBY bit is set but the oscillator is unusednot requested this bit will be 0
Value Description0 OSC20M is not stable1 OSC20M is stable
Bit 0 ndash SOSC Main Clock Oscillator Changing
Value Description0 The clock source for CLK_MAIN is not undergoing a switch1 The clock source for CLK_MAIN is undergoing a switch and will change as soon as the new
source is stable
ATtiny406Clock Controller (CLKCTRL)
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1055 1620 MHz Oscillator Control A
Name OSC20MCTRLAOffset 0x10Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 RUNSTDBY
Access R R R R R R RW R Reset 0 0 0 0 0 0 0 0
Bit 1 ndash RUNSTDBY Run StandbyThis bit forces the oscillator ON in all modes even when unused by the system In Standby Sleep modethis can be used to ensure immediate wake-up and not waiting for oscillator start-up time
When not requested by peripherals no oscillator output is provided
It takes four oscillator cycles to open the clock gate after a request but the oscillator analog start-up timewill be removed when this bit is set
ATtiny406Clock Controller (CLKCTRL)
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1056 1620 MHz Oscillator Calibration A
Name OSC20MCALIBAOffset 0x11Reset Based on FREQSEL in FUSEOSCCFGProperty Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 CAL20M[50]
Access RW RW RW RW RW RW Reset x x x x x x
Bits 50 ndash CAL20M[50] CalibrationThese bits change the frequency around the current center frequency of the OSC20M for fine-tuning
At Reset the factory calibrated values are loaded based on the FREQSEL bits in FUSEOSCCFG
ATtiny406Clock Controller (CLKCTRL)
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1057 1620 MHz Oscillator Calibration B
Name OSC20MCALIBBOffset 0x12Reset Based on FUSEOSCCFGProperty Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 LOCK TEMPCAL20M[30]
Access R RW RW RW RW Reset x x x x x
Bit 7 ndash LOCK Oscillator Calibration Locked by FuseWhen this bit is set the calibration settings in CLKCTRLOSC20MCALIBA andCLKCTRLOSC20MCALIBB cannot be changedThe Reset the value is loaded from the OSCLOCK bit in the Oscillator Configuration Fuse(FUSEOSCCFG)
Bits 30 ndash TEMPCAL20M[30] Oscillator Temperature Coefficient CalibrationThese bits tune the slope of the temperature compensation
At Reset the factory calibrated values are loaded based on the FREQSEL bits in FUSEOSCCFG
ATtiny406Clock Controller (CLKCTRL)
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1058 32 KHz Oscillator Control A
Name OSC32KCTRLAOffset 0x18Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 RUNSTDBY
Access RW Reset 0
Bit 1 ndash RUNSTDBY Run StandbyThis bit forces the oscillator ON in all modes even when unused by the system In Standby Sleep modethis can be used to ensure immediate wake-up and not waiting for the oscillator start-up time
When not requested by peripherals no oscillator output is provided
It takes four oscillator cycles to open the clock gate after a request but the oscillator analog start-up timewill be removed when this bit is set
ATtiny406Clock Controller (CLKCTRL)
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11 Sleep Controller (SLPCTRL)
111 Featuresbull Three sleep modes
ndash Idlendash Standbyndash Power-Down
bull Configurable Standby Sleep mode where peripherals can be configured as ON or OFF
112 OverviewSleep modes are used to shut down peripherals and clock domains in the device in order to save powerThe Sleep Controller (SLPCTRL) controls and handles the transitions between active and sleep mode
There are in total four modes available one active mode in which software is executed and three sleepmodes The available sleep modes are Idle Standby and Power-Down
When the device enters a sleep mode program execution is stopped and depending on the enteredsleep mode different peripherals and clock domains are turned off
To enter a sleep mode the SLPCTRL must be enabled and the desired sleep mode must be stated Thesoftware decides when to enter that sleep mode by using a dedicated SLEEP instruction
Interrupts are used to wake-up the device from sleep The available interrupt wake-up sources depend onthe configured sleep mode When an interrupt occurs the device will wake-up and execute the interruptservice routine before continuing normal program execution from the first instruction after the SLEEPinstruction Any Reset will take the device out of a sleep mode
The content of the register file SRAM and registers are kept during sleep If a Reset occurs during sleepthe device will reset start-up and execute from the Reset vector
1121 Block DiagramFigure 11-1 Sleep Controller in System
SLPCTRL
SLEEP Instruction
Interrupt Request
Peripheral
Interrupt Request
Sleep State
CPU
1122 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
ATtiny406Sleep Controller (SLPCTRL)
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Table 11-1 SLPCTRL System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections No -
Interrupts No -
Events No -
Debug Yes UPDI
11221 ClocksThis peripheral depends on the peripheral clock
Related LinksClock Controller (CLKCTRL)
11222 IO Lines and ConnectionsNot applicable
11223 InterruptsNot applicable
11224 EventsNot applicable
11225 Debug OperationWhen run-time debugging this peripheral will continue normal operation The SLPCTRL is only affectedby a break in debug operation If the SLPCTRL is in a sleep mode when a break occurs the device willwake-up and the SLPCTRL will go to Active mode even if there are no pending interrupt requests
If the peripheral is configured to require periodical service by the CPU through interrupts or similarimproper operation or data loss may result during halted debugging
113 Functional Description
1131 InitializationTo put the device into a sleep mode follow these steps
bull Configure and enable the interrupts that should wake-up the device from sleep Also enable globalinterrupts
WARNING If there are no interrupts enabled when going to sleep the device cannot wake-up againOnly a Reset will allow the device to continue operation
bull Select the sleep mode to be entered and enable the Sleep Controller by writing to the Sleep Modebits (SMODE) and the Enable bit (SEN) in the Control A register (SLPCTRLCTRLA) A SLEEPinstruction must be run to make the device actually go to sleep
ATtiny406Sleep Controller (SLPCTRL)
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1132 Operation
11321 Sleep ModesIn addition to Active mode there are three different sleep modes with decreasing power consumptionand functionality
Idle The CPU stops executing code no peripherals are disabledAll interrupt sources can wake-up the device
Standby The user can configure peripherals to be enabled or not using the respective RUNSTBY bitThis means that the power consumption is highly dependent on what functionality is enabledand thus may vary between the Idle and Power-Down levelsSleepWalking is available for the ADC moduleThe wake-up sources are pin interrupts TWI address match UART Start-of-Frame interrupt(if USART is enabled to run in Standby) RTC interrupt (if RTC enabled to run in Standby)and TCB interrupt
Power-Down
Only the WDT and the PIT (a component of the RTC) are activeThe only wake-up sources are the pin change interrupt and TWI address match
Table 11-2 Sleep Mode Activity Overview
Group Peripheral Active in Sleep Mode
Clock Idle Standby Power-Down
Active ClockDomain
CPU CLK_CPU
Peripherals CLK_PER X
RTC CLK_RTC X X
ADC CLK_PER X X
PIT (RTC) CLK_RTC X X X
WDT CLK_WDT X X X
Oscillators Main Clock Source X X
RTC Clock Source X X
WDT Oscillator X X X
Wake-UpSources
INTn and Pin Change X X X
TWI Address Match X X X
Periodic Interrupt Timer X X X
UART Start-of-Frame X X
ADC Window X X
RTC Interrupt X X
All other Interrupts X
Note bull X means active X indicates that the RUNSTBY bit of the corresponding peripheral must be set to
enter the active state
ATtiny406Sleep Controller (SLPCTRL)
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11322 Wake-Up TimeThe normal wake-up time for the device is six main clock cycles (CLK_PER) plus the time it takes to startup the main clock source
bull In Idle Sleep mode the main clock source is kept running so it will not be any extra wake-up timebull In Standby Sleep mode the main clock might be running so it depends on the peripheral
configurationbull In Power-Down Sleep mode only the ULP 32 KHz oscillator and RTC clock may be running if it is
used by the BOD or WDT All other clock sources will be OFF
Table 11-3 Sleep Modes and Start-Up Time
Sleep Mode Start-Up Time
IDLE 6 CLK
Standby 6 CLK + OSC start-up
Power-Down 6 CLK + OSC start-up
The start-up time for the different clock sources is described in the Clock Controller (CLKCTRL) section
In addition to the normal wake-up time it is possible to make the device wait until the BOD is ready beforeexecuting code This is done by writing 0x3 to the BOD Operation mode in Active and Idle bits (ACTIVE)in the BOD Configuration fuse (FUSEBODCFG) If the BOD is ready before the normal wake-up time thenet wake-up time will be the same If the BOD takes longer than the normal wake-up time the wake-uptime will be extended until the BOD is ready This ensures correct supply voltage whenever code isexecuted
1133 Configuration Change ProtectionNot applicable
ATtiny406Sleep Controller (SLPCTRL)
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114 Register Summary - SLPCTRL
Offset Name Bit Pos
0x00 CTRLA 70 SMODE[10] SEN
115 Register Description
ATtiny406Sleep Controller (SLPCTRL)
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1151 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SMODE[10] SEN
Access R R R R R RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 21 ndash SMODE[10] Sleep ModeWriting these bits selects the sleep mode entered when the Sleep Enable bit (SEN) is written to 1 andthe SLEEP instruction is executed
Value Name Description0x0 IDLE Idle Sleep mode enabled0x1 STANDBY Standby Sleep mode enabled0x2 PDOWN Power-Down Sleep mode enabledother - Reserved
Bit 0 ndash SEN Sleep EnableThis bit must be written to 1 before the SLEEP instruction is executed to make the MCU enter theselected sleep mode
ATtiny406Sleep Controller (SLPCTRL)
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12 Reset Controller (RSTCTRL)
121 Featuresbull Reset the device and set it to an initial statebull Reset Flag register for identifying the Reset source in softwarebull Multiple Reset sources
ndash Power supply Reset sources Brown-out Detect (BOD) Power-on Reset (POR)ndash User Reset sources External Reset pin (RESET) Watchdog Reset (WDT) Software Reset
(SW) and UPDI Reset
122 OverviewThe Reset Controller (RSTCTRL) manages the Reset of the device It issues a device Reset sets thedevice to its initial state and allows the Reset source to be identified by software
1221 Block DiagramFigure 12-1 Reset System Overview
RESET SOURCES
POR
BOD
WDT
CPU (SW)
RESET CONTROLLER
UPDI
UPDI
All other Peripherals
RESET External ResetFILTER
VDD
Pull-upResistor
1222 Signal Description
Signal Description Type
RESET External Reset (active-low) Digital input
ATtiny406Reset Controller (RSTCTRL)
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123 Functional Description
1231 InitializationThe Reset Controller (RSTCTRL) is always enabled but some of the Reset sources must be enabled(either by fuses or by software) before they can request a Reset
After any Reset the Reset source that caused the Reset is found in the Reset Flag register(RSTCTRLRSTFR)
After a Power-on Reset only the POR flag will be set
The flags are kept until they are cleared by writing a 1 to them
After Reset from any source all registers that are loaded from fuses are reloaded
1232 Operation
12321 Reset SourcesThere are two kinds of sources for Resets
bull Power supply Resets which are caused by changes in the power supply voltage Power-on Reset(POR) and Brown-out Detector (BOD)
bull User Resets which are issued by the application by the debug operation or by pin changes(Software Reset Watchdog Reset UPDI Reset and external Reset pin RESET)
Power-On Reset (POR)A Power-on-Reset (POR) is generated by an on-chip detection circuit The POR is activated when theVDD rises until it reaches the POR threshold voltage The POR is always enabled and will also detectwhen the VDD falls below the threshold voltage
All volatile logic is reset on POR All fuses are reloaded after the Reset is released
Brown-Out Detector (BOD) Reset SourceThe on-chip Brown-out Detection circuit will monitor the VDD level during operation by comparing it to afixed trigger level The trigger level for the BOD can be selected by fuses If BOD is unused in theapplication it is forced to a minimum level in order to ensure a safe operation during internal Reset andchip erase
All logic is reset on BOD Reset except the BOD configuration All fuses are reloaded after the Reset isreleased
Related LinksBrown-Out Detector (BOD)
Software ResetThe software Reset makes it possible to issue a system Reset from software The Reset is generated bywriting a 1 to the Software Reset Enable bit (SWRE) in the Software Reset register (RSTCTRLSWRR)
The Reset will take place immediately after the bit is written and the device will be kept in reset until theReset sequence is completed All logic is reset on software Reset except UPDI and BOD configurationAll fuses are reloaded after the Reset is released
External ResetThe external Reset is enabled by fuse (see fuse map)
ATtiny406Reset Controller (RSTCTRL)
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When enabled the external Reset requests a Reset as long as the RESET pin is low The device will stayin Reset until RESET is high again All logic is reset on external reset except UPDI and BODconfiguration All fuses are reloaded after the Reset is released
Related LinksConfiguration and User Fuses (FUSE)
Watchdog ResetThe Watchdog Timer (WDT) is a system function for monitoring correct program operation If the WDT isnot reset from software according to the programmed time-out period a Watchdog Reset will be issuedSee the WDT documentation for further details
All logic is reset on WDT Reset except UPDI and BOD configuration All fuses are reloaded after theReset is released
Related LinksWatchdog Timer (WDT)
Universal Program Debug Interface (UPDI) ResetThe UPDI contains a separate Reset source that is used to reset the device during external programmingand debugging The Reset source is accessible only from external debuggers and programmers All logicis reset on UPDI Reset except the UPDI itself and BOD configuration All fuses are reloaded after theReset is released See UPDI chapter on how to generate a UPDI Reset request
Related LinksUnified Program and Debug Interface (UPDI)
12322 Reset Time
The Reset time can be split in two
The first part is when any of the Reset sources are active This part depends on the input to the Resetsources The external Reset is active as long as the RESET pin is low the Power-on Reset (POR) andBrown-out Detector (BOD) is active as long as the supply voltage is below Reset source threshold
When all the Reset sources are released an internal Reset initialization of the device is done This timewill be increased with the start-up time given by the start-up time fuse setting (SUT in FUSESYSCFG1)The internal Reset initialization time will also increase if the CRC source is set up to run (CRCSRC inFUSESYSCFG0)
1233 Sleep Mode OperationThe Reset Controller continues to operate in all active and sleep modes
1234 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) In order to write tothese a certain key must be written to the CPUCCP register first followed by a write access to theprotected bits within four CPU instructions
It is possible to try writing to these registers any time but the values are not altered
The following registers are under CCP
ATtiny406Reset Controller (RSTCTRL)
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Table 12-1 RSTCTRL - Registers Under Configuration Change Protection
Register Key
RSTCTRLSWRR IOREG
Related LinksSequence for Write Operation to Configuration Change Protected IO Registers
ATtiny406Reset Controller (RSTCTRL)
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124 Register Summary - RSTCTRL
Offset Name Bit Pos
0x00 RSTFR 70 UPDIRF SWRF WDRF EXTRF BORF PORF
0x01 SWRR 70 SWRE
125 Register Description
ATtiny406Reset Controller (RSTCTRL)
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1251 Reset Flag Register
Name RSTFROffset 0x00Reset 0xXXProperty -
All flags are cleared by writing a 1 to them They are also cleared by a Power-on Reset with theexception of the Power-On Reset Flag (PORF)
Bit 7 6 5 4 3 2 1 0 UPDIRF SWRF WDRF EXTRF BORF PORF
Access R R RW RW RW RW RW RW Reset 0 0 x x x x x x
Bit 5 ndash UPDIRF UPDI Reset FlagThis bit is set if a UPDI Reset occurs
Bit 4 ndash SWRF Software Reset FlagThis bit is set if a Software Reset occurs
Bit 3 ndash WDRF Watchdog Reset FlagThis bit is set if a Watchdog Reset occurs
Bit 2 ndash EXTRF External Reset FlagThis bit is set if an External Reset occurs
Bit 1 ndash BORF Brown-Out Reset FlagThis bit is set if a Brown-out Reset occurs
Bit 0 ndash PORF Power-On Reset FlagThis bit is set if a Power-on Reset occurs
This flag is only cleared by writing a 1 to it
After a POR only the POR flag is set and all other flags are cleared No other flags can be set before afull system boot is run after the POR
ATtiny406Reset Controller (RSTCTRL)
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1252 Software Reset Register
Name SWRROffset 0x01Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 SWRE
Access R R R R R R R RW Reset 0 0 0 0 0 0 0 0
Bit 0 ndash SWRE Software Reset EnableWhen this bit is written to 1 a software Reset will occur
This bit will always read as 0
ATtiny406Reset Controller (RSTCTRL)
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13 CPU Interrupt Controller (CPUINT)
131 Featuresbull Short and Predictable Interrupt Response Timebull Separate Interrupt Configuration and Vector Address for Each Interruptbull Interrupt Prioritizing by Level and Vector Addressbull Two Interrupt Priority Levels 0 (normal) and 1 (high)bull Higher Priority for One Interruptbull Optional Round Robin Priority Scheme for Priority Level 0 Interruptsbull Non-Maskable Interrupts (NMI) for Critical Functionsbull Interrupt Vectors Optionally Placed in the Application Section or the Boot Loader Sectionbull Selectable Compact Vector Table
132 OverviewAn interrupt request signals a change of state inside a peripheral and can be used to alter programexecution Peripherals can have one or more interrupts and all are individually enabled and configured
When an interrupt is enabled and configured it will generate an interrupt request when the interruptcondition occurs
The CPU Interrupt Controller (CPUINT) handles and prioritizes interrupt requests When an interrupt isenabled and the interrupt condition occurs the CPUINT will receive the interrupt request Based on theinterrupts priority level and the priority level of any ongoing interrupts the interrupt request is eitheracknowledged or kept pending until it has priority When an interrupt request is acknowledged by theCPUINT the Program Counter is set to point to the interrupt vector The interrupt vector is normally ajump to the interrupt handler (ie the software routine that handles the interrupt) After returning from theinterrupt handler program execution continues from where it was before the interrupt occurred Oneinstruction is always executed before any pending interrupt is served
The CPUINT Status register (CPUINTSTATUS) contains state information that ensures that the CPUINTreturns to the correct interrupt level when the RETI (interrupt return) instruction is executed at the end ofan interrupt handler Returning from an interrupt will return the CPUINT to the state it had before enteringthe interrupt CPUINTSTATUS is not saved automatically upon an interrupt request
By default all peripherals are priority level 0 It is possible to set one single interrupt vector to the higherpriority level 1 Interrupts are prioritized according to their priority level and their interrupt vector addressPriority level 1 interrupts will interrupt level 0 interrupt handlers Among priority level 0 interrupts thepriority is determined from the interrupt vector address where the lowest interrupt vector address has thehighest interrupt priority
Optionally a round robin scheduling scheme can be enabled for priority level 0 interrupts This ensuresthat all interrupts are serviced within a certain amount of time
Interrupt generation must be globally enabled by writing a 1 to the Global Interrupt Enable bit (I) in theCPU Status register (CPUSREG) This bit is not cleared when an interrupt is acknowledged
ATtiny406CPU Interrupt Controller (CPUINT)
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1321 Block DiagramFigure 13-1 CPUINT Block Diagram
INT REQ
INT LEVEL
INT ACK
Peripheral 1
Peripheral n
Interrupt Controller
SleepController
CPU
PriorityDecoder
STATUS
CPUSREG
INT REQ
INT REQ
GlobalInterruptEnable
CPU RETICPU INT ACK
CPU INT REQ
Wake-upLVL0PRILVL1VEC
1322 Signal DescriptionNot applicable
1323 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
Table 13-1 CPUINT System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections No -
Interrupts No -
Events No -
Debug Yes UPDI
Related LinksDebug OperationClocks
13231 ClocksThis peripheral depends on the peripheral clock
Related LinksClock Controller (CLKCTRL)
13232 IO Lines and ConnectionsNot applicable
13233 InterruptsNot applicable
13234 EventsNot applicable
ATtiny406CPU Interrupt Controller (CPUINT)
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13235 Debug OperationWhen run-time debugging this peripheral will continue normal operation Halting the CPU in Debuggingmode will halt normal operation of the peripheral
If the peripheral is configured to require periodical service by the CPU through interrupts or similarimproper operation or data loss may result during halted debugging
Related LinksUnified Program and Debug Interface (UPDI)
133 Functional Description
1331 InitializationAn interrupt must be initialized in the following order
1 Configure the CPUINT if the default configuration is not adequate (optional)ndash Vector handling is configured by writing to the respective bits (IVSEL and CVT) in the Control
A register (CPUINTCTRLA)ndash Vector prioritizing by round robin is enabled by writing a 1 to the Round Robin Priority Enable
bit (LVL0RR) in CPUINTCTRLAndash Select the priority level 1 vector by writing its address to the Interrupt Vector (LVL1VEC) in the
Level 1 Priority register (CPUINTLVL1VEC)2 Configure the interrupt conditions within the peripheral and enable the peripherals interrupt3 Enable interrupts globally by writing a 1 to the Global Interrupt Enable bit (I) in the CPU Status
register (CPUSREG)
1332 Operation
13321 Enabling Disabling and ResettingGlobal enabling of interrupts is done by writing a 1 to the Global Interrupt Enable bit (I) in the CPU Statusregister (CPUSREG) To disable interrupts globally write a 0 to the I bit in CPUSREG
The desired interrupt lines must also be enabled in the respective peripheral by writing to the peripheralsInterrupt Control register ([peripheral]INTCTRL)
Interrupt flags are not automatically cleared after the interrupt is executed The respective INTFLAGSregister descriptions provide information on how to clear specific flags
13322 Interrupt Vector LocationsThe table below shows Reset addresses and Interrupt vector placement dependent on the value ofInterrupt Vector Select bit (IVSEL) in the Control A register (CPUINTCTRLA)
If the program never enables an interrupt source the Interrupt Vectors are not used and regular programcode can be placed at these locations
Table 13-2 Reset and Interrupt Vector Placement
IVSEL Reset Address Interrupt Vectors Start Address
0 0x0000 Application start address +Interrupt vector offset address
1 0x0000 Interrupt vector offset address
ATtiny406CPU Interrupt Controller (CPUINT)
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13323 Interrupt Response TimeThe minimum interrupt response time for all enabled interrupts is three CPU clock cycles one cycle tofinish the ongoing instruction two cycles to store the Program Counter to the stack and three cycles(1) tojump to the interrupt handler (JMP)
After the Program Counter is pushed on the stack the program vector for the interrupt is executed Seethe figure below first diagram
The jump to the interrupt handler takes three clock cycles(1) If an interrupt occurs during execution of amulticycle instruction this instruction is completed before the interrupt is served See the figure belowsecond diagram
If an interrupt occurs when the device is in sleep mode the interrupt execution response time isincreased by five clock cycles In addition the response time is increased by the start-up time from theselected sleep mode
A return from an interrupt handling routine takes four to five clock cycles depending on the size of theProgram Counter During these clock cycles the Program Counter is popped from the stack and theStack Pointer is incremented See the figure above third diagram
ATtiny406CPU Interrupt Controller (CPUINT)
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Figure 13-2 Interrupt Execution of a Single Cycle Instruction Multicycle Instruction and FromSleep(1)
Single Cycle Instruction
Multicycle Instruction
Sleep
Note 1 Devices with 8kB of Flash or less use RJMP instead of JMP which takes only two clock cycles
13324 Interrupt LevelThe interrupt level is default on level 0 (normal) for all interrupt sources It is possible to select oneinterrupt source to level 1 (high) by writing interrupt address to CPUINTLVL1VEC register This sourcewill have higher priority than normal level interrupts
ATtiny406CPU Interrupt Controller (CPUINT)
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An interrupt request from a level 1 source will interrupt any ongoing interrupt handler from a level 0interrupt When returning from the level 1 interrupt handler the execution of the level 0 interrupt handlerwill continue
13325 Interrupt Priority
Non-Maskable Interrupts (NMI)An NMI will be executed regardless of the setting of the I bit in CPUSREG and it will never change the Ibit No other interrupt can interrupt an NMI handler If more than one NMI is requested at the same timepriority is static according to the interrupt vector address where the lowest address has the highestpriority
Which interrupts are non-maskable is device-dependent and not subject to configuration Non-maskableinterrupts must be enabled before they can be used Refer to the Interrupt Vector Mapping of the devicefor available NMI lines
Related LinksInterrupt Vector Mapping
Static PriorityInterrupt Vectors (IVEC) are located at fixed addresses For static priority the interrupt vector addressdecides the priority within normal interrupt level where the lowest interrupt vector address has thehighest priority Refer to the Interrupt Vector Mapping of the device for available interrupt lines and theirbase address offset
Figure 13-3 Static Priority
Lowest Priority
Highest PriorityIVEC 0
IVEC x
IVEC x+1
IVEC n
Lowest Address
Highest Address
Related LinksInterrupt Vector Mapping
Round Robin SchedulingTo avoid starvation for priority level 0 (LVL0) interrupt requests with static priority (ie some interruptsmight never be served) the CPUINT offers round robin scheduling for LVL0 interrupts
Round robin scheduling for LVL0 interrupt requests is enabled by writing a 1 to the Round Robin PriorityEnable bit (LVL0RR) in the Control A register (CPUINTCTRLA)
ATtiny406CPU Interrupt Controller (CPUINT)
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When round robin scheduling is enabled the interrupt vector address for the last acknowledged LVL0interrupt will have the lowest priority the next time one or more LVL0 interrupts are requested asillustrated in the figure below
Figure 13-4 Round Robin Scheduling
IVEC x last acknowledgeinterrupt
IVEC x+1 last acknowledgeinterrupt
IVEC 0
IVEC x
IVEC x+1
IVEC n
IVEC x+2
IVEC x+1
IVEC x
IVEC 0
IVEC n
Lowest Priority
Highest Priority Lowest Priority
Highest Priority
Compact Vector TableThe Compact Vector Table (CVT) is a feature to allow writing of compact code
When CVT is enabled by writing a 1 to the CVT bit in the Control A register (CPUINTCTRLA) the vectortable contains these three interrupt vectors
1 The non-maskable interrupts (NMI) at vector address 12 The priority level 1 (LVL1) interrupt at vector address 23 All priority level 0 (LVL0) interrupts share vector address 3
This feature is most suitable for applications using a small number of interrupt generators
1333 EventsNot applicable
1334 Sleep Mode OperationNot applicable
1335 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) In order to write tothese a certain key must be written to the CPUCCP register first followed by a write access to theprotected bits within four CPU instructions
It is possible to try writing to these registers any time but the values are not altered
The following registers are under CCP
ATtiny406CPU Interrupt Controller (CPUINT)
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Table 13-3 INTCTRL - Registers under Configuration Change Protection
Register Key
IVSEL in CPUINTCTRLA IOREG
CVT in CPUINTCTRLA IOREG
Related LinksSequence for Write Operation to Configuration Change Protected IO Registers
ATtiny406CPU Interrupt Controller (CPUINT)
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134 Register Summary - CPUINT
Offset Name Bit Pos
0x00 CTRLA 70 IVSEL CVT LVL0RR
0x01 STATUS 70 NMIEX LVL1EX LVL0EX
0x02 LVL0PRI 70 LVL0PRI[70]
0x03 LVL1VEC 70 LVL1VEC[70]
135 Register Description
ATtiny406CPU Interrupt Controller (CPUINT)
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1351 Control A
Name CTRLAOffset 0x00Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 IVSEL CVT LVL0RR
Access RW RW RW Reset 0 0 0
Bit 6 ndash IVSEL Interrupt Vector SelectIf the boot section is defined it will be placed before the application section The actual start address ofthe application section is determined by the BOOTEND fuse
This bit is protected by the Configuration Change Protection mechanism
Value Description0 Interrupt vectors are placed at the start of the application section of the Flash1 Interrupt vectors are placed at the start of the boot section of the Flash
Bit 5 ndash CVT Compact Vector TableThis bit is protected by the Configuration Change Protection mechanism
Value Description0 Compact Vector Table function is disabled1 Compact Vector Table function is enabled
Bit 0 ndash LVL0RR Round Robin Priority EnableThis bit is not protected by the Configuration Change Protection mechanism
Value Description0 Priority is fixed for priority level 0 interrupt requests The lowest interrupt vector address has
highest priority1 Round Robin priority scheme is enabled for priority level 0 interrupt requests
ATtiny406CPU Interrupt Controller (CPUINT)
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1352 Status
Name STATUSOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 NMIEX LVL1EX LVL0EX
Access R R R Reset 0 0 0
Bit 7 ndash NMIEX Non-Maskable Interrupt ExecutingThis flag is set if a non-maskable interrupt is executing The flag is cleared when returning (RETI) fromthe interrupt handler
Bit 1 ndash LVL1EX Level 1 Interrupt ExecutingThis flag is set when a priority level 1 interrupt is executing or when the interrupt handler has beeninterrupted by an NMI The flag is cleared when returning (RETI) from the interrupt handler
Bit 0 ndash LVL0EX Level 0 Interrupt ExecutingThis flag is set when a priority level 0 interrupt is executing or when the interrupt handler has beeninterrupted by a priority level 1 interrupt or an NMI The flag is cleared when returning (RETI) from theinterrupt handler
ATtiny406CPU Interrupt Controller (CPUINT)
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1353 Interrupt Priority Level 0
Name LVL0PRIOffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 LVL0PRI[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash LVL0PRI[70] Interrupt Priority Level 0When Round Robin is enabled (LVL0RR bit in CPUINTCTRLA is 1) this bit field stores the vector of thelast acknowledged priority level 0 (LVL0) interrupt The stored vector will have the lowest priority next timeone or more LVL0 interrupts are pending
If Round Robin is disabled (LVL0RR in CPUINTCTRLA is 0) the vector address-based priority scheme(lowest address has the highest priority) is governing the priorities of LVL0 interrupt requests
If a system Reset is asserted the lowest interrupt vector address will have the highest priority within theLVL0
ATtiny406CPU Interrupt Controller (CPUINT)
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1354 Interrupt Vector with Priority Level 1
Name LVL1VECOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 LVL1VEC[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash LVL1VEC[70] Interrupt Vector with Priority Level 1This bit field contains the address of the single vector with increased priority level 1 (LVL1)
If this bit field has the value 0x00 no vector has LVL1 Consequently the LVL1 interrupt is disabled
ATtiny406CPU Interrupt Controller (CPUINT)
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14 Event System (EVSYS)
141 Featuresbull System for Direct Peripheral-to-Peripheral Signalingbull Peripherals can Directly Produce Use and React to Peripheral Eventsbull Short Response Timebull Up to Three Parallel Event Channels Available Two Asynchronous and One Synchronousbull Channels can be Configured to Have One Triggering Peripheral Action and Multiple Peripheral
Usersbull Peripherals can Directly Trigger and React to Events from Other Peripheralsbull Events can be Sent andor Received by Most Peripherals and by Softwarebull Works in Active mode and Standby Sleep mode
142 OverviewThe Event System (EVSYS) enables direct peripheral-to-peripheral signaling It allows a change in oneperipheral (the event generator) to trigger actions in other peripherals (the event users) through eventchannels without using the CPU It is designed to provide short and predictable response times betweenperipherals allowing for autonomous peripheral control and interaction and also for the synchronizedtiming of actions in several peripheral modules It is thus a powerful tool for reducing the complexity sizeand the execution time of the software
A change of the event generators state is referred to as an event and usually corresponds to one of theperipherals interrupt conditions Events can be directly forwarded to other peripherals using thededicated event routing network The routing of each channel is configured in software including eventgeneration and use
Only one trigger from an event generator peripheral can be routed on each channel but multiplechannels can use the same generator source Multiple peripherals can use events from the samechannel
A channel path can be either asynchronous or synchronous to the main clock The mode must beselected based on the requirements of the application
The Event System can directly connect analog and digital converters analog comparators IO port pinsthe real-time counter timercounters and the configurable custom logic peripheral Events can also begenerated from software and the peripheral clock
ATtiny406Event System (EVSYS)
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1421 Block DiagramFigure 14-1 Block Diagram
Sync user xSync user 0
Sync event channel rdquokrdquo
Async event channel rdquolrdquo
Sync event channel 0
Async event channel 0
Sync source 0Sync source 1
Sync source n
Async source 0Async source 1
Async source m
SYNCSTROBE
To sync user
To async user
SYNCUSER
Async user 0Async user y
ASYNCUSERASYNCCH
SYNCCH
ASYNCSTROBE
Figure 14-2 Example of Event Source Generator User and Action
|Event
RoutingNetwork Single
Conversion
Channel SweepCompare Match
Over-Underflow
Error
Event Generator Event User
Event Source Event Action
Event Action Selection
TimerCounter ADC
Note 1 For an overview of peripherals supporting events refer the block diagram of the device2 For a list of event generators refer to the Channel n Generator Selection registers
(EVSYSSYNCCH and EVSYSASYNCCH)3 For a list of event users refer to the User Channel n Input Selection registers (EVSYSSYNCUSER
and EVSYSASYNCUSER)
ATtiny406Event System (EVSYS)
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1422 Signal Description
Internal Event SignalingThe event signaling can happen either synchronously or asynchronously to the main clock (CLK_MAIN)
Depending on the underlying event the event signal can be a pulse with a duration of one clock cycle ora level signal (similar to a status flag)
Event Output to Pin
Signal Type Description
EVOUT[20] Digital Output Event Output
Related LinksIO LinesBlock Diagram - CLKCTRL
1423 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
Table 14-1 EVSYS System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections Yes PORTMUX
Interrupts No -
Events Yes EVSYS
Debug Yes UPDI
Related LinksClocksDebug Operation
14231 ClocksThe EVSYS uses the peripheral clock for IO registers and software events When set up correctly therouting network can also be used in sleep modes without any clock Software events will not work insleep modes where the peripheral clock is halted
Related LinksClock Controller (CLKCTRL)
14232 IO LinesThe EVSYS can output three event channels asynchronously on pins The output signals are calledEVOUT[20]
1 Configure which event channel (one of SYNCCH[10] or ASYNCCH[30]) is output on whichEVOUTn bit by writing to EVSYSASYNCUSER10 EVSYSASYNCUSER9 orEVSYSASYNCUSER8 respectively
2 Optional configure the pin properties using the port peripheral
ATtiny406Event System (EVSYS)
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3 Enable the pin output by writing 1 to the respective EVOUTn bit in the Control A register of thePORTMUX peripheral (PORTMUXCTRLA)
Related LinksPort Multiplexer (PORTMUX)IO Pin Configuration (PORT)
143 Functional Description
1431 InitializationBefore enabling events within the device the event users multiplexer and event channels must beconfigured
Related LinksEvent User Multiplexer SetupEvent System Channel
1432 Operation
14321 Event User Multiplexer SetupThe event user multiplexer selects the channel for an event user Each event user has one dedicatedevent user multiplexer Each multiplexer is connected to the supported event channel outputs and can beconfigured to select one of these channels
Event users which support asynchronous events also support synchronous events There are also eventusers that support only synchronous events
The event user multiplexers are configured by writing to the corresponding registersbull Event users supporting both synchronous and asynchronous events are configured by writing to the
respective asynchronous User Channel Input Selection n register (EVSYSASYNCUSERn)bull The users of synchronous-only events are configured by writing to the respective Synchronous
User Channel Input Selection n register (EVSYSSYNCUSERn)
The default setup of all user multiplexers is OFF
14322 Event System ChannelAn event channel can be connected to one of the event generators Event channels support eitherasynchronous generators or synchronous generators
The source for each asynchronous event channel is configured by writing to the respective AsynchronousChannel n Input Selection register (EVSYSASYNCCHn)
The source for each synchronous event channel is configured by writing to the respective SynchronousChannel n Input Selection register (EVSYSSYNCCHn)
14323 Event GeneratorsEach event channel can receive the events from several event generators For details on eventgeneration refer to the documentation of the corresponding peripheral
For each event channel there are several possible event generators only one of which can be selectedat a time The event generator trigger is selected for each channel by writing to the respective channelregisters (EVSYSASYNCCHn EVSYSSYNCCHn) By default the channels are not connected to anyevent generator
ATtiny406Event System (EVSYS)
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14324 Software EventIn a software event the CPU will ldquostroberdquo an event channel by inverting the current value for one systemclock cycle
A software event is triggered on a channel by writing a 1 to the respective Strobe bit in the appropriateChannel Strobe register
bull Software events on asynchronous channel l are initiated by writing a 1 to the ASYNCSTROBE[l]bit in the Asynchronous Channel Strobe register (EVSYSASYNCSTROBE)
bull Software events on synchronous channel k are initiated by writing a 1 to the SYNCSTROBE[k] bitin the Synchronous Channel Strobe register (EVSYSSYNCSTROBE)
Software events are no different to those produced by event generator peripherals with respect to eventusers when the bit is written to 1 an event will be generated on the respective channel and receivedand processed by the event user
1433 InterruptsNot applicable
1434 Sleep Mode OperationWhen configured the Event System will work in all sleep modes One exception is software events thatrequire a system clock
1435 Debug OperationThis peripheral is unaffected by entering Debug mode
Related LinksUnified Program and Debug Interface (UPDI)
1436 SynchronizationAsynchronous events are synchronized and handled by the compatible event users Event userperipherals not compatible with asynchronous events can only be configured to listen to synchronousevent channels
1437 Configuration Change ProtectionNot applicable
ATtiny406Event System (EVSYS)
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144 Register Summary - EVSYS
Offset Name Bit Pos
0x00 ASYNCSTROBE 70 ASYNCSTROBE[70]
0x01 SYNCSTROBE 70 SYNCSTROBE[70]
0x02 ASYNCCH0 70 ASYNCCH[70]
0x03 ASYNCCH1 70 ASYNCCH[70]
0x04
0x09
Reserved
0x0A SYNCCH0 70 SYNCCH[70]
0x0B
0x11
Reserved
0x12 ASYNCUSER0 70 ASYNCUSER[70]
0x13 ASYNCUSER1 70 ASYNCUSER[70]
0x14 ASYNCUSER2 70 ASYNCUSER[70]
0x15 ASYNCUSER3 70 ASYNCUSER[70]
0x16 ASYNCUSER4 70 ASYNCUSER[70]
0x17 ASYNCUSER5 70 ASYNCUSER[70]
0x18 ASYNCUSER6 70 ASYNCUSER[70]
0x19 ASYNCUSER7 70 ASYNCUSER[70]
0x1A ASYNCUSER8 70 ASYNCUSER[70]
0x1B ASYNCUSER9 70 ASYNCUSER[70]
0x1C ASYNCUSER10 70 ASYNCUSER[70]
0x1D
0x21
Reserved
0x22 SYNCUSER0 70 SYNCUSER[70]
0x23 SYNCUSER1 70 SYNCUSER[70]
145 Register Description
ATtiny406Event System (EVSYS)
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1451 Asynchronous Channel Strobe
Name ASYNCSTROBEOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 ASYNCSTROBE[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash ASYNCSTROBE[70] Asynchronous Channel StrobeIf the Strobe register location is written each event channel will be inverted for one system clock cycle(ie a single event is generated)
ATtiny406Event System (EVSYS)
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1452 Synchronous Channel Strobe
Name SYNCSTROBEOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SYNCSTROBE[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash SYNCSTROBE[70] Synchronous Channel StrobeIf the Strobe register location is written each event channel will be inverted for one system clock cycle(ie a single event is generated)
ATtiny406Event System (EVSYS)
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1453 Asynchronous Channel n Generator Selection
Name ASYNCCHOffset 0x02 + n0x01 [n=01]Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 ASYNCCH[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash ASYNCCH[70] Asynchronous Channel Generator SelectionTable 14-2 ASYNCCH0
Value Description
0x00 OFF
0x01 CCL_LUT0
0x02 CCL_LUT1
0x03 AC0_OUT
0x04 Reserved
0x05 Reserved
0x06 Reserved
0x07 Reserved
0x08 RTC_OVF
0x09 RTC_CMP
0x0A PORTA0
0x0B PORTA1
0x0C PORTA2
0x0D PORTA3
0x0E PORTA4
0x0F PORTA5
0x10 PORTA6
0x11 PORTA7
0x12 UPDI
Other Reserved
ATtiny406Event System (EVSYS)
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Table 14-3 ASYNCCH1
Value Description
0x00 OFF
0x01 CCL_LUT0
0x02 CCL_LUT1
0x03 AC0_OUT
0x04 Reserved
0x05 Reserved
0x06 Reserved
0x07 Reserved
0x08 RTC_OVF
0x09 RTC_CMP
0x0A PORTB0
0x0B PORTB1
0x0C PORTB2
0x0D PORTB3
0x0E PORTB4
0x0F PORTB5
0x10 PORTB6
0x11 PORTB7
Other Reserved
Note Not all pins of a port are actually available on devices with low pin counts Check the PinoutDiagram andor the IO Multiplexing table for details
ATtiny406Event System (EVSYS)
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1454 Synchronous Channel n Generator Selection
Name SYNCCHOffset 0x0AReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SYNCCH[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash SYNCCH[70] Synchronous Channel Generator SelectionTable 14-4 SYNCCH0
Value Description
0x00 OFF
0x01 TCB0
0x02 TCA0_OVF_LUNF
0x03 TCA0_HUNF
0x04 TCA0_CMP0
0x05 TCA0_CMP1
0x06 TCA0_CMP2
0x07 PORTC0
0x08 PORTC1
0x09 PORTC2
0x0A PORTC3
0x0B PORTC4
0x0C PORTC5
0x0D PORTA0
0x0E PORTA1
0x0F PORTA2
0x10 PORTA3
0x11 PORTA4
0x12 PORTA5
0x13 PORTA6
ATtiny406Event System (EVSYS)
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Value Description
0x14 PORTA7
Other Reserved
Note Not all pins of a port are actually available on devices with low pin counts Check the PinoutDiagram andor the IO Multiplexing table for details
ATtiny406Event System (EVSYS)
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1455 Asynchronous User Channel n Input Selection
Name ASYNCUSEROffset 0x12 + n0x01 [n=010]Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 ASYNCUSER[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash ASYNCUSER[70] Asynchronous User Channel SelectionTable 14-5 User Multiplexer Numbers
USERn User Multiplexer Description
n=0 TCB0 TimerCounter B 0
n=1 ADC0 ADC 0
n=2 CCL_LUT0EV0 CCL LUT0 Event 0
n=3 CCL_LUT1EV0 CCL LUT1 Event 0
n=4 CCL_LUT0EV1 CCL LUT0 Event 1
n=5 CCL_LUT1EV1 CCL LUT1 Event 1
n=67 Reserved Reserved
n=8 EVOUT0 Event OUT 0
n=9 EVOUT1 Event OUT 1
n=10 EVOUT2 Event OUT 2
Value Description0x0 OFF0x1 SYNCCH00x3 ASYNCCH00x4 ASYNCCH1
ATtiny406Event System (EVSYS)
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1456 Synchronous User Channel n Input Selection
Name SYNCUSEROffset 0x22 + n0x01 [n=01]Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SYNCUSER[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash SYNCUSER[70] Synchronous User Channel SelectionTable 14-6 User Multiplexer Numbers
USERn User Multiplexer Description
n=0 TCA0 TimerCounter A
n=1 USART0 USART
Value Name0x0 OFF0x1 SYNCCH0
ATtiny406Event System (EVSYS)
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15 Port Multiplexer (PORTMUX)
151 OverviewThe Port Multiplexer (PORTMUX) can either enable or disable functionality of pins or change betweendefault and alternative pin positions This depends on the actual pin and property and is described indetail in the PORTMUX register map
For available pins and functionalities refer to the Multiplexed Signals table
Related LinksIO Multiplexing and Considerations
ATtiny406Port Multiplexer (PORTMUX)
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152 Register Summary - PORTMUX
Offset Name Bit Pos
0x00 CTRLA 70 LUT1 LUT0 EVOUT2 EVOUT1 EVOUT0
0x01 CTRLB 70 SPI0 USART0
0x02 CTRLC 70 TCA05 TCA04 TCA03 TCA02 TCA01 TCA00
0x03 CTRLD 70 TCB0
153 Register Description
ATtiny406Port Multiplexer (PORTMUX)
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1531 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 LUT1 LUT0 EVOUT2 EVOUT1 EVOUT0
Access RW RW RW RW RW Reset 0 0 0 0 0
Bit 5 ndash LUT1 CCL LUT 1 outputWrite this bit to 1 to select alternative pin location for CCL LUT 1
Bit 4 ndash LUT0 CCL LUT 0 outputWrite this bit to 1 to select alternative pin location for CCL LUT 0
Bit 2 ndash EVOUT2 Event Output 2Write this bit to 1 to enable event output 2
Bit 1 ndash EVOUT1 Event Output 1Write this bit to 1 to enable event output 1
Bit 0 ndash EVOUT0 Event Output 0Write this bit to 1 to enable event output 0
ATtiny406Port Multiplexer (PORTMUX)
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1532 Control B
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SPI0 USART0
Access RW RW Reset 0 0
Bit 2 ndash SPI0 SPI 0 communicationWrite this bit to 1 to select alternative communication pins for SPI 0
Bit 0 ndash USART0 USART 0 communicationWrite this bit to 1 to select alternative communication pins for USART 0
ATtiny406Port Multiplexer (PORTMUX)
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1533 Control C
Name CTRLCOffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 TCA05 TCA04 TCA03 TCA02 TCA01 TCA00
Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bit 5 ndash TCA05 TCA0 Waveform output 5Write this bit to 1 to select alternative output pin for TCA0 waveform output 5 in Split mode
Not applicable when TCA in normal mode
Bit 4 ndash TCA04 TCA0 Waveform output 4Write this bit to 1 to select alternative output pin for TCA0 waveform output 4 in Split mode
Not applicable when TCA in normal mode
Bit 3 ndash TCA03 TCA0 Waveform output 3Write this bit to 1 to select alternative output pin for TCA0 waveform output 3 in Split mode
Not applicable when TCA in normal mode
Bit 2 ndash TCA02 TCA0 Waveform output 2Write this bit to 1 to select alternative output pin for TCA0 waveform output 2
In Split Mode this bit controls output from low byte compare channel 2
Bit 1 ndash TCA01 TCA0 Waveform output 1Write this bit to 1 to select alternative output pin for TCA0 waveform output 1
In Split mode this bit controls output from low byte compare channel 1
Bit 0 ndash TCA00 TCA0 Waveform output 0Write this bit to 1 to select alternative output pin for TCA0 waveform output 0
In Split mode this bit controls output from low byte compare channel 0
ATtiny406Port Multiplexer (PORTMUX)
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1534 Control D
Name CTRLDOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 TCB0
Access RW Reset 0
Bit 0 ndash TCB0 TCB0 outputWrite this bit to 1 to select alternative output pin for 16-bit timercounter B 0
ATtiny406Port Multiplexer (PORTMUX)
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16 IO Pin Configuration (PORT)
161 Featuresbull General Purpose Input and Output Pins with Individual Configurationbull Output Driver with Configurable Inverted IO and Pullupbull Input with Interrupts and Events
ndash Sense both edgesndash Sense rising edgesndash Sense falling edgesndash Sense low level
bull Asynchronous Pin Change Sensing That Can Wake the Device From all Sleep Modesbull Efficient and Safe Access to Port Pins
ndash Hardware read-modify-write through dedicated toggleclearset registersndash Mapping of often-used PORT registers into bit-accessible IO memory space (virtual ports)
162 OverviewThe IO pins of the device are controlled by instances of the port peripheral registers This device has thefollowing instances of the IO pin configuration (PORT) PORTA PORTB and PORTC
Refer to the IO Multiplexing table to see which pins are controlled by what instance of port The offsets ofthe port instances and of the corresponding virtual port instances are listed in the Peripherals andArchitecture section
Each of the port pins has a corresponding bit in the Data Direction (PORTDIR) and Data Output Value(PORTOUT) registers to enable that pin as an output and to define the output state For example pinPA3 is controlled by DIR[3] and OUT[3] of the PORTA instance
The Data Input Value (PORTIN) is set as the input value of a port pin with resynchronization to the mainclock To reduce power consumption these input synchronizers are not clocked if the Input SenseConfiguration bit field (ISC) in PORTPINnCTRL is INPUT_DISABLE The value of the pin can always beread whether the pin is configured as input or output
The port also supports synchronous and asynchronous input sensing with interrupts for selectable pinchange conditions Asynchronous pin-change sensing means that a pin change can wake the devicefrom all sleep modes including the modes where no clocks are running
All pin functions are configurable individually per pin The pins have hardware read-modify-write (RMW)functionality for a safe and correct change of drive value andor pull resistor configuration The directionof one port pin can be changed without unintentionally changing the direction of any other pin
The port pin configuration also controls input and output selection of other device functions
Related LinksIO Multiplexing and ConsiderationsPeripherals and Architecture
ATtiny406IO Pin Configuration (PORT)
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1621 Block DiagramFigure 16-1 PORT Block Diagram
DQ
R
DQ
R
Synchronizer
D Q
R
DIRn
OUTn
INn
Pxn
D Q
R
Input Disable
Digital Input Asynchronous event
Invert Enable
Pullup enable
Input Disable Override
OUT Override
DIR Override
Analog inputoutput
Synchronized input
1622 Signal Description
Signal Type Description
EXTINT Digital input External interrupt - available on all IO pins
Related LinksIO Multiplexing and Considerations
1623 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
ATtiny406IO Pin Configuration (PORT)
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Table 16-1 PORT System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections No -
Interrupts Yes CPUINT
Events Yes EVSYS
Debug No -
Related LinksEventsClocksInterrupts
16231 ClocksThis peripheral depends on the peripheral clock
16232 IO Lines and ConnectionsNot applicable
16233 InterruptsUsing the interrupts of this peripheral requires the interrupt controller to be configured first
Related LinksCPU Interrupt Controller (CPUINT)InterruptsSREG
16234 EventsThe events of this peripheral are connected to the Event System
Related LinksEvent System (EVSYS)
16235 Debug OperationThis peripheral is unaffected by entering Debug mode
163 Functional Description
1631 InitializationAfter Reset all standard function device IO pads are connected to the port with outputs tri-stated andinput buffers enabled even if there is no clock running
For best power consumption disable the input of unused pins and pins that are used as analog inputs oroutputs
Specific pins such as those used for connecting a debugger may be configured differently as requiredby their special function
ATtiny406IO Pin Configuration (PORT)
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1632 Operation
16321 Basic FunctionsEach IO pin Pxn can be controlled by the registers in PORTx Each pin group x has its own set of PORTregisters The base address of the register set for pin n is at the byte address PORT + 0x10 + Theindex within that register set is n
To use pin number n as an output only write bit n of the PORTxDIR register to 1 This can be done bywriting bit n in the PORTxDIRSET register to 1 which will avoid disturbing the configuration of other pinsin that group The nth bit in the PORTxOUT register must be written to the desired output value
Similarly writing a PORTxOUTSET bit to 1 will set the corresponding bit in the PORTxOUT register to1 Writing a bit in PORTxOUTCLR to 1 will clear that bit in PORTxOUT to zero Writing a bit inPORTxOUTTGL or PORTxIN to 1 will toggle that bit in PORTxOUT
To use pin n as an input bit n in the PORTxDIR register must be written to 0 to disable the output driverThis can be done by writing bit n in the PORTxDIRCLR register to 1 which will avoid disturbing theconfiguration of other pins in that group The input value can be read from bit n in register PORTxIN aslong as the ISC bit is not set to INPUT_DISABLE
Writing a bit to 1 in PORTxDIRTGL will toggle that bit in PORTxDIR and toggle the direction of thecorresponding pin
16322 Virtual PortsThe Virtual PORT registers map the most frequently used regular PORT registers into the bit-accessibleIO space Writing to the Virtual PORT registers has the same effect as writing to the regular registers butallows for memory-specific instructions such as bit-manipulation instructions which are not valid for theextended IO memory space where the regular PORT registers resideTable 16-2 Virtual Port Mapping
Regular PORT Register Mapped to Virtual PORT Register
PORTDIR VPORTDIR
PORTOUT VPORTOUT
PORTIN VPORTIN
PORTINTFLAG VPORTINTFLAG
Related LinksRegister Summary - VPORTIO Multiplexing and ConsiderationsPeripherals and Architecture
16323 Pin ConfigurationThe Pin n Configuration register (PORTPINnCTRL) is used to configure inverted IO pullup and inputsensing of a pin
All input and output on the respective pin n can be inverted by writing a 1 to the Inverted IO Enable bit(INVEN) in PORTPINnCTRL
Toggling the INVEN bit causes an edge on the pin which can be detected by all peripherals using thispin and is seen by interrupts or events if enabled
Pullup of pin n is enabled by writing a 1 to the Pullup Enable bit (PULLUPEN) in PORTPINnCTRL
ATtiny406IO Pin Configuration (PORT)
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Changes of the signal on a pin can trigger an interrupt The exact conditions are defined by writing to theInputSense bit field (ISC) in PORTPINnCTRL
When setting or changing interrupt settings take these points into accountbull If an INVEN bit is toggled in the same cycle as the interrupt setting the edge caused by the
inversion toggling may not cause an interrupt requestbull If an input is disabled while synchronizing an interrupt that interrupt may be requested on re-
enabling the input even if it is re-enabled with a different interrupt settingbull If the interrupt setting is changed while synchronizing an interrupt that interrupt may not be
acceptedbull Only a few pins support full asynchronous interrupt detection see IO Multiplexing and
Considerations These limitations apply for waking the system from sleep
Interrupt Type Fully Asynchronous Pins Other Pins
BOTHEDGES Will wake system Will wake system
RISING Will wake system Will not wake system
FALLING Will wake system Will not wake system
LEVEL Will wake system Will wake system
Related LinksIO Multiplexing and Considerations
1633 InterruptsTable 16-3 Available Interrupt Vectors and Sources
Offset Name Vector Description Conditions
0x00 PORTx PORT A B C interrupt INTn in PORTINTFLAGS is raised as configured by ISC bit inPORTPINnCTRL
Each port pin n can be configured as an interrupt source Each interrupt can be individually enabled ordisabled by writing to ISC in PORTPINCTRL
When an interrupt condition occurs the corresponding interrupt flag is set in the Interrupt Flags register ofthe peripheral (peripheralINTFLAGS)
An interrupt request is generated when the corresponding interrupt is enabled and the interrupt flag is setThe interrupt request remains active until the interrupt flag is cleared See the peripherals INTFLAGSregister for details on how to clear interrupt flags
ATtiny406IO Pin Configuration (PORT)
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Asynchronous Sensing Pin PropertiesTable 16-4 Behavior Comparison of FullyPartly Asynchronous Sense Pin
Property Synchronous or Partly Asynchronous SenseSupport
Full Asynchronous SenseSupport
Minimum pulse-widthto trigger interrupt
Minimum one system clock cycle Less than a system clockcycle
Waking the devicefrom sleep
From all interrupt sense configurations from sleepmodes with main clock running Only fromBOTHEDGES or LEVEL interrupt senseconfiguration from sleep modes with main clockstopped
From all interrupt senseconfigurations from all sleepmodes
Interrupt dead time No new interrupt for three cycles after theprevious
No limitation
Minimum wake-uppulse length
Value on pad must be kept until the system clockhas restarted
No limitation
Related LinksAVR CPUSREG
1634 EventsAll PORT pins are asynchronous event system generators PORT has as many event generators as thereare PORT pins in the device Each event system output from PORT is the value present on thecorresponding pin if the digital input driver is enabled If a pin input driver is disabled the correspondingevent system output is zero
PORT has no event inputs
1635 Sleep Mode OperationWith the exception of interrupts and input synchronization all pin configurations are independent of theSleep mode Peripherals connected to the ports can be affected by Sleep modes described in therespective peripherals documentation
The port peripheral will always use the main clock Input synchronization will halt when this clock stops
1636 SynchronizationNot applicable
1637 Configuration Change ProtectionNot applicable
ATtiny406IO Pin Configuration (PORT)
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164 Register Summary - PORT
Offset Name Bit Pos
0x00 DIR 70 DIR[70]
0x01 DIRSET 70 DIRSET[70]
0x02 DIRCLR 70 DIRCLR[70]
0x03 DIRTGL 70 DIRTGL[70]
0x04 OUT 70 OUT[70]
0x05 OUTSET 70 OUTSET[70]
0x06 OUTCLR 70 OUTCLR[70]
0x07 OUTTGL 70 OUTTGL[70]
0x08 IN 70 IN[70]
0x09 INTFLAGS 70 INT[70]
0x0A
0x0F
Reserved
0x10 PIN0CTRL 70 INVEN PULLUPEN ISC[20]
0x11 PIN1CTRL 70 INVEN PULLUPEN ISC[20]
0x12 PIN2CTRL 70 INVEN PULLUPEN ISC[20]
0x13 PIN3CTRL 70 INVEN PULLUPEN ISC[20]
0x14 PIN4CTRL 70 INVEN PULLUPEN ISC[20]
0x15 PIN5CTRL 70 INVEN PULLUPEN ISC[20]
0x16 PIN6CTRL 70 INVEN PULLUPEN ISC[20]
0x17 PIN7CTRL 70 INVEN PULLUPEN ISC[20]
165 Register Description - Ports
ATtiny406IO Pin Configuration (PORT)
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1651 Data Direction
Name DIROffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DIR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIR[70] Data DirectionThis bit field selects the data direction for the individual pins n of the portWriting a 1 to PORTDIR[n] configures and enables pin n as an output pin
Writing a 0 to PORTDIR[n] configures pin n as an input pin It can be configured by writing to the ISC bitin PORTPINnCTRL
ATtiny406IO Pin Configuration (PORT)
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1652 Data Direction Set
Name DIRSETOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DIRSET[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIRSET[70] Data Direction SetThis bit field can be used instead of a read-modify-write to set individual pins as outputWriting a 1 to DIRSET[n] will set the corresponding PORTDIR[n] bit
Reading this bit field will always return the value of PORTDIR
ATtiny406IO Pin Configuration (PORT)
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1653 Data Direction Clear
Name DIRCLROffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DIRCLR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIRCLR[70] Data Direction ClearThis register can be used instead of a read-modify-write to configure individual pins as inputWriting a 1 to DIRCLR[n] will clear the corresponding bit in PORTDIR
Reading this bit field will always return the value of PORTDIR
ATtiny406IO Pin Configuration (PORT)
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1654 Data Direction Toggle
Name DIRTGLOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DIRTGL[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIRTGL[70] Data Direction ToggleThis bit field can be used instead of a read-modify-write to toggle the direction of individual pins
Writing a 1 to DIRTGL[n] will toggle the corresponding bit in PORTDIR
Reading this bit field will always return the value of PORTDIR
ATtiny406IO Pin Configuration (PORT)
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1655 Output Value
Name OUTOffset 0x04Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 OUT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUT[70] Output ValueThis bit field defines the data output value for the individual pins n of the portIf OUT[n] is written to 1 pin n is driven high
If OUT[n] is written to 0 pin n is driven low
In order to have any effect the pin direction must be configured as output
ATtiny406IO Pin Configuration (PORT)
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1656 Output Value Set
Name OUTSETOffset 0x05Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 OUTSET[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUTSET[70] Output Value SetThis bit field can be used instead of a read-modify-write to set the output value of individual pins to 1Writing a 1 to OUTSET[n] will set the corresponding bit in PORTOUT
Reading this bit field will always return the value of PORTOUT
ATtiny406IO Pin Configuration (PORT)
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1657 Output Value Clear
Name OUTCLROffset 0x06Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 OUTCLR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUTCLR[70] Output Value ClearThis register can be used instead of a read-modify-write to clear the output value of individual pins to 0Writing a 1 to OUTCLR[n] will clear the corresponding bit in PORTOUT
Reading this bit field will always return the value of PORTOUT
ATtiny406IO Pin Configuration (PORT)
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1658 Output Value Toggle
Name OUTTGLOffset 0x07Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 OUTTGL[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUTTGL[70] Output Value ToggleThis register can be used instead of a read-modify-write to toggle the output value of individual pinsWriting a 1 to OUTTGL[n] will toggle the corresponding bit in PORTOUT
Reading this bit field will always return the value of PORTOUT
ATtiny406IO Pin Configuration (PORT)
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1659 Input Value
Name INOffset 0x08Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 IN[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash IN[70] Input ValueThis register shows the value present on the pins if the digital input driver is enabled IN[n] shows thevalue of pin n of the port The input is not sampled and cannot be read if the digital input buffers aredisabledWriting to a bit of PORTIN will toggle the corresponding bit in PORTOUT
ATtiny406IO Pin Configuration (PORT)
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16510 Interrupt Flags
Name INTFLAGSOffset 0x09Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 INT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash INT[70] Interrupt Pin FlagThe INT Flag is set when a pin changestate matches the pins input sense configurationWriting a 1 to a flags bit location will clear the flag
For enabling and executing the interrupt refer to ISC bit description in PORTPINnCTRL
ATtiny406IO Pin Configuration (PORT)
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16511 Pin n Control
Name PINCTRLOffset 0x10 + n0x01 [n=07]Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 INVEN PULLUPEN ISC[20]
Access RW RW RW RW RW Reset 0 0 0 0 0
Bit 7 ndash INVEN Inverted IO Enable
Value Description0 IO on pin n not inverted1 IO on pin n inverted
Bit 3 ndash PULLUPEN Pullup Enable
Value Description0 Pullup disabled for pin n1 Pullup enabled for pin n
Bits 20 ndash ISC[20] InputSense ConfigurationThese bits configure the input and sense configuration of pin n The sense configuration determines howa port interrupt can be triggered If the input buffer is disabled the input cannot be read in the IN register
Value Name Description0x0 INTDISABLE Interrupt disabled but input buffer enabled0x1 BOTHEDGES Sense both edges0x2 RISING Sense rising edge0x3 FALLING Sense falling edge0x4 INPUT_DISABLE Digital input buffer disabled0x5 LEVEL Sense low levelother - Reserved
ATtiny406IO Pin Configuration (PORT)
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166 Register Summary - VPORT
Offset Name Bit Pos
0x00 DIR 70 DIR[70]
0x01 OUT 70 OUT[70]
0x02 IN 70 IN[70]
0x03 INTFLAGS 70 INT[70]
167 Register Description - Virtual Ports
ATtiny406IO Pin Configuration (PORT)
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1671 Data Direction
Name DIROffset 0x00Reset 0x00Property -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers but allows formemory-specific instructions such as bit-manipulation instructions which are not valid for the extendedIO memory space where the regular PORT registers reside
Bit 7 6 5 4 3 2 1 0 DIR[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash DIR[70] Data DirectionThis bit field selects the data direction for the individual pins in the port
ATtiny406IO Pin Configuration (PORT)
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1672 Output Value
Name OUTOffset 0x01Reset 0x00Property -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers but allows formemory-specific instructions such as bit-manipulation instructions which are not valid for the extendedIO memory space where the regular PORT registers reside
Bit 7 6 5 4 3 2 1 0 OUT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash OUT[70] Output ValueThis bit field selects the data output value for the individual pins in the port
ATtiny406IO Pin Configuration (PORT)
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1673 Input Value
Name INOffset 0x02Reset 0x00Property -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers but allows formemory-specific instructions such as bit-manipulation instructions which are not valid for the extendedIO memory space where the regular PORT registers reside
Bit 7 6 5 4 3 2 1 0 IN[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash IN[70] Input ValueThis bit field holds the value present on the pins if the digital input buffer is enabledWriting to a bit of VPORTIN will toggle the corresponding bit in VPORTOUT
ATtiny406IO Pin Configuration (PORT)
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1674 Interrupt Flag
Name INTFLAGSOffset 0x03Reset 0x00Property -
Writing to the Virtual PORT registers has the same effect as writing to the regular registers but allows formemory-specific instructions such as bit-manipulation instructions which are not valid for the extendedIO memory space where the regular PORT registers reside
Bit 7 6 5 4 3 2 1 0 INT[70]
Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bits 70 ndash INT[70] Interrupt Pin FlagThe INT flag is set when a pin changestate matches the pins input sense configuration and the pin isconfigured as source for port interruptWriting a 1 to this flags bit location will clear the flag
For enabling and executing the interrupt refer to PORT_PINnCTRLISC
ATtiny406IO Pin Configuration (PORT)
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17 Brown-Out Detector (BOD)
171 Featuresbull Brown-out Detection monitors the power supply to avoid operation below a programmable levelbull There are three modes
ndash Enabledndash Sampledndash Disabled
bull Separate selection of mode for Active and Sleep modesbull Voltage Level Monitor (VLM) with Interruptbull Programmable VLM Level Relative to the BOD Level
172 OverviewThe Brown-out Detector (BOD) monitors the power supply and compares the voltage with twoprogrammable brown-out threshold levels The brown-out threshold level defines when to generate aReset A Voltage Level Monitor (VLM) monitors the power supply and compares it to a threshold higherthan the BOD threshold The VLM can then generate an interrupt request as an early warning when thesupply voltage is about to drop below the VLM threshold The VLM threshold level is expressed as apercentage above the BOD threshold level
The BOD is mainly controlled by fuses The mode used in Standby Sleep mode and Power-Down Sleepmode can be altered in normal program execution The VLM part of the BOD is controlled by IO registersas well
When activated the BOD can operate in Enabled mode where the BOD is continuously active and inSampled mode where the BOD is activated briefly at a given period to check the supply voltage level
ATtiny406Brown-Out Detector (BOD)
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1721 Block DiagramFigure 17-1 BOD Block Diagram
+
-
+
-
Bandgap
Bandgap
BOD Level and
Calibration
VLM Interrupt Level
Brown-out Detection
VDD
VLM InterruptDetection
1722 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
Table 17-1 BOD System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections No -
Interrupts Yes CPUINT
Events Yes EVSYS
Debug Yes UPDI
Related LinksClocksDebug OperationInterruptsEvents
17221 ClocksThe BOD uses the 32 KHz oscillator (OSCULP32K) as clock source for CLK_BOD
ATtiny406Brown-Out Detector (BOD)
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17222 IO Lines and ConnectionsNot applicable
17223 InterruptsUsing the interrupts of this peripheral requires the interrupt controller to be configured first
Related LinksCPU Interrupt Controller (CPUINT)SREGInterrupts
17224 EventsNot applicable
17225 Debug OperationThis peripheral is unaffected by entering Debug mode
The VLM interrupt will not be executed if the CPU is halted in Debug mode
If the peripheral is configured to require periodical service by the CPU through interrupts or similarimproper operation or data loss may result during halted debugging
173 Functional Description
1731 InitializationThe BOD settings are loaded from fuses during Reset The BOD level and operating mode in Active andIdle Sleep mode are set by fuses and cannot be changed by the CPU The operating mode in Standbyand Power-Down Sleep mode is loaded from fuses and can be changed by software
The Voltage Level Monitor function can be enabled by writing a 1 to the VLM Interrupt Enable bit(VLMIE) in the Interrupt Control register (BODINTCTRL) The VLM interrupt is configured by writing theVLM Configuration bits (VLMCFG) in BODINTCTRL An interrupt is requested when the supply voltagecrosses the VLM threshold either from above from below or from any direction
The VLM functionality will follow the BOD mode If the BOD is turned off the VLM will not be enabledeven if the VLMIE is 1 If the BOD is using Sampled mode the VLM will also be sampled When enablingVLM interrupt the interrupt flag will always be set if VLMCFG equals 0x2 and may be set if VLMCFG isconfigured to 0x0 or 0x1
The VLM threshold is defined by writing the VLM Level bits (VLMLVL) in the Control A register(BODVLMCTRLA)
If the BODVLM is enabled in Sampled mode only VLMCFG=0x1 (crossing threshold from above) inBODINTCTRL will trigger an interrupt
1732 InterruptsTable 17-2 Available Interrupt Vectors and Sources
Offset Name Vector Description Conditions
0x00 VLM Voltage Level Monitor Supply voltage crossing the VLM threshold as configured byVLMCFG in BODINTCTRL
ATtiny406Brown-Out Detector (BOD)
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When an interrupt condition occurs the corresponding interrupt flag is set in the Interrupt Flags register ofthe peripheral (peripheralINTFLAGS)
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheralsInterrupt Control register (peripheralINTCTRL)
An interrupt request is generated when the corresponding interrupt source is enabled and the interruptflag is set The interrupt request remains active until the interrupt flag is cleared See the peripheralsINTFLAGS register for details on how to clear interrupt flags
Related LinksAVR CPUSREG
1733 Sleep Mode OperationThere are two separate fuses defining the BOD configuration in different sleep modes One fuse definesthe mode used in Active mode and Idle Sleep mode (ACTIVE in FUSEBODCFG) and is written to theACTIVE bits in the Control A register (BODCTRLA) The second fuse (SLEEP in FUSEBODCFG)selects the mode used in Standby Sleep mode and Power-Down Sleep mode and is loaded into theSLEEP bits in the Control A register (BODCTRLA)
The operating mode in Active mode and Idle Sleep mode (ie ACTIVE in BODCTRLA) cannot bealtered by software The operating mode in Standby Sleep mode and Power-Down Sleep mode can bealtered by writing to the SLEEP bits in the Control A register (BODCTRLA)
When the device is going into Standby Sleep mode or Power-Down Sleep mode the BOD will changeoperation mode as defined by SLEEP in BODCTRLA When the device is waking up from Standby orPower-Down Sleep mode the BOD will operate in the mode defined by the ACTIVE bit field inBODCTRLA
1734 SynchronizationNot applicable
1735 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) In order to write tothese a certain key must be written to the CPUCCP register first followed by a write access to theprotected bits within four CPU instructions
It is possible to try writing to these registers any time but the values are not altered
The following registers are under CCP
Table 17-3 Registers Under Configuration Change Protection
Register Key
SLEEP in BODCTRLA IOREG
Related LinksSequence for Write Operation to Configuration Change Protected IO Registers
ATtiny406Brown-Out Detector (BOD)
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174 Register Summary - BOD
Offset Name Bit Pos
0x00 CTRLA 70 SAMPFREQ ACTIVE[10] SLEEP[10]
0x01 CTRLB 70 LVL[20]
0x02
0x07
Reserved
0x08 VLMCTRLA 70 VLMLVL[10]
0x09 INTCTRL 70 VLMCFG[10] VLMIE
0x0A INTFLAGS 70 VLMIF
0x0B STATUS 70 VLMS
175 Register Description
ATtiny406Brown-Out Detector (BOD)
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1751 Control A
Name CTRLAOffset 0x00Reset Loaded from fuseProperty Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 SAMPFREQ ACTIVE[10] SLEEP[10]
Access R R R R R R RW RW Reset 0 0 0 x x x x x
Bit 4 ndash SAMPFREQ Sample FrequencyThis bit selects the BOD sample frequency
The Reset value is loaded from the SAMPFREQ bit in FUSEBODCFG This bit is under ConfigurationChange Protection (CCP)
Value Description0x0 Sample frequency is 1 kHz0x1 Sample frequency is 125 Hz
Bits 32 ndash ACTIVE[10] ActiveThese bits select the BOD operation mode when the device is in Active or Idle mode
The Reset value is loaded from the ACTIVE bits in FUSEBODCFG
Value Description0x0 Disabled0x1 Enabled0x2 Sampled0x3 Enabled with wake-up halted until BOD is ready
Bits 10 ndash SLEEP[10] SleepThese bits select the BOD operation mode when the device is in Standby or Power-Down Sleep modeThe Reset value is loaded from the SLEEP bits in FUSEBODCFGThese bits are under Configuration Change Protection (CCP)
Value Description0x0 Disabled0x1 Enabled0x2 Sampled0x3 Reserved
ATtiny406Brown-Out Detector (BOD)
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1752 Control B
Name CTRLBOffset 0x01Reset Loaded from fuseProperty -
Bit 7 6 5 4 3 2 1 0 LVL[20]
Access R R R R R R R R Reset 0 0 0 0 0 x x x
Bits 20 ndash LVL[20] BOD LevelThese bits select the BOD threshold level
The Reset value is loaded from the BOD Level bits (LVL) in the BOD Configuration Fuse(FUSEBODCFG)
Value Name Description0x0 BODLEVEL0 18V0x1 BODLEVEL1 215V0x2 BODLEVEL2 260V0x3 BODLEVEL3 295V0x4 BODLEVEL4 330V0x5 BODLEVEL5 370V0x6 BODLEVEL6 400V0x7 BODLEVEL7 430V
ATtiny406Brown-Out Detector (BOD)
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1753 VLM Control A
Name VLMCTRLAOffset 0x08Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 VLMLVL[10]
Access R R R R R R RW RW Reset 0 0 0 0 0 0 0 0
Bits 10 ndash VLMLVL[10] VLM LevelThese bits select the VLM threshold relative to the BOD threshold (LVL in BODCTRLB)
Value Description0x0 VLM threshold 5 above BOD threshold0x1 VLM threshold 15 above BOD threshold0x2 VLM threshold 25 above BOD thresholdother Reserved
ATtiny406Brown-Out Detector (BOD)
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1754 Interrupt Control
Name INTCTRLOffset 0x09Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 VLMCFG[10] VLMIE
Access R R R R R RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 21 ndash VLMCFG[10] VLM ConfigurationThese bits select which incidents will trigger a VLM interrupt
Value Description0x0 Voltage crosses VLM threshold from above0x1 Voltage crosses VLM threshold from below0x2 Either direction is triggering an interrupt requestOther Reserved
Bit 0 ndash VLMIE VLM Interrupt EnableWriting a 1 to this bit enables the VLM interrupt
ATtiny406Brown-Out Detector (BOD)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 168
1755 VLM Interrupt Flags
Name INTFLAGSOffset 0x0AReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 VLMIF
Access R R R R R R R RW Reset 0 0 0 0 0 0 0 0
Bit 0 ndash VLMIF VLM Interrupt FlagThis flag is set when a trigger from the VLM is given as configured by the VLMCFG bit in theBODINTCTRL register The flag is only updated when the BOD is enabled
ATtiny406Brown-Out Detector (BOD)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 169
1756 VLM Status
Name STATUSOffset 0x0BReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 VLMS
Access R R R R R R R R Reset 0 0 0 0 0 0 0 0
Bit 0 ndash VLMS VLM StatusThis bit is only valid when the BOD is enabled
Value Description0 The voltage is above the VLM threshold level1 The voltage is below the VLM threshold level
ATtiny406Brown-Out Detector (BOD)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 170
18 Voltage Reference (VREF)
181 Featuresbull Programmable Voltage Reference Sources
ndash One for each ADC peripheralndash One for each AC peripheral
bull Each Reference Source Supports Five Different Voltagesndash 055Vndash 11Vndash 15Vndash 25Vndash 43V
182 OverviewThe Voltage Reference (VREF) peripheral provides control registers for the voltage reference sourcesused by several peripherals The user can select the reference voltages for the ADC0 by writing to theADC0 Reference Select bit field (ADC0REFSEL) in the Control A register (VREFCTRLA) and for AC0 bywriting to the AC0 Reference Select bit field DAC0REFSEL in VREFCTRLA
A voltage reference source is enabled automatically when requested by a peripheral The user canenable the reference voltage sources (and thus override the automatic disabling of unused sources) bywriting to the respective Force Enable bit (ADC0REFEN) in the Control B register (VREFCTRLB) Thismay be desirable to decrease start-up time at the cost of increased power consumption
1821 Block DiagramFigure 18-1 VREF Block Diagram
Reference se lect
Bandgap ReferenceGenerator
InternalReferenceBUF
11V15V25V43V
055V
Reference enable
Reference request
Bandgapenable
183 Functional Description
1831 InitializationThe default configuration will enable the respective source when the ADC0 AC0 is requesting areference voltage The default reference voltages are 055V but can be configured by writing to the
ATtiny406Voltage Reference (VREF)
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respective Reference Select bit field (ADC0REFSEL DAC0REFSEL) in the Control A register(VREFCTRLA)
ATtiny406Voltage Reference (VREF)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 172
184 Register Summary - VREF
Offset Name Bit Pos
0x00 CTRLA 70 ADC0REFSEL[20] DAC0REFSEL[20]
0x01 CTRLB 70 ADC0REFEN DAC0REFEN
185 Register Description
ATtiny406Voltage Reference (VREF)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 173
1851 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 ADC0REFSEL[20] DAC0REFSEL[20]
Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bits 64 ndash ADC0REFSEL[20] ADC0 Reference SelectThese bits select the reference voltage for the ADC0
Value Description0x0 055V0x1 11V0x2 25V0x3 43V0x4 15Vother Reserved
Bits 20 ndash DAC0REFSEL[20] AC0 Reference SelectThese bits select the reference voltage for the AC0
Value Description0x0 055V0x1 11V0x2 25V0x3 43V0x4 15Vother Reserved
ATtiny406Voltage Reference (VREF)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 174
1852 Control B
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 ADC0REFEN DAC0REFEN
Access RW RW Reset 0 0
Bit 1 ndash ADC0REFEN ADC0 Reference Force EnableWriting a 1 to this bit forces the voltage reference for the ADC0 to be running even if it is not requested
Writing a 0 to this bit allows automatic enabledisable of the reference source by the peripheral
Bit 0 ndash DAC0REFEN AC0 Reference Force EnableWriting a 1 to this bit forces the voltage reference for the AC0 to be running even if it is not requested
Writing a 0 to this bit allows automatic enabledisable of the reference source by the peripheral
ATtiny406Voltage Reference (VREF)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 175
19 Watchdog Timer (WDT)
191 Featuresbull Issues a System Reset if the Watchdog Timer is not Cleared Before its Time-out Periodbull Operating Asynchronously from System Clock Using an Independent Oscillatorbull Using the 1 kHz Output of the 32 kHz Ultra Low-Power Oscillator (OSCULP32K)bull 11 Selectable Time-out Periods from 8 ms to 8sbull Two Operation modes
ndash Normal modendash Window mode
bull Configuration Lock to Prevent Unwanted Changesbull Closed Period Timer Activation After First WDT Instruction for Easy Setup
192 OverviewThe Watchdog Timer (WDT) is a system function for monitoring correct program operation It allows thesystem to recover from situations such as runaway or deadlocked code by issuing a Reset Whenenabled the WDT is a constantly running timer configured to a predefined time-out period If the WDT isnot reset within the time-out period it will issue a system Reset The WDT is reset by executing the WDR(Watchdog Timer Reset) instruction from software
The WDT has two modes of operation Normal mode and Window mode The settings in the Control Aregister (WDTCTRLA) determine the mode of operation
A Window mode defines a time slot or window inside the time-out period during which the WDT must bereset If the WDT is reset outside this window either too early or too late a system Reset will be issuedCompared to the Normal mode the Window mode can catch situations where a code error causesconstant WDR execution
When enabled the WDT will run in Active mode and all Sleep modes It is asynchronous (ie runningfrom a CPU independent clock source) For this reason it will continue to operate and be able to issue asystem Reset even if the main clock fails
The CCP mechanism ensures that the WDT settings cannot be changed by accident For increasedsafety a configuration for locking the WDT settings is available
Related LinksConfiguration Change Protection (CCP)
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 176
1921 Block DiagramFigure 19-1 WDT Block Diagram
COUNT
=
=
Inside closed window
Enable open window and clear count
CLK_WDT
WDR(instruction)
SystemReset
CTRLA
CTRLA
WINDOW
PERIOD
1922 Signal DescriptionNot applicable
1923 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
Table 19-1 WDT System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections No -
Interrupts No -
Events No -
Debug Yes UPDI
Related LinksClocksDebug Operation
19231 ClocksA 1 KHz Oscillator Clock (CLK_WDT_OSC) is sourced from the internal Ultra Low-Power OscillatorOSCULP32K Due to the ultra low-power design the oscillator is not very accurate and so the exacttime-out period may vary from device to device This variation must be kept in mind when designingsoftware that uses the WDT to ensure that the time-out periods used are valid for all devices
The Counter Clock CLK_WDT_OSC is asynchronous to the system clock Due to this asynchronicitywriting to WDT Control register will require synchronization between the clock domains
Related LinksElectrical Characteristics
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 177
19232 IO Lines and ConnectionsNot applicable
19233 InterruptsNot applicable
19234 EventsNot applicable
19235 Debug OperationWhen run-time debugging this peripheral will continue normal operation Halting the CPU in Debuggingmode will halt normal operation of the peripheral
When halting the CPU in Debug mode the WDT counter is reset
When starting the CPU again and the WDT was operating in Window mode the first closed window time-out period will be disabled and a Normal mode time-out period is executed
Related LinksWindow Mode
193 Functional Description
1931 Initializationbull The WDT is enabled when a non-zero value is written to the Period bits (PERIOD) in the Control A
register (WDTCTRLA)bull Optional Write a non-zero value to the Window bits (WINDOW) in WDTCTRLA to enable Window
mode operation
All bits in the Control A register and the Lock bit (LOCK) in the STATUS register (WDTSTATUS) are writeprotected by the Configuration Change Protection mechanism
The Reset value of WDTCTRLA is defined by a fuse (FUSEWDTCFG) so the WDT can be enabled atboot time If this is the case the LOCK bit in WDTSTATUS is set at boot time
Related LinksRegister Summary - WDT
1932 Operation
19321 Normal ModeIn Normal mode operation a single time-out period is set for the WDT If the WDT is not reset fromsoftware using the WDR any time before the time out occurs the WDT will issue a system Reset
A new WDT time-out period will be started each time the WDT is reset by WDR
There are 11 possible WDT time-out periods (TOWDT) selectable from 8 ms to 8s by writing to the Periodbit field (PERIOD) in the Control A register (WDTCTRLA)
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 178
Figure 19-2 Normal Mode Operation
t [ms]
WDT Count
5 10 15 20 25 30 35
Timely WDT Reset (WDR)
TOWDT
WDT TimeoutSystem Reset
TO WDT = 16msHere
Normal mode is enabled as long as the WINDOW bit field in the Control A register (WDTCTRLA) is 0x0
Related LinksRegister Summary - WDT
19322 Window ModeIn Window mode operation the WDT uses two different time-out periods a closed Window Time-outperiod (TOWDTW) and the normal time out period (TOWDT)
bull The closed window time-out period defines a duration from 8 ms to 8s where the WDT cannot bereset If the WDT is reset during this period the WDT will issue a system Reset
bull The normal WDT time-out period which is also 8 ms to 8s defines the duration of the open periodduring which the WDT can (and should) be reset The open period will always follow the closedperiod so the total duration of the time-out period is the sum of the closed window and the openwindow time-out periods
When enabling Window mode or when going out of Debug mode the first closed period is activated afterthe first WDR instruction
If a second WDR is issued while a previous WDR is being synchronized the second one will be ignored
Figure 19-3 Window Mode Operation
t [ms]
WDT Count
5 10 15 20 25 30 35
Timely WDT Reset (WDR)
Clo
sed
TOWDTW
Ope
n
TOWDT
System ResetWDR too early
TOWDTW =TOWDT = 8msHere
The Window mode is enabled by writing a non-zero value to the WINDOW bit field in the Control Aregister (WDTCTRLA) and disabled by writing WINDOW=0x0
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 179
19323 Configuration Protection and LockThe WDT provides two security mechanisms to avoid unintentional changes to the WDT settings
The first mechanism is the Configuration Change Protection mechanism employing a timed writeprocedure for changing the WDT control registers
The second mechanism locks the configuration by writing a 1 to the LOCK bit in the STATUS register(WDTSTATUS) When this bit is 1 the Control A register (WDTCTRLA) cannot be changedConsequently the WDT cannot be disabled from software
LOCK in WDTSTATUS can only be written to 1 It can only be cleared in Debug mode
If the WDT configuration is loaded from fuses LOCK is automatically set in WDTSTATUS
Related LinksConfiguration Change Protection (CCP)
1933 EventsNot applicable
1934 InterruptsNot applicable
1935 Sleep Mode OperationThe WDT will continue to operate in any sleep mode where the source clock is active
1936 SynchronizationDue to asynchronicity between the main clock domain and the peripheral clock domain the Control Aregister (WDTCTRLA) is synchronized when written The Synchronization Busy flag (SYNCBUSY) in theSTATUS register (WDTSTATUS) indicates if there is an ongoing synchronization
Writing to WDTCTRLA while SYNCBUSY=1 is not allowed
The following registers are synchronized when writtenbull PERIOD bits in Control A register (WDTCTRLA)bull Window Period bits (WINDOW) in WDTCTRLA
The WDR instruction will need two to three cycles of the WDT clock in order to be synchronized Issuing anew WDR instruction while a WDR instruction is being synchronized will be ignored
1937 Configuration Change ProtectionThis peripheral has registers that are under Configuration Change Protection (CCP) In order to write tothese a certain key must be written to the CPUCCP register first followed by a write access to theprotected bits within four CPU instructions
It is possible to try writing to these registers any time but the values are not altered
The following registers are under CCP
Table 19-2 WDT - Registers Under Configuration Change Protection
Register Key
WDTCTRLA IOREG
LOCK bit in WDTSTATUS IOREG
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 180
List of bitsregisters protected by CCP
bull Period bits in Control A register (CTRLAPERIOD)bull Window Period bits in Control A register (CTRLAWINDOW)bull LOCK bit in STATUS register (STATUSLOCK)
Related LinksConfiguration Change Protection (CCP)Sequence for Write Operation to Configuration Change Protected IO RegistersCCP
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 181
194 Register Summary - WDT
Offset Name Bit Pos
0x00 CTRLA 70 WINDOW[30] PERIOD[30]
0x01 STATUS 70 LOCK SYNCBUSY
195 Register Description
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 182
1951 Control A
Name CTRLAOffset 0x00Reset From FUSEWDTCFGProperty Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 WINDOW[30] PERIOD[30]
Access RW RW RW RW RW RW RW RW Reset x x x x x x x x
Bits 74 ndash WINDOW[30] WindowWriting a non-zero value to these bits enables the Window mode and selects the duration of the closedperiod accordingly
The bits are optionally lock-protected
bull If LOCK bit in WDTSTATUS is 1 all bits are change-protected (Access = R)bull If LOCK bit in WDTSTATUS is 0 all bits can be changed (Access = RW)
Value Name Description0x0 OFF -0x1 8CLK 0008s0x2 16CLK 0016s0x3 32CLK 0032s0x4 64CLK 0064s0x5 128CLK 0128s0x6 256CLK 0256s0x7 512CLK 0512s0x8 1KCLK 1024s0x9 2KCLK 2048s0xA 4KCLK 4096s0xB 8KCLK 8192sother - Reserved
Bits 30 ndash PERIOD[30] PeriodWriting a non-zero value to this bit enables the WDT and selects the time-out period in Normal modeaccordingly In Window mode these bits select the duration of the open window
The bits are optionally lock-protected
bull If LOCK in WDTSTATUS is 1 all bits are change-protected (Access = R)bull If LOCK in WDTSTATUS is 0 all bits can be changed (Access = RW)
Value Name Description0x0 OFF -0x1 8CLK 0008s0x2 16CLK 0016s0x3 32CLK 0032s
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 183
Value Name Description0x4 64CLK 0064s0x5 128CLK 0128s0x6 256CLK 0256s0x7 512CLK 0512s0x8 1KCLK 10s0x9 2KCLK 20s0xA 4KCLK 41s0xB 8KCLK 82sother - Reserved
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 184
1952 Status
Name STATUSOffset 0x01Reset 0x00Property Configuration Change Protection
Bit 7 6 5 4 3 2 1 0 LOCK SYNCBUSY
Access RW R Reset 0 0
Bit 7 ndash LOCK LockWriting this bit to 1 write protects the WDTCTRLA register
It is only possible to write this bit to 1 This bit can only be cleared in Debug mode
If the PERIOD bits in WDTCTRLA are different from zero after boot code the lock will automatically beset
This bit is under CCP
Bit 0 ndash SYNCBUSY Synchronization BusyThis bit is set after writing to the WDTCTRLA register while the data is being synchronized from thesystem clock domain to the WDT clock domain
This bit is cleared by the system after the synchronization is finished
This bit is not under CCP
Related LinksSynchronizationConfiguration Change Protection
ATtiny406Watchdog Timer (WDT)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 185
20 16-bit TimerCounter Type A (TCA)
201 Featuresbull 16-Bit TimerCounterbull Three Compare Channelsbull Double Buffered Timer Period Settingbull Double Buffered Compare Channelsbull Waveform Generation
ndash Frequency generationndash Single-slope PWM (pulse-width modulation)ndash Dual-slope PWM
bull Count on Eventbull Timer Overflow InterruptsEventsbull One Compare Match per Compare Channelbull Two 8-Bit TimerCounters in Split Mode
202 OverviewThe flexible 16-bit PWM TimerCounter type A (TCA) provides accurate program execution timingfrequency and waveform generation and command execution
A TCA consists of a base counter and a set of compare channels The base counter can be used to countclock cycles or events or let events control how it counts clock cycles It has direction control and periodsetting that can be used for timing The compare channels can be used together with the base counter todo compare match control frequency generation and pulse width waveform modulation
Depending on the mode of operation the counter is cleared reloaded incremented or decremented ateach timercounter clock or event input
A timercounter can be clocked and timed from the peripheral clock with optional prescaling or from theevent system The event system can also be used for direction control or to synchronize operations
By default the TCA is a 16-bit timercounter The timercounter has a Split mode feature that splits it intotwo 8-bit timercounters with three compare channels each In Split mode each compare channel onlysupports single-slope PWM waveform generation
A block diagram of the 16-bit timercounter with closely related peripheral modules (in grey) is shown inthe figure below
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 186
Figure 20-1 16-bit TimerCounter and Closely Related Peripherals
CounterControl Logic
Timer Period
TimerCounterBase Counter Prescaler
EventSystem
CLK_PER
POR
TS
Comparator
Buffer
Compare Channel 2Compare Channel 1
Compare Channel 0
WaveformGeneration
This device provides one instance of the TCA peripheral TCA0
2021 Block DiagramThe figure below shows a detailed block diagram of the timercounter
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 187
Figure 20-2 TimerCounter Block DiagramBase Counter
Compare(Unit x = ABC)
Counter
=
CMPn
CMPnBUF
WaveformGeneration
BV
=
PERB
PER
CNT
BV
= 0
countclear
directionload
Control Logic
EVCTRL
CTRLA
OVFUNF(INT Req)
TOP
match CMPn(INT Req)
Control Logic
Clock Select
ev
UPD
ATE
BOTTOM
WOn Out
EventSelect
The counter register (TCAnCNT) period registers with buffer (TCAnPER and TCAnPERBUF) andcompare registers with buffers (TCAnCMPx and TCAnCMPBUFx) are 16-bit registers All bufferregisters have a buffer valid (BV) flag that indicates when the buffer contains a new value
During normal operation the counter value is continuously compared to zero and the period (PER) valueto determine whether the counter has reached TOP or BOTTOM
The counter value is also compared to the TCAnCMPx registers These comparisons can be used togenerate interrupt requests The Waveform Generator modes use these comparisons to set the waveformperiod or pulse width
A prescaled peripheral clock and events from the event system can be used to control the counter
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 188
Figure 20-3 TimerCounter Clock Logic
CKSEL
CNTEI
CLK_PER
event
Event SystemPrescaler
CNT
(Encoding)EVACTCLK_TCA
2022 Signal Description
Signal Description Type
WO[20] Digital output Waveform output
WO[53] Digital output Waveform output - Split Mode only
2023 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
Table 20-1 TCA System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections Yes WO[50]
Interrupts Yes CPUINT
Events Yes EVSYS
Debug Yes UPDI
Related LinksClocksDebug OperationInterruptsEvents
20231 ClocksThis peripheral uses the system clock CLK_PER and has its own prescaler
Related LinksClock Controller (CLKCTRL)
20232 IO Lines and ConnectionsUsing the IO lines of the peripheral requires configuration of the IO pins
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 189
Related LinksIO Multiplexing and ConsiderationsIO Pin Configuration (PORT)
20233 InterruptsUsing the interrupts of this peripheral requires the interrupt controller to be configured first
Related LinksCPU Interrupt Controller (CPUINT)SREGInterrupts
20234 EventsThe events of this peripheral are connected to the Event System
Related LinksEvent System (EVSYS)
20235 Debug OperationWhen run-time debugging this peripheral will continue normal operation Halting the CPU in Debuggingmode will halt normal operation of the peripheral
This peripheral can be forced to operate with halted CPU by writing a 1 to the Debug Run bit (DBGRUN)in the Debug Control register of the peripheral (peripheralDBGCTRL)
Related LinksUnified Program and Debug Interface (UPDI)
203 Functional Description
2031 DefinitionsThe following definitions are used throughout the documentation
Table 20-2 TimerCounter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes zero
MAX The counter reaches MAXimum when it becomes all ones
TOP The counter reaches TOP when it becomes equal to the highest value in the countsequence
UPDATE The update condition is met when the timercounter reaches BOTTOM or TOP depending onthe Waveform Generator mode
CNT Counter register value
CMP Compare register value
In general the term timer is used when the timercounter is counting periodic clock ticks The termcounter is used when the input signal has sporadic or irregular ticks
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 190
2032 InitializationTo start using the timercounter in a basic mode follow these steps
bull Write a TOP value to the Period register (TCAnPER)bull Enable the peripheral by writing a 1 to the ENABLE bit in the Control A register (TCAnCTRLA)
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bitfield (CLKSEL) in TCAnCTRLA
bull Optional By writing a 1 to the Enable Count on Event Input bit (CNTEI) in the Event Controlregister (TCAnEVCTRL) event inputs are counted instead of clock ticks
bull The counter value can be read from the Counter bit field (CNT) in the Counter register(TCAnCNT)
2033 Operation
20331 Normal OperationIn normal operation the counter is counting clock ticks in the direction selected by the Direction bit (DIR)in the Control E register (TCAnCTRLE) until it reaches TOP or BOTTOM The clock ticks are from theperipheral clock CLK_PER optionally prescaled depending on the Clock Select bit field (CLKSEL) in theControl A register (TCAnCTRLA)
When up-counting and TOP are reached the counter will wrap to zero at the next clock tick When down-counting the counter is reloaded with the Period register value (TCAnPER) when BOTTOM is reached
Figure 20-4 Normal OperationCNT written
update
CNT
DIR
MAX
TOP
BOTTOM
It is possible to change the counter value in the Counter register (TCAnCNT) when the counter isrunning The write access to TCAnCNT has higher priority than count clear or reload and will beimmediate The direction of the counter can also be changed during normal operation by writing to DIR inTCAnCTRLE
20332 Double BufferingThe Period register value (TCAnPER) and the Compare n register values (TCAnCMPn) are all doublebuffered (TCAnPERBUF and TCAnCMPnBUF)
Each buffer register has a Buffer Valid flag (PERBV CMPnBV) in the Control F register (TCAnCTRLF)which indicates that the buffer register contains a valid (ie new value that can be copied into thecorresponding Period or Compare register) When the Period register and Compare n registers are usedfor a compare operation the BV flag is set when data is written to the buffer register and cleared on anUPDATE condition This is shown for a Compare register below
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 191
Figure 20-5 Period and Compare Double Buffering
UPDATE
write enable data write
CNT
match
EN
EN
CMPnBUF
CMPn
BV
=
Both the TCAnCMPn and TCAnCMPnBUF registers are available as IO registers This allowsinitialization and bypassing of the buffer register and the double buffering function
20333 Changing the PeriodThe Counter period is changed by writing a new TOP value to the Period register (TCAnPER)
No Buffering If double buffering is not used any period update is immediate
Figure 20-6 Changing the Period Without Buffering
CNT
MAX
BOTTOM
Counter wraparound
update
write
New TOP written toPER that is higherthan current CNT
New TOP written toPER that is lowerthan current CNT
A counter wrap-around can occur in any mode of operation when up-counting without buffering This isdue to the fact that the registers TCAnCNT and TCAnPER are continuously compared if a new TOPvalue is written to TCAnPER that is lower than current TCAnCNT the counter will wrap first before acompare match happensFigure 20-7 Unbuffered Dual-Slope Operation
Counter wraparound
update
write
MAX
BOTTOM
CNT
New TOP written toPER that is higherthan current CNT
New TOP written toPER that is lowerthan current CNT
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 192
With Buffering When double buffering is used the buffer can be written at any time and still maintaincorrect operation The TCAnPER is always updated on the UPDATE condition as shown for dual-slopeoperation in the figure below This prevents wrap-around and the generation of odd waveformsFigure 20-8 Changing the Period Using Buffering
CNT
BOTTOM
MAX
update
write
New Period written toPERB that is higherthan current CNT
New Period written toPERB that is lowerthan current CNT
New PER is updatedwith PERB value
20334 Compare ChannelEach Compare Channel n continuously compares the counter value (TCAnCNT) with the Compare nregister (TCAnCMPn) If TCAnCNT equals TCAnCMPn the comparator n signals a match The matchwill set the Compare Channels interrupt flag at the next timer clock cycle and the optional interrupt isgenerated
The Compare n Buffer register (TCAnCMPnBUF) provides double buffer capability equivalent to that forthe period buffer The double buffering synchronizes the update of the TCAnCMPn register with thebuffer value to either the TOP or BOTTOM of the counting sequence according to the UPDATE conditionThe synchronization prevents the occurrence of odd-length non-symmetrical pulses for glitch-free output
Waveform GenerationThe compare channels can be used for waveform generation on the corresponding port pins To makethe waveform visible on the connected port pin the following requirements must be met
1 A Waveform Generation mode must be selected by writing the WGMODE bit field in TCAnCTRLB2 The TCA is counting clock ticks not events (CNTEI=0 in TCAnEVCTRL)3 The compare channels used must be enabled (CMPnEN=1 in TCAnCTRLB) This will override the
corresponding port pin output register An alternative pin can be selected by writing to therespective TCA Waveform Output n bit (TCA0n) in the Control C register of the Port Multiplexer(PORTMUXCTRLC)
4 The direction for the associated port pin n must be configured as an output (PORTxDIR[n]=1)5 Optional Enable inverted waveform output for the associated port pin n (INVEN=1 in PORTxPINn)
Frequency (FRQ) Waveform GenerationFor frequency generation the period time (T) is controlled by a TCAnCMPn register instead of the Periodregister (TCAnPER) The waveform generation output WG is toggled on each compare match betweenthe TCAnCNT and TCAnCMPn registers
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 193
Figure 20-9 Frequency Waveform Generation
CNT
WG Output
MAX
TOP
BOTTOM
Period (T) Direction change CNT written
update
The waveform frequency (fFRQ) is defined by the following equationFRQ = fCLK_PER2 CMPn+1where N represents the prescaler divider used (CLKSEL in TCAnCTRLA) and fCLK_PER is the systemclock for the peripherals
The maximum frequency of the waveform generated is half of the peripheral clock frequency (fCLK_PER2)when TCAnCMPn is written to zero (0x0000) and no prescaling is used (N=1 CLKSEL=0x0 inTCAnCTRLA)
Single-Slope PWM GenerationFor single-slope Pulse-Width Modulation (PWM) generation the period (T) is controlled by TCAnPERwhile the values of TCAnCMPn control the duty cycle of the WG output The figure below shows how thecounter counts from BOTTOM to TOP and then restarts from BOTTOM The waveform generator (WO)output is set at TOP and cleared on the compare match between the TCAnCNT and TCAnCMPnregisters
Figure 20-10 Single-Slope Pulse-Width Modulation
CNT
Output WOn
MAXTOP
CMPn
BOTTOM
Period (T) CMPn=BOTTOM CMPn=TOP updatematch
The TCAnPER register defines the PWM resolution The minimum resolution is 2 bits(TCAPER=0x0003) and the maximum resolution is 16 bits (TCAPER=MAX)
The following equation calculates the exact resolution for single-slope PWM (RPWM_SS)PWM_SS = log PER+1log 2The single-slope PWM frequency (fPWM_SS) depends on the period setting (TCA_PER) the systemsperipheral clock frequency fCLK_PER and the TCA prescaler (CLKSEL in TCAnCTRLA) It is calculated bythe following equation where N represents the prescaler divider used
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 194
PWM_SS = CLK_PER PER+1Dual-Slope PWMFor dual-slope PWM generation the period (T) is controlled by TCAnPER while the values ofTCAnCMPn control the duty cycle of the WG output
The figure below shows how for dual-slope PWM the counter counts repeatedly from BOTTOM to TOPand then from TOP to BOTTOM The waveform generator output is set on BOTTOM cleared on comparematch when up-counting and set on compare match when down-counting
Figure 20-11 Dual-Slope Pulse-Width Modulation
MAX
TOP
BOTTOM
CNT
Waveform Output WOn
Period (T) CMPn=BOTTOM CMPn=TOP updatematch
CMPn
Using dual-slope PWM results in a lower maximum operation frequency compared to the single-slopePWM operation
The period register (TCAnPER) defines the PWM resolution The minimum resolution is 2 bits(TCAnPER=0x0003) and the maximum resolution is 16 bits (TCAnPER=MAX)
The following equation calculates the exact resolution for dual-slope PWM (RPWM_DS)PWM_DS = log PER+1log 2The PWM frequency depends on the period setting (TCAnPER) the peripheral clock frequency(fCLK_PER) and the prescaler divider used (CLKSEL in TCAnCTRLA) It is calculated by the followingequationPWM_DS = CLK_PER2 sdot PERN represents the prescaler divider used
Port Override for Waveform GenerationTo make the waveform generation available on the port pins the corresponding port pin direction must beset as output (PORTxDIR[n]=1) The TCA will override the port pin values when the compare channel isenabled (CMPnEN=1 in TCAnCTRLB) and a Waveform Generation mode is selected
The figure below shows the port override for TCA The timercounter compare channel will override theport pin output value (OUT) on the corresponding port pin Enabling inverted IO on the port pin(INVEN=1 in PORTPINn) inverts the corresponding WG output
Figure 20-12 Port Override for TimerCounter Type A
Waveform
OUT
CMPnEN INVEN
WOn
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 195
20335 TimerCounter CommandsA set of commands can be issued by software to immediately change the state of the peripheral Thesecommands give direct control of the UPDATE RESTART and RESET signals A command is issued bywriting the respective value to the Command bit field (CMD) in the Control E register (TCAnCTRLESET)
An Update command has the same effect as when an update condition occurs except that the Updatecommand is not affected by the state of the Lock Update bit (LUPD) in the Control E register(TCAnCTRLE)
The software can force a restart of the current waveform period by issuing a Restart command In thiscase the counter direction and all compare outputs are set to zero
A Reset command will set all timercounter registers to their initial values A Reset can be issued onlywhen the timercounter is not running (ENABLE=0 in TCAnCTRLA)
20336 Split Mode - Two 8-Bit TimerCounters
Split Mode OverviewTo double the number of timers and PWM channels in the TCA a Split mode is provided In this Splitmode the 16-bit timercounter acts as two separate 8-bit timers which each have three comparechannels for PWM generation The Split mode will only work with single-slope down-count Split modedoes not support event action controlled operation
Split Mode Differences to Normal Modebull Count
ndash Down-count onlyndash Timercounter counter high and low byte are independent (TCAnLCNT TCAnHCNT)
bull Waveform Generationndash Single-slope PWM only (WGMODE=SINGLESLOPE in TCAnCTRLB)
bull Interruptndash No change for low byte TimerCounter (TCAnLCNT)ndash Underflow interrupt for high byte TimerCounter (TCAnHCNT)ndash No compare interrupt or flag for High-byte Compare n registers (TCAnHCMPn)
bull Event Actions Not Compatiblebull Buffer registers and Buffer Valid Flags Unusedbull Register Access Byte Access to all registersbull Temp register Unused 16-bit register of the Normal mode are Accessed as 8-bit TCA_H and
TCA_L Respectively
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 196
Block DiagramFigure 20-13 TimerCounter Block Diagram Split Mode
Base Counter
Compare (Unit n = 012)
Counter
= 0
Control Logic
HUNF(INT Req)
BOTTOML
Compare (Unit n = 012)
Waveform Generation
LCMPn(INT Req)
WOn Out
= match
BOTTOMH
count low load low
=
Waveform Generation
match
WO[n+3] Out
= 0
count high load high
Clock Select
LUNF(INT Req)
HPER CTRLALPER
LCMPn
LCNTHCNT
HCMPn
Split Mode InitializationWhen shifting between Normal mode and Split mode the functionality of some registers and bits changebut their values do not For this reason disabling the peripheral (ENABLE=0 in TCAnCTRLA) and doinga hard Reset (CMD=RESET in TCAnCTRLESET) is recommended when changing the mode to avoidunexpected behavior
To start using the timercounter in basic Split mode after a hard Reset follow these stepsbull Enable Split mode by writing a 1 to the Split mode enable bit in the Control D register (SPLITM in
TCAnCTRLD)bull Write a TOP value to the Period registers (TCAnPER)bull Enable the peripheral by writing a 1 to the ENABLE bit in the Control A register (TCAnCTRLA)
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bitfield (CLKSEL) in TCAnCTRLA
bull The counter values can be read from the Counter bit field in the Counter registers (TCAnCNT)
Activating Split mode results in changes to the functionality of some registers and register bits Themodifications are described in a separate register map
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 197
2034 EventsThe TCA is an event generator The following events will generate a one-cycle strobe on the eventchannel outputs
bull Timer overflowbull Timer underflow in Split modebull Compare match channel 0bull Compare match channel 1bull Compare match channel 2
The peripheral can take the following actions on an input event
bull The counter counts positive edges of the event signalbull The counter counts both positive and negative edges of the event signalbull The counter counts prescaled clock cycles as long as the event signal is highbull The counter counts prescaled clock cycles The event signal controls the direction of counting Up-
counting when the event signal is low and down-counting when the event signal is high
The specific action is selected by writing to the Event Action bits (EVACT) in the Event Control register(TCAnEVCTRL) Events as input are enabled by writing a 1 to the Enable Count on Event Input bit(CNTEI in TCAnEVCTRL)
Event controlled inputs are not used in Split mode
2035 InterruptsTable 20-3 Available Interrupt Vectors and Sources in Normal Mode
Offset Name Vector Description Conditions
0x00 OVF Overflow and compare matchinterrupt
The counter has reached its top value and wrapped tozero
0x04 CMP0 Compare channel 0 interrupt Match between the counter value and the Compare 0register
0x06 CMP1 Compare channel 1 interrupt Match between the counter value and the Compare 1register
0x08 CMP2 Compare channel 2 interrupt Match between the counter value and the Compare 2register
Table 20-4 Available Interrupt Vectors and Sources in Split Mode
Offset Name Vector Description Conditions
0x00 LUNF Low byte underflow interrupt Low byte timer reaches BOTTOM
0x02 HUNF High byte underflow interrupt High byte timer reaches BOTTOM
0x04 LCMP0 Compare channel 0 interrupt Match between the counter value and the low byte ofCompare 0 register
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 198
Offset Name Vector Description Conditions
0x06 LCMP1 Compare channel 1 interrupt Match between the counter value and the low byte ofCompare 1 register
0x08 LCMP2 Compare channel 2 interrupt Match between the counter value and the low byte of theCompare 2 register
When an interrupt condition occurs the corresponding interrupt flag is set in the Interrupt Flags register ofthe peripheral (peripheralINTFLAGS)
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheralsInterrupt Control register (peripheralINTCTRL)
An interrupt request is generated when the corresponding interrupt source is enabled and the interruptflag is set The interrupt request remains active until the interrupt flag is cleared See the peripheralsINTFLAGS register for details on how to clear interrupt flags
Related LinksAVR CPUSREG
2036 Sleep Mode OperationThe timercounter will continue operation in Idle Sleep mode
2037 Configuration Change ProtectionNot applicable
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 199
204 Register Summary - TCA in Normal Mode (CTRLDSPLITM=0)
Offset Name Bit Pos
0x00 CTRLA 70 CLKSEL[20] ENABLE
0x01 CTRLB 70 CMP2EN CMP1EN CMP0EN ALUPD WGMODE[20]
0x02 CTRLC 70 CMP2OV CMP1OV CMP0OV
0x03 CTRLD 70 SPLITM
0x04 CTRLECLR 70 CMD[10] LUPD DIR
0x05 CTRLESET 70 CMD[10] LUPD DIR
0x06 CTRLFCLR 70 CMP2BV CMP1BV CMP0BV PERBV
0x07 CTRLFSET 70 CMP2BV CMP1BV CMP0BV PERBV
0x08 Reserved
0x09 EVCTRL 70 EVACT[10] CNTEI
0x0A INTCTRL 70 CMP2 CMP1 CMP0 OVF
0x0B INTFLAGS 70 CMP2 CMP1 CMP0 OVF
0x0C
0x0D
Reserved
0x0E DBGCTRL 70 DBGRUN
0x0F TEMP 70 TEMP[70]
0x10
0x1F
Reserved
0x20 CNT70 CNT[70]
158 CNT[158]
0x22
0x25
Reserved
0x26 PER70 PER[70]
158 PER[158]
0x28 CMP070 CMP[70]
158 CMP[158]
0x2A CMP170 CMP[70]
158 CMP[158]
0x2C CMP270 CMP[70]
158 CMP[158]
0x2E
0x35
Reserved
0x36 PERBUF70 PERBUF[70]
158 PERBUF[158]
0x38 CMP0nBUF70 CMPBUF[70]
158 CMPBUF[158]
0x3A CMP1nBUF70 CMPBUF[70]
158 CMPBUF[158]
0x3C CMP2nBUF70 CMPBUF[70]
158 CMPBUF[158]
ATtiny40616-bit TimerCounter Type A (TCA)
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205 Register Description - Normal Mode
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 201
2051 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CLKSEL[20] ENABLE
Access RW RW RW RW Reset 0 0 0 0
Bits 31 ndash CLKSEL[20] Clock SelectThese bits select the clock frequency for the timercounter
Value Name Description0x0 DIV1 fTCA = fCLK_PER10x1 DIV2 fTCA = fCLK_PER20x2 DIV4 fTCA = fCLK_PER40x3 DIV8 fTCA = fCLK_PER80x4 DIV16 fTCA = fCLK_PER160x5 DIV64 fTCA = fCLK_PER640x6 DIV256 fTCA = fCLK_PER2560x7 DIV1024 fTCA = fCLK_PER1024
Bit 0 ndash ENABLE Enable
Value Description0 The peripheral is disabled1 The peripheral is enabled
ATtiny40616-bit TimerCounter Type A (TCA)
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2052 Control B - Normal Mode
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CMP2EN CMP1EN CMP0EN ALUPD WGMODE[20]
Access RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0
Bits 4 5 6 ndash CMPEN Compare n EnableIn the FRQ or PWM Waveform Generation mode these bits will override the PORT output register for thecorresponding pin
Value Description0 Port output settings for the pin with WOn output respected1 Port output settings for pin with WOn output overridden in FRQ or PWM Waveform
Generation mode
Bit 3 ndash ALUPD Auto-Lock UpdateThe Auto-Lock Update feature controls the Lock Update (LUPD) bit in the TCAnCTRLE register WhenALUPD is written to lsquo1rsquo LUPD will be set to lsquo1rsquo until the Buffer Valid (CMPnBV) bits of all enabled comparechannels are lsquo1rsquo This condition will clear LUPD
It will remain cleared until the next UPDATE condition where the buffer values will be transferred to theCMPn registers and LUPD will be set to lsquo1rsquo again This makes sure that CMPnBUF register values are nottransferred to the CMPn registers until all enabled compare buffers are written
Value Description0 LUPD in TCACTRLE not altered by system1 LUPD in TCACTRLE set and cleared automatically
Bits 20 ndash WGMODE[20] Waveform Generation ModeThese bits select the Waveform Generation mode and control the counting sequence of the counter TOPvalue UPDATE condition interrupt condition and type of waveform that is generated
No waveform generation is performed in the Normal mode of operation For all other modes the resultfrom the waveform generator will only be directed to the port pins if the corresponding CMPnEN bit hasbeen set to enable this The port pin direction must be set as output
Table 20-5 Timer Waveform Generation Mode
WGMODE[20] Group Configuration Mode of Operation Top Update OVF
000 NORMAL Normal PER TOP TOP
001 FRQ Frequency CMP0 TOP TOP
010 - Reserved - - -
011 SINGLESLOPE Single-slope PWM PER BOTTOM BOTTOM
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 203
WGMODE[20] Group Configuration Mode of Operation Top Update OVF
100 - Reserved - - -
101 DSTOP Dual-slope PWM PER BOTTOM TOP
110 DSBOTH Dual-slope PWM PER BOTTOM TOP and BOTTOM
111 DSBOTTOM Dual-slope PWM PER BOTTOM BOTTOM
Value Name Description0x0 NORMAL Normal operation mode0x1 FRQ Frequency mode0x3 SINGLESLOPE Single-slope PWM mode0x5 DSTOP Dual-slope PWM mode0x6 DSBOTH Dual-slope PWM mode0x7 DSBOTTOM Dual-slope PWM modeOther - Reserved
ATtiny40616-bit TimerCounter Type A (TCA)
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2053 Control C - Normal Mode
Name CTRLCOffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CMP2OV CMP1OV CMP0OV
Access RW RW RW Reset 0 0 0
Bit 2 ndash CMP2OV Compare Output Value 2See CMP0OV
Bit 1 ndash CMP1OV Compare Output Value 1See CMP0OV
Bit 0 ndash CMP0OV Compare Output Value 0The CMPnOV bits allow direct access to the waveform generators output compare value when the timercounter is not enabled This is used to set or clear the WG output value when the timercounter is notrunning
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 205
2054 Control D
Name CTRLDOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SPLITM
Access RW Reset 0
Bit 0 ndash SPLITM Enable Split ModeThis bit sets the timercounter in Split mode operation It will then work as two 8-bit timercounters Theregister map will change compared to normal 16-bit mode
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 206
2055 Control Register E Clear - Normal Mode
Name CTRLECLROffset 0x04Reset 0x00Property -
The individual Status bit can be cleared by writing a one to its bit location This allows each bit to becleared without the use of a read-modify-write operation on a single registerEach Status bit can be read out either by reading TCAnCTRLESET or TCAnCTRLECLR
Bit 7 6 5 4 3 2 1 0 CMD[10] LUPD DIR
Access RW RW RW RW Reset 0 0 0 0
Bits 32 ndash CMD[10] CommandThese bits are used for software control of update restart and reset of the timercounter The commandbits are always read as zero
Value Name Description0x0 NONE No command0x1 UPDATE Force update0x2 RESTART Force restart0x3 RESET Force hard Reset (ignored if TC is enabled)
Bit 1 ndash LUPD Lock UpdateLock update can be used to ensure that all buffers are valid before an update is performed
Value Description0 The buffered registers are updated as soon as an UPDATE condition has occurred1 No update of the buffered registers is performed even though an UPDATE condition has
occurred
Bit 0 ndash DIR Counter DirectionNormally this bit is controlled in hardware by the Waveform Generation mode or by event actions but thisbit can also be changed from software
Value Description0 The counter is counting up (incrementing)1 The counter is counting down (decrementing)
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 207
2056 Control Register E Set - Normal Mode
Name CTRLESETOffset 0x05Reset 0x00Property -
The individual Status bit can be set by writing a 1 to its bit location This allows each bit to be set withoutthe use of a read-modify-write operation on a single registerEach Status bit can be read out either by reading TCAnCTRLESET or TCAnCTRLECLR
Bit 7 6 5 4 3 2 1 0 CMD[10] LUPD DIR
Access RW RW RW RW Reset 0 0 0 0
Bits 32 ndash CMD[10] CommandThese bits are used for software control of update restart and reset the timercounter The command bitsare always read as zero
Value Name Description0x0 NONE No command0x1 UPDATE Force update0x2 RESTART Force restart0x3 RESET Force hard Reset (ignored if TC is enabled)
Bit 1 ndash LUPD Lock UpdateLocking the update ensures that all buffers are valid before an update is performed
Value Description0 The buffered registers are updated as soon as an UPDATE condition has occurred1 No update of the buffered registers is performed even though an UPDATE condition has
occurred
Bit 0 ndash DIR Counter DirectionNormally this bit is controlled in hardware by the Waveform Generation mode or by event actions but thisbit can also be changed from software
Value Description0 The counter is counting up (incrementing)1 The counter is counting down (decrementing)
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 208
2057 Control Register F Clear
Name CTRLFCLROffset 0x06Reset 0x00Property -
The individual Status bit can be cleared by writing a 1 to its bit location This allows each bit to becleared without the use of a read-modify-write operation on a single register
Bit 7 6 5 4 3 2 1 0 CMP2BV CMP1BV CMP0BV PERBV
Access RW RW RW RW Reset 0 0 0 0
Bit 3 ndash CMP2BV Compare 2 Buffer ValidSee CMP0BV
Bit 2 ndash CMP1BV Compare 1 Buffer ValidSee CMP0BV
Bit 1 ndash CMP0BV Compare 0 Buffer ValidThe CMPnBV bits are set when a new value is written to the corresponding TCAnCMPnBUF registerThese bits are automatically cleared on an UPDATE condition
Bit 0 ndash PERBV Period Buffer ValidThis bit is set when a new value is written to the TCAnPERBUF register This bit is automatically clearedon an UPDATE condition
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 209
2058 Control Register F Set
Name CTRLFSETOffset 0x07Reset 0x00Property -
The individual status bit can be set by writing a one to its bit location This allows each bit to be setwithout the use of a read-modify-write operation on a single register
Bit 7 6 5 4 3 2 1 0 CMP2BV CMP1BV CMP0BV PERBV
Access RW RW RW RW Reset 0 0 0 0
Bit 3 ndash CMP2BV Compare 2 Buffer ValidSee CMP0BV
Bit 2 ndash CMP1BV Compare 1 Buffer ValidSee CMP0BV
Bit 1 ndash CMP0BV Compare 0 Buffer ValidThe CMPnBV bits are set when a new value is written to the corresponding TCAnCMPnBUF registerThese bits are automatically cleared on an UPDATE condition
Bit 0 ndash PERBV Period Buffer ValidThis bit is set when a new value is written to the TCAnPERBUF register This bit is automatically clearedon an UPDATE condition
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 210
2059 Event Control
Name EVCTRLOffset 0x09Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 EVACT[10] CNTEI
Access RW RW RW Reset 0 0 0
Bits 21 ndash EVACT[10] Event ActionThese bits define what type of event action the counter will increment or decrement
Value Name Description0x0 EVACT_POSEDGE Count on positive edge event0x1 EVACT_ANYEDGE Count on any edge event0x2 EVACT_HIGHLVL Count on prescaled clock while event line is 10x3 EVACT_UPDOWN Count on prescaled clock The Event controls the count direction Up-
counting when the event line is 0 down-counting when the event line is1
Bit 0 ndash CNTEI Enable Count on Event Input
Value Description0 Counting on Event input is disabled1 Counting on Event input is enabled according to EVACT bit field
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 211
20510 Interrupt Control Register - Normal Mode
Name INTCTRLOffset 0x0AReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CMP2 CMP1 CMP0 OVF
Access RW RW RW RW Reset 0 0 0 0
Bit 6 ndash CMP2 Compare Channel 2 Interrupt EnableSee CMP0
Bit 5 ndash CMP1 Compare Channel 1 Interrupt EnableSee CMP0
Bit 4 ndash CMP0 Compare Channel 0 Interrupt EnableWriting CMPn bit to 1 enables compare interrupt from channel n
Bit 0 ndash OVF Timer OverflowUnderflow Interrupt EnableWriting OVF bit to 1 enables overflow interrupt
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 212
20511 Interrupt Flag Register - Normal Mode
Name INTFLAGSOffset 0x0BReset 0x00Property -
The individual Status bit can be cleared by writing a 1 to its bit location This allows each bit to be setwithout the use of a read-modify-write operation on a single register
Bit 7 6 5 4 3 2 1 0 CMP2 CMP1 CMP0 OVF
Access RW RW RW RW Reset 0 0 0 0
Bit 6 ndash CMP2 Compare Channel 2 Interrupt FlagSee CMP0 flag description
Bit 5 ndash CMP1 Compare Channel 1 Interrupt FlagSee CMP0 flag description
Bit 4 ndash CMP0 Compare Channel 0 Interrupt FlagThe Compare Interrupt flag (CMPn) is set on a compare match on the corresponding compare channel
For all modes of operation the CMPn flag will be set when a compare match occurs between the Countregister (TCAnCNT) and the corresponding Compare register (TCAnCMPn) The CMPn flag will not becleared automatically and has to be cleared by software This is done by writing a one to its bit location
Bit 0 ndash OVF OverflowUnderflow Interrupt FlagThis flag is set either on a TOP (overflow) or BOTTOM (underflow) condition depending on theWGMODE setting OVF is not automatically cleared and needs to be cleared by software This is done bywriting a one to its bit location
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 213
20512 Debug Control Register
Name DBGCTRLOffset 0x0EReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DBGRUN
Access RW Reset 0
Bit 0 ndash DBGRUN Run in Debug
Value Description0 The peripheral is halted in Break Debug mode and ignores events1 The peripheral will continue to run in Break Debug mode when the CPU is halted
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 214
20513 Temporary Bits for 16-Bit Access
Name TEMPOffset 0x0FReset 0x00Property -
The Temporary register is used by the CPU for single-cycle 16-bit access to the 16-bit registers of thisperipheral It can be read and written by software See Accessing 16-Bit Registers There is one commonTemporary register for all the 16-bit registers of this peripheral
Bit 7 6 5 4 3 2 1 0 TEMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash TEMP[70] Temporary Bits for 16-bit Access
ATtiny40616-bit TimerCounter Type A (TCA)
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20514 Counter Register - Normal Mode
Name CNTOffset 0x20Reset 0x00Property -
The TCAnCNTL and TCAnCNTH register pair represents the 16-bit value TCAnCNT The low byte [70](suffix L) is accessible at the original offset The high byte [158] (suffix H) can be accessed at offset+ 0x01 For more details on reading and writing 16-bit registers refer to Accessing 16-Bit Registers
CPU and UPDI write access has priority over internal updates of the register
Bit 15 14 13 12 11 10 9 8 CNT[158]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CNT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 158 ndash CNT[158] Counter High ByteThese bits hold the MSB of the 16-bit counter register
Bits 70 ndash CNT[70] Counter Low ByteThese bits hold the LSB of the 16-bit counter register
ATtiny40616-bit TimerCounter Type A (TCA)
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20515 Period Register - Normal Mode
Name PEROffset 0x26Reset 0xFFFFProperty -
TCAnPER contains the 16-bit TOP value in the timercounter
The TCAnPERL and TCAnPERH register pair represents the 16-bit value TCAnPER The low byte[70] (suffix L) is accessible at the original offset The high byte [158] (suffix H) can be accessed at offset+ 0x01 For more details on reading and writing 16-bit registers refer to Accessing 16-Bit Registers
Bit 15 14 13 12 11 10 9 8 PER[158]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0 PER[70]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 158 ndash PER[158] Periodic High ByteThese bits hold the MSB of the 16-bit period register
Bits 70 ndash PER[70] Periodic Low ByteThese bits hold the LSB of the 16-bit period register
ATtiny40616-bit TimerCounter Type A (TCA)
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20516 Compare n Register - Normal Mode
Name CMPnOffset 0x28 + n0x02 [n=02]Reset 0x00Property -
This register is continuously compared to the counter value Normally the outputs from the comparatorsare then used for generating waveforms
TCAnCMPn registers are updated with the buffer value from their corresponding TCAnCMPnBUFregister when an UPDATE condition occurs
The TCAnCMPnL and TCAnCMPnH register pair represents the 16-bit value TCAnCMPn The lowbyte [70] (suffix L) is accessible at the original offset The high byte [158] (suffix H) can be accessed atoffset + 0x01 For more details on reading and writing 16-bit registers refer to Accessing 16-BitRegisters
Bit 15 14 13 12 11 10 9 8 CMP[158]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 158 ndash CMP[158] Compare High ByteThese bits hold the MSB of the 16-bit compare register
Bits 70 ndash CMP[70] Compare Low ByteThese bits hold the LSB of the 16-bit compare register
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 218
20517 Period Buffer Register
Name PERBUFOffset 0x36Reset 0xFFFFProperty -
This register serves as the buffer for the period register (TCAnPER) Accessing this register using theCPU or UPDI will affect the PERBV flag
The TCAnPERBUFL and TCAnPERBUFH register pair represents the 16-bit value TCAnPERBUF Thelow byte [70] (suffix L) is accessible at the original offset The high byte [158] (suffix H) can be accessedat offset + 0x01 For more details on reading and writing 16-bit registers refer to Accessing 16-BitRegisters
Bit 15 14 13 12 11 10 9 8 PERBUF[158]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0 PERBUF[70]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 158 ndash PERBUF[158] Period Buffer High ByteThese bits hold the MSB of the 16-bit period buffer register
Bits 70 ndash PERBUF[70] Period Buffer Low ByteThese bits hold the LSB of the 16-bit period buffer register
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 219
20518 Compare n Buffer Register
Name CMPnBUFOffset 0x38 + n0x02 [n=02]Reset 0x00Property -
This register serves as the buffer for the associated compare registers (TCAnCMPn) Accessing any ofthese registers using the CPU or UPDI will affect the corresponding CMPnBV status bit
The TCAnCMPnBUFL and TCAnCMPnBUFH register pair represents the 16-bit value TCAnCMPnBUFThe low byte [70] (suffix L) is accessible at the original offset The high byte [158] (suffix H) can beaccessed at offset + 0x01 For more details on reading and writing 16-bit registers refer to Accessing 16-Bit Registers
Bit 15 14 13 12 11 10 9 8 CMPBUF[158]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 CMPBUF[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 158 ndash CMPBUF[158] Compare High ByteThese bits hold the MSB of the 16-bit compare buffer register
Bits 70 ndash CMPBUF[70] Compare Low ByteThese bits hold the LSB of the 16-bit compare buffer register
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 220
206 Register Summary - TCA in Split Mode (CTRLDSPLITM=1)
Offset Name Bit Pos
0x00 CTRLA 70 CLKSEL[20] ENABLE
0x01 CTRLB 70 HCMP2EN HCMP1EN HCMP0EN LCMP2EN LCMP1EN LCMP0EN
0x02 CTRLC 70 HCMP2OV HCMP1OV HCMP0OV LCMP2OV LCMP1OV LCMP0OV
0x03 CTRLD 70 SPLITM
0x04 CTRLECLR 70 CMD[10] CMDEN[10]
0x05 CTRLESET 70 CMD[10] CMDEN[10]
0x06
0x09
Reserved
0x0A INTCTRL 70 LCMP2 LCMP1 LCMP0 HUNF LUNF
0x0B INTFLAGS 70 LCMP2 LCMP1 LCMP0 HUNF LUNF
0x0C
0x0D
Reserved
0x0E DBGCTRL 70 DBGRUN
0x0F
0x1F
Reserved
0x20 LCNT 70 LCNT[70]
0x21 HCNT 70 HCNT[70]
0x22
0x25
Reserved
0x26 LPER 70 LPER[70]
0x27 HPER 70 HPER[70]
0x28 LCMP0 70 LCMP[70]
0x29 HCMP0 70 HCMP[70]
0x2A LCMP1 70 LCMP[70]
0x2B HCMP1 70 HCMP[70]
0x2C LCMP2 70 LCMP[70]
0x2D HCMP2 70 HCMP[70]
207 Register Description - Split Mode
ATtiny40616-bit TimerCounter Type A (TCA)
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2071 Control A
Name CTRLAOffset 0x00Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 CLKSEL[20] ENABLE
Access RW RW RW RW Reset 0 0 0 0
Bits 31 ndash CLKSEL[20] Clock SelectThese bits select the clock frequency for the timercounter
Value Name Description0x0 DIV1 fTCA = fCLK_PER10x1 DIV2 fTCA = fCLK_PER20x2 DIV4 fTCA = fCLK_PER40x3 DIV8 fTCA = fCLK_PER80x4 DIV16 fTCA = fCLK_PER160x5 DIV64 fTCA = fCLK_PER640x6 DIV256 fTCA = fCLK_PER2560x7 DIV1024 fTCA = fCLK_PER1024
Bit 0 ndash ENABLE Enable
Value Description0 The peripheral is disabled1 The peripheral is enabled
ATtiny40616-bit TimerCounter Type A (TCA)
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2072 Control B - Split Mode
Name CTRLBOffset 0x01Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 HCMP2EN HCMP1EN HCMP0EN LCMP2EN LCMP1EN LCMP0EN
Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bit 6 ndash HCMP2EN High byte Compare 2 EnableSee LCMP0EN
Bit 5 ndash HCMP1EN High byte Compare 1 EnableSee LCMP0EN
Bit 4 ndash HCMP0EN High byte Compare 0 EnableSee LCMP0EN
Bit 2 ndash LCMP2EN Low byte Compare 2 EnableSee LCMP0EN
Bit 1 ndash LCMP1EN Low byte Compare 1 EnableSee LCMP0EN
Bit 0 ndash LCMP0EN Low byte Compare 0 EnableSetting the LCMPnENHCMPnEN bits in the FRQ or PWM Waveform Generation mode of operation willoverride the port output register for the corresponding WOn pin
ATtiny40616-bit TimerCounter Type A (TCA)
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2073 Control C - Split Mode
Name CTRLCOffset 0x02Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 HCMP2OV HCMP1OV HCMP0OV LCMP2OV LCMP1OV LCMP0OV
Access RW RW RW RW RW RW Reset 0 0 0 0 0 0
Bit 6 ndash HCMP2OV High byte Compare 2 Output ValueSee LCMP0OV
Bit 5 ndash HCMP1OV High byte Compare 1 Output ValueSee LCMP0OV
Bit 4 ndash HCMP0OV High byte Compare 0 Output ValueSee LCMP0OV
Bit 2 ndash LCMP2OV Low byte Compare 2 Output ValueSee LCMP0OV
Bit 1 ndash LCMP1OV Low byte Compare 1 Output ValueSee LCMP0OV
Bit 0 ndash LCMP0OV Low byte Compare 0 Output ValueThe LCMPnOVHCMPn bits allow direct access to the waveform generators output compare value whenthe timercounter is not enabled This is used to set or clear the WOn output value when the timercounteris not running
ATtiny40616-bit TimerCounter Type A (TCA)
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2074 Control D
Name CTRLDOffset 0x03Reset 0x00Property -
Bit 7 6 5 4 3 2 1 0 SPLITM
Access RW Reset 0
Bit 0 ndash SPLITM Enable Split ModeThis bit sets the timercounter in Split mode operation It will then work as two 8-bit timercounters Theregister map will change compared to normal 16-bit mode
ATtiny40616-bit TimerCounter Type A (TCA)
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2075 Control Register E Clear - Split Mode
Name CTRLECLROffset 0x04Reset 0x00Property -
The individual Status bit can be cleared by writing a 1 to its bit location This allows each bit to becleared without the use of a read-modify-write operation on a single register
Bit 7 6 5 4 3 2 1 0 CMD[10] CMDEN[10]
Access RW RW RW RW Reset 0 0 0 0
Bits 32 ndash CMD[10] CommandThese bits are used for software control of update restart and reset of the timercounter The commandbits are always read as zero
Value Name Description0x0 NONE No command0x1 - Reserved0x2 RESTART Force restart0x3 RESET Force hard Reset (ignored if TC is enabled)
Bits 10 ndash CMDEN[10] Command enableThese bits are used to indicate for which timercounter the command (CMD) is valid
Value Name Description0x0 NONE None0x1 LOW Command valid for low-byte TC0x2 HIGH Command valid for high-byte TC0x3 BOTH Command valid for both low-byte and high-byte TC
ATtiny40616-bit TimerCounter Type A (TCA)
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2076 Control Register E Set - Split Mode
Name CTRLESETOffset 0x05Reset 0x00Property -
The individual Status bit can be set by writing a 1 to its bit location This allows each bit to be set withoutthe use of a read-modify-write operation on a single register
Bit 7 6 5 4 3 2 1 0 CMD[10] CMDEN[10]
Access RW RW RW RW Reset 0 0 0 0
Bits 32 ndash CMD[10] CommandThese bits are used for software control of update restart and reset of the timercounter The commandbits are always read as zero The CMD bits must be used together with CMDEN Using the resetcommand requires that both low-byte and high-byte timercounter is selected
Value Name Description0x0 NONE No command0x1 - Reserved0x2 RESTART Force restart0x3 RESET Force hard Reset (ignored if TC is enabled)
Bits 10 ndash CMDEN[10] Command enableThese bits are used to indicate for which timercounter the command (CMD) is valid
Value Name Description0x0 NONE None0x1 LOW Command valid for low-byte TC0x2 HIGH Command valid for high-byte TC0x3 BOTH Command valid for both low-byte and high-byte TC
ATtiny40616-bit TimerCounter Type A (TCA)
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2077 Interrupt Control Register - Split Mode
Name INTCTRLOffset 0x0AReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 LCMP2 LCMP1 LCMP0 HUNF LUNF
Access RW RW RW RW RW Reset 0 0 0 0 0
Bit 6 ndash LCMP2 Low byte Compare Channel 0 Interrupt EnableSee LCMP0
Bit 5 ndash LCMP1 Low byte Compare Channel 1 Interrupt EnableSee LCMP0
Bit 4 ndash LCMP0 Low byte Compare Channel 0 Interrupt EnableWriting LCMPn bit to 1 enables low byte compare interrupt from channel n
Bit 1 ndash HUNF High byte Underflow Interrupt EnableWriting HUNF bit to 1 enables high byte underflow interrupt
Bit 0 ndash LUNF Low byte Underflow Interrupt EnableWriting HUNF bit to 1 enables low byte underflow interrupt
ATtiny40616-bit TimerCounter Type A (TCA)
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2078 Interrupt Flag Register - Split Mode
Name INTFLAGSOffset 0x0BReset 0x00Property -
The individual Status bit can be cleared by writing a lsquo1rsquo to its bit location This allows each bit to be setwithout the use of a read-modify-write operation on a single register
Bit 7 6 5 4 3 2 1 0 LCMP2 LCMP1 LCMP0 HUNF LUNF
Access RW RW RW RW RW Reset 0 0 0 0 0
Bit 6 ndash LCMP2 Low byte Compare Channel 0 Interrupt FlagSee LCMP0 flag description
Bit 5 ndash LCMP1 Low byte Compare Channel 0 Interrupt FlagSee LCMP0 flag description
Bit 4 ndash LCMP0 Low byte Compare Channel 0 Interrupt FlagThe Compare Interrupt flag (LCMPn) is set on a compare match on the corresponding compare channel
For all modes of operation the LCMPn flag will be set when a compare match occurs between the LowByte Count register (TCAnLCNT) and the corresponding compare register (TCAnLCMPn) The LCMPnflag will not be cleared automatically and has to be cleared by software This is done by writing a lsquo1rsquo to itsbit location
Bit 1 ndash HUNF High byte Underflow Interrupt FlagThis flag is set on a high byte timer BOTTOM (underflow) condition HUNF is not automatically clearedand needs to be cleared by software This is done by writing a lsquo1rsquo to its bit location
Bit 0 ndash LUNF Low byte Underflow Interrupt FlagThis flag is set on a low byte timer BOTTOM (underflow) condition LUNF is not automatically cleared andneeds to be cleared by software This is done by writing a lsquo1rsquo to its bit location
ATtiny40616-bit TimerCounter Type A (TCA)
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2079 Debug Control Register
Name DBGCTRLOffset 0x0EReset 0x00Property -
Bit 7 6 5 4 3 2 1 0 DBGRUN
Access RW Reset 0
Bit 0 ndash DBGRUN Run in Debug
Value Description0 The peripheral is halted in Break Debug mode and ignores events1 The peripheral will continue to run in Break Debug mode when the CPU is halted
ATtiny40616-bit TimerCounter Type A (TCA)
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20710 Low Byte Timer Counter Register - Split Mode
Name LCNTOffset 0x20Reset 0x00Property -
TCAnLCNT contains the counter value in low byte timer CPU and UPDI write access has priority overcount clear or reload of the counter
Bit 7 6 5 4 3 2 1 0 LCNT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash LCNT[70] Counter Value for Low Byte TimerThese bits define the counter value of the low byte timer
ATtiny40616-bit TimerCounter Type A (TCA)
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20711 High Byte Timer Counter Register - Split Mode
Name HCNTOffset 0x21Reset 0x00Property -
TCAnHCNT contains the counter value in high byte timer CPU and UPDI write access has priority overcount clear or reload of the counter
Bit 7 6 5 4 3 2 1 0 HCNT[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash HCNT[70] Counter Value for High Byte TimerThese bits define the counter value in high byte timer
ATtiny40616-bit TimerCounter Type A (TCA)
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20712 Low Byte Timer Period Register - Split Mode
Name LPEROffset 0x26Reset 0x00Property -
The TCAnLPER register contains the TOP value of low byte timer
Bit 7 6 5 4 3 2 1 0 LPER[70]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 70 ndash LPER[70] Period Value Low Byte TimerThese bits hold the TOP value of low byte timer
ATtiny40616-bit TimerCounter Type A (TCA)
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20713 High Byte Period Register - Split Mode
Name HPEROffset 0x27Reset 0x00Property -
The TCAnHPER register contains the TOP value of high byte timer
Bit 7 6 5 4 3 2 1 0 HPER[70]
Access RW RW RW RW RW RW RW RW Reset 1 1 1 1 1 1 1 1
Bits 70 ndash HPER[70] Period Value High Byte TimerThese bits hold the TOP value of high byte timer
ATtiny40616-bit TimerCounter Type A (TCA)
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20714 Compare Register n For Low Byte Timer - Split Mode
Name LCMPOffset 0x28 + n0x02 [n=02]Reset 0x00Property -
The TCAnLCMPn register represents the compare value of compare channel n for low byte Timer Thisregister is continuously compared to the counter value of the low byte timer TCAnLCNT Normally theoutputs from the comparators are then used for generating waveforms
Bit 7 6 5 4 3 2 1 0 LCMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash LCMP[70] Compare Value of Channel nThese bits hold the compare value of channel n that is compared to TCAnLCNT
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 235
20715 High Byte Compare Register n - Split Mode
Name HCMPOffset 0x29 + n0x02 [n=02]Reset 0x00Property -
The TCAnHCMPn register represents the compare value of compare channel n for high byte timer Thisregister is continuously compared to the counter value of the high byte timer TCAnHCNT Normally theoutputs from the comparators are then used for generating waveforms
Bit 7 6 5 4 3 2 1 0 HCMP[70]
Access RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0
Bits 70 ndash HCMP[70] Compare Value of Channel nThese bits hold the compare value of channel n that is compared to TCAnHCNT
ATtiny40616-bit TimerCounter Type A (TCA)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 236
21 16-bit TimerCounter Type B (TCB)
211 Featuresbull 16-Bit Counter Operation Modes
ndash Periodic interruptndash Time-out checkndash Input capture
bull On eventbull Frequency measurementbull Pulse-width measurementbull Frequency and pulse-width measurement
ndash Single shotndash 8-bit Pulse-Width Modulation (PWM)
bull Noise Canceler on Event Inputbull Optional Operation Synchronous with TCA0
212 OverviewThe capabilities of the 16-bit TimerCounter type B (TCB) include frequency and waveform generationand input capture on event with time and frequency measurement of digital signals The TCB consists ofa base counter and control logic which can be set in one of eight different modes each mode providingunique functionality The base counter is clocked by the peripheral clock with optional prescaling
ATtiny40616-bit TimerCounter Type B (TCB)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 237
2121 Block DiagramFigure 21-1 TimerCounter Type B Block Diagram
Counter
=
CNT
= 0
countclear Control
EVCTRL
CTRLA
IF(INT Req)
TOP
ClockSelect
BOTTOM
Edge Select CTRLB Mode
CCMP
Output controland
logicAsynchronous
Synchronousoutput
Asynchronousoutput
Mode Output enable initial value
CLK_PER
LogicEvent System
TCB
DIV2
CLK_TCA
21211 Noise CancelerThe noise canceler improves noise immunity by using a simple digital filter scheme When the noise filteris enabled the peripheral monitors the event channel and keeps a record of the last four observedsamples If four consecutive samples are equal the input is considered to be stable and the signal is fedto the edge detector
When enabled the noise canceler introduces an additional delay of four system clock cycles between achange applied to the input and the update of the input compare register
The noise canceler uses the system clock and is therefore not affected by the prescaler
2122 Signal Description
Signal Description Type
WO Digital Asynchronous Output Waveform Output
Related LinksIO Multiplexing and Considerations
2123 System DependenciesIn order to use this peripheral other parts of the system must be configured correctly as described below
ATtiny40616-bit TimerCounter Type B (TCB)
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Table 21-1 TCB System Dependencies
Dependency Applicable Peripheral
Clocks Yes CLKCTRL
IO Lines and Connections Yes WO
Interrupts Yes CPUINT
Events Yes EVSYS
Debug Yes UPDI
Related LinksClocksDebug OperationInterruptsEvents
21231 ClocksThis peripheral uses the systems peripheral clock CLK_PER The peripheral has its own local prescaleror can be configured to run off the prescaled clock signal of the Timer Counter type A (TCA)
Related LinksClock Controller (CLKCTRL)
21232 IO Lines and ConnectionsUsing the IO lines of the peripheral requires configuration of the IO pins
Related LinksIO Multiplexing and ConsiderationsIO Pin Configuration (PORT)
21233 InterruptsUsing the interrupts of this peripheral requires the interrupt controller to be configured first
Related LinksCPU Interrupt Controller (CPUINT)SREGInterrupts
21234 EventsThe events of this peripheral are connected to the Event System
Related LinksEvent System (EVSYS)
21235 Debug OperationWhen the CPU is halted in Debug mode this peripheral will halt normal operation This peripheral can beforced to continue operation during debugging
This peripheral can be forced to operate with halted CPU by writing a 1 to the Debug Run bit (DBGRUN)in the Debug Control register of the peripheral (peripheralDBGCTRL)
ATtiny40616-bit TimerCounter Type B (TCB)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 239
Related LinksUnified Program and Debug Interface (UPDI)
213 Functional Description
2131 DefinitionsThe following definitions are used throughout the documentation
Table 21-2 TimerCounter Definitions
Name Description
BOTTOM The counter reaches BOTTOM when it becomes zero
MAX The counter reaches MAXimum when it becomes all ones
TOP The counter reaches TOP when it becomes equal to the highest value in the countsequence
UPDATE The update condition is met when the timercounter reaches BOTTOM or TOP depending onthe Waveform Generator mode
CNT Counter register value
CCMP CaptureCompare register value
In general the term timer is used when the timercounter is counting periodic clock ticks The termcounter is used when the input signal has sporadic or irregular ticks
2132 InitializationBy default the TCB is in Periodic Interrupt mode Follow these steps to start using it
bull Write a TOP value to the CompareCapture register (TCBnCCMP)bull Enable the counter by writing a 1 to the ENABLE bit in the Control A register (TCBnCTRLA)
The counter will start counting clock ticks according to the prescaler setting in the Clock Select bitfield (CLKSEL in TCBnCTRLA)
bull The counter value can be read from the Count register (TCBnCNT) The peripheral will generatean interrupt when the CNT value reaches TOP
2133 Operation
21331 ModesThe timer can be configured to run in one of the eight different modes listed below The event pulseneeds to be longer than one system clock cycle in order to ensure edge detection
Periodic Interrupt ModeIn the Periodic Interrupt mode the counter counts to the capture value and restarts from zero Aninterrupt is generated when the counter is equal to TOP If TOP is updated to a value lower than countthe counter will continue until MAX and wrap-around without generating an interrupt
ATtiny40616-bit TimerCounter Type B (TCB)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 240
Figure 21-2 Periodic Interrupt Mode
BOTTOM
MAX
Interrupt
TOP
TOP changed to a value lower than CNT
CNT
Counter wraps around
Time-out Check ModeIn this mode the counter counts to MAX and wraps-around On the first edge the counter is restarted andon the second edge the counter is stopped If the count register (TCBnCNT) reaches TOP before thesecond edge an interrupt will be generated In Freeze state the counter will restart on a new edgeReading count (TCBnCNT) or comparecapture (TCBnCCMP) register or writing run bit (RUN inTCBnSTATUS) in Freeze state will have no effectFigure 21-3 Time-out Check Mode
CNT
BOTTOM
MAX
ldquo Interruptrdquo
TOP
TOP changed to a valuelower than CNT
Counter wrapsaround
Event Input
Edge detector
Input Capture on Event ModeThe counter will count from BOTTOM to MAX continuously When an event is detected the counter valuewill be transferred to the CompareCapture register (TCBnCCMP) and interrupt is generated The modulehas an edge detector that can be configured to trigger count capture on either rising or falling edges
The figure below shows the input capture unit configured to capture on falling edge on the event inputsignal The interrupt flag is automatically cleared after the high byte of the Capture register has beenread
ATtiny40616-bit TimerCounter Type B (TCB)
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Figure 21-4 Input Capture on Event
CNT
MAX
BOTTOM
Interrupt
W rap aroundCopy CN T to CCMP
and in terrup tCopy CN T to CCMP
and in terrup t
Event Input
Edge detector
It is recommended to write zero to the TCBnCNT register when entering this mode from any other mode
Input Capture Frequency Measurement ModeIn this mode the TCB captures the counter value and restarts on either a positive or negative edge of theevent input signal
The interrupt flag is automatically cleared after the high byte of the CompareCapture register(TCBnCCMP) has been read and an interrupt request is generated
The figure below illustrates this mode when configured to act on rising edge
Figure 21-5 Input Capture Frequency Measurement
CNT
MAX
BOTTOM
Interrupt
Copy CNT to CCMPinterrupt and restart
Copy CNT to CCMPinterrupt and restart
Copy CNT to CCMPinterrupt and restart
Event Input
Edge detector
ATtiny40616-bit TimerCounter Type B (TCB)
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Input Capture Pulse-Width Measurement ModeThe input capture pulse-width measurement will restart the counter on a positive edge and capture on thenext falling edge before an interrupt request is generated The interrupt flag is automatically cleared whenthe high byte of the capture register is read The timer will automatically switch between rising and fallingedge detection but a minimum edge separation of two clock cycles is required for correct behavior
Figure 21-6 Input Capture Pulse-Width Measurement
CNT
MAX
BOTTOM
Interrupt
Resta rtcounter
Copy CN T to CCMPand in terrup t
Resta rtcounter
Copy CN T to CCMPand g ive inte rrupt
Resta rtcounter
Event Input
Edge detector
Input Capture Frequency and Pulse-Width Measurement ModeIn this mode the timer will start counting when a positive edge is detected on the even input signal Onthe following falling edge the count value is captured The counter stops when the second rising edge ofthe event input signal is detected and this will set the interrupt flag
Reading the capture will clear the interrupt flag When the capture register is read or the interrupt flag iscleared the TC is ready for a new capture sequence The counter register should therefore be readbefore the capture register as this is reset to zero at the next positive edge
ATtiny40616-bit TimerCounter Type B (TCB)
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Figure 21-7 Input Capture Frequency and Pulse-Width Measurement
CNT
MAX
BOTTOM
Interrupt
Startcounter
Copy CNT toCCMP
Stop counter andinterrupt
CPU reads the
Ignore tillCapture is read
Trigger nextcapture sequence
Event Input
Edge detector
CCMP register
Single-Shot ModeThis mode can be used to generate a pulse with a duration that is defined by the Compare register(TCBnCCMP) every time a rising or falling edge is observed on a connected event channel
When the counter is stopped the output pin is driven to low If an event is detected on the connectedevent channel the timer will reset and start counting from zero to TOP while driving its output high TheRUN bit in the STATUS register can be read to see if the counter is counting or not When the counterregister reaches the CCMP register value the counter will stop and the output pin will go low for at leastone prescaler cycle If a new event arrives during this time that event will be ignored The following figureshows an example waveform There is a two clock cycle delay from when the event is received until theoutput is set high If the ASYNC bit in TCBnCTRLB is written to 1 an asynchronous edge detector isused for input events to give immediate action When the EDGE bit of the TCBnEVCTRL register iswritten to 1 any edge can trigger the start of the counter If the EDGE bit is 0 only positive edges willtrigger the start
The counter will start as soon as the module is enabled even without triggering event This is preventedby writing TOP to the counter register
Similar behavior is seen if the EDGE bit in the TCBnEVCTRL register is 1 while the module is enabledWriting TOP to the Counter register prevents this as well
It is not recommended to change configuration while the module is enabled
ATtiny40616-bit TimerCounter Type B (TCB)
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Figure 21-8 Single-Shot Mode
CNT
TOP
BOTTOMInterrupt
Event startscounter
Counter reachesTOP value
Output
Ignored Ignored
Event startscounter
Counter reachesTOP value
Edge detector
If the ASYNC bit in TCBnCTRLB is 0 the event pulse needs to be longer than one system clock cycle inorder to ensure edge detection
8-Bit PWM ModeThis timer can be configured to run in 8-bit PWM mode where each of the register pairs in the 16-bitCompareCapture register (TCBnCCMPH and TCBnCCMPL) are used as individual compare registersThe counter will continuously count from zero to CCMPL and the output will be set at BOTTOM andcleared when the counter reaches CCMPH
When this peripheral is enabled and in PWM mode changing the value of the CompareCapture registerwill change the output but the transition may output invalid values It is hence recommended to
1 Disable the peripheral2 Write CompareCapture register to CCMPH CCMPL3 Write 0x0000 to count register4 Re-enable the module
CCMPH is the number of cycles for which the output will be driven high CCMPL+1 is the period of theoutput pulse
Output of the module for different capture register values are explained below
bull CCMPL = 0 Output = 0bull CCMPL = 0xFF
bull CCMPH = 0 Output = 0bull 0 lt CCMPH le 0xFF Output = 1 for CCMPH cycles low for the rest of the period
bull For 0 lt CCMPL lt 0xFFbull CCMPH = 0 Output = 0bull If 0 lt CCMPH le CCMPL Output = 1 for CCMPH cycles low for the rest of the periodbull CCMPH = CCMPL + 1 Output = 1
ATtiny40616-bit TimerCounter Type B (TCB)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 245
Figure 21-9 8-Bit PWM Mode
CNT
CCMPL
BOTTOM
Interrupt
(CNT == CCMPL) andoutput goes high
(CNT == CCMPH) andoutput goes low
Output
CCMPH
21332 OutputIf ASYNC in TCBnCTRLB is written to 0 (1) the output pin is driven synchronously (asynchronously) tothe TCB clock The bits CCMPINIT CCMPEN and CNTMODE in TCBnCTRLB control how thesynchronous output is driven The different configurations and their impact on the output are listed in thetable below
Table 21-3 Synchronous Output
CNTMODE Output CTRLB=rsquo0rsquoCCMPEN=1
Output CTRLB=rsquo1rsquoCCMPEN=1
Single-Shot mode Output high when the counterstarts and output low whencounter stops
Output high when event arrivesand output low when the counterstops
8-bit PWM mode PWM mode output PWM mode output
Modes except single shot andPWM
Bit CCMPINIT in TCBnCTRLB Bit CCMPINIT in TCBnCTRLB
21333 Noise CancelerThe noise canceler improves noise immunity by using a simple digital filter scheme When the noise filteris enabled the peripheral monitors the event channel and keeps a record of the last four observedsamples If four consecutive samples are equal the input is considered to be stable and the signal is fedto the edge detector
When enabled the noise canceler introduces an additional delay of four system clock cycles between achange applied to the input and the update of the input compare register
The noise canceler uses the system clock and is therefore not affected by the prescaler
21334 Synchronized with TCAnTCB can be configured to use the clock (CLK_TCA) of the TimerCounter type A (TCAn) by writing to theClock Select bit field (CLKSEL) in the Control A register (TCBnCTRLA) In this setting the TCB will counton the exect same clocks sources as selected in TCA
ATtiny40616-bit TimerCounter Type B (TCB)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 246
When the Synchronize Update bit (SYNCUPD) in the Control A register (TCBnCTRLA) is written to 1the TCB counter will restart when the TCA counter restarts
Related LinksBlock Diagram
2134 EventsThe TCB is an event generator Any condition that causes the CAPT flag in TCBnINTFLAGS to be setwill also generate a one-cycle strobe on the event channel output
The peripheral accepts one event input If the Capture Event Input Enable bit (CAPTEI) in the EventControl register (TCBnEVCTRL) is written to 1 incoming events will result in an event action as definedby the Event Edge bit (EDGE) in TCBnEVCTRL The Single-Shot mode event is edge triggered and willcapture changes on the event input shorter than one system clock cycle In all other modes the eventline must be held for at least one system clock cycle to ensure detection of an incoming event
Related LinksEVCTRLEvent System (EVSYS)
2135 InterruptsTable 21-4 Available Interrupt Vectors and Sources
Offset Name Vector Description Conditions
0x00 CAPT TCB interrupt Depending on operating mode See description of CAPT inTCBINTFLAG
When an interrupt condition occurs the corresponding interrupt flag is set in the Interrupt Flags register ofthe peripheral (peripheralINTFLAGS)
An interrupt source is enabled or disabled by writing to the corresponding enable bit in the peripheralsInterrupt Control register (peripheralINTCTRL)
An interrupt request is generated when the corresponding interrupt source is enabled and the interruptflag is set The interrupt request remains active until the interrupt flag is cleared See the peripheralsINTFLAGS register for details on how to clear interrupt flags
Related LinksCPU Interrupt Controller (CPUINT)INTFLAGS
2136 Sleep Mode OperationTCB will halt operation in the Power-Down Sleep mode Standby sleep operation is dependent on theRun in Standby bit (RUNSTDBY) in the Control A register (TCBCTRLA)
2137 SynchronizationNot applicable
2138 Configuration Change ProtectionNot applicable
ATtiny40616-bit TimerCounter Type B (TCB)
copy 2018 Microchip Technology Inc Datasheet Preliminary 40001976A-page 247