attiny23131 a seminar on avr microcontroller attiny2313

ATtiny2313ATtiny2313 11

A SEMINAR A SEMINAR ONON

AVR MICROCONTROLLERAVR MICROCONTROLLERATtiny2313ATtiny2313


OverviewOverview• FeaturesFeatures• Peripheral Features

• Special Microcontroller FeaturesSpecial Microcontroller Features• AVR CPU COREAVR CPU CORE• AVR ATtiny2313 MemoriesAVR ATtiny2313 Memories • System clockSystem clock• RegistersRegisters

• USARTUSART

• Universal Serial Interface – USIUniversal Serial Interface – USI


FeaturesFeatures

• Utilizes the AVR® RISC ArchitectureUtilizes the AVR® RISC Architecture

• AVR – High-performance and Low-AVR – High-performance and Low-power RISC Architecturepower RISC Architecture

• 120 Powerful Instructions – Most 120 Powerful Instructions – Most Single Clock Cycle ExecutionSingle Clock Cycle Execution

• 32 General Purpose Working 32 General Purpose Working RegistersRegisters

• Fully Static OperationFully Static Operation


AVR PeripheralsAVR Peripherals• USARTUSART

– Serial communication with the PCSerial communication with the PC• SPI – Serial Peripheral InterfaceSPI – Serial Peripheral Interface

– Synchronous serial communicationSynchronous serial communication• ADCADC

– Analog – Digital ConverterAnalog – Digital Converter• I/O PortsI/O Ports

– General Purpose Input Output pins General Purpose Input Output pins (GPIO)(GPIO)


• • Special Microcontroller Special Microcontroller FeaturesFeatures

• debug WIRE On-chip Debuggingdebug WIRE On-chip Debugging

• In-System Programmable via SPI In-System Programmable via SPI PortPort

• External and Internal Interrupt External and Internal Interrupt SourcesSources

• Low-power Idle, Power-down, and Low-power Idle, Power-down, and

Standby Modes Standby Modes • Enhanced Power- Enhanced Power-on Reset Circuiton Reset Circuit• Internal Calibrated OscillatorInternal Calibrated Oscillator


AVR Power ManagementAVR Power Management• Low Power operation – 15 mW @ 4 MHzLow Power operation – 15 mW @ 4 MHz• Multiple Sleep ModesMultiple Sleep Modes

– Sleep Modes: Shutdown unused componentsSleep Modes: Shutdown unused components– Idle Mode – 6 mWIdle Mode – 6 mW

•CPU OFF, all peripherals ONCPU OFF, all peripherals ON•CPU “woken up” by interruptsCPU “woken up” by interrupts

– Power Down Mode – 75 mWPower Down Mode – 75 mW•CPU and most peripherals OFFCPU and most peripherals OFF•External Interrupts, 2 Wire Interface, External Interrupts, 2 Wire Interface, Watchdog ONWatchdog ON

– Power Save Mode – 120 mWPower Save Mode – 120 mW•Similar to Power DownSimilar to Power Down•Timer0 continues to run “asynchronously”Timer0 continues to run “asynchronously”


•I/O and PackagesI/O and Packages– 18 Programmable I/O Lines– 18 Programmable I/O Lines– 20-pin PDIP, 20-pin SOIC, 20-pad – 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLFQFN/MLF

• • Operating Operating VoltagesVoltages– 1.8 - 5.5V (ATtiny2313V)– 1.8 - 5.5V (ATtiny2313V)– 2.7 - 5.5V (ATtiny2313– 2.7 - 5.5V (ATtiny2313 ))

••Power-down ModePower-down Mode< 0.1 μA at 1.8V< 0.1 μA at 1.8V


Pin ConfigurationPin Configuration


AVR CPU COREAVR CPU CORE

The main function of the CPU core is to The main function of the CPU core is to ensure correct ensure correct

program execution. The CPU must program execution. The CPU must therefore be able totherefore be able to

access memories, perform access memories, perform calculations, controlcalculations, control

peripherals, and handle interrupts.peripherals, and handle interrupts.


CPU CORECPU CORE

• FunctionsFunctions– Application ExecutionApplication Execution– Resource Resource

ManagementManagement– Peripheral Peripheral

InteractionInteraction

• RISC ArchitectureRISC Architecture– 8 bit ALU/data-path8 bit ALU/data-path– 128 Kb FLASH - 128 Kb FLASH - CodeCode– 4 Kb SRAM - 4 Kb SRAM - DataData– Multiple peripheralsMultiple peripherals


•AVR STATUS REGISTERAVR STATUS REGISTER


GENERAL PURPOSE GENERAL PURPOSE REGISTERSREGISTERS


System ClockSystem Clock

All the clocks need not be active at a given All the clocks need not be active at a given time. In order totime. In order to

reduce the power consumption, the clocks reduce the power consumption, the clocks can be halted bycan be halted by

using different modes.using different modes.

• CPU CLOCKCPU CLOCK

• I/O CLOCKI/O CLOCK

• FLASH CLOCKFLASH CLOCK


CLOCK SOURCESCLOCK SOURCES

• EXTERNAL CLOCKEXTERNAL CLOCK

• CALIBRATED INTERNAL RC CALIBRATED INTERNAL RC OSCILLATOR 4MhzOSCILLATOR 4Mhz

• CALIBRATED INTERNAL RC CALIBRATED INTERNAL RC OSCILLATOR 8MhzOSCILLATOR 8Mhz

• WATCHDOG OSCILLATORWATCHDOG OSCILLATOR

• CRYSTAL /CEREMIC OSCILLATORCRYSTAL /CEREMIC OSCILLATOR


INTERRUPTSINTERRUPTS

• SOFTWARE INTERRUPTSSOFTWARE INTERRUPTS

• EXTERNAL INTERRUPTSEXTERNAL INTERRUPTS

External interrupt contain registers:External interrupt contain registers:

• MCU CONTROL REGISTERMCU CONTROL REGISTER

• GERERAL INTERRUPT MASK REGISTER GERERAL INTERRUPT MASK REGISTER ( GIMSK)( GIMSK)

• EXTERNAL INTERRUPT FLAG REGISTER EXTERNAL INTERRUPT FLAG REGISTER ( EIFR)( EIFR)

• PIN CHANGE MASK REGISTER (PCMSK)PIN CHANGE MASK REGISTER (PCMSK)


Alternate Port Alternate Port FunctionsFunctions • Most port pins have alternate Most port pins have alternate

functions in addition to being general functions in addition to being general digital I/Os. The overriding signals digital I/Os. The overriding signals may not be present in all portmay not be present in all port pins . pins . The overriding signals are generated The overriding signals are generated internally in the modules having the internally in the modules having the alternate function.alternate function.

• PORT APORT A

• PORT BPORT B

• PORT CPORT C


8-BIT TIMER/COUNTER 8-BIT TIMER/COUNTER

Timer/counter is a general pupose 8-bit module Timer/counter is a general pupose 8-bit module with two with two

independent output compare units. It allows independent output compare units. It allows program executionprogram execution

timing.timing.

• Two independent output compare units.Two independent output compare units.

• Clear timer on compare match.Clear timer on compare match.

• Frequency generatorFrequency generator

• Interrupt sourcesInterrupt sources


USART USART The Universal Synchronous and The Universal Synchronous and Asynchronous serial Receiver and Asynchronous serial Receiver and TransmitterTransmitterhighly flexible serial communication highly flexible serial communication device. :device. :• • Full Duplex Operation (Independent Full Duplex Operation (Independent Serial Receive and Transmit Registers)Serial Receive and Transmit Registers)• • Asynchronous or Synchronous Asynchronous or Synchronous OperationOperation• • Master or Slave Clocked Synchronous Master or Slave Clocked Synchronous OperationOperation• • High Resolution Baud Rate GeneratorHigh Resolution Baud Rate Generator• • Odd or Even Parity Generation and Odd or Even Parity Generation and Parity Check Supported by HardwareParity Check Supported by Hardware• • Noise Filtering Includes False Start Noise Filtering Includes False Start Bit Detection and Digital Low Pass Bit Detection and Digital Low Pass FilterFilter• • Three Separate Interrupts on TX Three Separate Interrupts on TX Complete, TX Data Register Empty and Complete, TX Data Register Empty and RX CompleteRX Complete• • Multi-processor Communication ModeMulti-processor Communication Mode


AVR USART vs. AVR UART –AVR USART vs. AVR UART –CompatibilityCompatibility

• The USART is fully compatible with the The USART is fully compatible with the AVR UART regarding:AVR UART regarding:

• • • Bit locations inside all USART Registers.Bit locations inside all USART Registers.• • • Baud Rate Generation.Baud Rate Generation.• • • Transmitter Operation.Transmitter Operation.• • • Transmit Buffer Functionality.Transmit Buffer Functionality.• • • Receiver OperationReceiver Operation


Universal Serial InterfaceUniversal Serial InterfaceThe Universal Serial Interface, or USI, provides The Universal Serial Interface, or USI, provides

the basic the basic

hardware resources needed for serial hardware resources needed for serial communication.communication.

Combined with a minimum of control software, Combined with a minimum of control software, the USIthe USI

allows significantly higher transfer rates and allows significantly higher transfer rates and uses less codeuses less code

space than solutions based on software only. space than solutions based on software only. Interrupts areInterrupts are

included to minimize the processor load included to minimize the processor load


THANK YOUTHANK YOU

attiny23131 a seminar on avr microcontroller attiny2313

Documents

attiny2313 power

power consumption

power downtimer0

port pins

lowpower risc architecture

independent output

asynchronous serial

spi port external