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AT91EB42 Evaluation Board..............................................................................................

User Guide

AT91EB42 Evaluation Board User

Table of Contents

Section 1Overview............................................................................................... 1-1

1.1 Scope........................................................................................................1-11.2 Deliverables ..............................................................................................1-11.3 The AT91EB42 Evaluation Board .............................................................1-1

Section 2Setting Up the AT91EB42 Evaluation Board ................................................................ 2-1

2.1 Electrostatic Warning ................................................................................2-12.2 Requirements............................................................................................2-12.3 Layout .......................................................................................................2-12.4 Jumper Settings ........................................................................................2-22.5 Powering Up the Board .............................................................................2-22.6 Measuring Current Consumption on the AT91M42800A ..........................2-22.7 Testing the AT91EB42 Evaluation Board..................................................2-3

Section 3The On-board Software ........................................................................ 3-1

3.1 AT91EB42 Evaluation Board ....................................................................3-13.2 Boot Software Program.............................................................................3-13.3 Programmed Default Memory Mapping ....................................................3-23.4 Flash Uploader..........................................................................................3-23.5 Power-down Demonstration......................................................................3-33.6 Angel Debug Monitor ................................................................................3-33.7 Programmed Default Speed......................................................................3-3

Section 4Circuit Description................................................................................. 4-1

4.1 AT91M42800A Processor .........................................................................4-14.2 Expansion Connectors and JTAG Interface..............................................4-1

4.2.1 I/O Expansion Connector ...................................................................4-1

4.2.2 EBI Expansion Connector ..................................................................4-1

4.2.3 JTAG Interface ...................................................................................4-1

4.3 Memories ..................................................................................................4-24.4 Analog-to-digital Converter .......................................................................4-24.5 Power and Crystal Quartz .........................................................................4-24.6 Push-buttons, LEDs, Reset and Serial Interfaces.....................................4-34.7 Layout Drawing .........................................................................................4-3

Guide i

1708C–ATARM–12-May-05

Table of Contents

ii


Section 5Appendix A – Configuration Straps....................................................... 5-1

5.1 Functional Pin Assignment .......................................................................5-15.2 Configuration Straps (CB1 - 23, JP1 - 8) ..................................................5-25.3 Power Consumption Measurement Strap (JP5) .......................................5-75.4 Ground Links (JP6) ...................................................................................5-75.5 Increasing Memory Size ...........................................................................5-7

Section 6Appendix B – Schematics..................................................................... 6-1

6.1 Schematics ...............................................................................................6-1

Section 7Appendix C – Bill of Materials............................................................... 7-1

Section 8Appendix D – Flash Memory Mapping .................................................................................. 8-1

AT91EB42 Evaluation Board User Guide

Section 1

Overview

1.1 Scope The AT91EB42 Evaluation Board enables real-time code development and evaluation.It supports the AT91M42800A.

This user guide focuses on the AT91EB42 Evaluation Board as an evaluation and dem-onstration platform.

! Section 1 provides an overview.

! Section 2 describes how to set up the evaluation board.

! Section 3 details the on-board software.

! Section 4 contains a description of the circuit board.

! Section 5 and Section 6 are two appendixes covering configuration straps and schematics, including pin connectors.

1.2 Deliverables The evaluation board is delivered with a DB9 plug-to-DB9 socket straight-through serialcable to connect the target evaluation board to a PC. A bare power lead with a 2.1 mmjack on one end for connection to a bench power supply is also delivered.

The evaluation board is also delivered with a CD-ROM that contains an evaluation ver-sion of the software development toolkit, the documentation that outlines the AT91microcontroller family and the AT91 C Library.

The evaluation board is capable of supporting different kinds of debugging systems,using an ICE interface or the on-board Angel™ Debug Monitor.

1.3 The AT91EB42 Evaluation Board

The board consists of an AT91M42800A together with several peripherals:

! Two serial ports

! Reset push-button

! An indicator that memorizes a reset event

! Four user-defined push-buttons

! Eight LEDs

! A 256K bytes 16-bit SRAM (upgradeable to 1M byte)

AT91EB42 Evaluation Board User Guide 1-1

Rev. 1708C–ATARM–12-May-05

Overview

! A 2M bytes 16-bit Flash (of which 1M byte is available for user software)

! A 4M bytes Serial DataFlash

! An analog-to-digital converter with SPI access

! 2 x 32-pin EBI expansion connectors

! 2 x 32-pin I/O expansion connectors

! 20-pin JTAG interface connector

If required, user-defined peripherals can also be added to the board. See Section 5 fordetails.

Figure 1-1. AT91EB42 Evaluation Board Block Diagram

JTAGICE

Connector

ARM7TDMIProcessor

8K BytesRAM

EBIEBI

Expansion Connector

AMBABridge

Push-buttonsInterrupt

Controller

Watchdog

PIO

Timer Counters

AT91M42800A

ASB

APB

ResetController

ResetController

LEDs

SRAM

Flash

SPI

SerialPorts

I/OExpansionConnector

SerialDataFlash

RS232Transceivers

DB9 SerialConnectors

Reset

32.768 kHzCrystal

ClockGenerator

PIO

SystemTimer

2.1 mm DCPowerSocket

Fast-chargeController

BatteryConnector

Power Supply

10-bit ADC4 Channels

1-2 AT91EB42 Evaluation Board User Guide


Section 2

Setting Up theAT91EB42 Evaluation Board

2.1 Electrostatic Warning

The AT91EB42 Evaluation Board is shipped in protective anti-static packaging. Theboard must not be subjected to high electrostatic potentials. A grounding strap or similarprotective device should be worn when handling the board. Avoid touching the compo-nent pins or any other metallic element.

2.2 Requirements In order to set up the AT91EB42 Evaluation Board, the following requirements areneeded:

! The AT91EB42 Evaluation Board itself

! The DC power supply capable of supplying 7V to 12V at 1A (not supplied)

2.3 Layout Figure 2-1 shows the layout of the AT91EB42 Evaluation Board.

Figure 2-1. Layout of the AT91EB42 Evaluation Board



Setting Up the AT91EB42 Evaluation Board

2.4 Jumper Settings JP1 is used to boot standard or user programs. For standard operations, set it in theSTD position.

JP8 is used to select the core power supply of the AT91M42800A. Operations at 2V arenot supported on the current silicon.

For more information about jumpers and other straps, see Section 5.

2.5 Powering Up the Board

DC power is supplied to the board via the 2.1 mm socket (J1) shown in Figure 2-2. Thepolarity of the power supply is not critical. The minimum voltage required is 7V.

A battery is supplied on the AT91EB42. It supplies all on-board devices in the same waythat the external DC power operates. A battery fast-charge controller is provided on-board with a fast-charge indicator (D28), as shown in Figure 2-1.

Figure 2-2. 2.1 mm Socket

The board has a voltage regulator providing +3.3V. The regulator allows the input volt-age to range from 7V to 12V. When you switch the power on, the red LED markedPOWER lights up. If it does not, switch off and check the power supply connections.

2.6 Measuring Current Consumption on the AT91M42800A

The board is designed to generate the power for the AT91 product, and only the AT91product, through the jumpers JP5 (VDDIO) and JP8 (VDDCORE). This feature enables mea-surements of the consumption of the AT91 product to be made.

See Section 5 for further details.

positive (+)ornegative (-)

2.1 mm Connector




2.7 Testing the AT91EB42 Evaluation Board

To test the AT91EB42 Evaluation Board, perform the following procedure:

1. Hold down the SW1 button and power-up the board, or generate a reset and wait for the light sequence on each LED to complete. All the LEDs light.

2. Release the SW1 button. The LEDs D1 to D8 light up in sequential order. If all the LEDs light up twice, this indicates an error.

The LEDs represent the following test functions:

! D1 for the internal SRAM

! D2 for the external SRAM

! D3 for the external Flash

! D4 reserved

! D5 for the SPI DataFlash®

! D6 reserved

! D7 for the USART

! D8 for ADC with SPI access

During a complete test cycle, each LED flashes once to inform the user that the corre-sponding function has been successfully tested. If an error is detected, all the LEDs willlight up twice. After a complete test cycle, the embedded self-test software called Func-tional Test Software (FTS) restarts a new cycle.



Section 3

The On-board Software

3.1 AT91EB42 Evaluation Board

The AT91EB42 Evaluation Board embeds an AT49BV162A Flash memory device pro-grammed with default software. Only the lowest 8 x 8 KB sectors are used. Theremaining sectors are user definable, and can be programmed using one of the Flashdownloader “Flash_16x4” solutions offered in the AT91 Library.

When delivered, the Flash memory device contains:

! the Boot Software Program

! the Functional Test Software (FTS)

! the Flash Uploader

! the power-down function

! the Angel Debug Monitor

! a default user boot with a default application (LED Swing Application)

The Boot Software Program and Functional Test Software (FTS) are in sectors 0 and 1of the Flash. These sectors are not locked in order to provide an easy on-boardupgrade. The user must avoid overwriting these sectors.

3.2 Boot Software Program

The Boot Software Program configures the AT91M42800A, and thus controls the mem-ory and other board components.

The Boot Software Program is started at reset if JP1 is in the STD position. If JP1 is inthe USER position, the AT91M42800A boots from address 0x01100000 in the Flash,which must have a user-defined boot.

The Boot Software Program first initializes the master clock frequency at 32.768 MHz.The EBI then executes the REMAP procedure and checks the state of the buttons asdescribed below.

! When the SW1 button is pressed:

– All the LEDs light up together.

– The D1 LED remains lit when SW1 is released.

– The Functional Test Software (FTS) is started.





– Reserved




– The Flash uploader is activated.




– The power-down function is activated.

! When no buttons are pressed:

– Branch at address 0x01006000.

– The Angel Debug Monitor starts from this address by recopying itself inexternal SRAM.

3.3 Programmed Default Memory Mapping

Table 3-1 defines the mapping defined by the boot program.

The Boot Software Program, Functional Test Software (FTS), Flash Uploader and thepower-down demonstration are in sectors 0 and 1 of the Flash device. Sectors 3 to 8support the Angel Debug Monitor.

Sector 24 at address 0x0110 0000 can be programmed with a user application to bedebugged. This sector is mapped at address 0x0100 0000 (or 0x0 after a reset) whenthe jumper JP1 is in the USER position.

3.4 Flash Uploader The Flash Uploader included in the EB42 Boot Software is the same Flash Uploaderfactory-programmed in the Flash-based AT91 devices, the AT91FR4042 and theAT91FR40162/S. The Flash Uploader allows programming to Sector 24 of Flashthrough a serial port. Either of the on-chip USARTs can be used by the Flash Uploader.

To boot from the application downloaded in Sector 24, the downloading address mustbe 0x01100000. The boot starts the Flash Uploader if the SW3 button is pressed atreset.

The procedure is as follows:

1. Connect the Serial A or B port of the AT91EB42 Evaluation Board to a host PC Serial port using the straight serial cable provided.

2. Start the AT91Loader.exe program available in the AT91 Library on the host com-puter. The AT91 Loader must be configured beforehand. See the “Readme.pdf” file in folder <CDROM>\ToolBox\host_tools\Dev PC windev\AT91Loader\Doc.

Table 3-1. Memory Map

Part Name Start Address End Address Size Device

U1 0x01000000 0x011FFFFF 2M Bytes Flash AT49BV162A

U2 - U3 0x02000000 0x0203FFFF 256K Bytes SRAM




3. Check JP1 is in STD position. Power-on or press RESET, holding down the SW3 button simultaneously. Wait for all LEDs to light up together and then release SW3. LED3 remains lit. If the AT91Loader is configured in automatic mode, the download starts. Wait for the download to end.

4. Put JP1 in USER position and press RESET button. The application downloaded starts.

For further details, see the application note “Crystal Oscillator and PLL Considerationsfor AT91M42800A and AT91M55800A”, literature number 1740A. A PLL Filter Calcula-tor Tool is also available. See “Automatic_calculation_xls.zip”.

3.5 Power-down Demonstration

The AT91EB42 Evaluation Board is delivered with a battery unit to supply the boardwhen the main power supply is removed. The aim of the power-down demonstration isto save the battery unit. When the power-down function is started, the main clock of theAT91M42800A is switched to the slow clock oscillator at 32.768 kHz. The processor isput in IDLE mode and all peripheral clocks are turned off. The power-down mode is indi-cated by LED4 flashing every 10 seconds. The boot starts the power-downdemonstration if the SW4 button is pressed at reset.

The procedure is as follows:

1. Power-on or press RESET, holding down the SW4 button simultaneously.

2. Wait for all LEDs to light up and then release SW4. LED4 remains lit for 3 seconds and light off. Then LED4 flashes every 10 seconds.

3. Press SW4 or the reset button to re-start the board. When SW4 is pressed, the power-down demonstration re-configures the AT91M42800A to run at 32.768 MHz and branches to Angel.

3.6 Angel Debug Monitor

The Angel Debug Monitor is located in the Flash from 0x01006000 up to 0x01011FFF.The boot program starts it if no button is pressed at reset.

When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used byAngel is from 0x02020000 to 0x0203FFFF, i.e., the highest half part of the SRAM.

The Angel on the AT91EB42 Evaluation Board can be upgraded regardless of the ver-sion programmed on it.

Note that if the debugger is started through ICE while the Angel monitor is on, theAdvanced Interrupt Controller (AIC) and the USART channel are enabled.

3.7 Programmed Default Speed

As the speed of the AT91M42800A is programmable, the Boot Software Program initial-izes the device to run as fast as possible, i.e., at 32.768 MHz. The Boot SoftwareProgram and the Functional Test Software are run at this speed. When Angel is started,it also runs at 32.786 MHz and the user should not modify this frequency without repro-gramming the speed of the USARTs.



Section 4

Circuit Description

4.1 AT91M42800A Processor

Figure 6-1 on page 6-2 shows the AT91M42800A. The footprint is for a 144-pin TQFPpackage.

Strap CB20 enables the user to choose between the standard ICE debug mode and theJTAG boundary scan mode of operation.

The operating mode is defined by the state of the JTAGSEL input detected at reset.

Jumper JP5 (see Figure 6-8 on page 6-9 in Section 6, “Appendix B – Schematics”) canbe removed by the user to allow measurement of the consumption of the whole micro-controller (VDDIO and VDDCORE). Jumper JP8 can be removed to measure the coremicrocontroller consumption (VDDCORE).

4.2 Expansion Connectors and JTAG Interface

The two expansion connectors, I/O expansion connector and EBI expansion connector,and the JTAG interface are described below.

The I/O and EBI expansion connectors’ pinout and position are compatible with otherAT91 evaluation boards (except the I/O expansion connector pinout and position of theEB40) so that users can connect their prototype daughter boards to any of these evalu-ation boards.

4.2.1 I/O Expansion Connector

The I/O expansion connector makes the general-purpose I/O (GPIO) lines, VCC3V3and Ground, available to the user. Configuration straps CB2, CB3, CB4, CB11, CB13,CB14, CB15, CB17, CB18 and CB19 are used to select between the I/O lines beingused by the evaluation board or by the user via the I/O expansion connector.

4.2.2 EBI Expansion Connector

The schematic (see Figure 6-4 on page 6-5 in Section 6, “Appendix B – Schematics”)also shows the bus expansion connector. The 32 x 2 connector allows the user toaccess the data bus, all control bus signals and oscillator output. VCC3V3 and groundare also available on this connector.

Configuration strap CB1, when open, allows the user to connect the EBI expansion con-nector to the MPI expansion connector of an AT91EB63 evaluation board without anyconflict.

4.2.3 JTAG Interface An ARM®-standard 20-pin box header (P5) is provided to enable connection of an ICEinterface to the JTAG inputs on the AT91. This allows code to be developed on theboard without using system resources such as memory and serial ports.



Circuit Description

4.3 Memories The schematic (see Figure 6-3 on page 6-4 in Section 6, “Appendix B – Schematics”)shows one AT49BV162A 2M bytes 16-bit Flash, one AT45DB321 4M bytes serialDataFlash, one AT24C512 64K bytes EEPROM, one AT25256 32K Bytes EEPROMand two 128K/512K x 8 SRAM devices. Note: The AT24C512 64K byte EEPROM and the AT25256 32K byte EEPROM are

not mounted.

4.4 Analog-to-digital Converter

An on-board 4-channel, 10-bit ADC device (TLV1504 by Texas Instruments) is featuredon the AT91EB42. This device is interfaced to the AT91M42800A via the SPIA periph-eral and embeds its voltage reference equal to 2V. Four channels are used on theAT91EB42 for the following measurements:

! Channel 0 is used to measure the temperature near the 32.768 kHz crystal.

! Channel 1 is dedicated to supervise the External Power Supply.

! Channel 2 is dedicated to supervise the Battery Power Supply.

! Channel 3 is dedicated to supervise the VDDCORE.

Each ADC channel is fitted on the I/O extension connector and can be used in otherapplications. For this reason, each ADC input can be taken away from its function by itsappropriate jumper.

4.5 Power and Crystal Quartz

The AT91M42800A master clock is derived from a 32.768 kHz crystal. The on-chip low-power oscillator together with two PLL-based frequency multipliers and the prescalerresults in a programmable master clock between 500 Hz and 33 MHz. A temperaturesensor has been placed near the 32.768 kHz crystal and the analog signal output hasbeen fitted to Channel 0 of the on-board ADC.

Two sets of components for the PLL filters are fitted by default on the board (see Figure6-6 on page 6-7 in Section 6, “Appendix B – Schematics”). They are calculated to pro-vide a 16.77 MHz (PLLA: multiplier factor of 512 and settling time of 600 µs) or a 32.768MHz (PLLB: multiplier factor of 1000 and settling time of 6 ms) master clock frequency.

For further details, see the application note “Crystal Oscillator and PLL Considerationsfor AT91M42800A and AT91M55800A”, literature number 1740A. A PLL Filter Calcula-tor Tool is also available. See “Automatic_calculation_xls.zip”.

The voltage regulator provides 3.3V to the board and will light the red POWER LED(D11) when operating.

Power can be applied via the 2.1 mm connector to the regulator in either polaritybecause of the diode-rectifying circuit. Another regulator allows the user to power theAT91M42800A core with 3.3V or 1.8V by means of the JP8 jumper.

All functions can be supplied by the on-board battery. A connector permits the user todisconnect the battery. The type of battery and connection to be used are shown in Sec-tion 6 of this user guide. This type of battery will ensure the power supply of the boardfor approximately one hour. A battery fast-charge controller is provided on-board tocharge it and maintains the full charge. The user is warned while the fast-charge isstarted via the on-board indicator (D28) or a logical signal on I/O port PB18.



Circuit Description

4.6 Push-buttons, LEDs, Reset and Serial Interfaces

The IRQ0, TIOA0, PB6 and PB21 switches are debounced and buffered.

A supervisory circuit has been included in the design to detect and consequently resetthe board when the 3.3V supply voltage drops below 3.0V. Note that this voltage can bechanged depending on the board production series. The supervisory circuit also pro-vides a debounced reset signal. This device can also generate the reset signal in caseof watchdog timeout as the pin NWDOVF of the AT91M42800A is connected to its inputMR.

The assertion of this reset signal will light up the red RESET LED (D10). By pressing theCLEAR RESET push-button (S1), the LED can be turned off.

Another supervisory circuit initializes separately the microcontroller-embeddedJTAG/ICE interface when the 3.3V supply voltage drops below 3.0V. Note that this volt-age can be changed, depending on the board production series. These separated resetlines allow the user to reset the board without resetting the JTAG/ICE interface whiledebugging.

The schematic (see Figure 6-5 on page 6-6 in Section 6, “Appendix B – Schematics”)also shows eight general-purpose LEDs connected to Port B PIO pins (PB8 to PB15).

Two 9-way D-type connectors (P3/4) are provided for serial port connection.

Serial Port A (P3) is used primarily for host PC communication and is a DB9 female con-nector. TXD and RXD are swapped so that a straight-through cable can be used. CTSand RTS are connected together, as are DCD, DSR and DTR.

Serial Port B (P4) is a DB9 male connector with TXD and RXD obeying the standardRS-232 pinout. Apart from TXD, RXD and ground, the other pins are not connected.

LEDs are connected to the TX and RX signals of both serial ports and show activity onthese serial links.

A MAX3223 device (U10) and associated bulk storage capacitors provide RS-232 levelconversion.

4.7 Layout Drawing The layout diagram (see Figure 6-1 on page 6-2 in Section 6, “Appendix B – Schemat-ics”) shows an approximate floor plan for the board. This has been designed to give thelowest board area, while still providing access to all test points, jumpers and switches onthe board.

The board is provided with four mounting holes, one at each corner, into which feet areattached. The board has two signal layers and two power planes.



Circuit Description



Section 5

Appendix A – Configuration Straps

5.1 Functional Pin Assignment

The following table provides a list of each peripheral used on the AT91EB42 EvaluationBoard.

Table 5-1. Functional Pin Assignment

Pin Designation Function Used on the AT91EB42

NCS0 Chip Select signal for the Flash Memory (AT49BV162A)

NCS1 Chip Select signal for the Static RAMs

PB7/TIOA0 General I/O input line for the User Interface Push-button (SW1)

PA0/IRQ0 General I/O input line for the User Interface Push-button (SW2)

PB6/TCLK0 General I/O input line for the User Interface Push-button (SW3)

PB21/TCLK5 General I/O input line for the User Interface Push-button (SW4)

PB8/TIOB0 General I/O output line for the User Interface Light Indicator (Led D1)

PB9/TCLK1 General I/O output line for the User Interface Light Indicator (Led D2)

PB10/TIOA1 General I/O output line for the User Interface Light Indicator (Led D3)



PB13/TIOA2 General I/O output line for the User Interface Light Indicator (Led D6)



PA6/TXD0 To the RS232 Transceiver device and dedicated for the Serial A socket

PA7/RXD0 To the RS232 Transceiver device and dedicated for the Serial A socket

PA9/TXD1/NTRI To the RS232 Transceiver device and dedicated for the Serial B socket

PA10/RXD1 To the RS232 Transceiver device and dedicated for the Serial B socket

PB18/TCLK4 General I/O input line to detect the fast-charge mode for the battery

PB16/TIOA3 General I/O output line to generate SCL signal dedicated for a two wire bus access




5.2 Configuration Straps (CB1 - 23, JP1 - 8)

By adding the I/O and EBI expansion connectors, users can connect their own peripher-als to the evaluation board. These peripherals may require more I/O lines than availablewhile the board is in its default state. Extra I/O lines can be made available by disablingsome of the on-board peripherals or features. This is done using the configuration strapsdetailed below. Some of these straps present a default wire (notified by the default men-tion) that must be cut before soldering the strap.

Note: 1. Hardwired default position: To cancel this default configuration, the user should cutthe wire on the board.


PB17/TIOB3 General I/O input/output line to generate SDA signal dedicated for a two wire bus access

PA13/MOSIA To generate SPI bus Access to the DataFlash, EEPROM and ADC devices

PA12/MISOA To generate SPI bus Access to the DataFlash, EEPROM and ADC devices

PA11/SPCKA To generate SPI bus Access to the DataFlash, EEPROM and ADC devices

PA14/NPCSA0/NSSA Chip Select signal for the SPI device: DataFlash

PA15/NPCSA1 Chip Select signal for the SPI device: EEPROM

PA16/NPCSA2 Chip Select signal for the SPI device: ADC

PA3/IRQ3 Interrupt line from the ADC device

Table 5-1. Functional Pin Assignment (Continued)

Pin Designation Function Used on the AT91EB42

CB1 On-board PB5/A23/CS4 Signal

Closed(1) AT91 PB5/A23/CS4 signal is connected to the EBI expansion connector (P1-B21).

Open AT91 PB5/A23/CS4 signal is not connected to the EBI expansion connector (P1-B21).

This authorizes users to connect the EBI expansion connector of this board to the MPI expansion connector of an AT91EB63 Evaluation Board without conflicting problems.

CB3 On-board IRQ3 Signal

Closed(1) AT91 IRQ3 signal is connected to the external ADC (U20 pin 4).

Open AT91 IRQ3 signal is not connected to the external ADC (U20 pin 4). This authorizes the user to use this signal for other applications via the I/O Expansion connector (P2 - A8).









CB4 ADC Chip Select Line

Closed(1) ADC (U20) control lines enabled.

Open ADC (U20) control lines disabled. This authorizes users to connect the corresponding chip select line to their own resources via the I/O expansion connector.

CB5 Standard Power Supply Supervisory Enabling

Closed(1) Standard power supply is supervised by the ADC (U20) channel 1 via a resistor bridge. The ratio is set to 0.1013 so that the standard power supply can be supervised up to 15V.

Open Standard power supply is not connected to the ADC (U20) channel 1. This allows the user to connect the corresponding ADC channel to their own resources via the I/O expansion connector.

CB6 VDDCORE Voltage Monitoring

Closed(1) The ADC channel 3 is connected at the VDDCORE power supply. This allows the user to tune the frequency clock according to the core voltage.

Open The ADC channel 3 is not connected and it is available on the I/O expansion connector for user application.

CB7 Battery Power Supply Supervisory Enabling

Closed(1) Battery power supply is supervised by the ADC (U20) channel 2 via a resistor bridge. The ratio is set to 0.24 so that the battery voltage range can be supervised (5.5V to 6.2V).

Open Battery power supply is not connected to the ADC (U20) channel 2. This authorizes the user to connect the corresponding ADC channel to their own resources via the I/O expansion connector.

CB8 Ambient Temperature Monitoring

Closed(1) The ADC channel 0 is connected to a temperature sensor near the 32.768 kHz crystal. This allows the user to evaluate the frequency drift according to the ambient temperature.

Open The ADC channel 0 is not connected and it is available on the I/O expansion connector for the user application.










CB9 On-board Boot Chip Select

Closed(1) AT91 NCS0 select signal is connected to the Flash memory.

Open AT91 NCS0 select signal is not connected to the Flash memory. This authorizes the user to connect the corresponding select signal to their own resources via the EBI expansion connector.

CB10 Flash Reset

Closed(1) The on-board reset signal is connected to the Flash NRESET input.

Open The on-board reset signal is not connected to the Flash NRESET input.

CB12 Boot Mode Strap Configuration

Open(1) BMS AT91 input pin is set for the microcontroller to boot on an external 16-bit memory at reset.

Closed BMS AT91 input pin is set for the microcontroller to boot on an external 8-bit memory at reset.

CB13, CB14 Two-wire Interface EEPROM Enabling

Closed(1) EEPROM communication enabled.

Open EEPROM communication disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector.

CB15 Serial DataFlash Enabling

Closed(1) AT91 NPCSA0 select signal is connected to the serial DataFlash memory.

Open AT91 NPCSA0 select signal is not connected to the serial DataFlash memory. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector.

CB16 Control Line for the Internal Oscillator

Closed Disables the internal low frequency oscillator.

Open(1) Enables the internal oscillator.








CB17 SPI EEPROM Enabling

Closed(1) EEPROM communication enabled.

Open EEPROM communication disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector.

CB18 R(eturn) TCK ICE Signal Synchronization

1 - 2(1) The TCK and RTCK ICE signals are not synchronized with MCKO.

2 - 3 The TCK signal from the JTAG interface can be synchronized with the MCKO signal and returns to the JTAG interface (RTCK).

CB19 PB18 End of Fast Charge Signal

Closed(1) AT91 PB18 signal is connected to the battery charger (U16), NFASTCHG output pin.

Open AT91 PB18 signal is not connected to the battery charger (U16), NFASTCHG output pin. This authorizes users to connect the corresponding signal to their own resources via the I/O expansion connector.

CB20 JTAGSEL

1 - 2(1) AT91 standard ICE debug feature enabled

2 - 3 IEEE 1149.1 JTAG boundary scan feature enabled

CB21, CB22, CB23 Charger Device (U16): Programming the Battery Number of Cells

Number of Cells CB21 CB22 CB23

1 Open Closed Closed

2 Open Open Closed

4 Closed Open Closed

5(1) Open Closed Open

6 Open Open Open

8 Closed Open Open




JP1 User or Standard Boot Selection

2 - 3 The first half part of the Flash memory is accessible at its base address.

1 - 2 The second half part of the Flash memory is accessible at its base address. This authorizes users to download their own application software in this part and to boot on it.

JP2 Push Button Enabling

Open SW1-4 inputs to the AT91 are valid.

Closed SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector.

JP3 User or Standard Boot Selection

Open The RS-232 transceivers are enabled.

Closed The RS-232 transceivers are disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector.

JP4 PME Function (Protect Mode Enable)

Closed The AT91M42800A is in Protect Mode.

Open This is the default mode on the AT91EB42. The AT91M42800A internal registers are accessible in all processor modes.

JP8 Core Power Supply Selection

2 - 3 The AT91 core is powered by 3.3V power supply.

1 - 2 Not supported on the current microcontroller revision.




5.3 Power Consumption Measurement Strap (JP5)

The JP5 strap enables connection of an ammeter to measure the AT91M42800A globalconsumption (VDDCORE and VDDIO) when VDDCORE power supply is derived from VDDIO(JP8 in 3V3 position). Core consumption can be measured by connecting anotherammeter between JP8 1 - 2 or 2 - 3, depending on the power supply used to power thecore.

5.4 Ground Links (JP6)

The JP6 strap allows the user to connect the electrical and mechanical grounds.

5.5 Increasing Memory Size

The AT91EB42 Evaluation Board is supplied with two 128K x 8 SRAM memories. If,however, the user needs more than 256K bytes of memory, the devices can be replacedwith two 512K x 8 3.3V 10/15 ns SRAMs, giving a total of 1024K bytes. The followingreferences for the 512K x 8 SRAM are available.

Manufacturer Reference

Samsung KM68V4002BJ-15 in 36-SOJ-400 package

IDT 71V424-15 in 36-pin 400-mil SOJ package (SO36-1)



Section 6

Appendix B – Schematics

6.1 Schematics The following schematics are appended:

! Figure 6-1 – PCB Layout

! Figure 6-2 – AT91EB42 Blocks Overview

! Figure 6-3 – EBI Memories

! Figure 6-4 – I/O and EBI Expansion Connectors

! Figure 6-5 – Push-buttons, LEDs and Serial Interface

! Figure 6-6 – AT91M42800A

! Figure 6-7 – Reset and JTAG Interface

! Figure 6-8 – Power Supply and Battery Charger

! Figure 6-9 – SPI Memories, Two-wire Interface Memories and SPI ADC

The pin connectors are indicated on the schematics:

! P1 = EBI Expansion Connector (Figure 6-4)

! P2 = I/O Expansion Connector (Figure 6-4)

! P3 = Serial A (Figure 6-5)

! P4 = Serial B (Figure 6-5)

! P5 = JTAG Interface (Figure 6-7)




Figure 6-1. PCB Layout




Figure 6-2. AT91EB42 Blocks Overview

INP

UT

/ O

UT

PU

T O

N B

OA

RD

Ser

ial C

onne

ctor

s / P

.B. /

LE

D

PB

[6..

15]

PA

[6..

7]

PA

0

PA

[9..

10]

SU

PP

LY a

nd R

TC

SA

VE

pow

er s

uppl

y / b

atte

ry

PB

18

SE

RIA

L M

EM

OR

IES

SE

RIA

L M

EM

OR

IES

PB

17

MO

SIA

MIS

OA

SP

CK

A

PB

16

NR

ST

NP

CS

A0

NP

CS

A1

VIN

[1..

4]N

PC

SA

2

IRQ

3P

B1

9P

B2

0

EX

TE

NS

ION

S C

ON

NE

CT

OR

S

Ext

ensi

on C

onne

ctor

s

IOB

_[0.

.57]

EB

I_[0

..42

]

EB

I ME

MO

RIE

S

mem

orie

s co

nnec

ted

on E

BI

EB

I_[0

..42

]

A2

0

PB

22

MIC

RO

CO

NT

RO

LLE

R

mic

ro /

Rst

/ W

chdo

g / J

TA

G c

o.

EB

I_[0

..42

]

IOB

_[0.

.53]

IOB

_1

3IO

B_

12

IOB

_1

1

IOB

_4

7IO

B_

46

EB

I_[0

..42

]

EB

I_[0

..42

]

IOB

_[0.

.57]

IOB

_[0.

.57]

IOB

_[0.

.57]

IOB

_[36

..45

]

IOB

_[0.

.57]

IOB

_3

2IO

B_[

0..5

7]

EB

I_[0

..42

]E

BI_

41

IOB

_5

2

EB

I_[0

..42

]

IOB

_1

4IO

B_

15

IOB

_[0.

.53]

IOB

_[54

..57

]IO

B_

16

IOB

_3

IOB

_4

9IO

B_

50 IO

B_[

6..7

]

IOB

_0

IOB

_[9.

.10]

IOB

_[0.

.57]

IOB

_4

8




Figure 6-3. EBI Memories

512k

512k

128k

128k

128k

512k

512k

128k

layo

ut fo

r T

SS

OP

400

mil.

layo

ut fo

r S

OJ

400m

il.

2Mby

tes

FLA

SH

ME

MO

RY

1Mby

tes

( tw

o 51

2kX

8 )

SR

AM

with

two

foot

prin

ts o

r25

6kby

tes

( tw

o 12

8kX

8 )

SR

AM

with

two

foot

prin

ts.

ST

D B

OO

T

US

ER

BO

OT

NW

E

NR

ST

_1N

RS

T

NC

S0

NO

E

NC

S0_

1

NC

S1

NW

R1

D1

1

D8

A6

A1

8A

1

D1

0

A5

A2

A3

A7

A4

A1

9A

8

D9

D1

4

A1

4

D1

5

A1

6

D1

3

A1

5

D1

2A

13

A1

2

A1

7

A9

A1

1A

10

A4

A1

9

D1

D2

NW

R0

A8

A5

A1

8

A7

D0

A2

A6

D3

A3

A1

NC

S1

A1

4A

15

D6

A1

1

A1

3

D5

A1

6

A1

0

A1

2

NR

D

A1

7

D4

A9

D7

A1

1

A1

3

D1A1

8

A4

A5

A8

D8

NR

DD

7

A1

NW

R0

D3

A1

A1

9

A1

3

NC

S1

D1

4

A1

7

A1

9

D0

A1

2

A1

6

A4

D1

1D

5

D9

A1

2

D2

A1

0

D1

0

A6

A9

NW

R1

A7

A1

6

D1

5

A5

A3

NC

S1

A8

A1

4A

14

A1

7

A3

A9

A1

5

A6

A1

1

D1

3

A2

A1

8

A1

0

D6

A2

A1

5

NR

D

D1

2D

4

A7

GN

D

D9

D0

D2

D1

2

D3

A1

2

A1

8

D1

0

A1

5

CT

L5

NR

ST

NC

S0

CT

L4

D1

D1

1

D7

D6

A1

4A

13

D8

A1

A1

6A

17

D1

5

A2

D1

3

CT

L2

NR

DN

OE

A4

CT

L1

NW

R1

NU

B

A1

9

NC

S1

CT

L6

A[0

..19]

A9

A7

A6

A8

D[0

..15

]

D5

A5

A1

0A

11

D1

4

D4

A3

EBI_

[0..1

5]D

[0..

15]

A[0

..19]

EBI_

[16.

.35]

CT

L[0.

.6]

EBI_

[36.

.42]

CT

L0

NW

R0

NW

E

A2

0B

IOB

_3

2

NR

D

A2

0B

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

VC

C3

V3

C5

100n

F

R1

10

0k

1 2

R2

10

0k

1 2

U3 ID

T71

V42

4S10

Y

A0

1

A1

2

A2

3

A3

4

A4

5

A5

14

A6

15

A7

16

A8

17

A9

18

A1

02

0A

11

21

A1

22

2A

13

23

A1

42

4

A1

53

2A

16

33

CS

6

WE

13

OE

31

D1

8

D2

11

D3

12

D4

25

D5

26

D6

29

D7

30

VC

C2

7G

ND

10

A1

73

4A

18

35

VC

C9

GN

D2

8

D0

7

NC

19

NC

36

U2 ID

T71

V42

4S10

Y

A0

1

A1

2

A2

3

A3

4

A4

5

A5

14

A6

15

A7

16

A8

17

A9

18

A1

02

0A

11

21

A1

22

2A

13

23

A1

42

4

A1

53

2A

16

33

CS

6

WE

13

OE

31

D1

8

D2

11

D3

12

D4

25

D5

26

D6

29

D7

30

VC

C2

7G

ND

10

A1

73

4A

18

35

VC

C9

GN

D2

8

D0

7

NC

19

NC

36

U5 ID

T71

424S

10P

H

A0

3

A1

4

A2

5

A3

6

A4

7

A5

16

A6

17

A7

18

A8

19

A9

20

A1

02

6A

11

27

A1

22

8A

13

29

A1

43

0

A1

53

8A

16

39

CS

8

WE

15

OE

37

D1

10

D2

13

D3

14

D4

31

D5

32

D6

35

D7

36

VC

C3

3G

ND

12

A1

74

0A

18

41

NC

1

NC

2

VC

C1

1G

ND

34

NC

43

NC

44

D0

9

NC

21

NC

22

NC

23

NC

24

NC

25

NC

42

U4 ID

T71

424S

10P

H

A0

3

A1

4

A2

5

A3

6

A4

7

A5

16

A6

17

A7

18

A8

19

A9

20

A1

02

6A

11

27

A1

22

8A

13

29

A1

43

0

A1

53

8A

16

39

CS

8

WE

15

OE

37

D1

10

D2

13

D3

14

D4

31

D5

32

D6

35

D7

36

VC

C3

3G

ND

12

A1

74

0A

18

41

NC

1

NC

2

VC

C1

1G

ND

34

NC

43

NC

44

D0

9

NC

21

NC

22

NC

23

NC

24

NC

25

NC

42

U1 AT

49B

V16

2A

A0

25

A1

24

A2

23

A3

22

A4

21

A5

20

A6

19

A7

18

A8

8

A9

7

A1

06

A1

24

A1

33

A1

42

A1

51

A1

64

8

A1

71

7

A1

81

6

A1

91

5

NC

9

NC

10

NC

14

NC

/ V

pp1

3

CE

26

WE

11

OE

28

RE

SE

T1

2G

ND

27

GN

D4

6

VC

C3

7V

CC

Q4

7

I/O

02

9

I/O

13

1

I/O

23

3

I/O

33

5

I/O

43

8

I/O

54

0

I/O

64

2

I/O

74

4

I/O

83

0

I/O

93

2

I/O

103

4

I/O

113

6

I/O

123

9

I/O

134

1

I/O

144

3

A1

15

I/O

154

5

C1

100n

F

C2

100n

F

C3

100n

F

C4

100n

F

CB

9

12

CB

10

12

JP1

jum

per_

3P

1

2

3

U6A

74

LV

C0

21

2 31

CB

24

12

C8

910

0nF

U6C

74

LV

C0

2A

D

1

8 91

0

U6D

74

LV

C0

2A

D

1

11

12

13

7

14

EB

I_[0

..42

]

A2

0



Ap

pen

dix B

– Sch

ematics

AT

91

Fig

ure 6-4. I/O

and EB

I Expansion C

onnectors

ion Connector

PA8

PB[0..23]

IOB_[0..29]

PA10

PB9

PA5

PB7

PB14

PA9

PB19

PB13

PA23

PA14

PB12

PB10

PA24

PB18

PA11

PB17

PB22

IOB_[30..53]

IOB_[54..57]

PB21

PA13

PB15

PA6

PA15

PA7

PB11

PB8

PB20

PB23

PB16

PB6

PA22

PA12

2B

/O Ext. Conn.

PB6 / TCLK0B1

PB7 / TIOA0B2

PB8 / TIOB0B3

PB9 / TCLK1B4

PB10 / TIOA1B5

PB11 / TIOB1B6

PB12 / TCLK2B7

PB13 / TIOA2B8

PB14 / TIOB2B9

PB15 / TCLK3B10

PB16 / TIOA3B11

PB17 / TIOB3B12

PB18 / TCLK4B13

PB19 / TIOA4B14

PB20 / TIOB4B15

PB21 / TCLK5B16

PB22 / TIOA5B17

PB23 / TIOB5B18

PA5 / SCK0B19

PA6 / TXD0B20

PA7 / RXD0B21

PA8 / SCK1B22

PA9 / TXD1 / NTRIB23

PA10 / RXD1B24

PA22 / NPCSB1B25

PA23 / NPCSB2B26

PA24 / NPCSB3B27

PA12 / MISOAB28

PA13 / MOSIAB29

PA11 / SPCKAB30

PA14 / NPCSA0 / NSSAB31

PA15 / NPCSA1B32

IOB_[0..57]

EB

42 Evalu

ation

Bo

ard U

ser Gu

ide

6-5

1708C–A

TA

RM

–12-May-05

EBI Extension Connector I/O Extens

CS4_1

PB[0

..23]

PA28

D10

PA3

PB1

A[0

..19]

PA[0..29]

A14

A2A4

CS4 PB5

A3

D4

PA4

A15

CS5PB4

PA0

CTL[0..6]

A[0..19] EBI_[16..35]

A[0

..19]

CTL3

D1

D6 D7

D14

PA[0..29]

D12

A7

NCS3

A1

D5

CS7PB2

PB[0..23]

VIN[1..4]

CS6 PB3

NCS1 CTL6NCS0CTL4

A8

PA17

D13

PA21

PA16

D3 PA20

A19

D8

A16

D0

CTL5

A9

PA26

PA19

D11

A0

D15

PA25

CTL[0..6] EBI_[36..42]

CTL2CTL0

D2

D9

PA18

A13

A5

NCS2PB0

PA29

A6

D[0..15] EBI_[0..15]

A11

CTL1

A10

PA1

PA27

A12

PA2

A18A17

PB[0

..23]

VIN[1..4]VIN1VIN2VIN3VIN4

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

CB11 2

P1B

EBI Ext. Con.

GNDB1

NWR1 / NUBB2

NWAITB3

-B4

NCS1B5

PB1 / NCS3B6

NRSTB7

A1B8

A3B9

A5B10

A7B11

GNDB12

A9B13

A11B14

A13B15

A15B16

VCC3V3B17

A17B18

A19B19

PB3 / A21 / CS6B20

PB5 / A23 / CS4B21

GNDB22

D1B23

D3B24

D5B25

D7B26

VCC3V3B27

D9B28

D11B29

D13B30

D15B31

GNDB32

P

I

P1A

EBI Ext. Con.

GNDA1

NWR0 / NWEA2

NRD / NOEA3

PA25 / MCK0A4

NCS0A5

PB0 / NCS2A6

VCC3V3A7

A0 / NLBA8

A2A9

A4A10

A6A11

GNDA12

A8A13

A10A14

A12A15

A14A16

VCC3V3A17

A16A18

A18A19

PB2 / A20 / CS7A20

PB4 / A22 / CS5A21

GNDA22

D0A23

D2A24

D4A25

D6A26

VCC3V3A27

D8A28

D10A29

D12A30

D14A31

GNDA32

P2A

I/O Ext. Conn.

GNDA1

VCC3V3A2

PA0 / IRQ0A3

PA1 / IRQ1A4

GNDA5

PA2 / IRQ2A6

VCC3V3A7

PA3 / IRQ3A8

GNDA9

PA4 / FIQA10

VCC3V3A11

PA28 / HOLDAA12

PA29 / HOLDA13

VCC3V3A14

PA26A15

GNDA16

VIN1A17

VIN2A18

VIN3A19

VIN4A20

GNDA21

PA18 / SPCKBA22

PA19 / MISOBA23

PA20 / MOSIBA24

PA21 / NPCSB0 / NSSBA25

PA27 / BMSA26

GNDA27

PA17 / NPCSA3A28

PA16 / NPCSA2A29

GNDA30

VCC3V3A31

GNDA32

EBI_[0..42]


Figure 6-5. Push-buttons, LEDs and Serial Interface

Usart

0:

SERIAL A

Usart

1:

SERIAL B

VALID

RS232 on IOB

VALBP

DSR0

RTS0

CTS0

DTR0

DCD0

TX0

RX0

TX1

VAL_RS232

RX1

VALBP

VALBP

PA9

TXD1

PB9

PB15

PB12

PA7

RXD0

PB13

PA10

RXD1

PB11

PA[6..7]

TIOA0

PB7

PB[6..15]

IRQ0

PA0

PB8

PB6

TCLK0

PB14

TXD0

PA6

PB10

PA0

PA[9..10]

PA7

PB21

TCLK5

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

VCC3V3

R3

100K

C10

47nF

SW1

TP 33

R4

100K

C11

47nF

SW2

TP 33

R14

100K

SW3

TP 33

C14

47nF

D1

Red LED

R6

100R

D2

R7

100R

D3

R8

100R

D4

R9

100R

D5

R10

100R

R11

100R

D6

R12

100R

D7

D8

R13

100R

U8

74LV244D

GND SIGNAL

VCC3V3

EN

EN

1 2 4 6 8

19

11

13

15

17

3

10

57912

14

16

18

20

C17100nF

C19100nF

C18

100nF

C22

100nF

C21

22pF

P3

Sub D 9b F

594837261

C20

22pF

C23

22pF

C26

22pF

C27

22pF

R16

100k

P4

Sub D 9b M

594837261

C25

10nF

R17

100K

C13

100nF

C12

100nF

12

C16

100nF

JP2

jumper_NO

12

JP3

jumper_NO

12

C24

22pF

R5

100k

U9

74LV125D

EN

14

7

1 2 4 5

10 9

13

12

3 6 8 11

R75

100R

D31

R73

100R

D29

R76

100R

D32

R74

100R

D30

U10

MAX3223ECAP

EN

1

FORCEON

14

FORCEOFF

20

INVALID

11

GND18

R1IN

16

R2IN

9R1OUT

15

R2OUT

10

T1IN

13

T2IN

12

T1OUT

17

T2OUT

8

C1+

2

C1-

4

C2+

5

C2-

6

V+

3

V-

7

VCC19

R42

100k

R43

100k

R44

100k

R15

100K

SW4

TP 33

C15

47nF

R45

100k

PB[6..15]

PA[6..7]

PA0

PA[9..10]

PB21




Figure 6-6. AT91M42800A

Gua

rd ri

ng

PLL

filte

r A

PLL

filte

r B

Gua

rd ri

ng

Def

ault

boot

Mod

e :

16

Bits

JTA

G[0

..4]

EBI_

[0..1

5]D

[0..

15]

CT

L[0.

.6]

A[0

..19]

EBI_

[16.

.35]

CT

L[0.

.6]

EBI_

[36.

.42]

A[0

..19]

PB

[0..2

3]IO

B_[0

..29]

PA

[0..2

9]

PA

[0..2

9]

PB

[0..2

3]

PB

[0..2

3]

PB

[0..2

3]IO

B_[

30..

53]

VD

DIO

VD

DIO

VDDIO

VDDIOVDDIO

VDDIO

JTAG0

JTAG2JTAG1

JTAG3JTAG4

JTAGSEL

NWDOVF

PLLRCB

PLLRCA

XOUTXINVT

XO

UT

XIN

PL

LR

CB

PL

LR

CA

CT

L5

JTA

GS

EL

NW

DO

VF

PA29

PA26

PA27

PA28

BM

SP

A2

7

NW

AIT

CT

L3

VT

A0

D0

A1

7

D2

A1

3

CTL0

D15

D3

A1

5

A1

9

A5

A7

CTL2

A2

D5D6

A1

6

A6

D13

CTL4

CTL3

A1

0

D8

A1

2

A4

D4

D12

CTL6

D11

A1

4

CTL5 D14

A1

1

A8

A1

8

D1

A3

A1

D10

A9

D7

D9

CTL1

PA

5

VDDCORE

PB

23

PA

1

PA

9

PA

12

PB20

VD

DC

OR

E

PA

2

PA

8

PA

6

PB6

PB1

PA

4

PA

15

PA

22

PA

23

PA

18

PA

21

PB9

PA

13

PB

4

PB16

VD

DIO

PA

3

PB21

PB12PB11

PA

7

PA

0

PB13

PB19

VDDIOP

A1

9

PB7

PB

3

PB14

PA

24

PB18

VDDCORE

VD

DIO

PA

20

PA

11

PB15

PB

22

PB17

PB8

VD

DIO

PA

14

PB0

PB

5

PA

17

PB10

PB

2

PA

16

PA

10

PA

25

PA29

JTA

G[0

..4]

NR

ST

NW

DO

VF

JTA

GS

EL

VD

DC

OR

E

VDDPLL

VC

C3

V3

VC

C3

V3

VC

C3

V3

VD

DIO

VD

DIO

VD

DC

OR

E

VC

C3

V3

C3

0

100n

F

C4

9

100n

FC

50

100n

F

Y1

32,7

68kH

z

12C4

3

12

C4

4

12

R2

06

80

R 1

%1

2

C4

7

100n

F 1

0%

1 2

C4

81µF

10%

1 2

R1

91

00

R 1

%1

2

R2

11

20

R 1

%1

2

C4

6

100n

F 1

0%

1 2

R1

81

K5

0 1

%1

2

C4

5

10nF

10%1 2

R4

1

10

0K

CB

12

12

R4

6

10

0K

CB

16

12

R4

8

10

0K

C2

9

100n

F

C2

810

0nF

C5

1

100n

F

U11 AT

91M

4280

0AT

QF

P 1

44

GN

D1

GN

D2

NLB

/ A

03

A1

4

A2

5

A3

6

A4

7

A5

8

A6

9

A7

10

A8

11

A9

14

A1

01

5

A1

11

6

A1

21

7

A1

31

8

A1

41

9

A1

52

0

A1

62

1

A1

72

2

A1

82

3

A1

92

6

PB

2 / A

20 /

CS

72

7

PB

3 / A

21 /

CS

62

8

PB

4 / A

22 /

CS

52

9

PB

5 / A

23 /

CS

43

0

D0

31

D1

32

D2

33

D3

34

VD

DIO

12

GN

D1

3

GN

D2

5

VD

DC

OR

E3

5

VD

DIO

36

GND 37GND 38

GND 49

D4 39D5 40D6 41D7 42D8 43D9 44

D10 45D11 46D12 47

D13 50D14 51D15 52

PB6 / TCLK0 53PB7 / TIOA0 54PB8 / TIOB0 55PB9 / TCLK1 56PB10 / TIOA1 57PB11 / TIOB1 58PB12 / TCLK2 59

PB13 / TIOA2 62PB14 / TIOB2 63PB15 / TCLK3 64PB16 / TIOA3 65PB17 / TIOB3 66PB18 / TCLK4 67PB19 / TIOA4 68PB20 / TIOB4 69PB21 / TCLK5 70

VDDIO 48

VDDIO 60GND 61

VDDCORE 71VDDIO 72

GN

D7

3G

ND

74

PB

22 /

TIO

A5

75

PB

23 /

TIO

B5

76

PA

0 / I

RQ

07

7P

A1

/ IR

Q1

78

PA

2 / I

RQ

27

9P

A3

/ IR

Q3

80

PA

4 /

FIQ

81

PA

5 / S

CK

08

2P

A6

/ TX

D0

83

PA

7 / R

XD

08

6P

A8

/ SC

K1

87

PA

9 / T

XD

1 / N

TR

I8

8P

A10

/ R

XD

18

9

PA

11 /

SP

CK

A9

0P

A12

/ M

ISO

A9

1P

A13

/ M

OS

IA9

2P

A14

/ N

PC

SA

0 / N

SS

A9

3P

A15

/ N

PC

SA

19

4P

A16

/ N

PC

SA

29

5

PA

17 /

NP

CS

A3

98

VD

DIO

84

GN

D8

5

VD

DIO

96

GN

D9

7

PA

18 /

SP

CK

B9

9P

A19

/ M

ISO

B1

00

PA

20 /

MO

SIB

10

1P

A21

/ N

PC

SB

0 / N

SS

B1

02

PA

22 /

NP

CS

B1

10

3P

A23

/ N

PC

SB

21

04

PA

24 /

NP

CS

B3

10

5

PA

25 /

MC

KO

10

6

VD

DC

OR

E1

07

VD

DIO

10

8

GND109

GND110

PA26111

GND112

XIN113

XOUT114

PLLRCA116

VDDPLL117

PLLRCB118

VDDPLL119

GND115

VDDIO120

GND121

NWDOVF122

PA27 / BMS123

JTAGSEL124

TMS125

TDI126

TDO127

TCK128

NTRST129

NRST130

PA28131

GND133

VDDIO132

PA29 / PME134

NWAIT135

NOE / NRD136

NWE / NWR0137

NUB / NWR1138

NCS0139

NCS1140

PB0 / NCS2141

PB1 / NCS3142

VDDCORE143

VDDIO144

VD

DIO

24

R7

1

10

0K

JP4

12

IOB

_[0.

.53]

EB

I_[0

..42

]

Gua

rd ri

ng




Figure 6-7. Reset and JTAG Interface

JTA

G C

onne

ctor

(Fr

ont V

iew

)

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20




Figure 6-8. Power Supply and Battery Charger

VDD

CO

RE=

1.8V

VDD

CO

RE=

3.3V

I V

ddco

re

I V

ddio

5 ce

l. N

iCd

Tim

eout

264

mn

T˚C

34

VC

C3V

3

VIN

plug

1

VC

C1V

8

VD

DIO

VIN

1F

VIN

plug

2

VIN

_1V

IN

V+

Vbat

t-

Vbat

t-

Rth

1

Rth

2

Vbat

t+

VIN

Rth

2

Rth

1

v+Vbat

t-

VC

C3V

3

VD

DC

OR

EVD

DIO

VD

DP

LL

VD

DA

VC

C3V

3

Vbat

t+

Vps

C54

100n

FF1

1000

m A

/30V

D14

SM

T6T1

5CA

C57

10µF

/ 25

V

U15

LT15

07C

S8-

3.3

VIN

2V

SW

3

SE

NS

E7

SYN

C5

SH

TDN

4

BOOST1

VC 8

GND 6

D12

1N91

4L1 10

µH

D15

1N58

17C

58

100µ

F / 1

0V

+

C60

3,3n

F / 1

0%

C55

22pF

/ 25

V

C64

1µF

10%

C61

1µF

10%

C62

1µF

10%

C63

10µF

/ 16

V+

D18

10M

Q10

0ND

1910

MQ

100N

D16

10M

Q10

0ND

1710

MQ

100N

TP2

Test

Poi

nt C

orne

r 2

TP3

Test

Poi

nt C

orne

r 3

TP1

Test

Poi

nt C

orne

r 1

TP4

Test

Poi

nt C

orne

r 4

U17

LT15

03C

S8-

1.8

Vin

4Vo

ut1

C1+

3

C1-

2

C2+

6

C2-

8

SHD

N/S

S5

GN

D7

J1 Jack

Dia

.2.1

mm

C59

22pF

/ 25

VJP

6

jum

per_

NO

12

JP5

jum

per_

NO

12

JP8

jum

per_

3P

1

2

3

R30

150R

R29

100R

CB

191

2

D26

1N40

01

D24

1N40

01

Q1

2N61

09

R58

1K

U16

MA

X 7

12/7

13

Vlim

it1

Batt+

2

PGM

03

PGM

14

THI

5

TLO

6

Tem

p7

FAS

TCH

G8

PGM

29

PGM

310

CC 11

Batt-

12

DRV14 GND 13

V+

15

RE

F16

D28

R60

1K

C10

1

1µF

10%

1 2

C10

01µ

F 1

0%

12

C98

10nF

C10

310

nF

C99

10µF

/ 25

V

C10

2

10nF

R62

2R49

/ 1%

D25

1N40

01

R59

1K

R77

680R

R79

1K

CB

21JU

MPE

R_N

O

12

CB

221

2

CB

23JU

MPE

R_N

O

12

BT1

6V /

300m

AH

1 2

R61

10K

CTN

PB

18




Figure 6-9. SPI Memories, Two-wire Interface Memories and SPI ADC

Dat

a Fl

ash

Mem

ory

Seri

al E

EPR

OM

mem

ory

on P

IO

Seri

al E

EPR

OM

mem

ory

on S

PIA

NP

CS

A0

MO

SIA

MIS

OA

SP

CK

A

MO

SIA

MIS

OA

SP

CK

A

NR

ST

NP

CS

A1_

1

VIN

[1..4

]

NP

CS

A2

MIS

OA

MO

SIA

SP

CK

A

VIN

3

VIN

2

VD

DC

OR

EVI

N4

IOB

_57

VIN

3

IOB

_56

VIN

2

IOB

_55

VIN

1

IOB

_54IR

Q3

VIN

4V

BA

TT+

VIN

1

VP

S

VC

C3V

3V

CC

3V3

VC

C3V

3

VC

C3V

3

VC

C3V

3

VC

C3V

3

VC

C3V

3

VC

C3V

3

VC

C3V

3

VC

C3V

3

VC

C3V

3

VC

C3V

3V

CC

3V3

R31

100k

C65

100n

F

U19

AT2

4C51

2W1-

10S

C-2

.7

1211

A1

2A

01

GN

D10

VC

C20

NC

3

NC

4

NC

5

NC

6

NC

7

NC

8

NC

9N

C13

NC

14N

C15

NC

16N

C17

NC

18W

P19

C70

100n

F

U18

AT4

5DB

321-

TC

RD

Y/BU

SY1

WP

3R

ES

ET

2

SC

K14

SI

15

SO

16

CS

13

NC

4

NC

5

NC

6

NC

9

NC

10

NC

11

NC

12N

C17

NC

18N

C19

NC

20N

C21

NC

22N

C23

NC

24N

C25

NC

26N

C27

NC

28N

C29

NC

30N

C31

NC

32

GN

D8

VC

C7

U21

AT2

5256

W-1

0SC

-2.7

CS

1

WP

3S

O2

SI

5

SC

K6

HO

LD7

GN

D4

VC

C8

C67 10

0nF

CB

131

2

CB

141

2R

4010

0k

R34

100k

R32

100k

CB

15

12

R66

100k

CB

171

2

R51

100K

R52

100K

R53

100K

R65

100K

C10

61µ

F

C10

510

0nF

CB

41

2

U20

TLV

1504

SD

O1

SD

I2

SC

LK3

IOC

(INT)

4

VC

C5

A0

6

A1

7

A2

8A

39

CS

TAR

T10

GN

D11

PW

DN

12FS

13R

EFM

14R

EFP

15C

S16

CB

81

2

CB

51

2

CB

71

2

C90

100n

F

R80

9.09

K1%

R81

7.5K

1%R

6975

0-1%

U23

LM61

BIM

3

VC

C1

GN

D3

Vout

2

CB

31

2

C10

410

µF /

16V

+ CB

6

12

R70

2.37

K1%

R67

750-

1%C

71µ

FC

61µ

F

C11

010

0nF

R68

6.65

K-1

%

PB

17

PB

16

NR

ST

MO

SIA

SP

CK

A

IOB

_14

MIS

OA

NP

CS

A1

TW

D

TW

DT

WC

KT

WC

K

Not

Mou

nted

Not

Mou

nted



Section 7

Appendix C – Bill of Materials

Figure 7-1. Bill of Materials for AT91EB42

Item Qty. Reference Part Designation Manufacturer

1 1 BT1 6V battery NiCd pack battery 6V – 300 mAh Saft

2 2 JP1, JP8 3-point jumper Jumper

3 2 JP4, JP5 2-point Jumper

4 CB24(*) 2-point strap Soft-soldering jumper

5 30 C1, C2, C3, C4, C5, C12, C13, C16, C17, C18, C19, C22, C28, C29, C30, C49, C50, C51, C52, C53, C54, C65, C67, C70, C89, C90, C94, C96, C105, C110

100 nF Ceramic Y5 10V AVX

6 3 C6, C7, C106 1 µF Ceramic Y5V 10V AVX

7 4 C10, C11, C14, C15 47 nF Ceramic X7R 10V AVX

8 5 C20, C21, C23, C24, C26, C27 22 pF Ceramic NPO 10V AVX

9 14 C25, C71, C72, C73, C74, C75, C76, C77, C82, C83, C86, C98, C102, C103

10 nF Ceramic X7R 16V AVX

10 7 C43, C78, C79, C80, C81, C84, C85 10 pF Ceramic NPO 10V 5% AVX

11 1 C44 4 - 25 pF Varicap. serie TZBX4 MURATA

12 1 C45 10 nF CeramicX7R 10V 10% AVX

13 2 C46, C47 100 nF CeramicX7R 10V 10% AVX

14 3 C48, C100, C101 1 µF CeramicX7R 10V 10% AVX

15 2 C55, C59 22 pF CeramicX7R 25V AVX

16 2 C57, C99 10 µF Tantalum (TPS ou OS-CON) 25V ESR < 0.5Ω

AVX

18 1 C58 100 µF Tantalum (TPS ou 593D) 10V ESR < 0.5Ω

AVX

20 1 C60 3.3 nF Ceramic X7R/25V/10% SIEMENS

21 3 C61, C62, C64 1 µF CeramicX7R 10V 10% AVX

22 2 C104, C63 10 µF Tantalum 16V 10% TAJ AVX

23 9 D1, D2, D3, D4, D5, D6, D7, D8, D11

Red LED Red LED H.R. 3mm T1 7mcd 60° HP




24 2 D10, D28 Red LED Red CMS LED HP

25 2 D30, D29 Orange LED SMT Orange LED HP

26 2 D32, D31 Green LED SMT Green LED HP

27 1 D12 1N914 Diode Fairchild

28 1 D14 SMT6T15CA Transil 12.8V/600W/VBRmin. 14.3V ST

29 1 D15 1N5817 Schottky 1A/0.45V ST

30 7 D16, D17, D18, D19, D24, D25, D26 10MQ100N Rectifier diode 0.62V/0.77A I.R.

31 1 F1 1000 mA/30V Fuse rarm 1000 mA/30V Polyswitch

32 1 J1 Jack diam. 2.1mm Jack socket diam. 2.1 mm LUMBERG

33 1 L1 10 µH Self 10 µH @ 1A and 500 kHz COILCRAFT

34 1 P3 Sub D 9b F Sub D 9b F, female socket, right angle, mechanical strength, locking

ETEC

35 1 P4 Sub D 9b M Sub D 9b M, male socket, right angle, mechanical strength, locking

ETEC

36 1 P5 HE10 2x10 HE10 2 x 10, low-profile T&B

37 1 Q1 MJD45H11 Transistor PNP MOTOROLA

38 29 R1, R2, R3, R4, R5, R14, R15, R16, R17, R25, R27, R31, R32, R34, R40, R41, R42, R43, R44, R45, R46, R48, R51, R52, R53, R65, R66, R71, R78

100K Resistors @ 5% Vishay

39 15 R6, R7, R8, R9, R10, R11, R12, R13, R23, R24, R29, R73, R74, R75, R76

100R Resistor @ 5% Vishay

40 1 R18 1K50 1% Resistor @ 1%, 125 mW Vishay

41 1 R19 100R 1% Resistor @ 1%, 125 mW Vishay



44 1 R30 150R Resistor @ 1%, 125 mW Vishay

45 1 R58 10K Resistor @ 1%, 125 mW Vishay

46 1 R59, R60, R79 1k Resistor @ 1%, 125 mW Vishay

47 1 R61 10K CTN Therm. CTN 10k @ 25°C, B = 3730°K

SIEMENS

48 4 R62d, R62c, R62b, R62a (****) 10R Resistor 0.25W 5% RC01

49 1 R67 7.5K1% Resistor @ 1%, 125 mW Vishay



52 1 R70 100K1% Resistor @ 1%, 125 mW Vishay

53 1 R77 (****) 6R8 Resistor @ 1%, 125 mW Vishay


55 1 R81 75K1% Resistor @ 1%, 125 mW Vishay

56 4 SW1, SW2, SW3, SW4 TP 33 Push-button with black cap APEM

Figure 7-1. Bill of Materials for AT91EB42 (Continued)





Notes: 1. The AT91EB42 board is equipped with SRAM U2/U3 or U4/U5. The difference is in the type of case used. The selection ismade based on availability.

2. U18 is wired according to availability.3. Cannot be seen in Figure 6-1.

57 1 SW5 TP 33 Push-button with red cap APEM

58 1 S1 B.P. SMT Push-button J.RENAUD

59 4 TP1, TP2, TP3, TP4 Test Point Corner SMT Test point

60 1 U1(1) AT49BV162A-70TI 2-Mbyte x 16-bit Flash Atmel

61 2 U3, U2(2) IDT71V424S10Y Static memory: 128K x 8 - 15 ns/36-pin 400 mil SOJ

IDT

62 2 U5, U4(2) IDT71424S10PH Static memory: 128K x 8 - 15 ns/44-pin TSOP Type II

IDT

63 1 U6 74LVC02AD QUAD 2-INPUT NOR Gate TI Philips

64 1 U8 74LV244D Buffer TI Philips

65 1 U9 74LV125D Tri-state buffer TI Philips

66 1 U10 MAX3223ECAP Driver RS232 + ESD “E” MAXIM

67 1 U11 AT91M42800A 32-bit Arm/Thumb Microcontroller Atmel

68 1 U12 74LVC74AD D flip-flop (LVC Serial) TI Philips

69 2 U13, U14 MAX6315US30D4-T Circuit LVD-reset Maxim

70 1 U15 LT1507CS8-3.3 Voltage Regulator DC/DC Linear Technology

71 1 U16 MAX 712/713 NiCd/NiMH Battery Fast-charge Controllers

MAXIM

72 1 U17 LTC 1503CS8-2 Voltage Regulator DC/DC Linear Technology

73 1 U18(3) AT45DB321-TC Serial DataFlash Atmel

75 1 U20 TLV1504 4 analog-to-digital converter with SPI protocol (D package)

TI

77 1 U23 LM61BIM3 2.7V, SOT-23 Temperature Sensor NS

78 1 U30 74LCX74 D flip-flop (LCX serie) TI Philips

79 1 Y1 32,768kHz Crystal 32.768 kHz/50 ppm MICRO CRYSTAL

80 2 P1, P2 2 x 32 male HE10 Header 2.54 mm FCI

81 4 R62d, R62c, R62b, R62a 14R7 Resistor 0.25W 5% RC01

82 1 R77 680 Resistor 0.25W 5% RC01 Vishay

83 2 P1, P2 2 x 32-point, male HE13 Header 2.54 mm FCI

84 4 R62d, R62c, R62b, R62a 14R7 Resistor 0.25W 5% RC01

85 1 Socket to be bonded to BT1(4) 4-point socket, male 2.54 mm pitch KK® vertical friction lock header, series 6410/7395

Molex

86 1 Connector to supply battery(1) 4-point connector, female 2.54 mm pitch KK crimp terminal housing, series 6471

Molex

Figure 7-1. Bill of Materials for AT91EB42 (Continued)




Section 8

Appendix D – FlashMemory Mapping

Figure 8-1 shows the embedded software mapping after the remap. It describes thelocation of the different programs in the AT49BV162A Flash memory and the divisioninto sectors.

Figure 8-1. EB42 Flash Memory Software Mapping

Not Used

LED Swing Application(Example)

Not Used

Not Used

Angel DebugMonitor

Free Sector forBoot Upgrade

Flash UploaderFunctional Test Software

Boot Program

0x011FFFFF

0x01100000

0x01011FFF

0x010060000x01005FFF

0x010040000x01000000

15 Sectors(64K Bytes/Sector)


1 Sector(64K Bytes/Sector)

5 Sectors(8K Bytes/Sector) +




1M ByteUser Mode

1M ByteStandard

Mode



Appendix D – Flash Memory Mapping



Document Details

Title AT91EB42 Evaluation Board User Guide

Literature Number 1708

Revision History

Version C Publication Date: 12-May-05

Revisions since last issue

All pages Removed all references to SRAM Downloader

Removed all references to two-wire interface

Changed all occurrences of AT49B1604(A) or AT49BV1614(A) or AT49BV16x4 toAT49BV162A.

Section 1.3 Removed references to:

64K bytes of EEPROM with two-wire access

32K bytes of SPI EEPROM

Fig.1-1 Removed the 2 "SERIAL EEPROM" boxes

Section 2.7 Changed

- D4 for the EEPROM with two-wire access to D4 reserved

- D6 for the SPI EEPROM to D6 reserved

Section 3.2 Replaced the description of "When SW2 button is pressed" by Reserved

Section 3.4 Removed

Section 3.5 Replaced AT91F40816 and AT91FR4081 by AT91FR4042 and AT91FR40162/S

Section 4.3 Added note:

The AT24C512 64K byte EEPROM and the AT25256 32K byte EEPROM are notmounted.

Appendix A Removed the table describing CB24

Figure 6-3 EBI Memories

Changed AT49BV16X4-90TC to AT49BV162A for U1 part.

Figure 6-9 Changed figure names into SPI and TWI Memories.

For U19 & U21 part: Add note NOT MOUNTED

Table 7-1 Removed items 74 & 76

Item 60 / "Part" Column --> changed to AT49BV162A-70TI


Figure 8-1 Updated with new memory sizes


Printed on recycled paper.


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