at-spex.comat-spex.com/services/graphics/ste10-100a_test_plan.docx · web view//ste reads tx...

// 1 Aug 2008 // Reference: STE10/100A Test Plan Revision 6// At-Spex LMO Test Systems// Co-Authors: James Perry/ Danny ONeill

// Overview of Test:// 1. Apply power to the DUT.// 2. Reset DUT.// 3. Read PCI Configuration Header via PCI port.// 4. Configure DUT via PCI port.// 4. Set up receive and transmit descriptors.// 5. Enable PHY and wrap Ethernet transactions for 10 Mbps.// 6. Go to 2 and repeat for 100 Mbps.//-------------------------------------------------------------------------------------------------------------------------------------//Register Initialization//Operation Register Data Description//--------- -------- ---------- ---------------------------//Read CR2 0x0200xxA1//Read CR32 0x2774104A//Write CR5 0x80000000 Set up MBA.//Read CR5 0x80000000//Write CR1 0x00000147 Turn on PERR#/SERR#.//Read CR1 0x02800147//Read CR15 0x00000100 //Write CSR0 0x0000C001 SW Reset.//Read CSR5 xxxxxxxx x000000x xxxxxxxx xxxxxxxxb //Read CSR0 0x0000C000 Need to write after reset.//Write XR0 0x8000 Reset PHY.//Write CSR25 0xBBAA0000//Write CSR26 0xXXXXDDCC//Write CSR3 0x88000000 Receive Descriptor Base Address//Write CSR4 0x40000000 Transmit Descriptor Base Address//-------------------------------------------------------------------------------------------------------------------------------------////Wait 6 seconds for PHY reset to complete.////-------------------------------------------------------------------------------------------------------------------------------------//Write XR0 0x0100 Full Duplex.//Read XR2 0x1C04 PHY ID//Read XR3 0x0010 Model No.//Read XR8 xxxxxx1x xxxxxxxxb//Read XR0 0x3000 for 100 Mbps / 0x2000 for 10Mbps//Read XR10//Write CSR6 0x000820CA Turn on RX and TX/internal loopback//-------------------------------------------------------------------------------------------------------------------------------------//STE Reads TX DESCRIPTOR in 4 word burst//STE Reads RX DESCRIPTOR in 4 word burst//STE Reads TX BUFFER in 16 word burst//-------------------------------------------------------------------------------------------------------------------------------------////Read CSR5 0xFC365410 TX FIFO fill/RX wait for data/No Fatal bus error////Wait 2000 cycles to give TX time to complete.////Write CSR6 0x000000c8 Shut off RX/TX////-------------------------------------------------------------------------------------------------------------------------------------//STE Reads TX DESCRIPTOR in 4 word burst////Withhold GNT from STE////STE Writes RX BUFFER in 10-11 word burst//

//Read XR10 xx00xx01 1x010100b////--------------------------------------------//For XCVR loopback: //STE Reads TX BUFFER//STE Writes RXDESC0 0x0022AB26//STE Writes TXDESC0 0x2A1B0000////Read CSR5 0xFC71d550////STE writes TXDESC0 0x1A170000//-------------------------------------------//For MAC loopback: //STE Writes RX BUFFER FCS in 2 word burst// 0xA3396430// 0x00441008//STE Reads TX BUFFER//STE Writes RXDESC0 0x00441300//STE Writes TXDESC0 0x2A190000////Read CSR5 0xFC71d550////STE writes TXDESC0 0x1A170000//-------------------------------------------------------------------------------------------------------------------------------------//Descriptor Initialization//Contents Description //--------- ----------- //0x80000000 TXDES0//0x62000040 TXDES1 64byte message buffer//0xA0000000 TXDES2//0x00000000 TXDES3//----------------------//0x80000000 RXDES0//0x02000080 RXDES1//0xC0000000 RXDES2//0xD0000000 RXDES3//-------------------------------------------------------------------------------------------------------------------------------------

#include "ste10.def"vFormat PCICLK RSTn FRAMEn IRDYn GNTn AD[31:0] CBEB[3:0] TRDYn IDSEL DEVSELn REQn STOPn PERRn SERRn PAR INTAn PMEn BRA[16:0] BRD[4:0] BrCSn BrOEn BrWEn LEDLK LEDC1 LEDSpd Vccdct Vauxdct BD6 BD7 EECS;

// D LLLVV // P F CCCC E EEECA // C R I //// T I V S P S I B BB B BBB DDDCU // I R A R G A A A A BBBB R D S R T E E N P R RR R RRR MMMDX E// C S M D N D D D D EEEE D S E E O R R P T M A AA D COW 111ED BBE // L T E Y T 3 2 1 0 nnnn Y E L Q P R R A A E 1 00 0 SEE LFSTE DDC // K n n n n 1 3 5 7 3210 n L n n n n n R n n 6 87 4 nnn KDPET 67S // - - - - - -------- -------- -------- -------- ---- - - - - - - - - - - ----------------- ----- --- ----- --- Start:

K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Rep.1000Reset_uut:


;Rep.101000K 0 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Originally waited 34 seconds worst case PCI spec// ;ldlc.340

Reset_deassert:K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Rep.100000K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;Loop.Reset_deassert// Minimum 5 clocks after Reset# deasserted before Frame# asserted PCI Spec Rev 2.2 Section 4.3.2 Reset// Maximum 2**25 clocks after Reset# deasserted before first access//-------------------------------------------------------------------------------------------------------------------------------------Read_Config_Hdr://Read CR2 Should be: 0200XXA1h

K 1 0 1 1 00000000 00000000 00000000 00001000 1010 X 1 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;ldlc.15Read_CR2:

K 1 1 0 1 LLLLLLHL LLLLLLLL XXXXXXXX HLHLLLLH 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Read_CR21 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_Read_CR2

//Read_CR32//Should be: 2774104Ah

K 1 1 1 1 00000000 00000000 00000000 10000000 0000 H 0 H X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

K 1 0 1 1 ######## ######## ######## ######## 1010 H 1 H X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;ldlc.15Read_CR32:

K 1 1 0 1 LLHLLHHH LHHHLHLL LLLHLLLL LHLLHLHL 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Read_CR32K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


Write_CR5://Set MBA Register

K 1 1 1 1 00000000 00000000 00000000 00010100 0000 X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

K 1 0 1 1 ######## ######## ######## ######## 1011 H 1 H X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;ldlc.15target_ready_1:

K 1 1 0 1 10000000 00000000 00000000 00000000 0000 L 0 L X X H X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.target_ready_1K 1 1 0 1 10000000 00000000 00000000 00000000 0000 X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_Write_CR5

//Read_CR5//Should be: 0x80000000



;ldlc.15Read_CR5:

K 1 1 0 1 HLLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL 0000 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Read_CR5K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;JmpFail.No_Read_CR5Write_CR1://Set Memory Space Access






@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_Write_CR1

//Read_CR1//Should be: Read-only Bits 25 and 23 should be H, bits 2,1,0 should be H// K 1 1 1 1 00000000 00000000 00000000 00000100 0000 H 0 H X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX //@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 0 1 1 ######## ######## ######## ######## 1010 H 1 H X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;ldlc.15//Read_CR1:// K 1 1 0 1 XXXXXXHX HXXXXXXX XXXXXXXH XHXXXHHH 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;Match.Read_CR1// K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;JmpFail.No_Read_CR1//Read_CR15



;ldlc.15Read_CR15:

K 1 1 0 1 LLLLLLLL LLLLLLLL LLLLLLLH LLLLLLLL 0000 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Read_CR151 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


//-----------------------------------------------Write_CSR0://Reset MAC; MBA offset = 0


K 1 0 1 1 ######## ######## ######## ######## 0111 H 0 H X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;ldlc.15target_ready_3:



@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_Write_CSR0

//Read_CSR5--NOTE: Don't read until after sw reset to avoid erroneous error messages//Check PHY stopped; MBA offset = 28h

K 1 0 1 1 10000000 00000000 00000000 00101000 0110 X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;ldlc.15

Read_CSR5:K 1 1 0 1 XXXXXXXX XLLLLLLX XXLXXXXX XXXXXXXX 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Match.Read_CSR5K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_Read_CSR5


//------------------------------Wait_Control_reset_done:


;Rep.10//------------------------------

Write_CSR0_1://MBA offset = 0


K 1 0 1 1 ######## ######## ######## ######## 0111 H 0 H X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;ldlc.15target_ready_3a:


;Match.target_ready_3aK 1 1 0 1 00000000 00000000 11000000 00000000 0000 X 0 X X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


//Read_CSR0//Check PHY stopped; MBA offset = 00h


;ldlc.15Read_CSR0:

K 1 1 0 1 XXXXXXXL LXLXXLLX HHLLLLLL LLLLLLLL 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Read_CSR01 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


Write_XR0://Reset PHY; MBA offset = b4h






@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_Write_XR0

//Write to CSR25 (PAR0)= BB, AA, 00, 00 and CSR26 (PAR1) = XX, XX, DD, CCWrite_MAC_Addr:

K 1 1 1 1 10000000 00000000 00000000 10100100 0000 X 0 H X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

K 1 0 1 1 ######## ######## ######## ######## 0111 H 0 H X X X X # X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...



;Match.target_ready_5K 1 1 1 1 10111011 10101010 00000000 00000000 0000 X 0 X X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX;JmpFail.No_Write_CSR25

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 1 1 1 10000000 00000000 00000000 10101000 0000 X 0 H X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...K 1 0 1 1 ######## ######## ######## ######## 0111 H 0 H X X X X # X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;ldlc.15

target_ready_6:K 1 1 0 1 00000000 00000000 11011101 11001100 0000 L 0 L X X H X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Match.target_ready_6K 1 1 1 1 00000000 00000000 11011101 11001100 0000 X 0 X X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


//Write to CSR3; MBA offset = 18h//RX_Ptr = 88000000hWrite_RX_Ptr:







//Write to CSR4; MBA offset = 20h//TX_Ptr = 40000000hWrite_TX_Ptr:








//-------------------------------------------------------------------------------------------------------------------------------------// wait six seconds for PHY reset to complete.

;ldlc.60Wait_PHY_reset_done:


;Rep.100000


;Loop.Wait_PHY_reset_done

//-------------------------------------------------------------------------------------------------------------------------------------//Write_XR0://Loopback_Debug--turn-on internal loopback at XR0 [14] (XLBEN)//vector 69:



;ldlc.15target_ready_8a:// K 1 1 0 1 00000000 00000000 00110010 00000000 1100 L 0 L X X H X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


;Match.target_ready_8a// K 1 1 1 1 00000000 00000000 00110010 00000000 1100 X 0 X X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 1 1 1 00000000 00000000 01000001 00000000 1100 X 0 X X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;JmpFail.No_Write_XR0//------------------------------------------------------------------------------------------------------------------------------------- //Read XCVR PHYID 1//Read_XR2


;ldlc.15Read_XR2:

K 1 1 0 1 XXXXXXXX XXXXXXXX LLLHHHLL LLLLLHLL 1100 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Read_XR2K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_Read_XR2

//Read XCVR PHY ID 2 and Model and Revision No.//Read_XR3


;ldlc.15Read_XR3:

K 1 1 0 1 XXXXXXXX XXXXXXXX LLLLLLLL LLLHLLLL 1100 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...



//Test 10MBps//Read XCVR Configuration and Interrupt Status XR8 [9:8] SPEED/DUPLEX bits to verify speed selection is correctly set to 0 for 10/ 1 for 100//Read_XR8


;ldlc.15Read_XR8:

K 1 1 0 1 XXXXXXXX XXXXXXXX XXXXXXLH XXXXXXXX 1100 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...


@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;JmpFail.No_Read_XR8K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Read XCVR Control Register XR0 [15] XRST to verify PHY reset complete

//Read_XR0K 1 0 1 1 10000000 00000000 00000000 10110100 0110 X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;ldlc.15

Read_XR0:K 1 1 0 1 XXXXXXXX XXXXXXXX LHLLLLLH LLLLLLLL 1100 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Match.Read_XR01 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


//Read_XR10// K 1 0 1 1 10000000 00000000 00000000 11011100 0110 X 0 X X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX //@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;ldlc.15//Read_XR10:// K 1 1 0 1 XXXXXXXX XXXXXXXX XXLLXXLH HXLLLLLL 1100 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;Match.Read_XR10// K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;JmpFail.No_Read_XR10//Write Network Access RegisterWrite_CSR6:



;ldlc.15target_ready_9://No internal loopback

K 1 1 0 1 00000000 00001000 00100000 11001010 0000 L 0 L X X H X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Enable internal loopback// K 1 1 0 1 00000000 00001000 00100100 11001010 0000 L 0 L X X H X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.target_ready_9 K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

// ;Rep.1000//Read_XR10// K 1 0 1 1 10000000 00000000 00000000 11011100 0110 X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX //@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;ldlc.15//Read_XR10:// K 1 1 0 1 XXXXXXXX XXXXXXXX XXLLXXLH HXLLLLLL 1100 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;Match.Read_XR10// 1 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;JmpFail.No_Read_XR10// K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//------------------------------------------------;ldlc.100

//Wait 100 clocks for a PCI REQ# from UUT after TX turned onWait_TX_Desc_REQ:

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_TX_Desc_REQ

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_TX_Desc_REQ//GNT# REQ#

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;ldlc.17//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61Wait_Memory_Access_1:

K 1 L H 0 LHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_Memory_Access_1//Delays driving bus one clock--klunk vs. PCI timing

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_TX_Desc_Access//Read TXDES0--own bit set for STE10

K 1 L L 0 10000000 00000000 00000000 00000000 XXXX 0 0 0 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Read TXDES1, 2, 3//was 32 byte size = 6 bytes x 2 addr + 2 bytes length + 18 data bytes; CSR18 default is 64bytes K 1 L L 0 01100010 00000000 00000000 01000000 LLLL 0 0 0 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Buffer Address K 1 L L 0 10100000 00000000 00000000 00000000 LLLL 0 0 0 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 H L 0 00000000 00000000 00000000 00000000 LLLL 0 0 0 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//--------------------------------------------------------------//Request PCI Access: ;ldlc.100//Wait for UUT to access RX Descriptor Buffer AddressWait_RX_Descriptor_REQ: K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_RX_Descriptor_REQ//GNT# REQ#

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_RX_Desc_REQ

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;ldlc.17//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61Wait_Memory_Access_2:

K 1 L X 0 HLLLHLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_Memory_Access_2//Delays driving bus one clock--klunk vs. PCI timing//Read RXDES0

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_RX_Desc_Access

K 1 L L 0 10000000 00000000 00000000 00000000 XXXX 0 0 0 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Read RXDES1, 2, 3 K 1 L L 0 00000010 00000000 00000000 10000000 LLLL 0 0 0 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 11000000 00000000 00000000 00000000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 H L 0 00000000 00000000 00000000 00000000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//--------------------------------------------------------------//Wait for UUT to access TX Descriptor Buffer Address ;ldlc.100Wait_TX_Buffer_REQ: K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_TX_Buffer_REQ//GNT# REQ#

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_TX_Buffer_REQ

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...Wait_BufferMemory_Access_1:

K 1 L X 0 HLHLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_BufferMemory_Access

K 1 L L 0 11111111 11111111 11111111 11111111 LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 11111111 11111111 00000000 00000000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 10111011 10101010 11011101 11001100 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00000000 00101110 00000000 00000001 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00000010 00000011 00000100 00000101 LLLL 0 0 0 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00000110 00000111 00001000 00001001 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00001010 00001011 00001100 00001101 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00001110 00001111 00010000 00010001 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 10101010 01010101 10101010 01010101 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 10100101 10100101 10100101 10100101 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 01011010 01011010 01011010 01011010 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00000000 11111111 00000000 11111111 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 11111111 00001111 11110000 00000000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 01011010 11110000 00001111 10100101 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00010010 00110100 01010110 01111000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 H L 0 10011010 10111100 11011110 11110000 LLLL 0 0 0 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//--------------------------------------------------------------//Read_CSR5//Check PHY stopped; MBA offset = 28h

K 1 0 1 1 10000000 00000000 00000000 00101000 0110 X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX @@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;ldlc.15Read_CSR5_status_3:

K 1 1 0 1 HHHHHHLL LLHHLHHL LHLHLHLL LLLHLLLL 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.Read_CSR5_status_3

1 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;JmpFail.No_Read_CSR5//----------------------------------------------------//Wait longer for message to complete transmission K 1 H H 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Rep.2000//----------------------------------------------------//Write Network Access RegisterWrite_CSR6_2:



;ldlc.15target_ready_9a://No internal loopback

K 1 1 0 1 00000000 00000000 00000000 11001000 0000 L 0 L X X H X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Enable internal loopback// K 1 1 0 1 00000000 00000000 00000100 11001000 0000 L 0 L X X H X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

;Match.target_ready_9a K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_Write_CSR6

K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//---------------------------------------------------------------------------------------------------------------------------------//Wait 100 clocks for a PCI REQ# from UUT after TX turned on ;ldlc.100Wait_Memory_Access_3:

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_Memory_Access_3

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_TX_Desc_REQ//GNT# REQ#

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...Memory_Access_3://vector 140:

K 1 L H 0 LHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Reread TXDES0--own bit set for STE10

K 1 L L 0 10000000 00000000 00000000 00000000 XXXX 0 0 0 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Reread TXDES1, 2, 3//CSR18 default is 64bytes K 1 L L 0 01100010 00000000 00000000 01000000 LLLL 0 0 0 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Buffer Address K 1 L L 0 10100000 00000000 00000000 00000000 LLLL 0 0 0 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 H L 0 00000000 00000000 00000000 00000000 LLLL 0 0 0 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//----------------------------------------//Withhold grant from UUT: K 1 H H 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Rep.10000

K 1 H H 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//-----------------------------------------

//Wait for UUT to write RX Buffer: ;ldlc.1000Wait_Write_RX_Buffer_REQ: K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_Write_RX_Buffer_REQ//GNT# REQ#

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_RX_Buffer_REQ

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXXRX_Buffer_Access:

K 1 L X 0 HHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HHHHHHHH HHHHHHHH LLLLLLLL LLLLLLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 L L 0 LLHLHHLH LLHLHLHL HHLHLHLH LLHLHLHL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// should be 0xBBAADDC// K 1 L L 0 HLHHHLHH HLHLHLHL HHLHHHLH HHLLHHLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 L L 0 HHLHLLHL HLHLHHLH LLHLHHLH LLHLHHLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 X X 0 LLLLLLLL LLHLHHHL LLLLLLLL LLLLLLLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 X X 0 HLLLLLLL LHLHLLHL HHLHLLHL HHLHLLHL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 X X 0 LLLLLLHL LLLLLLHH LLLLLHLL LLLLLHLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 X X 0 HHHHHHHH HHHHHHHH HLLLLLLL LHHHHHHH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 X X 0 LLLLLHHL LLLLLHHH LLLLHLLL LLLLHLLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 X X 0 LLHLHHLH LLLLLLLL LHHHHLLL LLLLLHHH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LLLLHLHL LLLLHLHH LLLLHHLL LLLLHHLH LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX K 1 L L 0 HHLLLLHH HHLHLLHL HLLLLHHH HHHHHLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LLLLHHHL LLLLHHHH LLLHLLLL LLLHLLLH LLLL 0 0 0 L X X X L X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX K 1 L L 0 HLLLLHHH HHHHLHHL HHHLLHLH HHLHLHLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HLHLHLHL LHLHLHLH HLHLHLHL LHLHLHLH LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX K 1 L L 0 LLHLLLHL LLHHLLHL HLHLLLLH HLLHLLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HLHLLHLH HLHLLHLH HLHLLHLH HLHLLHLH LLLL 0 0 0 L X X X L X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX K 1 L L 0 LLHLLLHL LLHHLLHL LHLHHLLL LHHLHHLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LHLHHLHL LHLHHLHL LHLHHLHL LHLHHLHL LLLL 0 0 0 L X X X L X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX K 1 H L 0 LLLLLLLL LLHLLLHL HLHLHLLL LLHLHHHL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LLLLLLLL HHHHHHHH LLLLLLLL HHHHHHHH XXXX 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX// K 1 H L 0 LLLLLLLL LLHLLHHL HLHLHLLL LLHLHHHL XXXX 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HHHHHHHH LLLLHHHH HHHHLLLL LLLLLLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LHLHHLHL HHHHLLLL LLLLHHHH HLHLLHLH LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 LLLHLLHL LLHHLHLL LHLHLHHL LHHHHLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 L L 0 HLLHHLHL HLHHHHLL HHLHHHHL HHHHLLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 H L 0 LLLHLLHL LLHHLHLL LHLHLHHL LHHHHLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

// K 1 H L 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

;ldlc.100

//Wait 100 clocks for a PCI REQ# from UUT after RX data receivedWait_TX_BUF_REQ_2: K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_TX_BUF_REQ_2//GNT# REQ#


;JmpFail.No_TX_Desc_REQ

//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61//Read TX Buffer Address = 0xA0000000Wait_Memory_Access_4_2:

K 1 L H 0 HLHLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;JmpFail.No_BufferMemory_Access K 1 L L 0 11111111 11111111 11111111 11111111 LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

K 1 L L 0 11111111 11111111 00000000 00000000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 10111011 10101010 11011101 11001100 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00000000 00101110 00000000 00000001 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00000010 00000011 00000100 00000101 LLLL 0 0 0 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00000110 00000111 00001000 00001001 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00001010 00001011 00001100 00001101 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00001110 00001111 00010000 00010001 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 10101010 01010101 10101010 01010101 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 10100101 10100101 10100101 10100101 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 01011010 01011010 01011010 01011010 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00000000 11111111 00000000 11111111 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 11111111 00001111 11110000 00000000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 01011010 11110000 00001111 10100101 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 L L 0 00010010 00110100 01010110 01111000 LLLL 0 0 0 L X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 H L 0 10011010 10111100 11011110 11110000 LLLL 0 0 0 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//----------------------------------------------------------------

//Wait for UUT to write RX Descriptor with status: ;ldlc.1000Wait_UUT: K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_UUT//GNT# REQ#

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_RX_Desc_REQ

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...Wait_Access:

K 1 L X 0 HLLLHLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

K 1 H L 0 LLLLLLLL LLHLLLHL HLHLHLHH LLHLLHHL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//---------------------------------------------------------------------------------------------------------------------------------

;ldlc.100Wait_Memory_Access_6:

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_Memory_Access_6

K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_TX_Desc_Access//GNT# REQ#

K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...Memory_Access_6:

K 1 L H 0 LHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 H L 0 LLHLHLHL LLLHHLHH LLLLLLLL LLLLLLLL LLLL 0 0 0 L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//---------------------------------------------------------------------------------------------------------------------------------

//Read_CSR5K 1 0 1 1 10000000 00000000 00000000 00101000 0110 X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;ldlc.15

Read_CSR5_status_2:K 1 1 0 1 HHHHHHLL LHHHLLLH HHLHLHLH LHLHLLLL 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Match.Read_CSR5_status_21 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


K 1 H H 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//Read_XR10K 1 0 1 1 10000000 00000000 00000000 11011100 0110 X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;ldlc.15

Read_XR10:K 1 1 0 1 XXXXXXXX XXXXXXXX XXLLXXLH HXLHLHLL 1100 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Match.Read_XR101 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//------------------------------------------

;ldlc.100

//Wait 100 clocks for a PCI REQ# from UUT after RX data receivedWait_RX_FCS_WRITE_REQ: K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_RX_FCS_WRITE_REQ//GNT# REQ#


;JmpFail.No_TX_Desc_REQ//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61//Write RX Buffer Location 16/17 (17th/18th writes) Address = 0xc0000040Wait_Memory_Access_4:

K 1 L H 0 LHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... K 1 H L 1 LLLHHLHL LLLHLHHH LLLLLLLL LLLLLLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 H L 1 LLLLLLLL LHLLLHLL LLLHLLLL LLLLHLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//---------------------------------------------------------------------------------------------------------------------------------

//Read_CSR5K 1 0 1 1 10000000 00000000 00000000 00101000 0110 X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;ldlc.15

Read_CSR5_status:K 1 1 0 1 HHHHHHLL LHHHLLLH HHLHLHLH LHLHLLLL 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...;Match.Read_CSR5_status1 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX


K 1 H H 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...

//---------------------------------------------------------------------------------------------------------------------------------// ;ldlc.100//Wait 100 clocks for a PCI REQ# from UUT after TX turned on//Wait_Memory_Access_5:// K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;Match.Wait_Memory_Access_5// K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;JmpFail.No_RX_Desc_REQ//GNT# REQ#// K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Write to RX Desc0//Memory_Access_5:// K 1 L H 0 HLLLHLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// K 1 H L 0 LLLLLLLL LHLLLHLL LLLHLLHH LLLLLLLL LLLL 0 0 0 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//---------------------------------------------------------------------------------------------------------------------------------//---------------------------------------------------------------------------------------------------------------------------------//Wait for UUT to write TX Descriptor with status:// ;ldlc.1000//Wait_UUT:// K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;Match.Wait_UUT//GNT# REQ#// K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;JmpFail.No_TX_Desc_REQ// K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Wait_Access:// K 1 L X 0 LHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX//@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...Finish:// K 1 H L 0 LLLHHLHL LLLHLHHH LLLLLLLL LLLLLLLL LLLL 0 0 0 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

K 1 H H 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;halt

//---------------------------------------------------------------------------------------------------------------------------------//Add change to set to high speed on PHY and jump to waiting for descriptor access

//-------------------------------------------------------------------------------------------------------------------------------------// ;jmp.Reset_uut //continuous loop//-------------------------------------------------------------------------------------------------------------------------------------

//vector 207//Error Detection:No_Read_CR2:

1 1 1 0 1 LLLLLLHL LLLLLLLL XXXXXXXX HLHLLLLH 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Read_CR32:

1 1 1 0 1 LLHLLHHH LHHHLHLL LLLHLLLL LHLLHLHL 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Write_CR5:

1 1 1 0 1 10000000 00000000 00000000 00000000 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Read_CR5:

1 1 1 0 1 HLLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL 0000 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Write_CR1:

1 1 1 0 1 00000000 00000000 00000000 00000111 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;halt//No_Read_CR1:// 1 1 1 0 1 XXXXXXHX HXXXXXXX XXXXXXXH XHXXXHHH 0000 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX// ;haltNo_Read_CR15:

1 1 1 0 1 LLLLLLLL LLLLLLLL LLLLLLLH LLLLLLLL 0000 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Read_CSR5:

1 1 1 0 1 HHHHHHHH HHHHHHHH HHHHHHHH HHHHHHHH 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Read_CSR0:

1 1 1 0 1 XXXXXXXX LXLXXLLX HHLLLLLL LLLLLLLL 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Write_CSR0:

1 1 1 0 1 00000000 00000000 00000000 00000001 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Write_XR0:

1 1 1 0 1 00000000 00000000 10000000 00000000 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;halt

No_Write_CSR25: 1 1 1 0 1 10111011 10101010 00000000 00000000 0000 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

;haltNo_Write_CSR26:

1 1 1 0 1 00000000 00000000 11011101 11001100 0000 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;halt

No_Write_CSR3: 1 1 1 0 1 10001000 00000000 00000000 00000000 0000 L 0 L X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;halt

No_Write_CSR4: 1 1 1 0 1 01000000 00000000 00000000 00000000 0000 L 0 L X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;halt

No_Read_XR2: 1 1 1 0 1 XXXXXXXX XXXXXXXX LLLHHHLL LLLLLHLL 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX

;haltNo_Read_XR3:

1 1 1 0 1 XXXXXXXX XXXXXXXX LLLLLLLL LLLHLLLL 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Read_XR8:

1 1 1 0 1 XXXXXXXX XXXXXXXX XXXXXXLX XXXXXXXX 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Read_XR0:

1 1 1 0 1 XXXXXXXX XXXXXXXX LLLLLLLL LLLLLLLL 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_Write_CSR6:

K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;halt//vector 226:No_Read_XR10:

1 1 1 0 1 XXXXXXXX XXXXXXXX XXLLXXLH HXLHLHLL 0000 L 0 L X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_TX_Desc_REQ: 1 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_TX_Desc_Access:

1 1 L H 0 LHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHH 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_RX_Desc_REQ: K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_RX_Desc_Access: K 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_BufferMemory_Access: 1 1 1 1 1 LLLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL XXXX X 0 X L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_TX_Buffer_REQ: 1 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_TX_Buffer_REQ_2: 1 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_TX_Buffer_REQ_3: 1 1 1 1 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX X 0 X L X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;haltNo_RX_Buffer_REQ: 1 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX ;halt//-------------------------------------------------------------------------------------------------------------------------------------//Don't add below here!//compiler likes line feeds after halt microinstruction

at-spex.comat-spex.com/services/graphics/ste10-100a_test_plan.docx · web view//ste reads tx...

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