assembly language for intel-based computers, 5th edition chapter 2
TRANSCRIPT
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Assembly Language for Intel-BasedComputers, 5th Edition
Chapter 2: IA-32 ProcessorArchitecture
Kip Irvine
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 2
Chapter Overview
• General Concepts• IA-32 Processor Architecture• IA-32 Memory Management• Components of an IA-32 Microcomputer• Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 3
General Concepts
•Basic microcomputer design• Instruction execution cycle•Reading from memory•How programs run
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 4
Basic Microcomputer Design
• clock synchronizes CPU operations• control unit (CU) coordinates sequence of execution steps• ALU performs arithmetic and bitwise processing
Central Processor Unit(CPU)
Memory StorageUnit
registers
ALU clock
I/ODevice
#1
I/ODevice
#2
data bus
control bus
address bus
CU
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 5
Clock
•synchronizes all CPU and BUS operations•machine (clock) cycle measures time of a single
operation•clock is used to trigger events
one cycle
1
0
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 6
What's Next
• General Concepts• IA-32 Processor Architecture• IA-32 Memory Management• Components of an IA-32 Microcomputer• Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 7
Instruction Execution Cycle
• Fetch• Decode• Fetch operands• Execute• Store output
I-1 I-2 I-3 I-4
PC program
I-1instructionregister
op1op2
memory fetch
ALU
registers
writ
e
decode
execute
read
writ
e
(output)
registers
flags
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 8
Multi-Stage Pipeline
• Pipelining makes it possible for processor to executeinstructions in parallel
• Instruction execution divided into discrete stages
S1 S2 S3 S4 S51
Cyc
les
Stages
S6
23456789
101112
I-1
I-2
I-1
I-2
I-1
I-2
I-1
I-2
I-1
I-2
I-1
I-2
Example of a non-pipelined processor.Many wasted cycles.
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 9
Pipelined Execution
• More efficient use of cycles, greater throughput of instructions:
S1 S2 S3 S4 S51
Cyc
les
Stages
S6
2
34567
I-1I-2 I-1
I-2 I-1I-2 I-1
I-2 I-1I-2 I-1
I-2
For k states and ninstructions, thenumber of requiredcycles is:
k + (n –1)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 10
Wasted Cycles (pipelined)
• When one of the stages requires two or more clock cycles, clockcycles are again wasted.
S1 S2 S3 S4 S51
Cyc
les
Stages
S6
234567
I-1I-2I-3
I-1I-2I-3
I-1I-2I-3
I-1
I-2 I-1I-1
89
I-3 I-2I-2
exe
1011
I-3I-3
I-1
I-2
I-3
For k states and ninstructions, thenumber of requiredcycles is:
k + (2n –1)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 11
Superscalar
A superscalar processor has multiple execution pipelines. In thefollowing, note that Stage S4 has left and right pipelines (u and v).
S1 S2 S3 u S51
Cyc
les
Stages
S6
234567
I-1I-2I-3I-4
I-1I-2I-3I-4
I-1I-2I-3I-4
I-1
I-3 I-1I-2 I-1
v
I-2
I-4
S4
89
I-3I-4
I-2I-3
10 I-4
I-2
I-4
I-1
I-3
For k states and ninstructions, thenumber of requiredcycles is:
k + n
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 12
Reading from Memory
• Multiple machine cycles are required when reading from memory,because it responds much more slowly than the CPU. The steps are:• address placed on address bus• Read Line (RD) set low• CPU waits one cycle for memory to respond• Read Line (RD) goes to 1, indicating that the data is on the data
busCycle 1 Cycle 2 Cycle 3 Cycle 4
Data
Address
CLK
ADDR
RD
DATA
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 13
Cache Memory
•High-speed expensive static RAM both inside andoutside the CPU.•Level-1 cache: inside the CPU•Level-2 cache: outside the CPU
•Cache hit: when data to be read is already in cachememory
•Cache miss: when data to be read is not in cachememory.
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 14
How a Program Runs
Operatingsystem
User
Currentdirectory
Systempath
Directoryentry
sends programname to
gets startingcluster from
searches forprogram in
loads andstarts
Program
returns to
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 15
Multitasking
•OS can run multiple programs at the same time.•Multiple threads of execution within the same
program.•Scheduler utility assigns a given amount of CPU time
to each running program.•Rapid switching of tasks
•gives illusion that all programs are running at once•the processor must support task switching.
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 16
IA-32 Processor Architecture
•Modes of operation•Basic execution environment•Floating-point unit• Intel Microprocessor history
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 17
Modes of Operation
•Protected mode•native mode (Windows, Linux)
•Real-address mode•native MS-DOS
•System management mode•power management, system security, diagnostics
•Virtual-8086 mode•hybrid of Protected•each program has its own 8086 computer
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 18
Basic Execution Environment
•Addressable memory•General-purpose registers• Index and base registers•Specialized register uses•Status flags•Floating-point, MMX, XMM registers
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 19
Addressable Memory
•Protected mode•4 GB•32-bit address
•Real-address and Virtual-8086 modes•1 MB space•20-bit address
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 20
General-Purpose Registers
CS
SS
DS
ES
EIP
EFLAGS
16-bit Segment Registers
EAX
EBX
ECX
EDX
32-bit General-Purpose Registers
FS
GS
EBP
ESP
ESI
EDI
Named storage locations inside the CPU, optimized forspeed.
Used for arithmetic and data movement.
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 21
Accessing Parts of Registers
•Use 8-bit name, 16-bit name, or 32-bit name•Applies to EAX, EBX, ECX, and EDX
AH AL
16 bits
8
AX
EAX
8
32 bits
8 bits + 8 bits
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 22
Index and Base Registers
•Some registers have only a 16-bit name for theirlower half:
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 23
Some Specialized Register Uses (1 of 2)
•General-Purpose•EAX –accumulator•ECX –loop counter•ESP –stack pointer•ESI, EDI –index registers•EBP –extended frame pointer (stack)
•Segment•CS –code segment•DS –data segment•SS –stack segment•ES, FS, GS - additional segments
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 24
Some Specialized Register Uses (2 of 2)
•EIP –instruction pointer•EFLAGS
•status and control flags•each flag is a single binary bit
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 25
Status Flags•Carry
•unsigned arithmetic out of range•Overflow
•signed arithmetic out of range•Sign
•result is negative•Zero
•result is zero•Auxiliary Carry
•carry from bit 3 to bit 4 in an 8-bit operand•Parity
•sum of 1 bits is an even number
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 26
Floating-Point, MMX, XMM Registers
• Eight 80-bit floating-point data registers
•ST(0), ST(1), . . . , ST(7)
•arranged in a stack
•used for all floating-pointarithmetic
• Eight 64-bit MMX registers
• Eight 128-bit XMM registers for single-instruction multiple-data (SIMD) operations
ST(0)
ST(1)
ST(2)
ST(3)
ST(4)
ST(5)
ST(6)
ST(7)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 27
Intel Microprocessor History
• Intel 8086, 80286• IA-32 processor family•P6 processor family•CISC and RISC
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 28
Early Intel Microprocessors
• Intel 8080•64K addressable RAM•8-bit registers•CP/M operating system•S-100 BUS architecture•8-inch floppy disks!
• Intel 8086/8088• IBM-PC Used 8088•1 MB addressable RAM•16-bit registers•16-bit data bus (8-bit for 8088)•separate floating-point unit (8087)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 29
The IBM-AT
• Intel 80286•16 MB addressable RAM•Protected memory•several times faster than 8086•introduced IDE bus architecture•80287 floating point unit
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 30
Intel IA-32 Family
•Intel386•4 GB addressable RAM, 32-bit registers,
paging (virtual memory)
•Intel486•instruction pipelining
•Pentium•superscalar, 32-bit address bus, 64-bit
internal data path
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 31
Intel P6 Family
•Pentium Pro•advanced optimization techniques in microcode
•Pentium II•MMX (multimedia) instruction set
•Pentium III•SIMD (streaming extensions) instructions
•Pentium 4 and Xeon•Intel NetBurst micro-architecture, tuned for
multimedia
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 32
CISC and RISC
• CISC –complex instruction set• large instruction set•high-level operations• requires microcode interpreter•examples: Intel 80x86 family
• RISC –reduced instruction set•simple, atomic instructions•small instruction set•directly executed by hardware•examples:
•ARM (Advanced RISC Machines)•DEC Alpha (now Compaq)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 33
What's Next
• General Concepts• IA-32 Processor Architecture• IA-32 Memory Management• Components of an IA-32 Microcomputer• Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 34
IA-32 Memory Management
•Real-address mode•Calculating linear addresses•Protected mode•Multi-segment model•Paging
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 35
Real-Address mode
•1 MB RAM maximum addressable•Application programs can access any area
of memory•Single tasking•Supported by MS-DOS operating system
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 36
Segmented Memory
Segmented memory addressing: absolute (linear) address is acombination of a 16-bit segment value added to a 16-bit offset
00000
10000
20000
30000
40000
50000
60000
70000
80000
90000
A0000
B0000
C0000
D0000
E0000
F0000
8000:0000
8000:FFFF
seg ofs
8000:0250
0250
linea
ra d
dre s
ses
one segment
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 37
Calculating Linear Addresses
•Given a segment address, multiply it by 16 (add ahexadecimal zero), and add it to the offset
•Example: convert 08F1:0100 to a linear address
Adjusted Segment value: 0 8 F 1 0
Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 38
Your turn . . .
What linear address corresponds to the segment/offsetaddress 028F:0030?
028F0 + 0030 = 02920
Always use hexadecimal notation for addresses.
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 39
Your turn . . .
What segment addresses correspond to the linear address28F30h?
Many different segment-offset addresses can produce thelinear address 28F30h. For example:
28F0:0030, 28F3:0000, 28B0:0430, . . .
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 40
Protected Mode (1 of 2)
•4 GB addressable RAM•(00000000 to FFFFFFFFh)
•Each program assigned a memory partition whichis protected from other programs
•Designed for multitasking•Supported by Linux & MS-Windows
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 41
Protected mode (2 of 2)
•Segment descriptor tables•Program structure
•code, data, and stack areas•CS, DS, SS segment descriptors•global descriptor table (GDT)
•MASM Programs use the Microsoft flat memorymodel
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 42
Flat Segment Model
• Single global descriptor table (GDT).• All segments mapped to entire 32-bit address space
00000000
FFFFFFFF(4GB)
physicalRA
M00000000
Segment descriptor, in theGlobal Descriptor Table
00040 - - - -
base address limit access
00040000
notused
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 43
Multi-Segment Model
• Each program has a local descriptor table (LDT)•holds descriptor for each segment used by the program
3000
RAM
00003000
Local Descriptor Table
000200008000 000A00026000 0010
base limit access
8000
26000
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 44
Paging
•Supported directly by the CPU•Divides each segment into 4096-byte blocks called
pages•Sum of all programs can be larger than physical
memory•Part of running program is in memory, part is on disk•Virtual memory manager (VMM) –OS utility that
manages the loading and unloading of pages•Page fault –issued by CPU when a page must be
loaded from disk
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 45
What's Next
• General Concepts• IA-32 Processor Architecture• IA-32 Memory Management• Components of an IA-32 Microcomputer• Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 46
Components of an IA-32 Microcomputer
•Motherboard•Video output•Memory• Input-output ports
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 47
Motherboard
•CPU socket•External cache memory slots•Main memory slots•BIOS chips•Sound synthesizer chip (optional)•Video controller chip (optional)• IDE, parallel, serial, USB, video, keyboard, joystick,
network, and mouse connectors•PCI bus connectors (expansion cards)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 48
Intel D850MD Motherboard
dynamic RAM
Pentium 4 socket
Speaker
IDE drive connectors
mouse, keyboard,parallel, serial, and USBconnectors
AGP slot
Battery
Video
Power connector
memory controller hub
Diskette connector
PCI slots
I/O Controller
Firmware hub
Audio chip
Source: Intel® Desktop Board D850MD/D850MV Technical ProductSpecification
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 49
Video Output
•Video controller•on motherboard, or on expansion card•AGP (accelerated graphics port technology)*
•Video memory (VRAM)•Video CRT Display
•uses raster scanning•horizontal retrace•vertical retrace
•Direct digital LCD monitors•no raster scanning required
* This link may change over time.
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 50
Sample Video Controller (ATI Corp.)
•128-bit 3D graphicsperformance powered byRAGE™ 128 PRO
•3D graphics performance
• Intelligent TV-Tuner withDigital VCR
•TV-ON-DEMAND™
• Interactive Program Guide
•Still image and MPEG-2 motionvideo capture
•Video editing
•Hardware DVD video playback
•Video output to TV or VCR
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 51
Memory• ROM
• read-only memory• EPROM
• erasable programmable read-only memory• Dynamic RAM (DRAM)
• inexpensive; must be refreshed constantly• Static RAM (SRAM)
• expensive; used for cache memory; no refresh required• Video RAM (VRAM)
• dual ported; optimized for constant video refresh• CMOS RAM
• complimentary metal-oxide semiconductor• system setup information
• See: Intel platform memory (Intel technology brief: link address maychange)
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 52
Input-Output Ports
•USB (universal serial bus)•intelligent high-speed connection to devices•up to 12 megabits/second•USB hub connects multiple devices•enumeration: computer queries devices•supports hot connections
•Parallel•short cable, high speed•common for printers•bidirectional, parallel data transfer•Intel 8255 controller chip
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 53
Input-Output Ports (cont)
•Serial•RS-232 serial port•one bit at a time•uses long cables and modems•16550 UART (universal asynchronous receiver
transmitter)•programmable in assembly language
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 54
What's Next
• General Concepts• IA-32 Processor Architecture• IA-32 Memory Management• Components of an IA-32 Microcomputer• Input-Output System
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 55
Levels of Input-Output
• Level 3: Call a library function (C++, Java)•easy to do; abstracted from hardware; details hidden•slowest performance
• Level 2: Call an operating system function•specific to one OS; device-independent•medium performance
• Level 1: Call a BIOS (basic input-output system) function•may produce different results on different systems•knowledge of hardware required•usually good performance
• Level 0: Communicate directly with the hardware•May not be allowed by some operating systems
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 56
Displaying a String of Characters
When a HLL programdisplays a string ofcharacters, thefollowing steps takeplace:
Application Program
OS Function
BIOS Function
Hardware Level 0
Level 1
Level 2
Level 3
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 57
ASM Programming levels
ASM Program
OS Function
BIOS Function
Hardware Level 0
Level 1
Level 2
ASM programs can perform input-output ateach of the following levels:
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 58
Summary
•Central Processing Unit (CPU)•Arithmetic Logic Unit (ALU)• Instruction execution cycle•Multitasking•Floating Point Unit (FPU)•Complex Instruction Set•Real mode and Protected mode•Motherboard components•Memory types• Input/Output and access levels
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Irvine, Kip R. Assembly Language for Intel-Based Computers 5/e, 2007. Web site Examples 59
42 69 6E 61 72 79