aspire 4551 g

1. ABCDE11Compal Confidential 22PEW71/91/51 M/B Schematics Document Intel Arrandale Processor with DDRIII + Ibex Peak-M NV N11P-GV2H and N11P-GE2010-06-0733REV:1.0442009/08/01Issued DateCompal Electronics, Inc.Compal Secret DataSecurity Classification2010/08/01Deciphered DateTitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.SCHEMATICS,MB A5893 Rev C401869Date:ABCDSheetWednesday, June 30, 2010 E1of56

2. ABCDEClock GeneratorCompal ConfidentialIDT: 9LVS3199AKLFT Realtek: RTM890N-631-VB-GRTModel Name : NEW71/91 File Name : LA5893P133/120/100/96/14.318MHZ to PCHFan Controlpage 41page 1211PEG(DIS)100MHzPCI-E 2.0x16 5GT/s PER LANEpage 4,5,6,7,8,9CRT(DIS) FDI x8 (UMA) CRT Conn.page 30 2LVDS Conn.page 29DMI x4100MHz1GB/s x4MINI Card x2 WLAN, WWAN USB port 12,13 page 34port 1page 38DC/DC Interface CKT. page 424Power Circuit DC/DC page 43~533.3V 24MHzALC272XSPIpage 39port 0SATA HDD Conn. page31TI TPS6017 40 pagepage 13SATA CDROM Conn. page 31LPC BUS333MHzInt. SpeakerENE KB926Phone Jack x 2page 40page 40page 36USB/B 2 Ports USB Port 0,2 page 35 Card Reader USB Port9 RTS5160Audio AMPport 1Touch PadInt.KBDpage 37page 37CPU XDP page 35page 5EC ROMLS-5893Ppage 37LS-5894PPower/BPCH XDPLID_SW/B4page 38page 21LS-5895P 3G USB Port10,132009/08/01Issued DateCompal Electronics, Inc.Compal Secret DataSecurity Classificationpage 352010/08/01Deciphered DateTitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:Apage 35 2SPI ROM x1page 32LS-5896P Power On/Off CKT.USB port 9page 283.3V 48MHzBCM57780Sub-board LS-5891P page 15USB port 8page 35HDA Codecpage 13,14,15,16 17,18,19,20,21100MHzpage 33RTC CKT.USB port 11LAN(GbE)RJ453Card Reader RTS5160PCH100MHzSATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)CMOS CameraHD AudioIntel Ibex Peak-Mpage 30PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)Bluetooth ConnUSB port 1USBx14LVDS(UMA) CRT(UMA) TMDS(UMA)HDMI Level ShiftUSB conn x3 USB port 0, 2 on USB/B page 35100MHz2.7GT/spage 28HDMI(UMA)port 2page 10,111.5V DDRIII 800/1066Processor rPGA988ALVDS(DIS)HDMI Conn.BANK 0, 1, 2, 3Arrandale (UMA/DIS)page 22,23,24,25,26,27HDMI(DIS)Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual ChannelIntel133MHzNV N11P-GV2H NV N11P-GEBCDSCHEMATICS,MB A5893 Document NumberRev C401869 SheetWednesday, June 30, 2010 E2of56 3. ABCDVoltage Rails Power PlaneS1DescriptionS3VINN/AN/AN/ABattery power supply (12.6V)N/AN/AN/AB+AC or battery power rail for power circuit.N/AN/AN/A+CPU_CORECore voltage for CPUONOFFOFF+VGA_CORECore voltage for GPUONOFFOFF+VGFX_CORECore voltage for Arrandale GPU (only for arrandaleCPU)ONOFFOFF+0.75VS+0.75VP to +0.75VS switched power rail for DDR terminatorONOFFOFF+1.0VSDGPU+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPUONOFF+1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU ONOFF+1.05VS_VTT to +1.05VS_PCH power for PCHONOFFOFF+1.5V+1.5VP to +1.5V power rail for DDRIIIONONOFF+1.5VS+1.5V to +1.5VS switched power railONOFFOFFVcc Ra/Rc/Re+1.5VSDGPU+1.5VS to +1.5VSDGPU switched power rail for GPUONOFFOFFBoard ID+1.8VS(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ONOFFOFF+3VALW+3VALW always on power railONONON*+3VALW_EC+3VALW always to KBCONONON*+3V_LAN+3VALW to +3V_LAN power rail for LANONONON*+3V+3VALW to +3V power rail for PCH (Short Jumper)ONONON*+3VS+3VALW to +3VS power railONOFFOFF+5VALW+5VALWP to +5VALW power railONONON*+5V+5VALW to +5V switched power rail for PCH (Short resister)ONONON*0 1 2 3 4 5 6 7+5VS+5VALW to +5VS switched power railONOFF+VSBP to +VSB always on power rail for sequence controlONONON*+RTCVCCRTC powerONONON+V+VSClockOFF+VSB+VALWOFF+1.05VS_PCHSLP_S1# SLP_S3# SLP_S4# SLP_S5#OFF+1.05VS_VTT2Adapter power supply (19V)BATT+1SIGNALSTATES5EHIGHHIGHHIGHHIGHONONONONS1(Power On Suspend)LOWHIGHHIGHHIGHONONONLOWS3 (Suspend to RAM)LOWLOWHIGHHIGHONONOFFOFFS4 (Suspend to Disk)LOWLOWLOWHIGHONOFFOFFOFFS5 (Soft OFF)LOWLOWLOWLOWONOFFOFFOFFFull ONBoard ID / SKU ID Table for AD channelDeviceDeviceBoard ID 0 1 2 3 4 5 6 70001 011X bAddressPCH SM Bus address DeviceAddressClock Generator (9LVS3199AKLFT, RTM890N-631-VB-GRT)1001 000XbDDR DIMM21001 010XbV AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 VBTO Item UMA ONLY Discrete Discrete Only VRAM Switchable UMA ONLY & OPTIMUS 3G Blue Tooth OPTIMUS NonSG SKUNEW71 NEW91 N11P-GV2H N11P-GE1 N11P-GV2H-A2 N11P-GV2H-A3 Non OPT SKU SG or OPTUSB Port Table USB 2.0 USB 1.1 Port3UHCI0BOM Config move to page 56UHCI1 EHCI1 UHCI2VRAM BOM Config X7621@: X76198BOL21 ALT. GROUP PARTS 1G SAMUHCI3X7622@UHCI4X76198BOL22V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 VBTO Option Table PCB Revision 0.1 0.2 0.3 1.01101 0010bDDR DIMM0V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 VBOARD ID TableEC SM Bus2 addressAddressSmart Battery3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC2Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.EC SM Bus1 address1ALT. GROUP PARTS 1G HYNEHCI2UHCI5 UHCI60 1 2 3 4 5 6 7 8 9 10 11 12 133 External USB Port USB/B (Right Side) USB Port (Left Side) USB/B (Right Side)Camera Card Reader SIM Card Blue Tooth Mini Card(WLAN) Mini Card(GPS)BOM Structure UMA ONLY@ DIS@ DIS ONLY@ X76@ SG@ UMOP@ 3G@ BT@ OPT@ NonSG@ 71@ 91@ GV2H@ GE1@ GV2HA2@ GV2HA3@ NonOPT@ SGOPT@3VRAM P/N : Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!) Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO! )442009/08/01Issued DateCompal Electronics, Inc.Compal Secret DataSecurity ClassificationDeciphered Date2010/08/01TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:ABCDSCHEMATICS,MB A5893 Document NumberRev C401869 SheetWednesday, June 30, 2010 E3of56 4. 54321JCPU1E PEG_IRCOMPR485 12 49.9_0402_1%EXP_RBIASR493 12 750_0402_1%RSVD32 RSVD33DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]B24 D23 B23 A22DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]DMI_HTX_PRX_N0 DMI_HTX_PRX_N1 DMI_HTX_PRX_N2 DMI_HTX_PRX_N3D24 G24 F23 H23DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3D25 F24 E23 G23DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7]H_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7D22 C21 D20 C18 G22 E20 F20 G19FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7]15 H_FDI_FSYNC0 15 H_FDI_FSYNC1F17 E17FDI_FSYNC[0] FDI_FSYNC[1]15 H_FDI_INTC17FDI_INT15 H_FDI_LSYNC0 15 H_FDI_LSYNC1F18 D17FDI_LSYNC[0] FDI_LSYNC[1]CPCI EXPRESS -- GRAPHICSE22 D21 D19 D18 G21 E19 F21 G18Intel(R) FDIH_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN715milDMIDMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3DA24 C23 B22 A21BPEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIASB26 A26 B27 A25PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31PEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0C586 C561 C584 C559 C582 C557 C580 C555 C578 C553 C576 C551 C574 C549 C572 C5471 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ [email protected]_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7KPEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]10milL34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0C585 C560 C583 C558 C581 C556 C579 C554 C577 C552 C575 C550 C573 C548 C571 C5461 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ [email protected]_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7KPEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30AJ13 AJ12RSVD34 RSVD35AH25 AK26RSVD36 RSVD_NCTF_37AL26 AR2RSVD38 RSVD39RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF (CFD Only) SB_DIMM_VREF (CFD Only) RSVD11 RSVD12 RSVD13 RSVD14AJ26 AJ271@R61 3.01K_0402_1% R60 3.01K_0402_1%1 DIS@ @ 1R59 3.01K_0402_1%1@2CFG02 2CFG3 CFG42CFG7WW41 Recommend not pull down PCIE2.0 Jitter is over on ES1AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86B19 A19R501 0_0402_5%DMI_PTX_HRX_N[0..3] 15 DMI_PTX_HRX_P[0..3] 15H_FDI_TXN[0..7] H_FDI_TXP[0..7]15 15RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9RSVD21 RSVD22RSVD_NCTF_23 RSVD_NCTF_24RSVD26 RSVD27A34 A33RSVD_NCTF_28 RSVD_NCTF_29C35 B35PEG_HTX_C_GRX_N[0..15] 22 PEG_HTX_C_GRX_P[0..15] 22E15 F15 A2 D15 C15 AJ15 AH15RSVD19 RSVD20J29 J28PEG_GTX_C_HRX_N[0..15] 22 PEG_GTX_C_HRX_P[0..15] 22RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65RSVD17 RSVD18C1 A3DMI_HTX_PRX_N[0..3] 15 DMI_HTX_PRX_P[0..3] 15AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32RSVD15 RSVD16AC9 AB9H_RSVD17_R H_RSVD18_RA20 B20 U9 T9R497 0_0402_5% @ 1 2 @ 1 2AT3 AR1RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58DAP1 AT2RSVD_NCTF_42 RSVD_NCTF_43R58 3.01K_0402_1%RSVD_NCTF_40 RSVD_NCTF_41RESERVEDJCPU1A DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3RSVD_NCTF_30 RSVD_NCTF_31IC,AUB_CFD_rPGA,R1P0 CONN@VSSCR146 0_0402_5% RSVD64_R 2 @ @ RSVD65_R 2 R147 0_0402_5%1 1BAP34IC,AUB_CFD_rPGA,R1P0 CONN@AeDP Signals Mapping eDP Singal PEG Singals PEG_HTX_C_GRX_P15 eDP_TX0 eDP_TX#0 PEG_HTX_C_GRX_N15 eDP_TX1 PEG_HTX_C_GRX_P14 eDP_TX#1 PEG_HTX_C_GRX_N14 eDP_TX2 PEG_HTX_C_GRX_P13 eDP_TX#2 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_P12 eDP_TX3 eDP_TX#3 PEG_HTX_C_GRX_N12 eDP_AUX PEG_GTX_C_HRX_P13 eDP_AUX# PEG_GTX_C_HRX_N13 eDP_HPD# PEG_GTX_C_HRX_P12H_FDI_FSYNC0 H_FDI_FSYNC1R519 1 DIS ONLY@ 2 R517 1 DIS ONLY@ 21K_0402_5% 1K_0402_5%H_FDI_INTR513 1 DIS ONLY@ 21K_0402_5%H_FDI_LSYNC0 H_FDI_LSYNC1Lane Reversal PEG_HTX_C_GRX_P0 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_N3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_P3R520 1 DIS ONLY@ 2 R515 1 DIS ONLY@ 2CFG0 - PCI-Express Configuration SelectCFG4 - Display Port Presence*1:Single PEG 0:Bifurcation enabled*1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port1K_0402_5% 1K_0402_5%CheckList0.8 1.22 Auburndale Graphics DisableCFG3 - PCI-Express Static Lane Reversal*:Default*1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...ACompal Electronics, Inc.Compal Secret DataSecurity Classification 2009/08/01Issued DateDeciphered Date2010/08/01TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:5432SCHEMATICS,MB A5893 Document NumberRev C401869 Wednesday, June 30, 2010Sheet 14of56 5. 54321JCPU1BAT23COMP3R507 21 20_0402_1%H_COMP2AT24COMP2R521 21 49.9_0402_1%H_COMP1G16COMP1R503 21 49.9_0402_1%H_COMP0AT26COMP0SKTOCC#_RAH24SKTOCC#T7@PADDH_CATERR#H_PECI_R2AT15CATERR#THERMAL THERMALR547 1 0_0402_5%18 H_PECIAK14PECIBCLK BCLK#A16 B16BCLK_ITP BCLK_ITP#E16 D16DPLL_REF_SSCLK DPLL_REF_SSCLK#A18 A17CLK_CPU_XDP CLK_CPU_XDP#AR30 AT30PEG_CLK PEG_CLK#CLK_CPU_BCLK 18 CLK_CPU_BCLK# 18SM_DRAMRST#CLK_CPU_DMI 14 CLK_CPU_DMI# 14THERMTRIP#AP26RESET_OBS#R123 1 0_0402_5%C2H_PM_SYNC_RAL15PM_SYNCR122 1 0_0402_5%15 H_PM_SYNC2H_CPUPWRGD_1AN14VCCPWRGOOD_1R121 1 0_0402_5%18 H_CPUPWRGDR150 1 0_0402_5%15 PM_DRAM_PWRGD2R489 1 0_0402_5%VCCPWRGOOD_0AK132 H_VTTPWRGD_R 0_0402_5%SM_DRAMPWROK VTTPWRGOODAM26TAPPWRGOODPLT_RST#_R2AM15H_PWRGD_XDP_RAL14+1.05VS_VTT2009/08/14 #425302 CP_S3PowerReduction WhitePaper_Rev1.0SM_DRAMRST# 10PM_EXT_TS#[0] PM_EXT_TS#[1]AN15 AP15PM_EXTTS#0 PM_EXTTS#1_RAT28 AP27XDP_PRDY# XDP_PREQ#TCK TMS TRST#AN28 AP28 AT27XDP_TCLK XDP_TMS XDP_TRST#TDI TDO TDI_M TDO_MAT29 AR27 AR29 AP29XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_MDBR#AN25XDP_DBR#_RBPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23RSTIN#1 R5672 100K_0402_5% R539 1 R538 1 R548 1+1.05VS_VTT2 10K_0402_5% 2 10K_0402_5% 2 0_0402_5%SM_RCOMP_0 R578 1 SM_RCOMP_1 R576 1 SM_RCOMP_2 R573 1R89 R496 R495 R90 R62R499 1XDP_TDI_R XDP_TDO_MSM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2XDP_PRDY# XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLKXDP_TRST#AL1 AM1 AN1@ @ @ @ @R488 1 R475 11 1 1 1 151_0402_5% 51_0402_5% 51_0402_5% 51_0402_5% 51_0402_5%2 2 2 2 2PM_EXTTS#0_1 10,112 51_0402_5%2 100_0402_1% 2 24.9_0402_1% 2 130_0402_1% 2 0_0402_5% 2 0_0402_5%@XDP_TDI XDP_TDOR871R480 0_0402_5%2 0_0402_5% XDP_DBRESET#XDP_DBRESET# 15,21 XDP_TDI_M XDP_TDO_RXDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7C@1 R481 1 R4762 2 0_0402_5% 0_0402_5%JTAG MAPPING 2009/09/16 update2009/2/4 #414044 DG Update Rev1.11R125 750_0402_1%STUFF -> R488 ,R475 NO STUFF -> R480 , R481 , R476 STUFF -> R481,R476 NO STUFF -> R488, R475 , R4802IC,AUB_CFD_rPGA,R1P0 CONN@STUFF -> R488 , R480 , R476 NO STUFF -> R475 , R481CPU Only2009/2/4 Delete dampling resistor for power noise and Layout space issue12Scan Chain (Default)GMCH OnlyR126 1 1.5K_0402_1%17,21,32,36 PLT_RST#AN27PM_DRAM_PWRGD_RH_VTTPWRGD 1 @ R540 H_PWRGD_XDPH_CPUPWRGD_02PWR MANAGEMENT PWR MANAGEMENTH_CPURST#2 0_0402_5% 2 0_0402_5%1AK15DDR3 MISCH_THERMTRIP#_R2PROCHOT#R504 1 R510 1DF6SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]JTAG & BPMR124 1 0_0402_5%18 H_THERMTRIP#AN26CLK_CPU_DP_R CLK_CPU_DP#_RCLK_CPU_DP_R CLK_CPU_DP#_RPRDY# PREQ#H_PROCHOT#53 H_PROCHOT#2009/08/14 remove DP REF SSCLK2H_COMP3CLOCKS1 20_0402_1%MISC MISCR512 2+1.05VS_VTTR127 R88 R912 2 2@1 49.9_0402_1% 1 68_0402_5% 1 68_0402_5%H_CATERR# H_PROCHOT# H_CPURST# JP2B2009/8/14 change back to 2KB1APU38 H_VTTPWRGD 25+3VALWMC74VHC1G08DFT2G_SC70-54H_VTTPWRGD_RXDP_OBS2 XDP_OBS31GYXDP_OBS0 XDP_OBS1R550 2K_0402_1% 1 2 R542351 H_VTTPWRGDXDP_PREQ# XDP_PRDY#1K_0402_1%2XDP_OBS4 XDP_OBS5#425302 CP_S3PowerReduction WhitePaper_Rev0.7XDP_OBS6 XDP_OBS7+3VALWP G5Need to check Voltage Level+1.5V_13R152 @ 1.1K_0402_1%R151H_VTTPWRGD1MC74VHC1G08DFT2G_SC70-5R197 1K_0402_5% H_CPUPWRGD 1 2 H_PWRGOOD_R R84 1 2 PBTN_OUT#_XDP 15,21,36 PBTN_OUT# 0_0402_5% +1.05VS_VTT H_PWRGD_XDP 1 C211 @ 21 SMB_DATA_S3 0.1U_0402_16V4Z 21 SMB_CLK_S3 21.5K_0402_1%XDP_TCLK22AAY114U11 B 21 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59XDP ConnectorGND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 CONN@BH_RESET#_RR83 1K_0402_5% 1 2 @ 1 2H_CPURST# PLT_RST#R85 0_0402_5% CLK_CPU_XDP CLK_CPU_XDP# H_RESET#_R XDP_DBRESET# XDP_TDO XDP_TRST# XDP_TDI XDP_TMS+1.05VS_VTT2 R81 1K_0402_5% 2 R79 51_0402_5%1 1+3VS +1.05VS_VTTASAMTE_BSH-030-01-L-D-A11PM_DRAM_PWRGD_R2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND172R1492009/04/23 Intel CRB 1.55 Update Change R68 to 1.1K_1%, R71 to 3.01K_1%Compal Electronics, Inc.Compal Secret DataSecurity Classification750_0402_1%2R148 @ 3.01K_0402_1%2009/08/01Issued DateDeciphered Date2010/08/01TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:5432SCHEMATICS,MB A5893 Document NumberRev C401869 Wednesday, June 30, 2010Sheet 15of56 6. 4CB10 DDR_A_BS0 10 DDR_A_BS1 10 DDR_A_BS210 DDR_A_CAS# 10 DDR_A_RAS# 10 DDR_A_WE#A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14DDR_A_BS0 DDR_A_BS1 DDR_A_BS2AC3 AB2 U7DDR_A_CAS# DDR_A_RAS# DDR_A_WE#AE1 AB3 AE9SA_CK[0] SA_CK#[0] SA_CKE[0] SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]SA_BS[0] SA_BS[1] SA_BS[2]SA_CAS# SA_RAS# SA_WE#AA6 AA7 P7DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63DDR_A_CLK0 10 DDR_A_CLK0# 10 DDR_A_CKE0 10SA_CK[1] SA_CK#[1] SA_CKE[1]Y6 Y5 P6DDR_A_CLK1 10 DDR_A_CLK1# 10 DDR_A_CKE1 10SA_CS#[0] SA_CS#[1]AE2 AE8DDR_A_CS0# 10 DDR_A_CS1# 10SA_ODT[0] SA_ODT[1]AD8 AF9DDR_A_ODT0 10 DDR_A_ODT1 10SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]DDR SYSTEM MEMORY ADDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D632B9 D7 H7 M7 AG6 AM7 AN10 AN13DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]C9 F8 J9 N9 AH7 AK9 AP11 AT13DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]C8 F9 H9 M9 AH8 AK10 AN11 AR13DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA1511 DDR_B_CAS# 11 DDR_B_RAS# 11 DDR_B_WE#B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10SB_CK[0] SB_CK#[0] SB_CKE[0]DDR_B_BS0 DDR_B_BS1 DDR_B_BS2AB1 W5 R7 AC5 Y7 AC6V7 V6 M2DDR_B_CLK1 11 DDR_B_CLK1# 11 DDR_B_CKE1 11AB8 AD6DDR_B_CS0# 11 DDR_B_CS1# 11SB_ODT[0] SB_ODT[1]AC7 AD1DDR_B_ODT0 11 DDR_B_ODT1 11SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]D4 E1 H3 K1 AH1 AL2 AR4 AT8DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]D5 F4 J4 L4 AH2 AL4 AR5 AR8DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]C5 E3 H4 M5 AG2 AL5 AP5 AR7DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]SB_CAS# SB_RAS# SB_WE#DDR_B_CLK0 11 DDR_B_CLK0# 11 DDR_B_CKE0 11SB_CS#[0] SB_CS#[1]SB_BS[0] SB_BS[1] SB_BS[2]W8 W9 M3SB_CK[1] SB_CK#[1] SB_CKE[1]SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]DDR_B_CAS# DDR_B_RAS# DDR_B_WE#11 DDR_B_BS0 11 DDR_B_BS1 11 DDR_B_BS21JCPU1D11 DDR_B_D[0..63] 11 DDR_B_DM[0..7] 11 DDR_B_DQS#[0..7] 11 DDR_B_DQS[0..7] 11 DDR_B_MA[0..15]JCPU1C10 DDR_A_D[0..63] 10 DDR_A_DM[0..7] 10 DDR_A_DQS#[0..7] 10 DDR_A_DQS[0..7] 10 DDR_A_MA[0..15]D3DDR SYSTEM MEMORY - B5U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15DCBIC,AUB_CFD_rPGA,R1P0 CONN@ IC,AUB_CFD_rPGA,R1P0 CONN@AACompal Electronics, Inc.Compal Secret DataSecurity Classification 2009/08/01Issued DateDeciphered Date2010/08/01TitleTHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:5432SCHEMATICS,MB A5893 Document NumberRev C401869 Wednesday, June 30, 2010Sheet 16of56 7. 54321JCPU1FWW15 MOW +CPU_COREPeak 21A 48AA1.1V RAIL POWERVTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J1510U_0805_6.3V6M +CPU_CORE11C25821C27421C2862C282210U_0805_6.3V6M1C28821C284210U_0805_6.3V6M1C28110U_0805_6.3V6M 12 10U_0805_6.3V6M10U_0805_6.3V6M 1C676210U_0805_6.3V6MC6772110U_0805_6.3V6M 1C66921C674210U_0805_6.3V6M10U_0805_6.3V6M 1C65721C652210U_0805_6.3V6M10U_0805_6.3V6M 1C67921C262210U_0805_6.3V6MC232210U_0805_6.3V6M(Place these capacitors between inductor and socket on Bottom) +CPU_CORE 1 +10U_0805_6.3V6M1 C2682+C66711C24210U_0805_6.3V6M 1C2231C25710U_0805_6.3V6M 1C2611C2691C275C1552 2330U_X_2VM_R6M222222330U_X_2VM_R6M 10U_0805_6.3V6M10U_0805_6.3V6M10U_0805_6.3V6M10U_0805_6.3V6M(Place these capacitors under CPU socket, top layer)CSC (Current Sense Configuration) 8/25 +1.05VS_VTT R436 1 R451 1@2 1K_0402_1% 2 1K_0402_1%CPU_VID1R437 1 R452 1@2 1K_0402_1% 2 1K_0402_1%CPU_VID2R438 1 R453 1@CPU_VID3R439 1 R454 1@2 1K_0402_1% 2 1K_0402_1%CPU_VID4R440 1 R455 1@2 1K_0402_1% 2 1K_0402_1%22U_0805_6.3V6M C2781C27712 2 22U_0805_6.3V6MCPU_VID5 CPU_VID6R441 1 R456 1 R442 1 R457 1@ @H_DPRSLPVR R443 1 R458 1PSI#AN33 AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34@R444 1 R459 122U_0805_6.3V6M2 1K_0402_1% 2 1K_0402_1%C157@ G15H_VTTVID1C2762122U_0805_6.3V6M C27021C2562122U_0805_6.3V6MC24121C231222U_0805_6.3V6M1222U_0805_6.3V6M(Place these capacitors on CPU cavity, Bottom Layer)2 1K_0402_1% 2 1K_0402_1% 2 1K_0402_1% 2 1K_0402_1%+CPU_CORE2 1K_0402_1% 2 1K_0402_1%22U_0805_6.3V6M2 1K_0402_1% 2 1K_0402_1%C222CPU_VID0 53 CPU_VID1 53 CPU_VID2 53 CPU_VID3 53 CPU_VID4 53 CPU_VID5 53 CPU_VID6 53 H_DPRSLPVR 53VTT_SELECT122U_0805_6.3V6MH_PSI# 53VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR@H_PSI#C+CPU_CORE1C6512122U_0805_6.3V6M C65821C666222U_0805_6.3V6M122U_0805_6.3V6MC66521C668222U_0805_6.3V6M1222U_0805_6.3V6M(Place these capacitors on CPU cavity, Bottom Layer) BT8 PADVTT Rail H_VTTVID1 = low, 1.1V H_VTTVID1 = high, 1.05VAuburndale +1.1VS_VTT=1.05V Clarksfield +1.1VS_VTT=1.1V +CPU_COREISENSEVCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTTAN35AJ34 AJ35 B15 A154 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)IMVP_IMON 53VCCSENSE_R R450 1 VSSSENSE_R R449 11 R435 VCCSENSE VSSSENSE2 0_0402_5% 2 0_0402_5%VTT_SENSE 51VSS_SENSE_VTT R523 12 100_0402_1%1 R4482 100_0402_1%+CPU_COREVCCSENSE 53 VSSSENSE 531 +1 +C5412 330U_X_2VM_R6M2 0_0402_5%21@330U_X_2VM_R6M+C13621 +C2512330U_X_2VM_R6M330U_X_2VM_R6MC1342 330U_X_2VM_R6MTOP side (under inductor)+CPU-CORE Decoupling SPCAP,Polymer2009/08/01Issued DateC,uFESR, mohm4X470uF3m ohm/1216X10uFStuffing Option4m ohm/416X22uF3m ohm/162X470uFACompal Electronics, Inc.Compal Secret DataSecurity ClassificationIC,AUB_CFD_rPGA,R1P0 CONN@1+C97MLCC 0805 X5R2010/08/01Deciphered DateTitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:5D+1.05VS_VTTCPU_VID0POWERB+1.05VS_VTT 10U_0805_6.3V6M 10U_0805_6.3V6MAH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11+1.05VS_VTTCPU VIDSCVCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100SENSE LINESDCPU CORE SUPPLYAG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26Continuous 18A432SheetWednesday, June 30, 2010 17of56 8. 54321+VGFX_CORE JCPU1G 10U_0805_6.3V6MC802 0.1U_0402_16V4Z UMOP@21UMOP@1UMOP@ UMOP@ 2 2C6731C6721UMOP@ UMOP@ 2 22330U_X_2VM_R6M 22U_0805_6.3V6M 10U_0805_6.3V6MCJ24 J23 H25VTT1_45 VTT1_46 VTT1_4715AGRAPHICS GRAPHICS091211 EMI ADD 0.1UVAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG363A122C260FDI22U_0805_6.3V6M1AR22 AT22GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]AM22 AP22 AN22 AP23 AM23 AP24 AN24GFX_VR_EN GFX_DPRSLPVR GFX_IMONAR25 AT25 AM24VCC_AXG_SENSE 52 VSS_AXG_SENSE 52 DGFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_EN GFXVR_DPRSLPVR_RR92R9952 52 52 52 52 52 52UMOP@ 2 330_0402_5%1 R98Reserved for +1.5V to +1.5V_11 2 DIS ONLY@+1.5V_1GFXVR_EN 52 GFXVR_DPRSLPVR 52 GFXVR_IMON 522 0_0402_5%122U_0805_6.3V6MVDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H11U_0402_6.3V4Z21K_0402_5%1U_0402_6.3V4Z22U_0805_6.3V6M2C3071C30821C30921C30621C31021C303212C3151222U_0805_6.3V6M1.1V2VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_5811J2222111U_0402_6.3V4Z1U_0402_6.3V4Z+1.5VS1U_0402_6.3V4ZC22U_0805_6.3V6MShort for +1.5VS to +1.5V_1 11/03 add four 0.1u 0402 Intel suggest for S3 reduse +1.5V_1+1.5V1 11VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68J22 J20 J18 H21 H20 H19VCCPLL1 VCCPLL2 VCCPLL3L26 L27 M26120.1U_0402_16V4Z1C2670.1U_0402_16V4ZC798 2 C799 20.1U_0402_16V4Z1P10 N10 L10 K10C797 2C800 20.1U_0402_16V4Z10U_0805_6.3V6MC283 22U_0805_6.3V6M B+1.8VS0.6A1.8V2K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E252+1.05VS_VTTVTT0_59 VTT0_60 VTT0_61 VTT0_62PEG & DMI22U_0805_6.3V6M BC2851@ JUMP_43X118211@ JUMP_43X118+ C326 330U_D2_2V_Y+1.05VS_VTT12@ JUMP_43X1181+1.05VS_VTTC287+1.5V J4J3+1.05VS_VTTC253VAXG_SENSE VSSAXG_SENSE- 1.5V RAILSR514 0_0402_5% DIS ONLY@C272DDR3D+1SENSE LINES12C250GRAPHICS VIDsC675 1AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16POWER22U_0805_6.3V6M2.2U_0603_6.3V4Z+1.8VS_VCCSFR C230 1U_0402_6.3V4ZIC,AUB_CFD_rPGA,R1P0 CONN@1212C224121U_0402_6.3V4ZC2351R97 0_0805_5% 1 240mil C23421C2332 22U_0805_6.3V6M4.7U_0805_10V4ZAACompal Electronics, Inc.Compal Secret DataSecurity Classification 2009/08/01Issued DateDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:5432Wednesday, June 30, 2010Sheet 18of56 9. 5432DCBVSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80JCPU1IVSSVSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9IC,AUB_CFD_rPGA,R1P0 CONN@VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233DCVSSNCTFJCPU1HAT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE351VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7AT35 AT1 AR34 B34 B2 B1 A35H_NCTF1 H_NCTF2@ @PAD T14 PAD T19H_NCTF6 H_NCTF7@ @PAD T18 PAD T15BIC,AUB_CFD_rPGA,R1P0 CONN@AACompal Electronics, Inc.Compal Secret DataSecurity Classification 2009/08/01Issued DateDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:5432Wednesday, June 30, 2010Sheet 19of56 10. 54321+1.5VDIMMA VREFDQ M1 CircuitJDIMM16 DDR_A_DQS#[0..7] +DIMM_VREFDQA+1.5V6 DDR_A_D[0..63]16 DDR_A_DM[0..7] +DIMM_VREFDQAR22211DDR_A_D0 DDR_A_D1 C402 DDR_A_DM00.1U_0402_16V4Z6 DDR_A_MA[0..15]20mil2C4016 DDR_A_DQS[0..7]1K_0402_1%222.2U_0603_6.3V4Z DDR_A_D2 DDR_A_D31DDR_A_D8 DDR_A_D9 R227DDDR_A_DQS#1 DDR_A_DQS121K_0402_1%DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2DIMMA & DIMMB VREFCA circuit +1.5V 1DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25+DIMM_VREFCAR203DDR_A_DM31K_0402_1% +1.5VR201R254 0_0402_5% 1 @ 21K_0402_1%DDR_A_CKE026 DDR_A_CKE0DSDIMM_DRAMRST# 1 Q17 BSS138LT1G_SOT23-335 SM_DRAMRST#G GC218 RST_GATEDIMM_DRAMRST# 11DDR_A_BS26 DDR_A_BS2DDR_A_MA12 DDR_A_MA9C422RST_GATE1DDR_A_MA8 DDR_A_MA52DDR_A_MA3 DDR_A_MA10.047U_0402_16V7KDDR_A_CLK0 DDR_A_CLK0#6 DDR_A_CLK0 6 DDR_A_CLK0#DDR_A_MA10 DDR_A_BS06 DDR_A_BS0DDR_A_WE# DDR_A_CAS#6 DDR_A_WE# 6 DDR_A_CAS#DDR_A_MA13 DDR_A_CS1#6 DDR_A_CS1#DDR_A_D32 DDR_A_D33Layout Note: Place near JDIMM1DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35Layout Note: Place these 4 Caps near Command and Control signals of DIMMADDR_A_D40 DDR_A_D41B+1.5VDDR_A_DM5 10U_0805_6.3V6M10U_0805_6.3V6M0.1U_0402_16V4Z0.1U_0402_16V4Z DDR_A_D42 DDR_A_D43110U_0805_6.3V6MC35521C356210U_0805_6.3V6M1C40521C404210U_0805_6.3V6M1C406210U_0805_6.3V6M1122C3620.1U_0402_16V4Z12C3631C39921C400 2C35412+ C425 330U_2.5V_M_R15 @DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D510.1U_0402_16V4ZDDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59Layout Note: Place near JDIMM1.203 & JDIMM1.204 R218 12 10K_0402_5%1U_0402_6.3V4Z12C403 2.2U_0603_6.3V4Z1U_0402_6.3V4Z12C3981+3VS +0.75VS1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS2573 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS262 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDDR_A_DM1 DIMM_DRAMRST# DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31R27421K_0402_1%DDR_A_D26 DDR_A_D271#425302 CP_S3PowerReduction WhitePaper_Rev1.01220mil+1.5VR217 0.1U_0402_16V4Z 10K_0402_5%205G2G174 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204DDR_A_CKE1206DDR_A_CKE1 6DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7CDDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK1#DDR_A_CLK1 6 DDR_A_CLK1# 6DDR_A_BS1 DDR_A_RAS#DDR_A_BS1 6 DDR_A_RAS# 6DDR_A_CS0# DDR_A_ODT0DDR_A_CS0# 6 DDR_A_ODT0 6DDR_A_ODT1+DIMM_VREFCADDR_A_ODT1 620milDDR_VREF_CA_DIMMA R202 12 0_0402_5%DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39C358 2.2U_0603_6.3V4ZDDR_A_D44 DDR_A_D451122C361 0.1U_0402_16V4Z BDDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLKPM_EXTTS#0_1 5,11 D_CK_SDATA 11,12 D_CK_SCLK 11,12+0.75VSFOX_AS0A626-U8RN-7F A2ACKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT21 C391 21 C38821 C39721 C396122DDR3 SO-DIMM A H=8mmC394 10U_0805_6.3V6M2009/08/01Issued Date1U_0402_6.3V4ZCompal Electronics, Inc.Compal Secret DataSecurity Classification 1U_0402_6.3V4Z2010/08/01Deciphered DateTitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:5432SheetWednesday, June 30, 2010 110of56 11. 54321+1.5V +1.5V JDIMM22008/9/8 #400755 Calpella Clarksfield DDR3 SO-DIMM VREFDQ Platform Design Guide Change Details6 DDR_B_DQS#[0..7] 6 DDR_B_D[0..63] 6 DDR_B_DM[0..7]1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71C433 2.2U_0603_6.3V4Z6 DDR_B_DQS[0..7]1C4312DDR_B_D0 DDR_B_D11DDR_B_DM02DDR_B_D2 DDR_B_D36 DDR_B_MA[0..15]0.1U_0402_16V4Z DDR_B_D8 DDR_B_D9DDDR_B_DQS#1 DDR_B_DQS1DIMMB VREFDQ M1 CircuitDDR_B_D10 DDR_B_D11+1.5V 1DDR_B_D16 DDR_B_D17+DIMM_VREFDQBR282DDR_B_DQS#2 DDR_B_DQS21K_0402_1%DDR_B_D18 DDR_B_D191220milDDR_B_D24 DDR_B_D25R281 1K_0402_1% 2DDR_B_DM3 DDR_B_D26 DDR_B_D27DDR_B_CKE06 DDR_B_CKE0DDR_B_BS26 DDR_B_BS2CDDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_CLK0 DDR_B_CLK0#6 DDR_B_CLK0 6 DDR_B_CLK0#DDR_B_MA10 DDR_B_BS06 DDR_B_BS0DDR_B_WE# DDR_B_CAS#6 DDR_B_WE# 6 DDR_B_CAS#Layout Note: Place near JDIMM2DDR_B_MA13 DDR_B_CS1#6 DDR_B_CS1#Layout Note: Place these 4 Caps near Command and Control signals of DIMMBDDR_B_D32 DDR_B_D33+1.5V 10U_0805_6.3V6M0.1U_0402_16V4ZDDR_B_DQS#4 DDR_B_DQS40.1U_0402_16V4ZDDR_B_D34 DDR_B_D35110U_0805_6.3V6MC43610U_0805_6.3V6M 221C42021C41821C41621C429212C4301C41721C419212+C395 330U_2.5V_M_R15DDR_B_D40 DDR_B_D412C4371C435B1DDR_B_DM5 10U_0805_6.3V6M10U_0805_6.3V6M10U_0805_6.3V6M0.1U_0402_16V4ZDDR_B_D42 DDR_B_D430.1U_0402_16V4ZDDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6Layout Note: Place near JDIMM2.203 & JDIMM2.204DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57+0.75VSDDR_B_DM7 1U_0402_6.3V4Z DDR_B_D58 DDR_B_D59 C41312 1U_0402_6.3V4ZC4121C427212C42611 C411R279 1 +3VS2210U_0805_6.3V6MR278 C432111C428A2.2U_0603_6.3V4Z 1U_0402_6.3V4Z1U_0402_6.3V4Z220.1U_0402_16V4Z2 10K_0402_5%73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 G1VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS262 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT274 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204G2DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13DDDR_B_DM1 DIMM_DRAMRST#2009/08/01DIMM_DRAMRST# 10DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 DDR_B_DM2 DDR_B_D22 DDR_B_D23 DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31DDR_B_CKE1206DDR_B_CKE1 6DDR_B_MA15 DDR_B_MA14 CDDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_CLK1 DDR_B_CLK1# DDR_B_BS1 DDR_B_RAS# DDR_B_CS0# DDR_B_ODT0 DDR_B_ODT120milDDR_B_CLK1 6 DDR_B_CLK1# 6 DDR_B_BS1 6 DDR_B_RAS# 6 DDR_B_CS0# 6 DDR_B_ODT0 6 DDR_B_ODT1 6DDR_VREF_CA_DIMMB R270 1+DIMM_VREFCA2 0_0402_5%DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39C414 2.2U_0603_6.3V4ZDDR_B_D44 DDR_B_D451122C415 0.1U_0402_16V4Z BDDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D53 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 PM_EXTTS#0_1 D_CK_SDATA D_CK_SCLKPM_EXTTS#0_1 5,10 D_CK_SDATA 10,12 D_CK_SCLK 10,12+0.75VS ADDR3 SO-DIMM B H=4mmFOX_AS0A626-U4RN-7F CONN@Compal Electronics, Inc.Compal Secret DataSecurity Classification Issued Date2 10K_0402_5%VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25205+DIMM_VREFDQB2010/08/01Deciphered DateTitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:5432SheetWednesday, June 30, 2010 111of56 12. ABCDEFGHSM010014520 3000ma 220ohm@100mhz DCR 0.04+1.05VS_VTT1+CLK_3VSSM010014520 3000ma 220ohm@100mhz DCR 0.04+CLK_1.05VS40mil40mil0.1U_0402_16V4ZL76 2 1 FBMA-L11-201209-221LMA30T_0805 1 1 1 1 C774 C757 C770 C782 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2L69 2 1 FBMA-L11-201209-221LMA30T_0805+3VS1C737112C74010U_0805_10V4Z 2210U_0805_10V4Z12140mil 0.1U_0402_16V4ZC768 C781 10U_0805_10V4ZC7412L75 2 1 FBMA-L11-201209-221LMA30T_0805+1.5VS10.1U_0402_16V4ZL74 2 1 FBMA-L11-201209-221LMA30T_0805 +CLK_1.5VS @SM010014520 3000ma 220ohm@100mhz DCR 0.04C75010U_0805_10V4Z1122C74211C77122C769 0.1U_0402_16V4Z0.1U_0402_16V4Z+CLK_3VS22+CLK_3VSClock Generator+CLK_1.5VS U4714 CLK_BUF_DREF_96M 14 CLK_BUF_DREF_96M# 22 27M_CLK 22 27M_SSC14 CLK_BUF_PCIE_SATA 14 CLK_BUF_PCIE_SATA# 14 CLK_BUF_CPU_DMI 14 CLK_BUF_CPU_DMI#CLK_BUF_DREF_96M CLK_BUF_DREF_96M# R717 0_0402_5% @ 1 2 1 2 R716 0_0402_5% @27M_CLK_R 27M_SSC_RCLK_BUF_PCIE_SATA CLK_BUF_PCIE_SATA# CLK_BUF_CPU_DMI CLK_BUF_CPU_DMI# +CLK_1.05VSH_STP_CPU#1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 33SCL SDA REF_0/CPU_SEL VDD_REF XTAL_IN XTAL_OUT VSS_REF CKPWRGD/PD#32 31 30 29 28 27 26 25VDD_CPU CPU_0 CPU_0# VSS_CPU CPU_1 CPU_1# VDD_CPU_IO VDD_SRCVDD_USB_48 VSS_48M DOT_96 DOT_96# VDD_27 27MHZ 27MHZ_SS USB_4824 23 22 21 20 19 18 17VSS_27M SATA SATA# VSS_SRC SRC_1 SRC_1# VDD_SRC_IO CPU_STOP#D_CK_SCLK D_CK_SDATA REF_0/CPU_SEL R682 1D_CK_SCLK 10,11 D_CK_SDATA 10,11 CLK_BUF_ICH_14M 142 33_0402_5%CLK_XTAL_IN CLK_XTAL_OUT CK505_PWRGD CLK_BUF_CPU_BCLK CLK_BUF_CPU_BCLK#CLK_BUF_CPU_BCLK 14 CLK_BUF_CPU_BCLK# 14+CLK_1.05VS +CLK_1.5VSIDT SA00003HR00TGNDSLG8SP587VTR_QFN32_5X5IDT: 9LRS3199AKLFT, SA000030P0033SILEGO: SLG8SP587V(WF), SA00002XY10 +3VSLow Power: +3VSR678 4.7K_0402_5% 1 21132SD_CK_SCLK Y4 14.31818MHZ 20PF 7A14300003Q45 2N7002E-T1-GE3_SOT23-3133MHz100MHz14,21,34 PCH_SMBCLKCLK_XTAL_IN+3VS1R677 4.7K_0402_5% 1 2DCPU_1133MHzVGATE 15,532 CLK_ENABLE# 53 G Q48 2N7002E-T1-GE3_SOT23-3C755 127P_0402_50V8J C762 27P_0402_50V8J 2 1100MHzChange to 5x3.22009/08/01Deciphered Date4Compal Electronics, Inc.Compal Secret DataSecurity Classification Issued DateCLK_XTAL_OUT20 (Default)CPU_0R691 0_0402_5% @ 1 2+3VS2 10K_0402_5% REF_0/CPU_SELPIN 30 4SQ46 2N7002E-T1-GE3_SOT23-32 GR683 1D_CK_SDATA3FOR RealtekCK505_PWRGDD+3VSS14,21,34 PCH_SMBDATA1 DIDT Have Internal Pull-Down1+3VSH_STP_CPU#12 10K_0402_5%2 GR690 1R693 10K_0402_5%Realtek: RTM890N-631-VB-GRT, SA00003HQ10Silego Have Internal Pull-Up3IDT 9LVS3199AKLFT NC2IDT: 9LVS3199AKLFT, SA00003HR002010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:ABCDEFWednesday, June 30, 2010 GSheet12of H56 13. 54321+RTCBATT PCH_RTCRST# PCH_RTCX1OSC4NCOSC1R615232.768KHZ_12.5PF_Q13MC14610002 C722 2 1DU41A10M_0402_5%+RTCBATT_RREV1.0 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3D33 B33 C32 A32LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3FWH4 / LFRAME#B13 D13PCH_RTCX2C34LPC_FRAME#LDRQ0# LDRQ1# / GPIO23A34 F34SERIRQAB9SERIRQSATA0RXN SATA0RXP SATA0TXN SATA0TXPAK7 AK6 AK11 AK9SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0SATA_DTX_C_PRX_N0 31 SATA_DTX_C_PRX_P0 31 SATA_PTX_DRX_N0 31 SATA_PTX_DRX_P0 31SATA1RXN SATA1RXP SATA1TXN SATA1TXPAH6 AH5 AH9 AH8SATA_DTX_C_PRX_N1 SATA_DTX_C_PRX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1SATA_DTX_C_PRX_N1 31 SATA_DTX_C_PRX_P1 31 SATA_PTX_DRX_N1 31 SATA_PTX_DRX_P1 31SATA2RXN SATA2RXP SATA2TXN SATA2TXPAF11 AF9 AF7 AF6SATA3RXN SATA3RXP SATA3TXN SATA3TXPAH3 AH1 AF3 AF1SATA4RXN SATA4RXP SATA4TXN SATA4TXPAD9 AD8 AD6 AD5SATA5RXN SATA5RXP SATA5TXN SATA5TXPAD3 AD1 AB3 AB1RTCX1 RTCX218P_0402_50V8Jclose to RAM doormodify to 330K1 2 R675 @ 10K_0603_5% C365 1U_0603_10V6K 1 2RTCRST#PCH_SRTCRST#+RTCVCCRC Delay 18~25mSC14 D17SRTCRST#R213 12 1M_0402_5%SM_INTRUDER#A16INTRUDER#R212 12 330K_0402_1% PCH_INTVRMENA14INTVRMENHDA_BITCLK_PCHA30HDA_BCLKHDA_SYNC_PCHD29HDA_SYNCR32712 33_0402_5% 2 33_0402_5%39 PCH_SPKR(SPKR Have internal Pull-Down) 39 HDA_RST_AUDIO#1R328PCH_SPKR1HDA_RST_PCH#2 33_0402_5%P1SPKRC30HDA_RST#G3039 HDA_SDIN0HDA_SDIN0 HDA_SDIN1 HDA_SDIN2F32HDA_SDIN3HDA_SDOUT_PCHB29HDA_SDOPCH_GPIO33#H32HDA_DOCK_EN# / GPIO33J30HDA_DOCK_RST# / GPIO13M3JTAG_TCKK3JTAG_TMS21 PCH_JTAG_TDIK1JTAG_TDI21 PCH_JTAG_TDOJ2JTAG_TDOJ4TRST#HDA_SDO ,This signal has a weak internal pull-down resistor. Should not be Pull HighCIHDAF30 E32PCH_SPKRHave internal PD SERIRQ39 HDA_SDOUT_AUDIOR324If GPIO33 pull down, ME will not working. For factory update ME, pull down resistor pull under door.12 33_0402_5%GPIO33 can not pull down (manufacturing environments)1PCH_GPIO33# D2 GPCH_JTAG_TCK21 PCH_JTAG_TCK Q3921 PCH_JTAG_TMSS 2N7002E-T1-GE3_SOT23-33136 ME_OVERRIDE221 PCH_JTAG_RST#GPIO33 has a weak internal pull-up NOTE: Asserting the GPIO33 low on the rising edge of PWROK will also halt Intel Management Engine after chipset bringup and disable runtime Intel Management Engine features. This is a debug mode and must not be asserted after manfacturing/ debug.+1.05VS_PCHPCH_SPI_CLK_1 R665 12 0_0402_5%PCH_SPI_CLKPCH_SPI_CS0#2 15_0402_5%PCH_SPI_CS0#_R AV32009/08/23 Debug Port DG1.7 P27.28R662 1 T24 PADPCH_SPI_MOSI_1 R664 1 TDO,TDI,TMS Pull Up for Production Units PCH_SPI_MISO_1 R661 1 unpop TDO,TDI,TMS resisterPCH_SPI_CS1#@BA21SERIRQ 36AY3SATAICOMPIAF15R205 1PCH_SPI_MOSI AY1SATA_COMP2 10K_0402_5%+3VSSATALED#SPI_MOSI2 33_0402_5%PCH_SPI_MISO AV1@1 R644 1 R724 1 R722PCH_JTAG_TDO51_0402_5% 2 200_0402_5% 2 100_0402_5% 2@1 R645 1 R728 1 R727T3PCH_SATALED# 37SATA0GP / GPIO21Y9GPIO21 Project ID2SPI_MISOSATA1GP / GPIO19V1PCH_JTAG_TDI51_0402_5% 2 20K_0402_5% 2 10K_0402_5% 2@1 R643 1 R721 1 R723PCH_JTAG_RST#PCH_GPIO21 21 PCH_GPIO19 21+3VSB2 10K_0402_5%R259 NonSG@ 10K_0402_5%R268 @ 10K_0402_5%+3VS U18 +3VSR301 1 R271 12 3.3K_0402_5% 2 3.3K_0402_5%PCH_SPI_CS0# SPI_WP1# SPI_HOLD1#1 3 7 4CS# WP# HOLD# GNDVCC SCLK SI SO8 6 5 2PCH_SPI_CLK_1 PCH_SPI_MOSI_1 PCH_SPI_MISO_1PCH_SPI_CLK_1 @2 10P_0402_50V8JGPIO19OPTPCH_JTAG_TCK1 C729dGPU iGPU SGGPIO37PCH_GPIO19MX25L3205DM2I-12G SOP 8P SA000021A00SPI ROM Footprint 200milR647+3VS R267 1R260 1 SGOPT@ 10K_0402_5% 2TDO: Reserved on ES1 Sample Mount R724, R722 on ES2 Sample MP mount R646, R644, R645, R643 and remove othersSATA for ODD2 37.4_0402_1%PCH_SATALED# R652 1SPI_CS1#2 15_0402_5%SATA for HDD1AF162PCH_JTAG_TMS51_0402_5% 2 200_0402_5% 2 100_0402_5% 2120mil0.1U_0402_16V4Z+1.05VS_PCHSATAICOMPOIBEXPEAK-M_FCBGA1071 R646 1 R726 1 R72522+CHGRTC C7242/10 SATA2, SATA3 not support on HM552008 Intel MOW36/[email protected]_0402_5%VGA_PRSNT_L#0 0 10 1 0AS3 CRB 1.1 Change to 4.7K@1R663PCH_SPI_MOSIDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.MOSI This signal has a weak internal pull-down resistor. This signal must be sampled low. 52009/08/01Issued Dateenable iTPM: SPI_MOSI HighCompal Electronics, Inc.Compal Secret DataSecurity Classification 1K_0402_5% 2DCSPI_CS0#+3V51_0402_5% 2 200_0402_5% 2 100_0402_5% 2A20milLPC_FRAME# 36SPI_CLKSPIBD8 BAS40-04_SOT23-3 +RTCVCC1R580 100K_0402_5%JTAG1 2 R237 10K_0402_5%36 36 36 361R330SATA39 HDA_BITCLK_AUDIOHDA_SYNC On Die PLL VR is supplied by 1.5V when sampled High, 1.8V when sampled Low.R650 1K_0402_5% @ 1 2LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3INTVRMEN - Integrated SUS 1.05V VRM Enable High - Enable Internal VRsHDA for AUDIO(HDA_SYNC Have internal Pull-Down) 39 HDA_SYNC_AUDIO+3VSLPCPCH_RTCRST#RTC+RTCVCCPCH_SRTCRST#1 2 R214 20K_0402_1%1NC211321 2 R671 @ 10K_0603_5% C366 1U_0603_10V6K 1 2R336 1K_0402_5%20milX23close to RAM door2C723 18P_0402_50V8J 2 1RC Delay 18~25mS21 2 R215 20K_0402_1%+RTCVCCRev C401869Date:432Wednesday, June 30, 2010Sheet 113of56 14. 43REV1.0PERN7 PERP7 PETN7 PETP72 0_0402_5%R266 1PCH_GPIO732 0_0402_5%P9 AM43 AM4534 CLK_PCIE_MINI1# 34 CLK_PCIE_MINI1For Wireless LAN 34 MINI1_CLKREQ# 21 PCH_GPIO18PCH_GPIO18U4 AM47 AM48PCH_GPIO2021 PCH_GPIO20N4 AH42 AH41PCH_GPIO252009/08/25: Change back to +3V remove mini2+3V2009/08/25: remove mini2 clk1BA8R241MINI2_CLKREQ#_1AM51 AM53 M9SMBusC6 G8DM14PCH_GPIO74SML1CLK / GPIO58E10PCH_SML1CLKSML1DATA / GPIO75G12PCH_SML1DATDGPU_PWR_EN+3V1 T13 T11CL_RST1#T9H110K_0402_5%PEG_CLKREQ#_R11AD43 AD45CLKOUT_DMI_N CLKOUT_DMI_PCLK_CPU_DMI# 5 CLK_CPU_DMI 5CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P2N7002E-T1-GE3_SOT23-3AW24 BA24CLKIN_BCLK_N CLKIN_BCLK_PAP3 AP1CLK_BUF_CPU_BCLK# 12 CLK_BUF_CPU_BCLK 12CLKIN_DOT_96N CLKIN_DOT_96PF18 E18CLK_BUF_DREF_96M# 12 CLK_BUF_DREF_96M 12AH13 AH12CLK_BUF_PCIE_SATA# 12 CLK_BUF_PCIE_SATA 12REFCLK14IN CLKIN_PCILOOPBACKJ421 R163XTAL25_IN XTAL25_OUTPCIECLKRQ4# / GPIO26AF382 10_0402_5%1 C31910K_0402_5% 2 10K_0402_5% 2H61 R265 MINI1_CLKREQ# PCH_GPIO20 1 R649AK53 AK51 PCH_GPIO56Schematic_Checklist_Rev1.6 GPIO18 GPIO25Main (core) power well (+V3.3S)Muxed with PCIECLKRQ1#. If not used, requires 8.2-k to 10-k pull-up to +Vcc_3.3 (+V3.3S)Resume (Sus) well (+V3.3A)P13PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ# / GPIO56XCLK_RCOMPR170 12 90.9_0402_1%CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66T42CLKOUTFLEX3 / GPIO671 R623 1 R602 1 R62610K_0402_5% 21 R208 1 R639 1 R249PCH_SML1CLK PCH_SML1DAT10K_0402_5% 21 R207PCH_GPIO742.2K_0402_5% 2.2K_0402_5%1 R624 5PCH_GPIO25*Discrete *Optimus10K_0402_5% 2 10K_0402_5% 2 10K_0402_5% 21 R244 1 R206 1 R257 4PCH_GPIO44 PCH_GPIO56 PCH_GPIO732C694 27P_0402_50V8J UMOP@+3VS0GPIO66 ID0 0PCH_SML1CLK2009/08/016Structure1NEW701+3VSNEW8010NEW90100NEW71/91110Deciphered DateEC_SMB_CK2EC_SMB_CK2 22,36Q19A 2N7002DWH_SOT363-6PCH_SML1DATPull high +3VS at KB926 side34EC_SMB_DA2EC_SMB_DA2 22,36Q19B 2N7002DWH_SOT363-6NEW71/91Compal Electronics, Inc.Compal Secret DataSecurity Classification Issued Date2009/08/13: Change back to +3VChange to 5x3.21PCH_GPIO602 2GPIO65 ID1 00EC_LID_OUT# PCH_SMBCLK PCH_SMBDATABY2 25MHZ_20PF_7A25000012 UMOP@2 10K_0402_5%R144 1 2 10K_0402_5% NonOPT@ R157 1 2 10K_0402_5% @ R167 1 2 10K_0402_5%PROJECT_ID0Project Structure GPIO21 ID2 010K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 210K_0402_5% 2OPT@+3VSR564 1M_0402_5% UMOP@IBEXPEAK-M_FCBGA10709/1: Change to +3VSR156 1+1.05VS_PCHN50+3V+3VProject Structure IDT45 P43 PROJECT_ID1Muxed with PCIECLKREQ3# If not used, requires 8.2-k to 10-k pull-up to +V3.3A rail.AC693 UMOP@ 27P_0402_50V8J 1 2XTAL25_IN XTAL25_OUT2PCH_GPIO44CLKOUTFLEX0 / GPIO641109 RF request5+3VSCLKOUT_PCIE5N CLKOUT_PCIE5PR563 DIS ONLY@ 0_0402_5% 1 2122 10P_0402_50V8JCLK_PCI_FB 17AH51 AH53XCLK_RCOMPCLKOUT_PCIE4N CLKOUT_PCIE4P6/9 MOW23 Request add 25MHz crystal supporting Integrated GraphicsCLK_BUF_ICH_14MP41CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25CCLK_BUF_CPU_DMI# 12 CLK_BUF_CPU_DMI 12CLKIN_DMI_N CLKIN_DMI_PClock Flex2AJ50 AJ52PEG_CLKREQ# 22 R276 @ 2.2K_0402_5%AT1 AT3CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_PPCIECLKRQ2# / GPIO203Q18 R247 DIS@ @ 2.2K_0402_5%CLK_PEG_VGA# 22 CLK_PEG_VGA 22AN4 AN2CLKOUT_PEG_A_N CLKOUT_PEG_A_P10K_0402_5% MINI2_CLKREQ#_1R275 DIS@ 10K_0402_5%R6362 GLinkControllerCL_CLK1 CL_DATA1PEG_A_CLKRQ# / GPIO47PERN8 PERP8 PETN8 PETP818,21,38,421SML1ALERT# / GPIO741R258 1SML0CLK232 LAN_CLKREQ#PCH_GPIO601AK48 AK4732 CLK_PCIE_LAN# 32 CLK_PCIE_LANFor PCIE LANPCH_SMBDATA 12,21,34J142CPCH_SMBDATASML0DATAPEGBG34 BJ34 BG36 BJ36PCH_SMBCLK 12,21,34C8EC_LID_OUT# 362AT34 AU34 AU36 AV362/10 PCIE7, PCIE8 not support on HM55SML0ALERT# / GPIO60PCH_SMBCLK1PERN6 PERP6 PETN6 PETP6SMBDATAH141. Connect Directly EXPRESS CARD, MINI1, MINI2 2. Level Shift1, Pull-Up to +3VS CLOCK GEN, DIMM1, DIMM2 3. Level Shift2, Pull-Up to +3VS LAN 4. Level Shift3, Pull-Up to +3VS CPU & PCH XDP2PERN5 PERP5 PETN5 PETP52009/08/25: remove PCIE5For Mini2SMBCLKEC_LID_OUT#SPERN4 PERP4 PETN4 PETP4SMBALERT# / GPIO11B9DPERN3 PERP3 PETN3 PETP3DPERN1 PERP1 PETN1 PETP1PCI-E*C332 2 C334 2PERN2 PERP2 PETN2 PETP2BF33 BH33 BG32 BJ322 2From CLK BUFFERPCIE_DTX_C_PRX_N2 PCIE_DTX_C_PRX_P2 PCIE_PTX_C_DRX_N2 PCIE_PTX_C_DRX_P21 1BA34 AW34 BC34 BD3434 34 34 34C335 C339PCIE_DTX_C_PRX_N2 AW30 PCIE_DTX_C_PRX_P2 BA30 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30BA32 BB32 BD32 BE32For Wireless LANPCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P11 1AU30 AT30 AU32 AV3232 32 32 32For PCIE LAN12U41B PCIE_DTX_C_PRX_N1 PCIE_DTX_C_PRX_P1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 0.1U_0402_16V7K PCIE_PTX_DRX_P1BG30 BJ30 BF29 BH292252010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:32Wednesday, June 30, 2010Sheet 114of56A 15. 543DMI_HTX_PRX_P[0..3]4 DMI_HTX_PRX_P[0..3]DMI_PTX_HRX_N[0..3]4 DMI_PTX_HRX_N[0..3]DMI_PTX_HRX_P[0..3]4 DMI_PTX_HRX_P[0..3]H_FDI_TXN[0..7] U41C H_FDI_TXP[0..7] DMI_HTX_PRX_N0 BC24 DMI_HTX_PRX_N1 BJ22 DMI_HTX_PRX_N2 AW20 DMI_HTX_PRX_N3 BJ20 DMI_HTX_PRX_P0 DMI_HTX_PRX_P1 DMI_HTX_PRX_P2 DMI_HTX_PRX_P3BD22 BH21 BC20 BD18DMI0TXP DMI1TXP DMI2TXP DMI3TXP@4BJ12H_FDI_LSYNC04BG14H_FDI_LSYNC14DMI_IRCOMPT6SYS_RESET#WAKE#SYS_PWROK_R1 0_0402_5% 1 0_0402_5%M6SYS_PWROKB17 K5LAN_RST#A10 D95 PM_DRAM_PWRGD PCH_RSMRST#36 SUS_PWR_DN_ACKH_FDI_FSYNC1XDP_DBRESET#SYS_PWROKBBH13C16SUS_PWR_DN_ACKM1PWROK MEPWROK LAN_RST# DRAMPWROK RSMRST#36 EC_SWI#Y1PM_CLKRUN#SUS_STAT# / GPIO61P8PCH_GPIO61 SUSCLKPCH_ACINP74C32,34PM_CLKRUN# 36@PADT10SUSCLK / GPIO62 SLP_S5# / GPIO63E4PM_SLP_S5# 36SLP_S4#H7PM_SLP_S4# 36SLP_S3#P12SLP_M#K8PM_SLP_M#@PADT11TP23N2PM_SLP_DSW# @PADT22ACPRESENT / GPIO31A6BATLOW# / GPIO72SUSCLK 36PM_SLP_S3# 36B@ 1 0_0402_5%R605 2 Q41 MMBT3906_SOT23-3 PCH_RSMRST# 1 3EC_RSMRST# 36EPWRBTN#PCH_PCIE_WAKE#F3SUS_PWR_DN_ACK / GPIO30P5PCH_GPIO725,21,36 PBTN_OUT# 2 10K_0402_5% 2 D6 CH751H-40PT_SOD323-2PCH_PCIE_WAKE#CLKRUN# / GPIO32PBTN_OUT#1 R2401J124EC_SWI#F14PMSYNCHRI#SLP_LAN# / GPIO29BJ10 F6H_PM_SYNC 52 BR620 2 R631 2H_FDI_FSYNC0FDI_FSYNC1DMI_ZCOMPH_FDI_INTCBF25BJ14 BF13FDI_LSYNC1BH25 DMI_COMPFDI_INT09/09/14 WW37 PCH WAKE# PU 10KSYS_PWROK VGATE36 EC_ACINH_FDI_TXP0 H_FDI_TXP1 H_FDI_TXP2 H_FDI_TXP3 H_FDI_TXP4 H_FDI_TXP5 H_FDI_TXP6 H_FDI_TXP7FDI_FSYNC0FDIR600 49.9_0402_1% 1 25,21 XDP_DBRESET#+3VBB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12R604 10K_0402_5%PM_SLP_LAN#1 R598IBEXPEAK-M_FCBGA1072 4.7K_0402_5%+3VD20A2CDMI0TXN DMI1TXN DMI2TXN DMI3TXNDH_FDI_TXN0 H_FDI_TXN1 H_FDI_TXN2 H_FDI_TXN3 H_FDI_TXN4 H_FDI_TXN5 H_FDI_TXN6 H_FDI_TXN7FDI_LSYNC0+1.05VS_PCH SUS_PWR_DN_ACK 2 10K_0402_5% PCH_GPIO72 2 8.2K_0402_5% EC_SWI# 2 10K_0402_5% PCH_PCIE_WAKE# 2 10K_0402_5% PM_SLP_LAN# 2 10K_0402_5%BE22 BF21 BD20 BE18BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7DMI0RXP DMI1RXP DMI2RXP DMI3RXPDMI_PTX_HRX_P0 DMI_PTX_HRX_P1 DMI_PTX_HRX_P2 DMI_PTX_HRX_P3+3VBD24 BG22 BA20 BG20DMI_PTX_HRX_N0 DMI_PTX_HRX_N1 DMI_PTX_HRX_N2 DMI_PTX_HRX_N3PM_CLKRUN# 2 8.2K_0402_5%FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN71+3VSREV1.0DMI0RXN DMI1RXN DMI2RXN DMI3RXNDMI4 H_FDI_TXP[0..7]System Power Management4 H_FDI_TXN[0..7] D1 R648 1 R628 1 R198 1 R641 1 @ R2481DMI_HTX_PRX_N[0..3]4 DMI_HTX_PRX_N[0..3]1 R65721 6 2 BAV99DW-7_SOT363 D20B4AY1VGATE4 3EC_PWROK 36,385VGATE 12,53R591 2.2K_0402_5%BAV99DW-7_SOT363MC74VHC1G08DFT2G_SC70-52321 SYS_PWROKEC_PWROK1U44 2P SYS_PWROKBG5+3VSASYS_PWROK1 R6062 10K_0402_5%EC_PWROK1 R6322 10K_0402_5%LAN_RST#1 R6172 10K_0402_5%Compal Electronics, Inc.Compal Secret DataSecurity Classification 2009/08/01Issued DateDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.No used Integrated LAN, connecting LAN_RST# to GNDRev C401869Date:5A432Wednesday, June 30, 2010Sheet 115of56 16. 54321U41D IGPU_BKLT_ENT48 T4728 DPST_PWML_BKLTCTLPCH_LCD_CLK PCH_LCD_DATAAB48 Y45 AB46 V48SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTPAP39 AP41LVD_VREFAT43 AT42LVD_VREFH LVD_VREFLSDVO_CTRLCLK SDVO_CTRLDATAR131 1@2 2.2K_0402_5%PCH_LCD_DATA2 10K_0402_5%LCTLA_CLKR132 1 R133 12 10K_0402_5% 2 2.2K_0402_5%LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+BB48 BA50 AY49 AV48LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3AA52 AB53 AD53CRT_BLUE CRT_GREEN CRT_REDPCH_CRT_CLK2 2.2K_0402_5%BB47 BA52 AY48 AV47LCTLB_DATAR546 1 R545 1C28 PCH_TXOUT0+ 28 PCH_TXOUT1+ 28 PCH_TXOUT2+PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-PCH_CRT_DATAR551 R552 R5531 1 1UMOP@ UMOP@ UMOP@PCH_CRT_B 150_0402_1% PCH_CRT_G 150_0402_1% PCH_CRT_R 150_0402_1%2 2 229 PCH_CRT_B 29 PCH_CRT_G 29 PCH_CRT_R 29 PCH_CRT_CLK 29 PCH_CRT_DATAPCH_CRT_B PCH_CRT_G PCH_CRT_R PCH_CRT_CLK PCH_CRT_DATABENBKLR135 1 UMOP@ 20_0402_5%V51 V531UMA ONLY & OPTIMUS USEDDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3PBD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3DDPC_CTRLCLK DDPC_CTRLDATAY49 AB49DDPC_AUXN DDPC_AUXP DDPC_HPDBE44 BD44 AV40DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P2 100K_0402_5%BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36PCH_DPB_HPD C313 C305 C320 C323 C317 C314 C327 C3252 2 2 2 2 2 2 21 1 1 1 1 1 1 1UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ UMOP@ [email protected]_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K30PCH_TMDS_D2# 30 PCH_TMDS_D2 30 PCH_TMDS_D1# 30 PCH_TMDS_D1 30 PCH_TMDS_D0# 30 PCH_TMDS_D0 30 PCH_TMDS_CK# 30 PCH_TMDS_CK 30HDMI D2 HDMI D1 HDMI D0 HDMI CLKCU50 U52DDPD_AUXN DDPD_AUXP DDPD_HPDREV1.0BC46 BD46 AT38DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3PBJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36B1 R143 1K_0402_0.5%22 R103 1 DIS ONLY@ 2R171 1IBEXPEAK-M_FCBGA107 R134 100K_0402_5%ENBKLDAC_IREF CRT_IRTNSDVO_SCLK 30 SDVO_SDATA 30PCH_DPB_HPDCRT_HSYNC CRT_VSYNCCRT_IREF AD48 AB51IGPU_BKLT_ENT51 T53 BG44 BJ44 AU38CRT_DDC_CLK CRT_DDC_DATAY53 Y5129 PCH_CRT_HSYNC 29 PCH_CRT_VSYNCDDDPB_AUXN DDPB_AUXP DDPB_HPDDDPD_CTRLCLK DDPD_CTRLDATACRTPCH_LCD_CLKLVDSA_CLK# LVDSA_CLKAY51 AT48 AU50 AT512 2.2K_0402_5%AV53 AV51AY53 AT49 AU52 AT53@28 PCH_TXOUT028 PCH_TXOUT128 PCH_TXOUT2-PCH_TXCLKPCH_TXCLK+AP48 AP4728 PCH_TXCLK28 PCH_TXCLK+R130 1BF45 BH45SDVO_CTRLDATA strap Pull High at Level Shift PageLVD_IBG LVD_VBGDigital Display InterfaceLVDS_IBGR162 1 UMOP@ 2 0_0402_5%11/21 intel JIM suggest Pull high at LVDS ConnBJ48 BG48L_CTRL_CLK L_CTRL_DATAR166 1 UMOP@ 2 2.37K_0402_1%+3VSBJ46 BG46L_DDC_CLK L_DDC_DATALCTLA_CLK LCTLB_DATA28 PCH_LCD_CLK 28 PCH_LCD_DATASDVO_TVCLKINN SDVO_TVCLKINPLVDSDL_BKLTEN L_VDD_ENY4828 PCH_ENVDD2/3 Change to 1K_0402_0.5% from Intel Suggestion. (EDS 1.0 is incorrect)0_0402_5% VGA_BKL_ENDIS ONLY USE+5VS U25 22 VGA_BKL_ENIGPU_BKLT_ENA17,28,29 DGPU_SELECT# 28 IGPU_SELECT#2 5 1 71A 2A 1OE# 2OE#VCC 1B 2B GND8 3 6 4C472 SG@ 0.1U_0402_16V4Z 1 2 ENBKLAENBKL 36SN74CBTD3306CPWR_TSSOP8 SG@Compal Electronics, Inc.Compal Secret DataSecurity Classification 2009/08/01Issued DateDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:5432Wednesday, June 30, 2010Sheet 116of56 17. R577 R574 R572 R153R568 R570 R565 R566C1 1 1 12 2 2 21 1 1 12 2 2 21 1 1 12 2 2 28.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%16,28,29 DGPU_SELECT#28 DGPU_PWMSEL#PCI_GNT2# ESI Strap (Server Only) this signal should not be pulled lowGNT0# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# T12 PAD@TP_PCI_RST#K6PCIRST#E44 E50SERR# PERR#A42 H44 F46 C46IRDY# PAR DEVSEL# FRAME#PCI_PLOCK#D49PCI_STOP# PCI_TRDY#D41 C48STOP# TRDY#M7R561 R1421 12 22_0402_5% 2 22_0402_5%CLK_PCI_LPC_R CLK_PCI_FB_RB1AYMC74VHC1G08DFT2G_SC70-5 DIS@NV_RCOMP R660 1@+1.8VSNV_ALER233 1@2 1K_0402_5%If not implemented, the dual channel NAND interface signals, including NV_RCOMP, can be left as No Connect.NV_CLER225 1@2 1K_0402_5%Intel Anti-Theft Techonlogy USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2B25USB_BIASD25OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14N16 J16 F16 L16 E14 G16 F12 T15USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P235 35 35 35 35 35NV_ALEUSB/B (Right Side) USB Port (Left Side)NV_CLE0LPC01Reserved (NAND)10PCI11SPISet to Vcc when HIGH Set to Vss when LOWDisable Intel Anti-Theft Technologyfloating(internal PD)CMOS Camera (LVDS) Card ReaderNV_CLEMini Card(SIM Card)DMI termination voltage. weak internal PU, don't PDEHCI 2Bluetooth Mini Card(WLAN) Mini Card(WWAN)BD51 2 R191 22.6_0402_1%USB_OC#0_RUSB_OC#0_R 21USB_OC#2_RPLTRST#N52 P53 P46 P51 P48CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4USB_OC#0_R USB_OC#1_R USB_OC#2_R USB_OC#3_R USB_OC#4_R USB_OC#5_R USB_OC#6_R USB_OC#7_RR216 12 0_0402_5%R210 12 0_0402_5%USB_OC#2_R 21(For USB Port0, 2)USB_OC#0 35 USB_OC#1_R 21 USB_OC#2 35 USB_OC#3_R 21 USB_OC#4_R 21 USB_OC#5_R 21 USB_OC#6_R 21 USB_OC#7_R 21(For USB Port1)RP1 USB_OC#3_R USB_OC#5_R USB_OC#6_R USB_OC#7_R1 2 3 48 7 6 5+3V10K_1206_8P4R_5%PCI_GNT0#R137 1@2 1K_0402_5%@2 1K_0402_5%@2 1K_0402_5%USB_OC#1_RPCI_GNT1#R159 1R601 12 10K_0402_5%USB_OC#4_RHave internal PUR603 12 10K_0402_5%Have internal PU PCI_GNT3#R558 1AHave internal PUA16 swap overide Strap/Top-Block Swap Override jumperCompal Electronics, Inc.Compal Secret DataSecurity ClassificationLow=A16 swap override/Top-Block PCI_GNT3# Swap Override enabled High=Default *2009/08/01Issued DateDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:5*NV_ALE Enable Intel Anti-Theft Technology8.2K PU to +3VS2/10 USB6, USB7 not support on HM55 USB20_N8 28 USB20_P8 28 USB20_N9 35 USB20_P9 35 USB20_N10 34 USB20_P10 34 USB20_N11 35 USB20_P11 35 USB20_N12 34 USB20_P12 34 USB20_N13 34 USB20_P13 34CDMI Termination VoltageUSB/B (Right Side) EHCI 1USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 USB20_N12 USB20_P12 USB20_N13 USB20_P13High=Endabled Low=Disable(floating)Boot BIOS Location0*PLTRST_VGA# 222 32.4_0402_1%OC[0..3] use for EHCI 1 OC[4..7] use for EHCI 2PCI_GNT#12R622 100K_0402_5% DIS@IBEXPEAK-M_FCBGA107AR619 1 DIS@ 100_0402_5%4Design Guide 1.5 Ver: 3.26.13 Terminating Unused Braidwood InterfaceBoot BIOS Strap PCI_GNT#0DNV_ALE,NV_CLE has a weak internal pull-downNV_ALE NV_CLEH18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24PME#2008/1/6 2009MOW01 change to 22 ohm18,21 DGPU_HOLD_RST#USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13PPLOCK#PLT_RST#U432USBRBIASPIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5PCI_DEVSEL# PCI_FRAME#36 CLK_PCI_LPC 14 CLK_PCI_FBAV11 BF5R621 100K_0402_5%2 +3VSDGPUUSBRBIAS#B41 K53 A36 A48PCI_IRDY#5,21,32,36 PLT_RST#AY8 AY5NV_WE#_CK0 NV_WE#_CK1PCI_SERR# PCI_PERR#BNV_WR#0_RE# NV_WR#1_RE#PLT_RST_BUF# 341REQ0# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54AV7@ 0.1U_0402_16V7K42F51 A46 B45 M53AU2NV_RB#Y1PIRQA# PIRQB# PIRQC# PIRQD#PCI_GNT0# F48 PCI_GNT1# K45 DGPU_PWMSEL# F36 PCI_GNT3# H53PCI_GNT0#,PCI_GNT1#,PCI_GNT2#,PCI_GNT3# has a weak internal pull-upNV_RCOMPA5G38 H51 B37 A44PCI_REQ0# PCI_REQ1# DGPU_SELECT# PCI_REQ3#PCI_FRAME# PCI_REQ1# PCI_PIRQH# PCI_TRDY#BD3 AY6B11PPCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#PCI_IRDY# PCI_PIRQD# DGPU_SELECT# PCI_DEVSEL#NV_ALE NV_CLEC4432GC/BE0# C/BE1# C/BE2# C/BE3#PCI_REQ0# PCI_PIRQB# PCI_PIRQF# PCI_REQ3#U42 PLT_RST#3J50 G42 H47 G34PCI_PLOCK# PCI_PERR# PCI_PIRQE# PCI_STOP#AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6MC74VHC1G08DFT2G_SC70-558.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%AV9 BG8NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15+3VSAY9 BD1 AP15 BD8NV_DQS0 NV_DQS1NVRAM2 2 2 2PCI_PIRQA# PCI_PIRQG# PCI_PIRQC# PCI_SERR#12R556 R557 R559 R5601 1 1 18.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5% 8.2K_0402_5%NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3USBR554 R555 R581 R5792 2 2 2AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31PCID1 1 1 1REV1.0H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H362PU41E+3VSR160 R588 R585 R1583G435432Wednesday, June 30, 2010Sheet 117of56 18. 54321+3VS+3VSEC_GA20 CRT_DET2 10K_0402_5% PCH_GPIO22R651 12 10K_0402_5% PCH_GPIO39R264 1 @TACH3 / GPIO7EC_SMI#F10PCH_GPIO12K9 T72 10K_0402_5% PCH_GPIO48 2 10K_0402_5% PCH_TEMP_ALERT# 17,21 DGPU_HOLD_RST# 2 10K_0402_5% VGA_PWROK R161 1 50 VGA_PWROK 0_0402_5% 2 10K_0402_5% PCH_GPIO34 2 10K_0402_5% EC_SCI#R243 1 R178 1LAN_PHY_PWR_CTRL / GPIO12SATA4GP / GPIO16CLKOUT_BCLK0_N / CLKOUT_PCIE8NAM3CLK_CPU_BCLK# 5TACH0 / GPIO17CLKOUT_BCLK0_P / CLKOUT_PCIE8PAM1CLK_CPU_BCLK 5H10GPIO24AB12GPIO27PCH_GPIO28V13GPIO28PCH_GPIO34M11STP_PCI# / GPIO34PCH_GPIO35V621 PCH_GPIO282 10K_0402_5% PCH_GPIO24SCLOCK / GPIO22PECI RCIN#BG10 T1PROCPWRGDBD10DIS@ R262 12 10K_0402_5% VGA_PRSNT_L#R659 12 10K_0402_5% DGPU_HOLD_RST#R154 1 @2 10K_0402_5% DGPU_PWROK_110 RST_GATEAB7SATA2GP / GPIO36TP1AB13SATA3GP / GPIO37TP2AW22V3SLOAD / GPIO38TP3R229 12 10K_0402_5% PCH_GPIO35R263 1 @SDATAOUT0 / GPIO39TP4H3PCIECLKRQ6# / GPIO45TP5F1PCIECLKRQ7# / GPIO46TP6AV43SDATAOUT1 / GPIO48TP7AV45SATA5GP / GPIO49TP8AF13GPIO192 1CRT_DET1High: CRT Plugged2 G 2N7002E-T1-GE3_SOT23-3dGPU iGPU * SGGPIO37PCH_GPIO19VGA_PRSNT_L#0 0 10 1 0D Q20 @329 CRT_DET#SGPIO8This signal has a weak internal pull up can't Pull low GPIO27On-Die PLL Voltage Regulator This signal has a weak internal pull up*HOn-Die voltage regulator enable LOn-Die PLL Voltage Regulator disableNote: the internal pull-up is disabled after RSMRST# de-asserts. The On-Die PLL voltage regulator is enabled when sampled high. When sampled low the On-Die PLL Voltage Regulator is disabled.AF8A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53TP9CMAINPWON 44,45,47+1.05VS_PCHR224 @ 330_0402_5% 1 2C2 BEVSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31N18TP11AK41TP13AK42TP14M32TP15N32TP16M30TP17N30TP18H12TP19AB38NC_3AB42NC_4AB41NC_5BAB45NC_2H_THERMTRIP#AA23NC_1T39INIT3_3V#REV1.0Q14 2SC2411K_SOT23-3 @AJ24TP12GPIO57M18TP10R656 10K_0402_5%BAB6PCH_TEMP_ALERT# AA4 PCH_GPIO57+3VS+1.05VS_PCHAY46RST_GATEH_THERMTRIP# 51 56_0402_5%AY452 10K_0402_5% PCH_GPIO27GPIO27 (Have internal Pull-High) High: VCCVRM VR Enable Low: VCCVRM VR DisableH_THERMTRIP#BB22P3PCH_GPIO48 21,36 PCH_TEMP_ALERT#51 56_0402_5%2009/08/23 Series resistor of 565% Pull-up of 565% to VTT (both these should be close to PCH)BA22VGA_PRSNT_L#PCH_GPIO4521 VGA_PRSNT_L#DGPU_PWR_ENVGA_PRSNT_R#14,21,38,42 DGPU_PWR_ENPCH_GPIO28 PCH_GPIO57 PCH_GPIO45 RST_GATE2 R221310K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%H_CPUPWRGD THRMTRIP_PCH#SATACLKREQ# / GPIO35RSVD2 2 2 2EC_KBRST# 36BE10THRMTRIP#H_PECI 5 EC_KBRST#2 R220NCTFC1 1 1 1EC_GA20 36F38PCH_GPIO39R642 R640 R633 R630EC_GA20AA2PCH_GPIO242 1K_0402_5% PCH_GPIO15 @U2DGPU_PWROK_1Y710/7 Not Use PCH_GPIO15 PU 1K to +3VR242 1A20GATEGPIO15PCH_GPIO222 10K_0402_5% PCH_GPIO12 2 10K_0402_5% EC_SMI#R239 1DGPIO8(GPIO8 Have Internal Pull High,Should not be Pull-Low)(GPIO27 Have Internal Pull High) PCH_GPIO27 R245 1 R246 1AF48 AF47DGPU_HOLD_RST#22009/09/07 GPIO24 pull high +3V +3VCLKOUT_PCIE7N CLKOUT_PCIE7PTACH2 / GPIO6J32(GPIO15 Have Internal Pull Down) PCH_GPIO15R236 1 R658 1 R155 12 10K_0402_5%AH45 AH46TACH1 / GPIO1D37EC_SCI#36 EC_SMI#2 10K_0402_5% DGPU_PWR_ENC38DGPU_HPD_INT#36 EC_SCI#CLKOUT_PCIE6N CLKOUT_PCIE6PBMBUSY# / GPIO0DGPU_EDIDSEL#30 DGPU_HPD_INT#DGPU_PWR_EN Pull Low at Page 43Y3CPUD2 10K_0402_5%121 CRT_DET 28 DGPU_EDIDSEL#R238 1R654 1EC_KBRST# R653 1U41F10K_0402_5% VGA_PRSNT_R# 10K_0402_5% VGA_PRSNT_L#2 2 UMA ONLY@MISCR655 1 R261 12 10K_0402_5% DGPU_EDIDSEL# 2 10K_0402_5% DGPU_HPD_INT#GPIOR582 1 R583 1TP24P62009/08/23 (Have internal PH,Do not pull down)C10TP24_SST@PAD T21INIT3_3VThis signal has weak internal PH, can't pull lowIBEXPEAK-M_FCBGA107AGPIO15 LIntel ME Crypto Transport Layer Security(TLS) chiper suite with no confidentiality HIntel ME Crypto Transport Layer Security(TLS) chiper suite with confidentiality*Compal Electronics, Inc.Compal Secret DataSecurity Classification 2009/08/01Issued DateDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.CRB has a 1-k pull-up on this signal to +3.3VA rail. 5Rev C401869Date:432Wednesday, June 30, 2010Sheet 118of56 19. 54321Need Modify 180 ohm @ 100MHz Bead+1.05VS_VTT +1.05VS_PCH+3VSNear AB24Near AB24 Top SideIntel suggest follow CRB 8/21All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V railsDG 1.6 (Page 329) Have Internal VRMC+1.05VS_PCH10U_0805_10V4Z 1 C719Near AN20 1 C3212Top Side1U_0402_6.3V4Z 1 C34221 C34521U_0402_6.3V4Z1U_0402_6.3V4Z 1 C348221U_0402_6.3V4Z+3VSFollow Intel suggestion 8/21Near AN35 0.1U_0402_16V4Z C329 2 1BDG 1.6 (Page 329) T9 PAD Have Internal VRM+VCCAPLL_FDI@+1.05VS_PCH1 AF51300mA VCCALVDSLVDS42mAVCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO[50] VCCIO[51] VCCIO[52] VCCIO[53]AN30 AN31VCCIO[54] VCCIO[55]AN35VCC3_3[1]VCCFDIPLLAM23VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]AB34VCC3_3[3]AD35VCCIO[1]C331Near AE5061mA6mA+3VSL20 UMOP@ 2 1 0.1UH_MLF1608DR10KT_10%_16080.1uH inductor, 200mA 1 2 R145 DIS ONLY@ 0_0402_5%+3VS1CNear AB34VCCDMI[2]2 0_0805_5%+1.05VS_PCHR192 12 0_0805_5%+1.8VS+VCCVRMAT24VCCDMI[1]+1.05VS_PCH10milAU16156mACRB 0.9 is 180 ohm @ 100MHz DG0.8 is 600 ohm FB (Page 290)+1.8VS15mil+VCCTX_LVDS C300 C316 1 UMOP@ 1 1 0.01U_0402_16V7K 22U_0805_6.3V6M C304 0.01U_0402_16V7K UMOP@ 2 2 UMOP@ 240milAT16VCCPNAND[1] VCCPNAND[2] VCCPNAND[3] VCCPNAND[4] VCCPNAND[5] VCCPNAND[6] VCCPNAND[7] VCCPNAND[8] VCCPNAND[9]D2R138 1 UMOP@ 2 0_0805_5%Near AP430.1U_0402_16V4Z 235mA220 ohm bead,350mA2AB35VCC3_3[4]VCCVRM[2]1 2 L19 MBK1608221YZF_2PR172 0_0402_5% DIS ONLY@AP43 AP45 AT46 AT453208mA22U_0805_6.3V6M 1 C476C291R186 1 @VCCVRM[1]BJ1822U_0805_6.3V6M 11C2980.1U_0402_16V4Z 22+VCCA_LVDSAH39VCCAPLLEXPAN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH270.01U_0402_16V7K 1 C296R136 0_0402_5% @AH38VSSA_LVDSVCC3_3[2]BJ24VCCIO[24]AT22+VCCVRM10milVSSA_DAC[2]HVCMOS@ +VCCAPLL_EXPAF5359mA AK24T20 PADVSSA_DAC[1]+VCCADACAE5220mil+1.05VS_PCH10milAE50VCCADAC[2]DMIShort J4 for PCH VCCCORE2VCCADAC[1]69mA2C344VCCCORE[1] VCCCORE[2] VCCCORE[3] VCCCORE[4]1524mA VCCCORE[5] VCCCORE[6] VCCCORE[7] VCCCORE[8] VCCCORE[9] VCCCORE[10] VCCCORE[11] VCCCORE[12] VCCCORE[13] VCCCORE[14] VCCCORE[15]1C7182AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ3160mA15mil21U_0402_6.3V4Z 1CRT10U_0805_10V4Z 11NAND / SPI1PCI E*2@ JUMP_43X118FDI2 DPOWERU41GVCC COREJ1+VCC_DMIR204 12 0_0805_5%1 C368 1U_0402_6.3V4Z 2AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15Near AT16+1.8VSC3721B0.1U_0402_16V4Z 285mA VCCME3_3[1] VCCME3_3[2] VCCME3_3[3] VCCME3_3[4]AM8 AM9 AP11 AP9REV1.0Near AK13 +3VSC387IBEXPEAK-M_FCBGA10710.1U_0402_16V4Z 2Near AM8AACompal Electronics, Inc.Compal Secret DataSecurity Classification 2009/08/01Issued DateDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:5432Wednesday, June 30, 2010Sheet 119of56 20. 43@ C295 C324 22U_0805_6.3V6M 1U_0402_6.3V4Z 2 2C2942 22U_0805_6.3V6MNear AD381U_0402_6.3V4ZVCCME[7] VCCME[8]V42VCCME[9] VCCME[10] VCCME[11]Near V39All Ibex Peak-M Power rails with netnames +1.1VS and +1.1V rails are actually +1.05VS and +1.05V railsY42 C390 10mil 0.1U_0402_16V4Z +VCCRTCEXT 1 2Near V9 CAU24+VCCVRM20mil +VCCADPLLA20milC330 1U_0402_6.3V4Z212Near AF32C351+PCH_VCCIO 2 0_0603_5% 2 1 C336 1U_0402_6.3V4Z1 R1391U_0402_6.3V4ZNear AH35+3V72mA VCCADPLLA[1] VCCADPLLA[2]73mAVCCSUS3_3[30]U20VCCSUS3_3[31]U222VCCSUS3_3[32]VCC3_3[5]V16VCC3_3[6]1 Y162C36010.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z Near2AU18AT18A20milA12VCC3_3[7]V_CPU_IO[1] V_CPU_IO[2]2mA VCCRTCC3861C377+VCC5REFChange to 1U for power sequence issue on ICH9220.1U_0402_16V4ZNear A121C692 1U_0402_6.3V4Z22Near BD51D4 CH751H-40PT_SOD323-2 R141 100_0402_5% 1 2212/12 Follow EDS1.11 Change to 100 ohmC+5VSC299 1U_0402_6.3V6KN36 P36C337U350.1U_0402_16V4Z 2AD131Near J38 +3VSNear AD13AK3 AK110mil +VCCSATAPLL @2 C376 0.1U_0402_16V4ZPAD T23DG 1.6 (Page 329) Have Internal VRM BAH22 AT20VCCIO[10]AH19VCCIO[11]AD20VCCIO[12]AF221VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16]AD19 AF20 AF19 AH20C371 1U_0402_6.3V4Z 2VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20]AB19 AB20 AB22 AD22VCCME[13] VCCME[14] VCCME[15] VCCME[16]AA34 Y34 Y35 AA356mA VCCSUSHDA+VCCVRM +1.05VS_PCH+5VALWNear AB1942 SBPWR_EN#PCH_VCCME13 PCH_VCCME14 PCH_VCCME15 PCH_VCCME16R179 R164 R165 R1731 1 1 12 2 2 2L30R176 0_0402_5% 2 @ 1 C343 @ 0.1U_0402_16V4Z+1.05VS_PCH15milS21Q8R169 0_0402_5%G@ D AO3413L_SOT23-320_0603_5% 0_0603_5% 0_0603_5% 0_0603_5%+5V+3V C357 1A2 1U_0402_6.3V4ZNear L30Compal Electronics, Inc.Compal Secret DataSecurity Classification0.1U_0402_16V4Z 2@Near K491C373 1U_0402_6.3V4Z1+3VSVCCVRM[4]IBEXPEAK-M_FCBGA1072C349 1U_0402_6.3V6K1+RTCVCC11+5VNear F24VCC3_3[12]> 1mA10milR189 2 100_0402_5%1M36DCPSUSRTC4.7U_0805_10V4Z110milVCC3_3[11]VCCSUS3_3[29]AT18 C359+VCC5REFSUSVCC3_3[10]VCCSATAPLL[1] VCCSATAPLL[2]U191+VCCADPLLB+3VS2/12 Follow EDS1.11 Change to 100 ohmVCCIO[9]Near V151+1.05VS_PCH+1.05VS_PCHY222009/08/01Issued DateDeciphered Date2010/08/01TitleSCHEMATICS,MB A5893THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Rev C401869Date:543DD5 CH751H-40PT_SOD323-2L3832mADCPSSTV15C364+3VJ38VCC3_3[9]C689 220U_B2_2.5VM_R351+3VS+1.05VS_PCHK492 1U_0402_6.3V4Z2+10milVCC3_3[8]VCCIO[4]V12Near P180.1U_0402_16V4ZV5REF357mAR562 0_0402_5% @L61 1 2 10UH_LB2012T100MR_20%2>1mAC691 @Near U23VCCIO[3]P18C370F24VCCIO[2]Y220.1U_0402_16V4ZV5REF_SUS>1mAC688 220U_B2_2.5VM_R3510uH inductor, 120mAVCC3_3[14]VCCIO[21] VCCIO[22] VCCIO[23]V12C369V231+0.1U_0402_16V4Z 2Near A26VCC3_3[13]VCCADPLLB[1] VCCADPLLB[2]AF32+VCCSUS 1 2 C353 Near 0.1U_0402_16V4Z10milBVCCVRM[3]BD51 BD53AH34+VCCSST 1 2 C375 Near 0.1U_0402_16V4Z10milDCPRTCAF34Near AH23 1BB51 BB53VCCME[12]AH23 AJ35 AH35+VCCADPLLB+1.05VS_PCHV9U23VCCIO[56]VCCME[6]Y412V39 V41C3412AF42Y39C293163mAVCCME[5]0.1U_0402_16V4Z 2111C3471211C350Near BB51L60 1 2 10UH_LB2012T100MR_20%10uH inductor, 120mA3AF41 1VCCSUS3_3[28]VCCME[4]09/09/14 WW37 remove +VCCADPLLA +VCCADPLLA,+VCCADPLLB external 1U1VCCME[3]AF43+3VNear V24222U_0805_6.3V6M 1VCCME[2]AD41Follow Intel suggestionVCCME[1]AD39Near Y20+1.05VS_PCHC340 1U_0402_6.3V4Z 22+1.05VS_PCH1998mAAD380.1U_0402_16V4Z 2V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26+1.05VS_PCH111DCPSUSBYPUSB2Near AF23Y20HDAC367+PCH_VCCD6WVCCSUS3_3[1] VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5] VCCSUS3_3[6] VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCSUS3_3[21] VCCSUS3_3[22] VCCSUS3_3[23] VCCSUS3_3[24] VCCSUS3_3[25] VCCSUS3_3[26] VCCSUS3_3[27]344mAClock and Miscellaneous10milV24 V26 Y24 Y26PCI/GPIO/LPCC352 1U_0402_6.3V4Z 2 @DG2.0 Table162 Note2 (C295 unpop)1VCCLAN[2]1R199 0_0402_5%DVCCLAN[1]AF24+VCCLANVCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8]SATA2VCCACLK[2]PCI/GPIO/LPC@1R187 1 0_0603_5%15milVCCACLK[1]AF23+1.05VS_PCH11REV1.052mAAP51 AP53DG 1.6 (Page 329) Have Internal VRM2POWERU41J10mil+1.1VS_VCCACLK@T17 PADCPU52Wednesday, June 30, 2010Sheet 120of56 21. 54U41IBAU41HVSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VS

aspire 4551 g

Technology

switched power rail

pch power

vs power railonoffoff

valw power railononon

power circuit dcdc page

lan power rail

battery power rail

p power onoff