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Back in 2015, only Outsourced Semi-conductor Assembly and Test (OSAT)players were involved in Fan-Out (FO)packaging. But in 2016, TSMC led theentry of foundries into this market. Withits integrated FO (inFO) packagingtechnology, TSMC and Apple introducedthe first high density FO package in themobile segment. Now, Integrated DeviceManufacturers (IDMs) like Samsung havejoined the race with new in-housetechnology at the panel level. The result isthat in 2019 OSATs have only a third ofthe market. Even with this reduced share,they are still developing and enhancingtheir portfolio in this segment. ASE, inpartnership with Deca Technologies, hasdeveloped FO technology targeting thecore market. Formerly a user ofEmbedded Wafer Level Ball Grid Array(eWLB) packaging, ASE has moved to M-series packaging technology for itsadvanced Wafer Level Packaging (aWLP).
With production maturity, fablesscompanies like Qualcomm are seekingyield loss improvements, reducing thenumber of chipped dies following dicing.FOWLP was eventually adopted as side-wall protection to help manage incomingdies regardless of whether they’re on200mm or 300mm wafers, which resolvedthe yield issue. In the past, Qualcomm hasused eWLB for side-wall protection forthis purpose. But now the M-seriestechnology from Deca Technologies ismature. ASE, the current OSAT supplierfor Qualcomm, has switched packagingproduction.
One of the main advantages of thetechnology is that at a similar price to theeWLB technology, the M-series offersbetter quality and board level reliability(BLR). Indeed, one of the key enablers isthe use of epoxy molding compound(EMC) between the die and theredistribution layers (RDLs).
This report includes a full investigation ofthe component, featuring a detailed studyof the PMIC including packaging, diedesign and cross-sections. It contains acomplete cost analysis and a selling priceestimation of the component. Finally, itfeatures a comparison with theQualcomm WCD9335 Audio Codec,featuring eWLB packaging.
COMPLETE TEARDOWN WITH
• Detailed photos and cross-sections
• Precise measurements
• Material analysis
• Manufacturing process flow
• Supply chain evaluation
• Manufacturing cost analysis
• Comparison with WCD9335 using eWLB for Side Wall Protection
• Estimated sales price
ASE/Deca’s patented fan-out technology has penetrated a new commerciallyavailable device, the Qualcomm PM8150 PMIC.
REVERSE COSTING® – STRUCTURE, PROCESS & COST REPORT
Title: ASE/Deca M-Series Fan-Out Process
Pages: 111
Date: September 2019
Format: PDF & Excel file
Price: EUR 3,990
ASE/Deca M-Series Fan-Out Process
IC – LED – RF – MEMS – IMAGING – PACKAGING – SYSTEM – POWER - DISPLAY
TABLE OF CONTENTS
Overview/Introduction
Qualcomm Company profile and ASE/DecaRoadmap
Samsung Galaxy S10 5G USA Teardown
Market Analysis
Physical Analysis
• Physical Analysis Methodology
• M-Series Packaging Analysis
o Package view and dimensions
o Package cross-section: RDLs, UBM, copper studs
o Package process analysis
• PMIC Die Analysis
o Die view and dimensions
o Die delayering and main block IDs
o Die cross-section
o Die process
Manufacturing Process Flow
• PMIC Die Process and Fabrication Unit
• M-Series Packaging Process Flow and Fabrication Unit
Cost analysis
• Overview of the Cost Analysis
• Supply Chain Description
• Yield Hypotheses
• PMIC Die cost Analyses
o Front-end cost
o Wafer and die cost
• M-Series Package Cost Analysis
o Packaging front-end cost
o Packaging cost by process step
• Final Test Cost
• Component Cost
Estimated Price Analysis
Comparison between eWLB and M-Series for Side Wall Protection
ASE/DECA M-SERIES FAN-OUT PROCESS
RELATED REPORTS
AUTHORS
Dr. Stéphane Elisabeth has joinedSystem Plus Consulting's team in 2016.He has a deep knowledge of Materialscharacterizations and Electronicssystems. He holds an EngineeringDegree in Electronics and NumericalTechnology, and a PhD in Materials forMicroelectronics.
Nicolas Radufe is in charge of physicalanalysis at System Plus Consulting. Hehas a deep knowledge in chemical andphysical analyses. He previouslyworked in microelectronics R&D forCEA/LETI in Grenoble and forSTMicroelectronics in Crolles.
Advanced packaging technology in the Apple Watch Series 4’s SiPFour major packaging technologies: ASE’s SiP & modified SESUB, TSMC’s inFO-ePoP, Skyworks’ Double Side BGA.January 2019 - EUR 3,990*
Samsung Exynos 9110 with ePLP: First Generation of Samsung’s FO-PLPThe first ultra-small multi-chip High Volume Manufacturing (HVM) FO-PLP device for consumer applications found in the Samsung Galaxy Watch.November 2018 - EUR 3,990*
Intel’s Embedded Multi-Die Interconnect Bridge (EMIB)First consumer application in the Intel Core 8th Generation i7-8809G, the world’s first On-Package CPU and GPU with High Bandwidth Memory.October 2018 - EUR 3,490*
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