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EL3010 Computer Architecture 2012 MidTerm Exam #2 Due: Wednesday 2 May,2012 1. Using the Booth Algorithm multiply two 6 bit numbers: 2 * -18. The result is stored in a 12 bit register. Show the steps in the table format shown in class. (Multiplicand = 2 and multiplier is -18) Last Row : 1111 1101 1100 = -36 2. Show a sequence of MIPS instructions to implement while (a < p) { x = x * -2.0; a++; } Assume a is $t0, p is $t1 and x is $t3. Single Cycle Implementation MIPS(Refer to the diagrams and tables for the single cycle). 3. List the value of the control signals for the following instructions a. addi $a1, $t0, 0x003 b. slt $s0, $t0, $0 4. We want to add two instructions addu and subu. In the figure 5.12 and 5.13, we need to add two new entries (rows) for the R-type instructions. To distinguish these instructions from other R-type you must consider the FUNCT field for each instruction. The value chosen for the ALU control input is up to you. Cache and Memory Hierarchy 5. Here is a series of address references: 1, 2, 5, 7, 20, 15, 17, 45, 76, 11, 4, 3, 6. Assuming a direct mapped cache with 16 lines (or blocks) and each line contains 2 words. Label each reference as hit or miss and show the final content of the cache. 6. Consider a memory hierarchy using one of the three organization of main memory (one word (8 bits), wide, and interleaving). Assume that a cache block is 64 bits and width of the wide organization is 16 bits). If the address cycle is 1 cycle, the memory latency is 9 cycle and the data transfer is 2 cycle, what are the miss penalties for each organization? 7. The first-level data cache for a certain processor contains 2048 blocks. Assume that the word size is 32 bits, the block size is 64 bytes, the size of the physical memory is 2 GB, and the cache is 2-way set associative. Do not forget the valid bit. a. How many bits are used for Tag, Index, and Offset? b. What is the size of the cache in bytes? MIPS Programming 8. Create a program to compute determinant of a 2x2 matrix. Remember how a a 2-D array is stored in memory. Result is stored in memory. Use integer only operations and assume all result are 32-bit

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Page 1: Arsitektur Komputer

EL3010 Computer Architecture 2012

MidTerm Exam #2Due: Wednesday 2 May,2012

1. Using the Booth Algorithm multiply two 6 bit numbers: 2 * -18. The result is stored in a 12bit register. Show the steps in the table format shown in class. (Multiplicand = 2 andmultiplier is -18)Last Row : 1111 1101 1100 = -36

2. Show a sequence of MIPS instructions to implement while (a < p) {

x = x * -2.0;a++;

}Assume a is $t0, p is $t1 and x is $t3.

Single Cycle Implementation MIPS(Refer to the diagrams and tables for the single cycle).3. List the value of the control signals for the following instructions

a. addi $a1, $t0, 0x003b. slt $s0, $t0, $0

4. We want to add two instructions addu and subu. In the figure 5.12 and 5.13, we need to addtwo new entries (rows) for the R-type instructions. To distinguish these instructions fromother R-type you must consider the FUNCT field for each instruction. The value chosen forthe ALU control input is up to you.

Cache and Memory Hierarchy5. Here is a series of address references: 1, 2, 5, 7, 20, 15, 17, 45, 76, 11, 4, 3, 6. Assuming a

direct mapped cache with 16 lines (or blocks) and each line contains 2 words. Label eachreference as hit or miss and show the final content of the cache.

6. Consider a memory hierarchy using one of the three organization of main memory (one word(8 bits), wide, and interleaving). Assume that a cache block is 64 bits and width of the wideorganization is 16 bits). If the address cycle is 1 cycle, the memory latency is 9 cycle and thedata transfer is 2 cycle, what are the miss penalties for each organization?

7. The first-level data cache for a certain processor contains 2048 blocks. Assume that the wordsize is 32 bits, the block size is 64 bytes, the size of the physical memory is 2 GB, and thecache is 2-way set associative. Do not forget the valid bit.a. How many bits are used for Tag, Index, and Offset? b. What is the size of the cache in bytes?

MIPS Programming8. Create a program to compute determinant of a 2x2 matrix. Remember how a a 2-D array is

stored in memory. Result is stored in memory. Use integer only operations and assume allresult are 32-bit