arms processor
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The ARM Architecture
Delivered atSan Jose State University
28/4/10
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
ata at an pe nes
AMBA
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ARM Ltd
Founded in November 1990
Designs the ARM range of RISC processor cores
partners who fabricate and sell to their customers.
ARM does not fabricate silicon itself
Also develop technologies to assist with the design-in of the ARM architecture
Software tools, boards, debug hardware,
app ca on so ware, us arc ec ures,peripherals etc
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ARMs Activities
Software IP
Development Tools
memorymemoryProcessors
System Level IP:
Data Engines
Fabric
3D Graphics
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Physical IP
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ARM Connected Community 550+
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Nokia N95 Multimedia Computer
Applications ProcessorARM1136 processor-based
SoC, developed using Magma
Blast famil and winner of
Symbian OS v9.2Operating System supporting ARM
2005 INSIGHT Award for Most
Innovative SoC
processor- ase mo e ev ces,developed using ARM RealView
Compilation Tools
S60 3rd EditionS60 Platform su ortin ARM
Mobiclip Video CodecSoftware video codec for ARM
processor-based mobile devices
processor-based mobile devices
ST WLAN SolutionUltra-low power 802.11b/g WLAN
chip with ARM9 processor-basedMAC
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Connect. Collaborate. Create.
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Applications
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
ata at an pe nes
AMBA
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Architecture Versions
ARMv7-Cortexx1-4
Cortex-A9
-
x1-4ARMv6
ARM1176JZ(F)-S
ARM11 MPCore
ARMv5
ARM1156T2(F)-S
ARM1136J(F)-S
ARM1026EJ-S
Cortex-R4F
ARM966E-S
ARM968E-S
ARM926EJ-S
ARM946E-S
or ex-
ARMv4
SC200ARM7EJ-S
ARM922TARM920T
SC300Cortex-M3
10 10
SC100ARM7TDMI(S) Cortex-M1
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Relative Performance*
1200
800
1000
0.43
0.568
m z
400
600req z
0.360.335
0.235
0
ProcessorxA8
76JZ-S
26EJ-S
20T
TDMI
136J-S
026EJ-S
.0.35
Corte
ARM
1
ARM
9
ARM
ARM
ARM
1
ARM
1
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*Represents attainable speeds in 130, 90 or 65nm processes
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Cortex family
Cortex-A8
Architecture v7A
Cortex-R4
Architecture v7R
Cortex-M3
Architecture v7M
AXI VFP & NEON support
AXI
Dual Issue
AHB Lite & APB
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Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
en use n re at on to t e :
Byte means 8 bits
Halfword means 16 bits two b tes
Word means 32 bits (four bytes)
Most ARMs implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
Jazelle cores can also execute Java bytecode
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ARM and Thumb Performance
30000
20000
25000
10000
15000 ARM
Thumb
.@ 20MHz
0
5000
Memory width (zero wait state)
32-bit 16-bit 16-bit with32-bit stack
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Thumb-2 Instruction Set
Second generation of the Thumb architecture
Blended 16-bit and 32-bit instruction set
25% faster than Thumb
EEMBC Analysis - Performance
30% smaller than ARM
Increases performance but maintains code
Maximizes cache and tightly coupled memory
usage
EEMBC Analysis Code Size
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Processor Modes
The ARM has seven basic operating modes:
ser : unpr v ege mo e un er w c mos as s run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
Supervisor : entered on reset and when a Software Interrupt
instruction is executed
Abort : used to handle memory access violations
Undef : used to handle undefined instructions
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System : privileged mode using the same registers as user mode
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Exception Handling
When an exception occurs, the ARM:
_
Sets appropriate CPSR bits
Change to ARM state FIQ0x1C
Change to exception mode
Disable interrupts (if appropriate)
(Reserved)
Data Abort
x
0x14
0x10
_
Sets PC to vector address
To return, exception handler needs to:
Software Interrupt
Undefined Instruction
Reset
0x08
0x04
0x00
Vector Table Restore CPSR from SPSR_
Restore PC from LR_ Vector table can be at0xFFFF0000 on ARM720T
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. an on 9 10 am y ev ces
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Program Status Registers
2731
N Z C VQ
28 67
I F T mode
1623 815 5 4 024
f s x c
U n d e f i n e dJ
Condition code flags
N = Negative result from ALU
Z = Zero result from ALU
Interrupt Disable bits.
I = 1: Disables the IRQ.
F = 1: Disables the FIQ.
C = ALU operation Carried out
V = ALU operation oVerflowed T Bit
Architecture xT only
Sticky Overflow flag - Q flag
Architecture 5TE/J only
Indicates if saturation has occurred
T = 0: Processor in ARM state
T = 1: Processor in Thumb state
J bit Architecture 5TEJ only
J = 1: Processor in Jazelle state
Mode bits Specify the processor mode
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Cortex-M3 Programmers Model
Fully programmable in Cr0
r1
Main
Stack-based exception model
Only two processor modes
r2
r3r4
r5
rea o e or ser as s
Handler Mode for OS tasks and exceptions
Vector table contains addresses
r8
r9
r6
r7
Process
r11
r12
sp
lrsp
r15 (pc)
xPSR
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Conditional Execution and Flags
ARM instructions can be made to execute conditionally by postfixing them with theappropriate condition code field.
forward branch instructions.CMP r3,#0 CMP r3,#0
BE ski ADDNE r0 r1 r2
ADD r0,r1,r2
skip
By default, data processing instructions do not affect the condition code flags butthe flags can be optionally set by using S. CMP does not need S.
loop
SUBS r1,r1,#1
BNE loop if Z flag clear then branch
decrement r1 and set flags
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Classes of Instructions (v4T)
Load/Store
Miscellaneous
Data Operations
MOV PC, Rm
Change of Flow
BL
BLX
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Data processing Instructions
Consist of :
Arithmetic: ADD ADC SUB SBC RSB RSC
Logical: AND ORR EOR BIC
Comparisons: CMP CMN TST TEQ
Data movement:MOV MVN
These instructions only work on registers, NOT memory.
S ntax:
{}{S} Rd, Rn, Operand2
Comparisons set flags only - they do not specify Rd
Data movement does not specify Rn
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econ operan s sen o e v a arre s er.
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Using a Barrel Shifter:The 2nd Operand
Register, optionally with shift operation
Operand Operand
5 bit unsigned integer
Specified in bottom byte of.
Used for multiplication by constantShifter
8 bit number, with a range of 0-255.
Rotated right through evenALU
Allows increased range of 32-bit
constants to be loaded directly intore isters
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Single register data transfer
LDR STR Word
LDRB STRB Byte
a wor
LDRSB Signed byte load
Memory system must support all access sizes
Syntax:
LDR{}{} Rd, STR{}{} Rd,
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e.g. LDREQB
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
ata at an pe nes
AMBA
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The ARM7TDM Core
AddressIncrementer
A[31:0]ABE
nWAITMCLKBIGEND
PC U date
PC
Multiplier
Instruction
Decoder
nIRQnFIQ
nRWMAS[1:0]
ISYNC
Decode Stage
InstructionDecompression
A B
A
L
U
nMREQSEQ
ABORT
LOCK
nTRANS
BarrelShifter
Read DataRegister
and
Control
B
u
s
B
u
s
B
u
s
nCPICPACPB
nOPC
32 Bit ALU
Write DataRegister
og c
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D[31:0]DBE
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Pipeline changes for ARM9TDMI
RegRead
Shift ALUReg
WriteThumbARM
ARM decodeInstruction
Fetch
ARM7TDMI
Reg Select
FETCH DECODE EXECUTE
InstructionFetch
Shift + ALU MemoryAccess
RegWriteRegReg
ARM or ThumbInst Decode
eaeco e
FETCH DECODE EXECUTE MEMORY WRITE
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ARM10 vs. ARM11 Pipelines
Shift + ALUMemoryBranch ARM or
ARM10
ccess egWrite
eg ea
MultiplyInstructionFetch
umInstruction
Decode MultiplyAdd
ARM11
Shift ALU Saturate
Fetch1 Fetch2 Decode Issue WritebackMAC1 MAC2 MAC3
AddressData
CacheData
Cache
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Full Cortex-A8 Pipeline Diagram
13-Stage Integer Pipeline 10-Stage NEON Pipeline
Architectur
NEON
lregisterfile
registerfile
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
ata at an pe nes
AMBA
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An Example AMBA System
High PerformanceAPB
HighBandwidth
TimerAHB
ExternalMemoryInterface
BridgeKeypad
High-bandwidthon-chip RAM
DMABus Master
PIO
Low Power
High PerformancePipelinedBurst SupportMulti le Bus Masters
Non-pipelinedSimple Interface
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AHB Structure
Arbiter
HWDATA
Master
#1
Slave
#1
HADDR
HWDATA
HRDATA
HRDATA
Master#2
Slave#2
Address/Control
Master
Slave#3
Write Data
Read Data
Decoder
Slave#4
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
ata at an pe nes
AMBA
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Keil Development Tools for ARM
Includes ARM macro assembler, compilers (ARM RealView C/C++, , , ,
Debugger and Keil uVision IDE Keil uVision Debugger accurately simulates on-chip peripherals (I
2C, CAN,, , n errup s, or s, an conver ers, , e c.
Evaluation Limitations
16K byte object code + 16K data limitation
Some linker restrictions such as base addresses for code/constants
GNU tools provided are not restricted in any way
http://www.keil.com/demo/
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Keil Development Tools for ARM
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University Resources
http://www.arm.com/support/university/
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Beagle Board
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T ti it d l t
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Targeting community development
$149
> 1000 participantsand growing
, ,promotion ofcommunity
activity
Personallyaffordable
Freedom toinnovate
Active &technicalcommunit
Open access to Instant access to
Addressingopen source
ar waredocumentation
of code
needs
software
to tinker andlearn
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F t l fl ibl i
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Fast, low power, flexible expansion
OMAP3530 Processor
600MHz Cortex-A8Peripheral I/O
DVI-D video out
16KB/16KB L1$
256KB L2$
430MHz C64x+ DSP
SD/MMC+
S-Video out
USB 2.0 HS OTG
3
32K/32K L1$
48K L1D
32K L2
I2C, I2S, SPI,
MMC/SD
JTAG PowerVR SGX GPU
64K on-chip RAM Stereo in/out
Alternate power
RS-232 serial
128MB LPDDR RAM
256MB NAND flash USB Powered 2W maximum consumption
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OMAP is small % of that Many adapter options
Car, wall, battery, solar,
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On-going collaboration at BeagleBoard.org
And more
Other Features
Links to software projects to download
Peripheral I/O DVI-D video out
3 USR0
USR1
PMU STAT / +
S-Video out
USB HS OTG
_
PWR
2 buttons
USER
I C, I S, SPI,
MMC/SD
JTAG
RESET
4 boot sources
SD/MMC
Stereo in/out
Alternate power
RS-232 serial
USB
Serial
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Project Ideas Using Beagle
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Project Ideas Using Beagle
OS Projects OS porting to ARM/Cortex (TI OMAP), such as open source FreeBSD
Super-Beagle stack of Beagles as compute engine and taskdistribution
NEON Optimization Projects
Voice and image recognition
Open-source Flash player optimizations (swfdec)
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Fin
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