ARM Microprocessor and ARM-BasedMicrocontrollers

Nguatem William

24th May 2006

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A Microcontroller-Based Embedded System

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Introduction ARM Extensions IP Cores ARM based System Summary

Roadmap

1 IntroductionARMARM Basics

2 ARM ExtensionsThumbJazelleNEON & DSP EnhancementSummary

3 ARM Processor Cores

4 ARM based SystemMicrocontrollerARM Products

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Introduction ARM Extensions IP Cores ARM based System Summary

Roadmap

1 IntroductionARMARM Basics

2 ARM ExtensionsThumbJazelleNEON & DSP EnhancementSummary

3 ARM Processor Cores

4 ARM based SystemMicrocontrollerARM Products

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM

ARM

ARM History

ARM - Acorn RISC Machine from Acorn Computers Ltd. ofCambridge,UK.In 1990, ARM Ltd. was established and ARM wasrenamed as Advanced RISC Machines.

ARM Ltd.

A semiconductor IP - Intellectual Property company.Licenses IP cores to partner companies e.g Nokia, PhilipsSemiconductors.Also develop technologies to assist with the designing ofthe ARM architectureARM is not a chip producer.

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM

IP - Intellectual Property

IP - Intellectual PropertyARM provides hard and soft views to licensees (RTL andsynthesis flows GDSII layout) IPSoft views include gate level netlists (RTL source code)→ synthesizable from licensees using a suitable gatelibraryHard IP are the final GDSII layout given to the customerOEMs must use hard views to protect ARM IP

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

ARM feature (I)

Partly from Berkeley RISC concept

A load-store architecture.Fixed-length 32-bit instructions3-address instruction formatPipelined architectureConditional execution of all instructionsExtensible ISA through hardware CoprocessorsThe ability to perform a general shift operation and ageneral ALU operation in a single instruction that executesin a single clock cycle

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

ARM Features (II)

rejected from Berkeley RISC concept

Register Window.Delayed branches

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

Modes (I)

7 operating modes

user : Unprivileged, normal execution modeFIQ : High priority (fast) interrupt raisedIRQ : Low priority Interruptsvc: Software interrupt(SWI) is executedAbort: Handling of memory access violationssystem : Run privileged taskUndefined : Undefined instructions

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

Modes (II)

QuestionWhy FIQ and IRQ ?

Answer

FIQ has a higher priority than IRQGives a better mapping of different interrupt sourcesFIQ has extra bank registers than IRQ→ faster than IRQ

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

Registers

RegistersARM has 37 registers all of which are 32-bits long

1 dedicated program counter1 dedicated current program status register5 dedicated saved program status registers30 general purpose registers

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

Accessible RegistersThese registers cannot all be seen at once. The processorstate and operating mode dictate which registers are availableto the programmer.

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

Processor Status Register - CPSR

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

Data Sizes and Instruction Sets

Data sizesThe ARM is a 32-bit architecture.When used in relation to the ARM:

Byte means 8 bitsHalfword means 16 bits (two bytes)Word means 32 bits (four bytes)

ISAMost ARMs implement two instruction sets.

32-bit ARM Instruction Set16-bit Thumb Instruction Set

Jazelle cores can also execute Java bytecode

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

Memory

EndianessNeutrality to Endianess.Can be configured at power-up as either little- orbig-endian mode.Default alignment is little-endian due to many little-endianperipheral component available.

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Basics

Coprocessors

Coprocessor interfaceProvide support for hardware coprocessors.

AdvantagesExtends the instruction set,e.g On-Chip control of MMU and Cache, floating pointarithmetic

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Introduction ARM Extensions IP Cores ARM based System Summary

Roadmap

1 IntroductionARMARM Basics

2 ARM ExtensionsThumbJazelleNEON & DSP EnhancementSummary

3 ARM Processor Cores

4 ARM based SystemMicrocontrollerARM Products

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Introduction ARM Extensions IP Cores ARM based System Summary

Thumb

Thumb (I)

Thumb is a 16-bit instruction set.Core has additional execution state - ThumbSwitch between ARM and Thumb using BX instructionNot a complete ISA

Difference to ARM Inst.Conditional execution is not usedSource and destination registersidenticalThumb bit in CPRS is setInline barrel shifter not used

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Introduction ARM Extensions IP Cores ARM based System Summary

Thumb

Thumb (II)

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Introduction ARM Extensions IP Cores ARM based System Summary

Thumb

Thumb (III)

Thumb-216-bit coding of more ARM instruction.

Pros and Cons of Thumb+ Excellent code density for minimal system size.- No direct access of Status registers while in Thumb state- No conditional execution, excepting branch instructions- With 32-bit memory, the ARM code is 40% faster thanThumb code+ With 16-bit memory, the Thumb code is 45% faster thanARM code

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Introduction ARM Extensions IP Cores ARM based System Summary

Thumb

Thumb (IV)

Thumb ApplicationA typical embedded system, e.g. a mobile phone, will include asmall amount of fast 32-bit memory (to store speed-critical DSPcode) and 16-bit off-chip memory to store the control code.

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Introduction ARM Extensions IP Cores ARM based System Summary

Jazelle

Jazelle (I)

Hardware accelerated java code mechanism.

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Introduction ARM Extensions IP Cores ARM based System Summary

Jazelle

Jazelle (II)

FeaturesProcessor fetches one word containing 4-javabytes.J-bit of status register set

Jazelle typesJazelle DBX - Direct Byte eXecution: supports onlyjavabyte codesJazalle RCT - Run time CompilaTion: extension ofThumb-2,supports different VM.

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Introduction ARM Extensions IP Cores ARM based System Summary

Jazelle

TrustZone

TrustZone.Hardware based security mechanismComplete code separation

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Introduction ARM Extensions IP Cores ARM based System Summary

NEON & DSP Enhancement

NEON & DSP Enhancement

NEON.Hardware acceleration formultimedia applicationsCombines 64-bit and 128-bit hybridSIMDSeparate execution i.e completeinstruction architecture.

DSP ExtensionAdded DSP instructions to ARM ISA

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Introduction ARM Extensions IP Cores ARM based System Summary

Summary

Conclusion

Note- Extra logic needed for the hardware extension: e.gThumb decompression unit.- Increase die size and cost.+ Simple implementation+ Very efficient

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Introduction ARM Extensions IP Cores ARM based System Summary

Roadmap

1 IntroductionARMARM Basics

2 ARM ExtensionsThumbJazelleNEON & DSP EnhancementSummary

3 ARM Processor Cores

4 ARM based SystemMicrocontrollerARM Products

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM7 Core

Features32-bit RISC ArchitectureVon Neumann Architecture3-Stage Pipeline - Fetch, Decode ExecuteMost instructions execute in a single cycle.ARMv4 ISASupports up to 16 coprocessors.

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Introduction ARM Extensions IP Cores ARM based System Summary

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM9 Core

FeaturesPerformance of the ARM7 Von Neumann architecture limited bythe available bandwidth - memory accessed on almost everycycle either to fetch an instruction or to transfer data.

Harvard architecture improves CPI - Clock cycles PerInstructionHigher performance core than ARM7Five-stage pipeline - Fetch, Decode, Execute, Memory,and Write

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM9E

FeaturesARM9 core + DSP extensionsEnhanced multiplier for DSP performanceOn-Chip debug hardware

BenefitsSingle engine for both DSP and control codeSimple single memory system.Reduced chip complexity, die size and power consumptionSingle toolkit support with ARMs Development and Debugtools, giving faster time-to-market

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Introduction ARM Extensions IP Cores ARM based System Summary

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Introduction ARM Extensions IP Cores ARM based System Summary

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Introduction ARM Extensions IP Cores ARM based System Summary

Roadmap

1 IntroductionARMARM Basics

2 ARM ExtensionsThumbJazelleNEON & DSP EnhancementSummary

3 ARM Processor Cores

4 ARM based SystemMicrocontrollerARM Products

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Introduction ARM Extensions IP Cores ARM based System Summary

Microcontroller

ActelCoreMP7 andSubsystem

ARM7TDMI-S32/16-bit RISCarchitectureARM and Thumbinstruction setsEmbedded real-timedebug and JTAGinterface

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Introduction ARM Extensions IP Cores ARM based System Summary

Microcontroller

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Products

ARM Powered Products

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Introduction ARM Extensions IP Cores ARM based System Summary

ARM Products

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Introduction ARM Extensions IP Cores ARM based System Summary

Summary

SummaryARM Cores are IPsHybrid instruction encoding offers better efficiency inembedded applicationsBackward software compatibility for all new cores

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Introduction ARM Extensions IP Cores ARM based System Summary

Questions ?

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