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ARM AT91SAM 9XE512

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WHATISARM?

Advanced RISC Machine

Market-leader for low-power

and cost-sensitive embedded applications

Architectural simplicity

which allows

Very small implementations

which result in

Very low power consumption

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APPLICATIONS

Product Type Application

Consumer Smartphones, PDA, Set top box,Electronic toys, Digitalcameras etc

NetworkingWireless LAN, 802.11, bluetooth,Firewire etc

Automotive Power train, ABS, Body systems,

Navigation, etc

Embedded USB controllers, bluetoothcontrollers, medical scanners etc

Storage HDD controllers, solid state drives

etc

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THEHISTORYOFARM

Developed at Acorn Computers Limited,of Cambridge, England, between 1983 and 1985

Later they spun off the Acorn Computers and

launched a new company called ARM Ltd. In 1990.(Acorn, Apple & VLSI Technologies)

ARM architecture is licensable.

Licensees include ATMEL, INTEL,

SAMSUNG,PHILIPS(NXP), TEXAS etc.

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ARM ARCHITECTURE

Typical RISC architecture: Large uniform register file

Load/store architecture

Simple addressing modes

Uniform and fixed-length instruction fields

Increases speed most instructions executed in

single cycle

Pipeline Versions:

3-stage (ARM7TDMI and earlier)

5-stage (ARMS, ARM9TDMI)

6-stage (ARM10TDMI)

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ARMCORES

Architecture Family

ARMv1 ARM1

ARMv2 ARM2, ARM3

ARMv3 ARM6, ARM7

ARMv4 Strong ARM, ARM7TDMI,

ARM9TDMI

ARMv5 ARM7EJ, ARM9E, ARM10E,

XScale

ARMv6 ARM11

ARMv7 Cortex

ARMv8 Will support 64-bit data and

addressing

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ARM AT91SAM 9XE512

ATMELs Smart ARM-based Microcontrollers.

Incorporates the ARM926EJ-S ARM Processor.

DSP Instruction Extensions

Harvard Architecture

Two Instruction SetsARM 32-bit Instruction Set

Thumb 16-bit Instruction Set

5-Stage Pipeline

Fetch (F)

Decode (D)

Execute (E)

Data Memory (M)

Write back (W)

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REGISTERS

Sixteen 32 bit registers(R0-R15) & CPSR (currentprogram status register ).

R0 R12 are user registers.

R13 used as stack pointer (SP).

R14 is the link register (LR). On a function call, thereturn address is automatically stored in LR

R15 is the program counter (PC)

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CPSR

Divided into four 8 bits wide fields: flags, status,extension, and control.

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OPERATINGMODES

Seven different operating modes

Processor enters Abort Mode : when failed to access memory

FIQ Mode : when a high priority (fast) interrupt is raised

IRQ Mode : when a low priority (normal) interrupt is

raised Supervisor Mode : on reset and on a Software

Interrupt instruction is executed

Undefined Mode -when encounters an instruction thatis undefined or not supported

User Mode : unprivileged mode. Normal programexecution mode. Mode changed by exception only.

Systemmode - special version ofusermode, full read-write access to the CPSR

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BANKEDREGISTERS

20 registers are hiddenfrom a program.

Only available in

particular mode

Mode can be changed

by a program writes to

CPSR (except in user )

or by hardware

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EXCEPTIONHANDLING

When an exception occurs: Copies CPSR into SPSR _

CPU changes mode.

Stores the return address in LR_

PC be forced to exception vector.

To return from exception :

Restore CPSR from SPSR_ Restore PC from LR_

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ARM AT91SAM 9XE512BLOCKDIAGRAM

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Reset Controller(RSTC)

Shutdown Controller(SHDWC)

Four 32-bit backup registers(GPBREG)

32KHZ oscillator and a RC oscillator

Real-time Timer (32 bit RTT)

Main oscillator supports 3 to 20 MHz

Embeds 2 PLLs. PLL A outputs 80 to 240 MHz clock. PLL B outputs70 MHz to 130 MHz clock

Power Management Controller(PMC)

Advanced Interrupt Controller (AIC)

Debug Unit(DBGU) Periodic Interval Timer(20-bit PIT)

Watchdog Timer (16 bit WDT)

Brown Out Detect (BOR)

Power On Reset(POR)

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Two-slot Multimedia Card Interface (MCI)

4-channel 10-bit Analog to Digital Converter

Peripheral DMA Controller Channels (PDC)

Three 32-bit Parallel Input/Output Controllers

(PIOA, PIOB, PIOC)

2 Three-channel 16-bit Timer/Counters (TC)

One 2-wire UART

4 USART

2 Master/Slave SPI

USB 2.0 Full Speed Device Port (12 Mbps) 2 Two-wire Interfaces (TWI-I2C)

One Synchronous Serial Controllers (SSC- I2S)

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BUSMANAGEMENT

Consist of 2 Buses

6-layer AHB Matrix bus handling requests from 6

masters (Advanced High Performance Bus)

APB bus (Advanced Peripheral Bus)

Peripheral Bridge

24 channel Peripheral DMA Controller

Allows data transfers from peripheral to any memory

space without any intervention of the processor.

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MEMORYMAP

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MEMORYMAP

4 GBytes of address space

Divided into 16 banks of 256 Mbytes. Bank0 15

Bank 0 is reserved for the addressing of the internalmemories

The banks 1 to 7 are directed to the EBI that associates

these banks to the external chip selects EBI_NCS0 to

EBI_NCS7

The bank 15 is reserved for the peripherals