arm 11 presenatation for the beginners

7/28/2019 ARM 11 presenatation for the beginners

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Igor Kamzic

Brock University


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Previously known as Advanced RISCMachine

ARM architecture is 32 bit RISCprocessor architecture

Developed by ARM Limited

Widely used in embedded systemsARM 11 family compromises four series

of processors that implement the ARMarchitecture v6


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ARM 11 is the first implementation of theARMv6 instruction set architecture

It is the base for all family of ARM 11

coresThe key objective in developing ARM 11

microarchitecture was to deliver highperformance and low power consumption

together with low price ARM 11 has impact on wide variety of

applications in wireless, consumer,networking and automotive segments


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Superior performance of ARM 11 coresis possible because of ARMv6architecture

ARMv6 delivers superior performancetrough:

1. Media processing extensions

2. Improved cache architecture

3. Improved exception and interrupthandling

4. Unaligned and mixed endian data


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ARM 11 is Reduced Instruction SetComputer (RISC) and it incorporatesfollowing features:

1. Large uniform register file2. Load/store architecture where data

processing operations only operate on

register contents and not directly onmemory

3. Simple addressing modes with allload/store addresses being determined

from register contents and instruction


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In addition ARM 11 architectureprovides :

1. Control over ALU and the shifter in

most data processing instructions2. Auto increment and auto decrement

addressing modes to optimize program

loops3. Load and store multiple instructions to

maximize data throughput

4. Conditional execution on almost all

instructions to maximize execution


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ARM 11 has 31 general purpose 32-bitregisters and 6 status registers

At any of times only 16 of these

registers are visible and the others areused to speed up exception processing.

3 of those 16 visible registers have

special roles (stack pointer, link registerand program counter).


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ARM 11 supports 7 types of exceptions:

1. Reset

2. Attempted execution of undefined

instruction3. Software interrupts instruction

4. Prefetch abort

5. Data abort6. IRQ normal interrupt

7. FIQ fast interrupt


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ARM 11 instruction set can be dividedin 6 classes of instructions:

1. Branch instructions

2. Data processing instructions3. Status register transfer instructions

4. Load and store instructions

5. Coprocessors instructions6. Exception generating instructions


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To deliver enhanced performancekeyword in this architecture is pipeline

Pipeline in ARM 11 differs from all the

previous families of ARM cores innumber of stages it implements (8stages)

It enable 40 % better output then allprevious cores

ARM 11 avoids delays in pipeline byusing forwarding and branch prediction


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These techniques provide great efficiencyby reducing pipeline stalls

ARM 11 microarchitecture pipeline isscalar (issues one instruction at the time)

Improved memory access gives betteroverall performance significantly in ARM11

Instructions and data remain in cacheslonger which in turn reduces cache misses

One of the major improvements in ARM 11cores is non blocking operation ofmemory


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Even with pipeline that has single issueinstruction ARM 11 still manages toprovide parallelism

Parallelism is implemented at the backend of pipeline where we have separateunits for ALU and separate units for LS(load and store)

To maximize parallel pipeline ARM 11enables out of order completion(instructions dont have dependencies on

outcome of previous instruction)


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In some applications there is need for 64 bit processor

ARM 11 delivers 64 bit structure without

actually implementing the 64 bitsolution 64 bit data buses between processor

integer unit and instruction and data

caches and also between coprocessorsand integer unit (64 bit path allows twoinstructions to be fetched from cache inone cycle)

This gives great performance


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ARM 11 supports floating point asdesign option (cores with and coreswithout floating point processing units)

ARM 11 supports :

1.Java Decode

2. V6 SIMD Instructions

3. MIA Instructions (as coprocessors)

4. Performance Range (350 MHz - >1GHz)


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ARM 11 family of processors is widelyused in many areas

Some of the examples:

1. iPhone2. iPod Touch

3. NVIDIA GoForce 6100

4. Nokia E71 smartphone5. And many more


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The ARM 11 Microarchitecture

David Cormie

April 2002

www.cs.uiuc.edu/class/fa05/cs433ug/PROCESSORS/ARM%2011%20MicroArchitecture.pdf

www.arm.com (ARM 11documentation)

www.wikipedia.org

arm 11 presenatation for the beginners

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