A Reconfigurable FIR Filter Design Using DynamicPartial Reconfguration

Yeong-Jae Oh, Hanho Lee, Chong-Ho LeeSchool of Information and Communication Engineering

Inha University, Incheon, Korea.rokmcno6ggmail.com, {hhlee, chlee}ginha.ac.kr

Abstract This paper presents a novel partially The FIR filter is a special kind of digital filters and has areconfigurable FIR filter design that employs dynamic partial wide applicability because it has a good characteristic suchreconfiguration. Our scope is to implement a low-power, area- as linear phase and stability. However, it may need a largeefficient autonomously reconfigurable digital signal processing number of coefficients to obtain the desired specification.architecture that is tailored for the realization of arbitrary This results in the large number of area (slice) for FPGAresponse FIR filters. The implementation of design addresses design. Therefore, there are certain disadvantages associatedarea efficiency and flexibility allowing dynamically inserting with run-time reconfigurable design of higher order tap FIRand/or removing the partial modules. This design method filters using conventional FPGA design techniques. One ofshows the configuration time improvement by small the major disadvantages is the so called reconfigurableconfigured slice and good area efficiency as compared to the overhead, which is the time spent for reconfiguration. Thismethod of conventional FIR filters. depends on the reconfigurable device and the method of

I. INTRODUCTION reconfiguration. Partial reconfiguration can be used in thisFIR filters are emlydntecase since the 14-tap or 16-tap FIR filter have so manyFIR filters are employed in the majority of digital signal similarities in there structure. Therefore, partial

processing (DSP) based electronic systems. The emergence reconfiguration addresses the reduced reconfigurationof demanding applications (image, audio/video processing overhead, coefficient flexibility and area efficiency forand coding, sensor filtering, etc.) in terms of power, speed, higher order FIR filters.performance, system compatibility and reusability make itimperative to design the reconfigurable architectures. This paper is organized as follows. The modular designMoreover, in case of aerospace applications, there is the and module-based partial reconfiguration are described inadded concern for fault-tolerant FIR filtering fabrics, which Section II. Section III presents the design method ofare capable to respond to various malfunctions caused by reconfigurable FIR filter using DPR. Section IV presents theendogenous or exogenous factors. proposed design and implementation process for partially

reconfiguration of reconfigurable FIR filter. Section VThis paper presents a partially reconfigurable FIR filter describes experiment and result. The conclusion is given in

design that targets to meet all the objectives (low-power Section VI.consumption, autonomous adaptability/reconfigurability,fault-tolerance, etc.) on the FPGA, which are set by dynamicpartial reconfiguration (DPR). FPGAs are programmable II. MODULEBASED PARTIAL REcoNFIGuRATIoNlogic devices that permit the implementation of digitalsystems. They provide an array of logic cells that can be A ModularDesignconfigured to perform a given functionality by means of a The modular design flow allows the designer to split theconfiguration bitstream. Many ofFPGA systems can only be whole system into modules. For each module, the designerstatically configured. Static reconfiguration means to generates a configuration bitstream starting from an HDLcompletely configure the device before system execution. If description and going through the synthesis, mapping,a new reconfiguration is required, it is necessary to stop placement, and routing procedures, independently of othersystem execution and reconfigure the device it over again. modules [2]. The modular design flow consists of ModularSome FPGAs allow performing partial reconfiguration, Design Entry/Synthesis and Modular Design Implementationwhere a reduced bitstream reconfigures only a given subset steps. Modular Design Entry/Synthesis step must be done forof internal components. DPR allows the part of device be top-level design and the modules. Top-level design ismodified while the rest of the device (or system) continues to designed by the team leader and consists of 'black box' foroperate and unaffected by the reprogramming [1]. each sub-modules and 'wiring' for interconnection of each

sub-modules.

0-7803-9390-2/06/$20.00 ©2006 IEEE 4851 ISCAS 2006

Module Design-Q--(VHDL or Verilog)

Floorplanning of moduleAreas (Floorplanner)D D D D D es D D

Synthesis of each module(XST or Leonardo) Floorplanning of lOBs andD D D D DD D

global logic (Floorplanner)

Manua ionsertiont inr.ucfo Figure 3. n-tap transposed FIR filter.Initial Budgeting PhaseLOcosritfrbu

macro

CKC C~'+VC, C.. C~ ~ +K~ C4+ evenVoddActive Module Phase Augment .ucf with module-

level timing constraints Filter In -" 0

% ~~~~~~~~~~~~~~~~~~~n-ordern-order n-order n-orderFilter FiRter Filter Filter RgtSdNGDBUILD, MAP, PAR ~~~~~Module Module 2 Module 3 Module mMdl

Assembly ofthe entire BITGEN and PIMCREATE** -design ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Fifter Out

Design verification by Cokusing FPGA editor Cc

ResetBitstream generation and______________

upload on FPGAFigure 4. Block diagram of reconfigurable mxii order FIR filter.

Figure 1. Module-based partial reconfiguration flow.

Possible I/Os

I - - ~~~~~~~~~~~~~~~~~~~~thisblock~- __U

VAtpp- ~ ~ o

ii ~~~~A R B Iii ~~~~C U U Fixed

ii~~~~R S Logic -4 K ---- LD orch Aloje

IFixed PR M Jf uIm N_JsD ~ii Logic u Logic A Logic A

I~~gi

0 0 (~~~~~~~~~~~~~~MAC Module Rlobs Side Module

_ ___ -~~~~~~~~Loi IFigure 5. Reconfigurable multiply-accumulate (rMAC) module for FIRfiltering.

Boundaries

B. Module-Based Partial ReconfigurationFigure 2. Design layout with two reconfigurable modules. Module-based partial reconfiguration method is a special

Modular Design Implementation step comprises following case of modular design [3]. This method can reconfigurethree phase. only a given subset of internal components during device is

activating. A complete initial bitstream must be generated,1) Initial budget phase.- and then partial bitsteams are generated for each

In this phase, the team leader assigns top-level constraints to reconfigurable module. Fig. 1 shows the design flow ofthe op-eveldesgn.Top-eve contrant eedsto rea

module-based partial reconfiguration. Hardwired bus macrostetplvldsg.Tplvlconstraint needss tor areanmnt.must be included in design as shown in Fig. 2. These busconstraintadbusmacroassignment.macros guarantee that each time partial reconfiguration is

2) Active module implementation., performed routing channels between modules remainIn ths phse, he tam mmber impemen the unchanged, avoiding contentions inside the FPGA andIncothisg phasle, thduesta.ebes ipemn h keeping correct inter-module connections.

3) Final assembly. III. RE-CONFIGURABLE FIR FILTER DESIGN

Modulel Module2 Module3

Figure 6. Partial reconfiguration ofthe dashed area converts the 14-tapFIR filter to a 20-tap FIR filter.

Bus Macro

undertaken in either hardware or software. A software a) 14-tap FIR filter.implementation will require sequential execution of the filterfunctions. Hardware implementation of FIR filters allowsthe filter functions to be executed in a parallel manner which Modulel Module2 Module3makes improved filter processing speed possible, but is lessflexible for changes. Thus, reconfigurable FIR filter offerboth the flexibility of computer software, and the ability toconstruct custom high performance computing circuits.

The novel reconfigurable mm order FIR filter blockdiagram is presented in Fig. 4. The filter block employs afolded FIR structure, and shaves off and adds taps to theends of the impulse response to lower or raise the stop banddB level. The components in the filter block are m n-orderfilter modules and right side module. Each module consistsof n reconfigurable multiply-accumulate (rMAC) unit, us Macrowhich includes the serial-to-parallel register to getcoefficient inputs in serial. Each n order partial a) 20-tap FIR filter (modulel partial reconfiguration).reconfigurable filter modules are connected by bus macroson FPGA. Figure 7. PAR map of 14-tap FIR filter and 20-tap FIR using DPR.

IV. IMPLEMENTATION B. Bypassing

On adaptive systems, a limiting factor for the overall The 20-tap FIR filter and the 14-tap FIR filter have verysystem performance is often the speed of which the systemis able to adapt to perform a certain task. This section simllar hardware structures. In order to convert a 14-tap FIRdescribes the implementation method of 20-tap FIR filter filter to a 20-tap FIR filter we can simply load thewhich is reconfigured partially from 14-tap FIR filter. The

lower order taps (from to 6) as showni Filg.6. Thereforewhole system is implemented on a Xilinx Virtex 2XC2v6000 FPGA device. mstead of reconfiguring the whole chip, we can leave the

14-tap FIR filter on the device and just load the higher orderA. HDL Coding and Synthesis taps such that the filter is converted to a 20-tap FIR filter.

This step is composed to following two phases:C. Implemenation

* Top module design. * Initial Budget.In this phase, designer must consider each sub-module Thitep isageqmIintrcnncton are asirmn an bu, ar

This step iS a sequence of top module design. In this step,eassignment designer must do bus macro manual setting, sub moduleassignment. area constraint by using floorplanner and top module IOB

Reconfigurable sub-module design.- assignment. Fig. 7 describes area constraint thoughThis phase is same to traditional HDL design method. floorplanner. Bus macro is limited by target size. ThroughBut designer must 'cnsider Input and Output assign rule equation (1), designer can estimate maximum usable busfor partial reconfiguration. macro. rwCB l

If designer needs area optimization, optimized area can beestimated in a synthesis step.

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An optimized width equation is described byslice i 2) P IaI INotrow MRIIIII

4* row eAwhere slice is a maximum slice number estimated in a 1l[ Tsynthesis step and row is a target row size.

-Active module implementation.In this step, partially reconfigurable sub-modules are I -put Agenerated by top module and .ucf file. Each sub-module Final R5uktgenerates a partial bitstream during this step. Fig. 7 is apost-PAR (placement and routing) diagram. Through n- Inpu Border filter module 1 is reconfigured to bypass moduleon 14-tap FIR filter while other module is processing,20-tap FIR filter is composed by partial reconfigurationofmodule 1 showing Fig. 7(b).

Final module assemble. Figure 8. Test environment.

In this step, designer assembles one system fromparthiall ge erat ed les. oAl ti m Table I. FPGA device utilization for several FIR filters.partially generated modules. All partial modulesgenerated in active module implementation step are GF MBF DPRcombined to the top-level module. GF MBF DPR

Slice 3,058 5,349 4,733V. EXPERIMENT AND RESULT

The partial reconfiguration of reconfigurable symmetric LUT 5,980 9,669 8,427transposed FIR filters was implemented on Xilinx Virtex2 Gate Count NIA 76,024 68,063XC2v6000 FPGA device using test environment shown in GF: GeneralSymmetric FIR FilterFig. 8. For dynamic partial reconfiguration experiment, the MBF: Multiplexer Based Reconfigurable FIR Filterpartial reconfigurable module 1 with three rMAC units was DPR: Reconfigurable FIRfilter using DPRreconfigured to bypass module while other areas of modulesremain operational. For verification, post PAR simulation The proposed method produces a reduction in hardwareha bee codce for th reofgrb e cost and allows performing partial reconfiguration, where atranspsbeendFIRftedafterprthlreconfigurat .symmetric reduced bitstream reconfigures only a given subset oftransposed FIR filter after partial reconfiguration. internal components. In the future, self-reconfigurable

For performance comparison, we have implemented FIR hardware platform using microcontroller unit andfilter using variable multipliers, multiplexer based configuration memory will be promising solution forreconfigurable FIR filter and reconfigurable symmetric automatic partial reconfiguration of digital circuits in thetransposed FIR filter. Table 1 shows the utilization of slice, run-time environment.LUT and equivalent gate count after technology mapping.The reconfigurable symmetric transposed FIR filter using ACKNOWLEDGMENTDPR can save about 11.5% slice compared to the multiplexerbased reconfigurable FIR filter. Compared to the general This research was supported by the MIC (Ministry ofsymmetric FIR filter, the number of slice increased about (Information and Communication), Korea, under the ITRC54% because of adding bus macro, serial-to-parallel register (Information Technology Research Center) support program.and a little controller. But if we want to change one tap ingeneral symmetric FIR filter, we must do the full REFERENCESreconfiguration, which requires the slow configuration time. [1] D. Mesquita, F. Moraes, J. Palma, L. et. al., "Remote and PartialHowever, reconfigurable symmetric transposed FIR filter Reconfiguration of FPGAs: tools and trends," International Parallelusing DPR method requires the partial reconfiguration of and Distributed Processing Symposium, April 2003.about 1,499 slices for one coefficient tap that adds flexibility [2] Xilinx Corp., "Development System Reference Guide,"allowing dynamically inserting and/or removing the www.xiinx.com.coefficient taps. [3] Xilinx Corp., "XAPP 290: Two flows for Partial Reconfiguration:

Module Based or Difference Based," www.xilinx.com, Sept 2004.[4] Y. C. Lim and S. R. Parker, "FIR filter design over a discrete

VI. CONCLUSION powers of two coefficient space," IEEE Trans. on Acoustics, Speechand Signal Processing, Vol.ASSP-3 1, pp. 583-591, June 1983.

In this paper, we present a reconfigurable FIR filter [5] A. Shoa and s. Shirani., "Power savings In Channel Equalizersdesign using dynamic partial reconfiguration, which has area using Run-Time Reconfiguration":, CCECE, May. 2004.efficiency and flexibility allowing dynamically inserting [6] 5. Kelem, ";Virtex configuration architecture advanced user'sand/or removing the partial modules. gud, ' w~iix~o,Ot 04

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