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Architektura Systemów Wbudowanych 1
Architektura systemów wbudowanych
Prowadzący:
dr hab. inż. Janusz Smulko, prof. PG; tel. 348 6095 [email protected], pok. 445, konsultacje środa 11-13, (6h)
mgr inż. Mariusz Rudnicki; tel.: 347 2639 [email protected], pok. 759, dr inż. Iwona Kochańska (19h)
wykład: 25h, laboratorium: 30h
Sposób zaliczenia:
suma ocen za wykład – kolokwium (*0,4) oraz laboratorium (*0,6)
warunkiem zdania egzaminu (wykład) jest uzyskanie min. 50% punktów
Architektura Systemów Wbudowanych 2
Architektura systemów wbudowanych
Literatura:
Materiały do wykładu
http://rts.lab.asu.edu/web_ESP_Summer2014/ESP_Main_page.htm (przykładowy wykład)
http://intel-software-academic-program.com/pages/courses#iot (materiały firmy Intel)
Martinez, D. R., Bond, R. A., & Vai, M. M. (Eds.). (2008). High performance embedded computing handbook: A systems perspective. CRC Press.
Ecker, W., Müller, W., & Dömer, R. (2009). Hardware-dependent Software (pp. 1-13). Springer Netherlands.
Architektura Systemów Wbudowanych 3
Architektura systemów wbudowanych
Treść wykładu:
•Podstawowe pojęcia dotyczące budowy systemów wbudowanych
•Model systemu wbudowanego
•Techniki efektywnego wykorzystywania zasobów sprzętowych
•Metody optymalizacji kodu i techniki programowania, możliwości sprzętowe
•Zestawy uruchomieniowe (budowa) i programowanie elementów sprzętu
•Środowisko programistyczne, budowa interfejsu dla użytkownika
Laboratorium:
Zestawy Galileo, wraz z elementami ich rozszerzenia (czujniki, karty pamięci, karty WiFi, wyświetlacze, itp.) – finansowane przez Intel, Gdańsk
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Introduction
An Embedded System (ES) is a computer system with a dedicated function within a larger mechanical or electrical system, often with real-time computing constraints.
John Catsoulis (May 2005). Embedded Systems, An Introduction Using the Renesas RX62N Microcontroller.
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Introduction
Progress between 1950-2000: from 20 KOPS to 480 GFLOPS> Factor of 107 Growth
Martinez, D. R., Bond, R. A., & Vai, M. M. (Eds.). (2008). High performance embedded computing handbook: A systems perspective. CRC Press.
Architektura Systemów Wbudowanych 6
Introduction
Digital signal systems:
processors
microcontrollers
DSP (digital signal processors)
ASIC (application-specific integrated circuit)
FPGAs (field-programmable gate arrays)
System on a Chip
Son, C., Yun, J. H., Kang, H. G., & Han, T. (2006). Automatic Hardware/Software Interface Generation for Embedded System. JIPS, 2(3), 137-142.
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Introduction
Internet of Things (IoT)
The network of physical objects or "things" embedded with electronics, software, sensors and connectivity to enable data exchange between the identified devices.
Sensors and other elements:
Buzzer, Button, LED, Rotary Angle, Sound Sensor, Smart Relay, Temperature, Touch Sensor, LightSensor, Mini Servo, LCD RGB Backlight
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IntroductionEmbedded system:
A/D and D/A converters
Sensors
Actuators
Signal processing unit
Signal processingunit
A/D
D/A
A/D
ActuatorSensor OBJECT
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Introduction
Embedded system: signal processing requires fast preprocessing in additionalunit, dedicated to that task
Preprocessingunit
A/D
D/A
Processingunit
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Introduction
Embedded system requires:
Hardware (dedicated sensors/actuators, CPU)
Software (operating system, drivers, algorithms, etc.)
Hardware can comprise of ready electronic boards with necessarysensors/actuators
Software requires initialization procedure, tasks scheduling, multi-tasking for paralel events, has to solve constraints of CPU resources
Software means:
• application
• operating system (prepared mainly in C language; small percentage in assembler)
Architektura Systemów Wbudowanych 11
IntroductionGap between hardware design, system design and software design
Influence of economy – the way of selecting hardware
Time
Complexity
Hardware System
Software
Hardware: 2x/18 months
System: 1.6x/18 months
Software: 2x/24 months
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ES software modelHardware-dependent software
Ecker, W., Müller, W., & Dömer, R. (2009). Hardware-dependent Software. Springer Netherlands.
A
Middleware/Adapter Layerr
OS/RTOS
CommunicationProtocol Stacks
DeviceDrivers
Hardware Abstraction Layer
I/OPeripherals
Timer, Interrupt, Debug, Power, Clock
CPU Memory
Application Software
Bo
ot
Fir
mw
are
System Bus
Architektura Systemów Wbudowanych 13
ES software model
Application software: responsible for overall software functionality
Middleware: provides application-specific services (e.g. database access)
Operating System: manages and coordinates application software tasks for sharing of available software and hardware resources
Communication Protocol Stacks: software modules on top of devicedrivers
Device Drivers: software access to hardware resources by a fewfunctions (open, initialize, access, close)
Boot Firmware: performs initial boot proces
Hardware Abstraction Layer: an abstract interface to access hardware resources (access, register, functional shielding)
Architektura Systemów Wbudowanych 14
ES software model – operating systemProtection im space domain: sharing the same memory (a safety-critical application individual address spaces for processes are crucial)
App 1
OS Partition 1
App 2
OS Partition 2
App 3
OS Partition 3
OS: scheduler, I/O ports
Processor
Platform
Architektura Systemów Wbudowanych 15
ES software model – operating systemProtection in time domain: scheduler implements temporal partitioning in processes and sharing the procesor time
Time
Priority
P1
P2
P3
P4
P2
P1
Frame1 Frame2 Frame3 Frame1
Architektura Systemów Wbudowanych 16
ES software model – communicationCommunication can be performer at various layers
New systems enable tasks/data transmissions at hardware level
Application 1
Middleware
Operating System
Computer and network hardware
Application 1
Middleware
Operating System
Computer and network hardware
Architektura Systemów Wbudowanych 17
ES software model – initialization procedures
Initialization sequence:
• Intterupts disable, cache clearing
• Data copy from ROM into RAM memories
• Cache, interrupt vectors, system hardware initializations
• Zeroing memory
• Multitasking environment initialization, interrupt and rootstacks creation
• Initialization of I/O ports, drivers, setup networks
RTOS and Multi-tasking: tasks divisions and scheduling, Interrupts services
Processorinitialization
OS loading/booting
Architektura Systemów Wbudowanych 18
ES software structure
Application in linear programming
is a set of consecutive functions
Init_function()
Function_1()
Function_2()
Function_3() ISR_1() ISR_2()Init_function()
Return()
Main
Kernel of the RTOS
IDLE LOOP
In real-time system we require the kernel to assure fast interrupt service routines
Architektura Systemów Wbudowanych 19
ES software model – initialization procedures
RTOS and Multi-tasking: tasks divisions and scheduling, Interrupts services
Tasks synchronization State model of tasks in RTOS
Software task is defined by Task_start and Task_end events
Task 1RTOS context
schedule()
wait(wakeup_event)
notify(wakeup_event)
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ES Memory space
• Physical memory
• Virtual memory (user and kernel space)
App 1
Kernel
App 2
CPU
App 3 User virtual address memory
Memory Management Unit
Physical Memory
Kernel virtual address memory
Physical address memory
KERNEL – the modules of the OS that have been loaded into RAM and haveallocated memory
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Kernel of Operating Systems and Device Drivers
OS depends on the ES and can be established due to its functions, tasks and architecture
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Kernel of Operating Systems and Device Drivers
Kernel comprises of the modules which have to be registered in the OS
The modules in Linux OS have names, properties and methods
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Kernel of Operating Systems and Device Drivers
Device Drivers assure interface to handle requests for the device operations
Software interface to the device driver is implemented as kernel modules
Software interface can configure device, perform I/O operations, perform interruptrequests
Devices types:
• character device (terminal) – stream of bites like a file (open, close, read, write)
• block (disk) – transfer randomly data in blocks
• network; pseudodevice
We call a device driver at initialization/configuration I/O operations, interrupts
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Kernel of Operating Systems and Device DriversBasic Device Driver Structure:
File description table
drvnum - identifies the driver associated with the hardware device
Driver table
Differentiates multiple devices
drvnum Create Remove Open Close Read Write Ioctl
0 ** **
1
2
drvnum value
1
1 *dev
2
Device listPointer
1
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ES software preparation
The software files structure
Compilator C Linker Loader
Debugger
Assembler
Linker script
.obj
.bin
C code
.obj.asm.c
C functions library
Assembler library
.obj library
Executable
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ES compiler options
Compiler can use various options when preparing the executable code:
Level0 – all variables are located into the registers
Level1 – removes local variables and unused expressions + L0
Level2 – loops optimalization + L1
Level3 – removes unused functions + L2
Programming and hardware limitations
Detailed reports of hardware use
Power management using sleep modes and clock rate
Code length versus speed of the system performance
Other programming methods
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ES linker script
MEMORY command describes the location and size of blocks of memory in the target
SECTIONS command determines memory layout
/**************************************************************************/
MEMORY{ IPRAM : origin = 0x0, len = 0x1000
IDRAM : origin = 0x80000000, len = 0x10000}SECTIONS{.vectors > IPRAM.text> IPRAM.bss> IDRAM.cinit> IDRAM}
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ES debugging and testing
Real-time analysis and run control:
GUI can control:
source code, registers, function calls, variables, statistics, etc.; read/write memoryand registers; execution control (single step, breakpoint, watchpoint, etc.)
Target board can communicate with the PC by JTAG, USB, Ethernet etc.
Emulator: necessary fo debugging
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ES software preparation
The main rules for safety critical programming
(Gerard J. Holzmann NASA/JPL Laboratory for Reliable Software Pasadena)
• Restrict to simple control flow constructs
• Give all loops a fixed upper-bound
• Do not use dynamic memory allocation after initialization
• Limit functions to no more than 60 lines of text
• Use minimally two assertions per function on average
• Declare data objects at the smallest possible level of scope
• Check the return value of non-void functions, and check the validity of function parameters
• Limit the use of the preprocessor to file inclusion and simple macros
• Limit the use of pointers. Use no more than two levels of dereferencing per expression
• Compile with all warnings enabled, and use one or more source code analyzers(e.g. available at http://spinroot.com/static/)
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ES software preparation – general remarks
Executing and preparing programs in operating system
Process – an instance of a computer program, comprises of a code and can be characterized by its current activity
Process may be made of multiple threads of executions – instructions managedindependently by the scheduler (scheduler determines access to system resources)
Overheads for creating a thread are significantly less than for creating the proces
Switching between the threads is much less absorbing for the OS than doing the same between the processes
Multitasking – one proces serves to multiple clients
Multithreated programs have to be prepared more carefully (not all proces featuresare available)
Debugging is more difficult
Performance of a single procesor machine can be reduced due to multiple threads
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ES software preparation – threads in Linux
Thread states in Linux
Wait was satisfiedReady
Terminated
Running
Blocked
Preempted
Scheduled
Thread start
Wait to get resources
Done/Cancelled
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Process BProcess B Process A
ES software preparationKernel processes in Linux
A kernel proces can be preempted by another kernel proces
Critical regions, for competitive resources use, can be protected by disablinginterrupts or preemption
Multiprocessor system requires synchronization techniques for the data accessed by multiple CPUs
Mutual exclusion (MUTEX):
Protection against modifying the shared data by different threads usinglocking/unlocking mechanism of critical sections where the data could be shared
Process A User space
Time
Kernel space
Kernel entriedby the system call
Process A preempted Process A continues
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ES software preparationSemaphores
A dedicated variable used for controlling access to the resources by multipleprocesses
It is used in parallel programming or in multi-user environment
Gets values of 0, 1 (for binary semaphores of two options locked/unlocked) orhigher for arbitrary resources counting (counting semaphores)
Semaphores can be:
Initialized
Terminated
Increased
Decreased
Another mechanism ensuring mutual exclusion:
Busy-wait lock – lock is released and the thread waits until the lock is available
It is used when the mechanism is faster than putting the thread in a sleeping mode
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Unified Extensible Firmware Interface (UEFI)
Interface between operating system and platform firmware
• Device drivers can be prepared independently from the OS
• UEFI should replace BIOS (Basic Input/Output System)
• Will suport remote diagnostics and repair
• Is independent from the CPU
• Supports huge HDD
UEFI is answer to the limitations of the BIOS:
16- bits processors
Limited HDD size
Firmware
Hardware
Extensible Firmware Interface
Operating System
Architektura Systemów Wbudowanych 35
Hardware interfaces
Multicore systems are designed by applying various interfaces/links:
• Host Port Interface
• Serial Port (very simple and often available in the ES)
• Link Port
Clusters can be designed if the computational tasks can be divided into separateprocesses
Ecker, W., Müller, W., & Dömer, R. (2009). Hardware-dependent Software (pp. 1-13). Springer Netherlands.
Architektura Systemów Wbudowanych 36
Hardware interfacesAdvanced computing can be performer by cloud computing – centralized data storage and online access to computer services or resources
There are pros and cons of that solution:
Pros:
•Scale and cost
•Next generation architectures
•Choice and aglity (zwinność)
•Encapsulated change management
Cons:
•Lock-in
•Security
•Lack of control
•Reliability
Architektura Systemów Wbudowanych 37
Hardware interfaces
Cloud computing
The IoT Cloud Analytics site is provided as a service to the IoT development community
The data can be send to the cloud within a few steps only:
• Get an account from the Intel IoT Analytics Site
• Get and install the IoT Gateway Agent (Admin: tests connectivity, activates a device, registers time series and sends observations all from the command line; Agent: runs a a services by sending simple messages)
• Register your Device(s)
• Download and install the IoT Arduino Library (each sensor has to be registered)
• Write your scripts and send the data to the cloud
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CPU Architecture
CPU architecture depends on type of application:
• von Neuman architecture (CPU and memory with one bus)
• Harward architecture (CPU with two buses for data and program memoryseparately)
Specialized chips can have combination of both types of the CPU workingindependently (e.g. for video coding: one for video processing and the secondfor controlling interfaces
Necessary computations are performer by:
ALU, MAC, SHIFTER units
SHIFTER
Accumulator
ALU
Registers/Memory
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CPU Architecture
CPU architecture depends
on type of application
DSP optimized to perform
A*B+C operations
ALU, MAC, SHIFTER
and internal bus
Analog devices DSP:
Architektura Systemów Wbudowanych 40
CPU Architecture
CPU architecture for DSP algorithms with two independent streams of data performing A*B+Coperations
C6713 Texas Instruments
Digital Signal Processor
Mechanisms:
• pipelining
• parallelism
• VLIW
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CPU Architecture
Intel Quark SoC – ultra small chips for gadgets (wearable devices – small size and low power consumption)
Cheap with developed numerous interfaces;
Applied in Galileo board
The CPU instruction set is the same
as a Pentium (P54C/i586) CPU
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CPU Architecture
Intel Quark SoC – ultra small chips for gadgets (wearable devices – small size and low power consumption)
400 MHz maximum operating frequency
Cache, internal memory (flash, SRAM),
Low power options to run at half or at quarter of maximum CPU frequency
32-bit address bus, 32-bit data bus
16 Kbyte shared instruction and data L1 cache
Interfaces: UART, USB Host Port, I2C, SPI
Power management:S0 – full power on
S1, S2, S3, S4 – sleeping states; parts of the chip are in a sleeping state to reducepower consumption
S5 - system is switched off
Operating system: Linux (e.g. Debian 7.0 Wheezy)
one-fifth the size and one-tenth the power of low-end Atom chip
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CPU ArchitectureIntel Quark internal architecture includes: 32 bit RISC integer core; Single cycle execution;
Instruction pipelining; Floating-point unit; Cache for data and instructions; Memory management unit
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CPU Architecture
Atom Silvermont – low-power Atom processors used in systems on a chip
applied in Intel Edison board for tablets, smartphones and other wearabledevices; launched by Intel in 2012
Aplied in the Intel Edison board:
• high performance with high power efficiency
• pipeline mechanisms
• multi-core suport (two cores, second-level cache)
• WiFi
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Development boards
Various SDK systems have been proposed for different digital technologies
The common elements are:
Processor
Extensions
To another system
I/O access
Power supply
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Development boards
Various SDK systems have been proposed for different digital technologies
STM32F4 DISCOVERY
32-bits ARM Cortex®-M4 procesor; much faster with additional elements (build-in sensors, touchscreen, camera, memorycard)
Arduino – open-source computer software and hardware for sensing and controlling physical world; designed for Atmel AVR microcontrollers and microprocessors
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Development boards
Various SDK systems have been proposed for different digital technologies
Analog Devices Blackfin BF548 EZ-kit
touchscreen, keyboard, HDD, additionalinterfaces for video and audio applications
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Development boards – Galileo Intel Galileo board
400MHz 32-bit Intel® Pentium instruction set architecture(ISA)-compatible processor o 16 KBytes on-die L1 cache 512 KBytes of on-die embedded SRAM
Simple to program: Single thread, single core, constantspeed
ACPI compatible CPU sleep states supported
An integrated Real Time Clock (RTC), with an optional 3V “coin cell” battery for operation between turn on cycles; 10/100 Ethernet connector
Full PCI Express mini-card slot, with PCIe 2.0 compliantfeatures
Works with half mini-PCIe cards with optional converterplate
Provides USB 2.0 Host Port at mini-PCIe connector
USB 2.0 Host connector
Support up to 128 USB end point devices
USB Device connector, used for programming
10-pin Standard JTAG header for debugging
Reboot button to reboot the processor
Reset button to reset the sketch and any attached shields
http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf Galileo generation 1
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Development boards – Galileo
http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html Galileo generation 2
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Development boards – Galileo software
Galileo board assembly and programming
We have to install driver to connect the board with the PC as a terminal
SD has to be programmed with the Yocto Linux Image (by using PC and a program to create Win 32 image send to the SD from the PC by terminal connection)
We can prepare and run applications in the Galileo board using the environment:
• Arduino IDE
• Eclipse IDE (Java Runtime Engine has to be installed before it)
• Intel® IoT Dev Kit IDE
USB cable
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Development boards – Intel EdisonIntel Edison module
Intel Edison kit for Arduino:
UART (RX/TX), I2C and ICSP 6-pin header (SPI), 6 analog inputs, 20 digital input/output pins incl. 4 pins as PWM outputs,Micro USB connector, SD card connector, DC power jack
Intel Edison Breakout Board Kit:power supply, battery recharger, USB OTG power switch, UART to USB bridge, USB OTG port, and I/O header
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Development boards – software
http://www.intel.com/support/edison/sb/CS-035276.htm
Intel Edison: software stack
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Development boards – fast programming
Additional tools help to accelerate fast programming and apps preparation
Integrated Performances Primitives
• Signal processing
• Image processing
• Matrix operations
• Cryptograph
Math Kernel Library
• Various Math functions (e.g. FFT)
Cordova
• Building apps for BlackBerry, IOS, Android, Windows desktop
Sensors
• Sensors fusion (various measurements at the same time improve applicationsand results)
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Development boards – system preparation
https://www.yoctoproject.org/ „Documentation”
Intel Edison Yocto Project:
Open source project aimed to limit time for making the build systems
Compatible with various linux distributions (Ubuntu, Fedora, openSUSE, CentOS, Debian); stable releases are issued within a few months
Helps to develop industrial standards of reliable operating systems for ES
Software comprises of separate layers (each layer can be prepared using variousset of files)
Developer-specific layer
Commercial layer
UI-specyfic layer
Hardware-specific BSP
Yocto-specific layer Metadata
OpenEmbedded Core Metadata
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Development boards – exemplary programs, materials and tutorials
Intel materials:
http://intel-software-academic-program.com/pages/courses#iot
Intel Galileo projects:
https://www.hackster.io/intel-galileo
Competitor: Raspberry Pi (different prices but various elements like: cables, memory cards, ways of booting)
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Exemplary projects
Control Things connected to Intel Galileo
The main problem are the wired connections to the sensors
Very difficult and expensive to be applied e.g. at home
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Exemplary projects
Other companies than Intel proposed more practical solutions
ARTIK (12 mm x 12 mm) – power sensitive devices for wearables and IoT end nodes
Nucleus RTOS
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Exemplary projects
Intelligent house – exemplary solutions
Bluetooth or other well-know solutions are problematic
www.enocean.com
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Exemplary projects
Intelligent house – exemplary solutions
Bluetooth or other well-know solutions are problematic
www.enocean.com
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Exemplary projects
Intelligent house – exemplary solutions
z-Wave standard of wireless communication for home automation
SD3502 chip for high-volume applications:
• Integrated MCU and RF transceiver
• 128kB Flash, 16kB SRAM
• 1000 step dimmer (TRIAC/FET)
• 4-channel 12-bit rail-to-rail ADC
• 4-channel 16-bit LED PWM, 23 GPIOs
• USB full-speed device, SPI, UART, PWM, Keyscan controller up to 88 keys
• Flash programming through USB, UART and SPI
• Hardware AES 128 security engine
• 1µA sleep mode
• 9.6/40/100 kbit/s RF data rates
• Battery monitor, Power supply: 2.3-3.6V, QFN48 7mm x 7mm
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Exemplary projects
Intelligent house – exemplary solutions
EnOcean standard: utilizes energy harvesting wireless technology for self-poweredwireless switches and sensors
time of working: ~ 10-15 years and only 15-30 m range
www.enocean.com
15% cost savings in new constructions
70% cost savings in retrofits
secure data transmission
lower electromagnetic pollution
Architektura Systemów Wbudowanych 62
Sensors and Signal Processing
Android Devices – revolution in Motion Processing (np.: InvenSense.com)
Integracja kilku czujników i wstępne przetwarzanie (filtracja, całkowanie). Pojawia się dryf w wyniku całkowania
Zamiana wskazań poszczególnych rodzajów czujników różnych wielkości fizycznych aby poprawić wyniki działania (np. żyroskop i akcelerometr)