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Applied Surface Science

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Annealing time modulated the film microstructures and electrical propertiesof P-type CuO field effect transistors

Yu Yanga,b, Jiayan Yanga, Wenlei Yina, Fanming Huanga, Anyang Cuia, Dongxu Zhangc,Wenwu Lia,b,⁎, Zhigao Hua,b, Junhao Chua,b

a Key Laboratory of Polar Materials and Devices (Ministry of Education), Technical Center for Multifunctional Magneto-Optical Spectroscopy (Shanghai), Department ofElectronic Engineering, East China Normal University, Shanghai 200241, Chinab Shanghai Institute of Intelligent Electronics & Systems, Fudan University, Shanghai 200433, Chinac China Academy of Engineering and Physics, Mianyang 621900, China

A R T I C L E I N F O

Keywords:Sol-gel techniqueCuO filmsAnnealing timeMicrostructuresThin-film transistors

A B S T R A C T

P-type CuO films were prepared by solution processed method and annealed at 300 °C with the annealing time of10, 30, 60, 90, and 120min, respectively. X-ray diffraction and atomic force microscopy results reveal that theCuO film microstructures, crystallinity and grain size can be modified by annealing time. The CuO film annealedat 30min exhibits the optimal crystalline quality. The annealing time shows a significant impact on the mobility,Ion/Ioff ratio and subthreshold swing (SS) values of the prepared CuO thin-film transistors (TFTs). By changingthe annealing time, the mobility increases from 1.6×10−4 to 1.2×10−2 cm2 V−1 s−1 while the Ion/Ioff ratioincreases from 2×103 to 2×104. Moreover, the transistor with annealing time of 30min achieves the optimalfield-effect mobility (1.2× 10−2 cm2 V−1 s−1), Ion/Ioff ratio (2×104), and SS value (6.3 Vdec−1). It can beascribed to fewer grain boundaries and better interface contact of the CuO film, which will reduce the densitiesof trapping centers and scattering centers. This work demonstrates that the crystalline quality and micro-structures of CuO film and TFTs performance can be modulated by annealing time.

1. Introduction

In the past decades, field effect transistors based on metal oxidesand 2D materials have been widely studied due to its excellent electricalperformance and optical properties, which make it potential applica-tions in integrated circuits, sensors and active matrix display devices[1–7]. As a key architecture of integrated circuits, the complementarymetal oxide semiconductor (CMOS) circuits are constructed with high-performance n-type and P-type transistors [1,2]. Most of the previousstudies were dedicated to the thin film transistors (TFTs) based on n-type metal oxides such as ZnO [1], In2O3 [2], InZnO [3], and InGaZnO[4]. However, there are very few works focus on the P-type metaloxides based TFTs and the corresponding physical mechanism [8]. Thisis because the preparation of high quality and stable P-type metal oxidematerials is really difficult. In addition, P-type metal oxide semi-conductors often show lower mobility than n-type counterparts.Therefore, it is necessary to develop high-performance P-type oxideTFTs for CMOS circuit applications [9].

As we know, the typical P-type metal oxide semiconductors are CuO

[10], NiO [11], and SnO [12] materials. Among them, CuO is con-sidered as a promising P-type oxide semiconductor, owing to its sig-nificant reduction in the localization nature of the valence band max-imum (VBM) and effective hole transport [13]. Among the metal oxidesof 3d transition elements, CuO has square planar coordination of copperby oxygen in the monoclinic structure. P-type behavior arises from theexistence of negatively charged Cu vacancies [14]. Furthermore, CuOmaterials have the advantages of high transparency, low processingtemperature and good uniformity, chemical and thermal stability, low-cost preparation method, which make it possible applications intransparent electronics and active matrix devices [14,15]. There areseveral ways to fabricate CuO films, such as pulsed laser deposition[16], magnetron sputtering [17], and solution process. Among thesefabrication techniques, solution processed method is a promisingtechnique, which can be used to prepare low cost, large area, uniform,and low annealing temperature CuO films on various substrates [18].

Up to now, the TFTs based on CuO film exhibit relatively lowelectrical properties, such as low mobility and on/off ratio. This is be-cause the VBM of the CuO semiconductor is mainly composed of

https://doi.org/10.1016/j.apsusc.2019.03.130Received 27 October 2018; Received in revised form 28 February 2019; Accepted 13 March 2019

⁎ Corresponding author at: Key Laboratory of Polar Materials and Devices (Ministry of Education), Technical Center for Multifunctional Magneto-OpticalSpectroscopy (Shanghai), Department of Electronic Engineering, East China Normal University, Shanghai 200241, China.

E-mail address: wwli@ee.ecnu.edu.cn (W. Li).

Applied Surface Science 481 (2019) 632–636

Available online 14 March 20190169-4332/ © 2019 Elsevier B.V. All rights reserved.

T

anisotropic and local oxygen 2p orbitals, so this non-ideal electronconfiguration leads to large hole effective mass and low mobility [19].On the other hand, many parameters in the film fabrication process cansignificantly influence the film microstructures and electrical propertiesof CuO TFTs. For example, the annealing temperature and time are thekey factors affecting the surface morphology and crystalline quality ofthe films. The effects of annealing temperatures on the electricalproperties of CuxO TFTs have been reported by Yu et al. They foundthat the device performance of the as-fabricated CuxO TFTs was im-proved with increasing processing temperature from 400 to 600 °C[20]. However, the effect of annealing time on the film quality of CuOfilms remains unexplored. Therefore, it is desirable to carry out a de-tailed study regarding the essential effects of annealing time on filmmicrostructure and electrical properties of P-type CuO TFTs.

In this letter, CuO films were prepared using a solution processedmethod and then annealed at 300 °C with the annealing time of 10, 30,60, 90, and 120min, respectively. The effects of annealing time on thegrain size, crystalline quality, and microstructure for CuO film havebeen discussed. The CuO film annealed at 30min shows the highestquality for transistor applications. The electrical properties of CuO TFTsunder different annealing time and its physical mechanisms have beenanalyzed. The mobility, current on-off ratio (Ion/Ioff), subthresholdswing (SS), and the threshold voltage of CuO TFTs can be modulated tothe optimal value by changing the annealing time.

2. Experimental

The 0.1 M copper oxide precursor solution was prepared by in-corporating Cu(NO3)2·3H2O into a mixed solution of deionized waterand glycerol, with a ratio of 4:1. A highly doped Si wafer with a re-sistivity of 1.5× 10−3Ω cm and a SiO2 thermal oxide layer (100 nm)was used as the gate substrate and the gate dielectric layer, respec-tively. Before the spin coating, the substrate was cleaned with acetone,alcohol, and deionized water for 10min, respectively. Then the sub-strates were cleaned with oxygen plasma to improve the surface hy-drophilicity. At the acceleration step, the precursor solution was spin-coated onto the substrate with the speed of 500 rpm for 5 s, and thenthe solution was spin-coated with the speed of 5000 rpm for 25 s. Thedeposited film was dried at 150 °C in air for 2 h to remove residualorganic compounds. Finally, the CuO films were annealed at 300 °C inthe air for 10, 30, 60, 90 and 120min, respectively.

By using a shadow mask, the Au source and drain electrodes with athickness of 30 nm were deposited on the CuO films by vacuum thermalevaporation. The crystalline structures of the CuO films were analyzedby X-ray diffraction (XRD, D/MAX-2550, Rigaku Co.). The surfacemorphology and thickness of the CuO films were examined by atomicforce microscope (AFM: Digital Instruments Icon, Bruker). X-ray pho-toelectron spectroscopy (XPS) measurements were carried out on a RBDupgraded PHI-5000C ESCA system (Perkin-Elmer) to investigate thevalence states. The electrical properties of the CuO TFTs were analyzedwith a semiconductor parameter analyzer (Keithley 4200).

3. Results and discussion

Fig. 1 shows the crystalline structures of CuO films prepared atdifferent annealing times (TA). It can be found that all the films exhibita single CuO phase after annealing. Besides the strongest (021) dif-fraction peak, two weaker peaks with (020) and (−202) planes can beobserved, which illustrates that the films are polycrystalline with dif-ferent orientations. Note that the film annealed with 30min shows thestrongest diffraction intensity, which suggests that the film has theoptimal crystalline quality. The grain size of the CuO films, which isrelated to the crystallinity and microstructure of the films, can be cal-culated from the (021) diffraction peak according to the well-knownScherrer equation and estimated by AFM results. The grain sizes of theCuO films annealed for 10, 30, 60, 90, and 120min are estimated to

30.3, 33.1, 29.1, 30.2 and 30.4 nm, respectively. The calculated grainsizes change with the TA and the film annealed for 30min has themaximum grain size. A larger grain size results in fewer grain bound-aries and nonrecombination centers inside the film. It will further re-duce the trapping centers and carrier scattering behaviors [18,21].

The surface morphologies of the CuO films under different TA areshown in Fig. 2(a)–(e). The substrates are covered with nanoparticles ofdifferent sizes and the surface morphology of the films is significantlyaffected by TA. It can be concluded that the films have the nanocrys-talline growth pattern and the surfaces of all films are compact. Theroot-mean-square (RMS) values of the CuO films annealed for 10, 30,60, 90, and 120min are estimated to 0.7, 0.9, 0.9, 1 and 1.1 nm, re-spectively. It suggests that the surface roughness increases with in-creasing the TA from 10 to 120min. The increased surface roughnesswill further affect the contact interface between the channel layer andthe electrode of the transistor, resulting in increased trap density at theinterface [22]. Good interfacial contact is beneficial to improve theelectrical parameters of the transistors such as carrier mobility.Therefore, the electrical properties of CuO TFTs will be affected by thedifferent grain sizes and surface roughness. According to the AFM re-sults, the thickness of the prepared CuO films was estimated to about33 nm [see Fig. 1(f)].

Fig. 3 plots the XPS spectra of the CuO films to investigate the va-lence states. Two peaks relevant to Cu 2p states appear at about 935 eVand 955 eV. It can be ascribed to the Cu 2p3/2 state and Cu 2p1/2 state ofCuO phase, respectively [23]. In addition, a broad peak is observed near945 eV, which can be assigned to the oscillating satellite peak on thehigh binding energy side of the Cu 2p3/2 main peak. It is the char-acteristic of the 3d9 configuration of Cu2+, which has multiple splittingof Cu 2p levels [24]. The XPS results confirm that the prepared films areof CuO states. The Binding energy values of CuO film obtained in thisexperiment are similar to the results observed by Sanal et al. [14].

To investigate the effects of the TA on the CuO TFTs performance,bottom-gated TFTs were fabricated by using CuO thin film as thechannel layer. As illustrated in the inset of Fig. 4, the highly doped Sisubstrate was used as a back-gate electrode. The thickness of the CuOchannel layer and the Au electrode is 33 nm and 30 nm, respectively.The devices had a simple inverted staggered configuration without anypassivation layer. The length and width of the semiconductor channel is60 μm and 1200 μm, respectively. Fig. 4 shows the transfer character-istics of CuO TFTs. A large discrepancy is observed between the devicecharacteristics as the different TA applied. The transfer curves for dif-ferent TA obviously shift in the horizontal direction. The off-state cur-rent is virtually invariable, whereas the on state current reaches themaximum value of 9×10−5 A at strong inversion/accumulation (i.e.,at gate voltage (VGS)= 50 V). It implies that some electrical parameters

Fig. 1. The XRD results of CuO films annealed for 10min, 30min, 60min,90min, and 120min, respectively.

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such as the threshold voltage, mobility, and Ion/Ioff ratio are sig-nificantly affected by TA.

Some electrical parameters for the CuO TFTs at different TA are thussummarized in Table 1. The field-effect mobility (μFE) shown in thetable is extracted by the following equation [25–27]: μFE=(∂IDS / ∂VGS)(L /WCiVDS), where L is the channel length,W is the channel width, andCi is the areal capacitance of the gate dielectric. The μFE for different TAof 10, 30, 60, 90, and 120min are respectively corresponding to thevalues of 4.3× 10−3, 1.2× 10−2, 4.0× 10−3, 2.0× 10−3 and1.6×10−4 cm2 V−1 s−1. The μFE and Ion/Ioff ratio get the optimalvalue, and then degrade after TA reaching 30min. This result can beattributed to the increase of grain size in the polycrystalline CuO filmannealed with 30min, which further results in the increase of grainboundaries. The larger grain boundaries in the CuO film will reducecarrier scattering, which leads to an increase of carrier concentration inthe channel [28]. Moreover, the film annealed for 30min exhibits theoptimal crystalline quality, as demonstrated by XRD results. It will re-duce the defects and traps of the CuO film and further improve thedevice performances.

The degraded electrical performance of the CuO TFTs for the TAabove 30min is derived from the change of CuO film morphology, suchas crystallinity, surface roughness, et al. The surface roughness of theCuO films can be affected by the interfaces among the semiconductorlayer, the electrodes, and the dielectric layer [29]. Moreover, as thesurface roughness increases, the trap density at the interface also in-creases, which reduces the μFE values. The RMS value of the film an-nealed for 30min is smaller than that of the film annealed for 60 to

Fig. 2. The AFM images of the CuO films annealed for (a) 10min, (b) 30min, (c) 60min, (d) 90min, and (e) 120min. (f) The AFM topographies to confirm the CuOfilm thickness.

Fig. 3. The XPS spectra of Cu 2p peaks for CuO films with different TA.

Fig. 4. The transfer characteristics of CuO transistor annealed at different time.Insert shows the schematic diagram of the back-gate staggered transistor. Thehighly-doped Si substrate acts as a back-gate electrode.

Table 1Electrical parameters of CuO TFTs at different TA.

Time μFE Ion/Ioff Vth SS Dit

(min) (cm2 V−1 s−1) (V) (Vdec−1) (cm−2)

10 4.3× 10−3 7×103 −5.3 7.0 5.7× 1013

30 1.2× 10−2 2×104 −2.3 6.3 5.1× 1013

60 4.0× 10−3 4×103 −12.7 8.7 7.1× 1013

90 2.0× 10−3 2×103 −11.3 9.6 7.8× 1013

120 1.6× 10−4 2×103 −11.3 8.5 6.9× 1013

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120min. Consequently, the CuO TFT prepared by the TA of 30minprovides better semiconductor/dielectric interface morphology.

On the other hand, the band gap of CuO films is about 1.36 eV, andits conduction band minimum (about 4.07 eV) is lower than the vacuumenergy [30]. The CuO film was exposed to air during the annealingprocess, the adsorbed oxygen has a chemical potential of about 5.7 eVbelow the vacuum level, which results in the formation of an acceptorlevel near the valence band of the surface [31]. The electrons aretrapped by the absorbed oxygen, the energy band is bent upwards, anda hole-accumulating layer is formed on the surface of the CuO film. Thisprocess can be expressed as follow [32]: O2↔O2−+VacancyCu2++2hole. Therefore, when the TA increases from 10 to 30min, this equationtends to proceed to the right, which will enhance hole injection andthus larger carrier concentration is achieved in CuO TFT. As TA con-tinues to increase, this process tends to balance.

Note that the subthreshold slope (SS) is another important para-meter to consider. It determines the switching speed in logic circuits[33]. The SS can be calculated by the relationship: SS= ∂VGS/∂(logIDS).The estimated SS values, corresponding to the TA of 10, 30, 60, 90, and120min, are 7.0, 6.3, 8.7, 9.6, and 8.5 Vdec−1, respectively. Obviously,CuO TFTs annealed at 30min have the optimal value of SS, whichsuggests a faster transition between off state (low current) and on state(high current).

According to SS, the interfacial trap density of the semiconductor/dielectric interface could be evaluated by the following equation [34],

= ⎡⎣⎢

− ⎤⎦⎥

DSS

kT qClog 9(e)

/1

qiti

(1)

where k, T, and q is Boltzmann's constant, absolute temperature, andelectronic charge, respectively. The Dit for the TFTs corresponding tothe TA of 10, 30, 60, 90, and 120min are 5.7×1013, 5.1× 1013,7.1× 1013, 7.8× 1013, and 6.9×1013 cm−2, respectively. A low in-terfacial trap density allows unhindered transport in the channel andthus better performance is achieved for the CuO TFTs. The said elec-trical parameters and morphology analysis are consistent with thecalculated Dit, where different types of the parameter simultaneouslyapproach to the optimal value for the TA of 30min.

The output characteristics of the CuO TFTs annealed for 30min areshown in Fig. 5. The voltage applied in drain (VDS) lies in the rangebetween 0 to −80 V. The curves show distinct linear and saturatedregion, as VGS varying. Good P-type characteristics are observed in thisCuO TFTs. The linear and symmetric output curves at the low VDS in-dicate Ohmic contacts.

4. Conclusions

In summary, high-quality P-type CuO films are prepared by the sol-

gel method with different TA. By different parameters comparison, suchas crystalline quality, grain size, and surface roughness, the film an-nealed at 30min proves to achieve the best surface morphology. TheTA-dependent surface morphology turns out to be the main reason forthe electrical performance evolution of the CuO TFT, where the optimaltransfer and output characteristics are obtained after TA reaching30min. The extracted μFE, Ion/Ioff ratio, and SS from the CuO TFT forthe TA of 30min are 1.2×10−2 cm2 V−1 s−1, 2× 104 and 6.3 Vdec−1

respectively, which are superior to most reported P-type TFTs. Thiswork proposes a candidate method to modulate the microstructure ofCuO films and the electrical properties of P-type CuO TFTs, whichmakes possible for large-scale commercial application of CuO TFTs.

Acknowledgments

This work was financially supported by the National Key Researchand Development Program of China (Grant Nos. 2016YFB0501604,2017YFA0303403, and 2018YFB0406500), the National NaturalScience Foundation of China (Grant Nos. 61774061, 61504043,61674057, 61505182, 61604056, 11575062, and 21701151), the NSAFFoundation of China (Grant No. U1830130), the Projects of Science andTechnology Commission of Shanghai Municipality (Grant No.18JC1412400), and the Program for Professor of Special Appointment(Eastern Scholar) at Shanghai Institutions of Higher Learning and theFundamental Research Funds for the Central Universities (ECNU).

References

[1] R.L. Hoffman, B.J. Norris, J.F. Wager, ZnO-based transparent thin-film transistors,Appl. Phys. Lett. 82 (2003) 733–735, https://doi.org/10.1063/1.1542677.

[2] S.Y. Ju, A. Facchetti, Y. Xuan, J. Liu, F. Ishikawa, P. Ye, C.W. Zhou, T.J. Marks,D.B. Janes, Fabrication of fully transparent nanowire transistors for transparent andflexible electronics, Nat. Nanotechnol. 2 (2007) 378–384, https://doi.org/10.1038/nnano.2007.151.

[3] N.L. Dehuff, E.S. Kettenring, D. Hong, H.Q. Chiang, J.F. Wager, R.L. Hoffman,C.H. Park, D.A. Keszler, Transparent thin-film transistors with zinc indium oxidechannel layer, J. Appl. Phys. 97 (2005) 064505–064509, https://doi.org/10.1063/1.1862767.

[4] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, H. Hosono, Thin-film transistorfabricated in single-crystalline transparent oxide semiconductor, Science 300(2003) 1269–1272, https://doi.org/10.1126/science.1083212.

[5] W.W. Li, J.J. Zhu, J.R. Liang, Z.G. Hu, J. Liu, H.D. Chen, J.H. Chu, External electricfield manipulations on structural phase transition of vanadium dioxide nano-particles and its application in field effect transistor, J. Phys. Chem. C 115 (2011)23558–23563, https://doi.org/10.1021/jp207196g.

[6] M.J. Li, C.Y. Lin, S.H. Yang, Y.M. Chang, J.K. Chang, F.S. Yang, C.R. Zhong,W.B. Jian, C.H. Lien, C.H. Ho, H.J. Liu, R. Huang, W.W. Li, Y.F. Lin, J.H. Chu, Highmobilities in layered InSe transistors with indium-encapsulation-induced surfacecharge doping, Adv. Mater. 30 (2018) 1803690, , https://doi.org/10.1002/adma.201803690.

[7] M.J. Li, F.S. Yang, Y.C. Hsiao, C.Y. Lin, H.M. Wu, S.H. Yang, H.R. Li, C.H. Lien,C.H. Ho, H.J. Liu, W.W. Li, Y.F. Lin, Y.C. Lai, Low-voltage operational, low-powerconsuming, and high sensitive tactile switch based on 2D layered InSe tribotronics,Adv. Funct. Mater. 29 (2019) 1809119, , https://doi.org/10.1002/adfm.201809119.

[8] K. Matsuzaki, K. Nomura, H. Yanagi, T.O. Kamiya, M. Hirano, H. Hosono, Epitaxialgrowth of high mobility Cu2O thin films and application to p-channel thin filmtransistor, Appl. Phys. Lett. 93 (2008) 202107–202109, https://doi.org/10.1063/1.3026539.

[9] Z.Q. Yao, B. He, L. Zhang, C.Q. Zhuang, T.W. Ng, S.L. Liu, M. Vogel, A. Kumar,W.J. Zhang, C.S. Lee, S.T. Lee, X. Jiang, Energy band engineering and controlled P-type conductivity of CuAlO2 thin films by nonisovalent Cu-O alloying, Appl. Phys.Lett. 100 (2012) 062102–062105, https://doi.org/10.1063/1.3683499.

[10] S.Y. Sung, S.Y. Kim, K.M. Jo, J.H. Lee, J.J. Kim, S.G. Kim, K.H. Chai, S.J. Pearton,D.P. Norton, Y.W. Heo, Fabrication of p-channel thin-film transistors using CuOactive layers deposited at low temperature, Appl. Phys. Lett. 97 (2010)222109–222111, https://doi.org/10.1063/1.3521310.

[11] J. Jiang, X. Wang, Q. Zhang, J. Li, X.X. Zhang, Thermal oxidation of Ni films for P-type thin-film transistors, Phys. Chem. Chem. Phys. 15 (2013) 6875–6878, https://doi.org/10.1039/c3cp50197c.

[12] K. Okamura, B. Nasr, R.A. Brand, H. Hahn, Solution-processed oxide semiconductorSnO in p-channel thin-film transistors, J. Mater. Chem. 22 (2012) 4607–4610,https://doi.org/10.1039/c2jm16426d.

[13] S. Han, K.M. Niang, G. Rughoobur, A.J. Flewitt, Effects of post-deposition vacuumannealing on film characteristics of P-type Cu2O and its impact on thin film tran-sistor characteristics, Appl. Phys. Lett. 109 (2016) 173502–173505, https://doi.org/10.1063/1.4965848.

Fig. 5. The output curves with different VGS for the CuO transistor annealed for30min.

Y. Yang, et al. Applied Surface Science 481 (2019) 632–636

635

[14] K.C. Sanal, L.S. Vikas, M.K. Jayaraj, Room temperature deposited transparent p-channel CuO thin film transistors, Appl. Surf. Sci. 297 (2014) 153–157, https://doi.org/10.1016/j.apsusc.2014.01.109.

[15] Lei Wang, Liuan Li, Tian Xie, Xinzhi Wang, Xinke Liu, Jin-Ping Ao, Thresholdvoltage tuning in AlGaN/GaN HFETs with P-type Cu2O gate synthesized by mag-netron reactive sputtering, Appl. Surf. Sci. 437 (2018) 98–102, https://doi.org/10.1016/j.apsusc.2017.12.177.

[16] X. Zou, G.J. Fang, J.W. Wan, X. He, H.N. Wang, N.S. Liu, H. Long, X.Z. Zhao,Improved subthreshold swing and gate-bias stressing stability of P-type Cu2O thin-film transistors using a HfO2 high-k gate dielectric grown on a SiO2/Si substrate bypulsed laser ablation, IEEE Trans. Electron Devices 58 (2011) 2003–2007, https://doi.org/10.1109/TED.2011.2142313.

[17] E. Fortunato, V. Figueiredo, P. Barquinha, E. Elamurugu, R. Barros, G. Goncalves,S.K. Park, C.S. Hwang, R. M̧artins, Thin-film transistors based on P-type Cu2O thinfilms produced at room temperature, Appl. Phys. Lett. 96 (2010) 192102–192104,https://doi.org/10.1063/1.3428434.

[18] W.W. Li, W.L. Yu, Y.J. Jiang, C.B. Jing, J.Y. Zhu, M. Zhu, Z.G. Hu, X.D. Tang,J.H. Chu, Structure, optical, and room-temperature ferromagnetic properties ofpure and transition-metal-(Cr, Mn, and Ni)-doped ZnO nanocrystalline films grownby the sol-gel method, J. Phys. Chem. C 114 (2010) 11951–11957, https://doi.org/10.1021/jp103183v.

[19] A. Liu, S.B. Nie, G.X. Liu, H.H. Zhu, C.D. Zhu, B. Shin, E. Fortunato, R. Martins,F.K. Shan, In situ one-step synthesis of P-type copper oxide for low-temperature,solution-processed thin-film transistors, J. Mater. Chem. C 5 (2017) 2524–2530,https://doi.org/10.1039/c7tc00574a.

[20] J.M. Yu, G.X. Liu, A. Liu, Y. Meng, B. Shin, F.K. Shan, Solution-processed P-typecopper oxide thin-film transistors fabricated by using a one-step vacuum annealingtechnique, J. Mater. Chem. C 3 (2015) 9509–9513, https://doi.org/10.1039/c5tc02384j.

[21] X. Zou, G.J. Fang, L.Y. Yuan, M.Y. Li, W.J. Guan, X.Z. Zhao, Top-gate low-thresholdvoltage p-Cu2O thin-film transistor grown on SiO2/Si substrate using a high-k HfONgate dielectric, IEEE Electron Device Lett. 31 (2010) 827–829, https://doi.org/10.1109/LED.2010.2050576.

[22] Y.H. Lin, S.R. Thomas, H. Faber, R. Li, M.A. McLachlan, P.A. Patsalas,T.D. Anthopoulos, Al-doped ZnO transistors processed from solution at 120 °C, Adv.Electron. Mater. 2 (2016) 1600070–1600080, https://doi.org/10.1002/aelm.201600070.

[23] D. Barreca, A. Gasparotto, E. Tondello, CVD Cu2O and CuO nanosystems char-acterized by XPS, Surf. Sci. Spectra 14 (2007) 41–51, https://doi.org/10.1116/11.20080701.

[24] J. Ghijsen, L.H. Tjeng, J. van Elp, H. Eskes, J. Westerink, G.A. Sawatzky,M.T. Czyzyk, Electronic structure of Cu2O and CuO, Phys. Rev. B 38 (1988)11322–11330, https://doi.org/10.1103/PhysRevB.38.11322.

[25] F.F. Fang, A.B. Fowler, Hot electron effects saturation velocities in silicon inversionlayers, J. Appl. Phys. 41 (1970) 1825–1831, https://doi.org/10.1063/1.1659111.

[26] Y. Xu, H.B. Sun, E.Y. Shin, Y.F. Lin, W.W. Li, Y.Y. Noh, Planar-processed polymertransistors, Adv. Mater. 28 (2016) 8531–8537, https://doi.org/10.1002/adma.201601589.

[27] F. Huang, A. Liu, H. Zhu, Y. Xu, F. Balestra, G. Ghibaudo, Y. Noh, J. Chu, W. Li,Reliable mobility evaluation of organic field-effect transistors with different contactmetals, IEEE Electron Device Lett. (2019), https://doi.org/10.1109/LED.2019.2901315.

[28] N. Gupta, B.P. Tyagi, An analytical model of the influence of grain size on themobility and transfer characteristics of polysilicon thin-film transistors, Phys. Scr.71 (2005) 225–228, https://doi.org/10.1238/Physica.Regular.071a00225.

[29] X. Yu, J. Smith, N. Zhou, L. Zeng, P. Guo, Y. Xia, A. Alvarez, S. Aghion, H. Lin, J. Yu,Spray-combustion synthesis: efficient solution route to high-performance oxidetransistors, Proc. Natl. Acad. Sci. U. S. A. 112 (2015) 3217–3222, https://doi.org/10.1073/pnas.1501548112.

[30] F.P. Koffyberg, F.A. Benko, A photoelectrochemical determination of the position ofthe conduction and valence band edges of P-type CuO, J. Appl. Phys. 53 (1982)1173–1177, https://doi.org/10.1063/1.330567.

[31] C. Wang, X.Q. Fu, X.Y. Xue, Y.G. Wang, T.H. Wang, Surface accumulation con-duction controlled sensing characteristic of P-type CuO nanorods induced byoxygen adsorption, Nanotechnology 18 (2007) 145506–145510, https://doi.org/10.1088/0957-4484/18/14/145506.

[32] V. F. Kiselev, O. V. Krylov, Adsorption and Catalysis on Transition Metals and TheirOxides, Springer Berlin Heidelberg 9 (1989) 136–265.

[33] Yong Xu, Huabin Sun, Eul-Yong Shin, Yen-Fu Lin, Wenwu Li, Yong-Young Noh,Exploring the charge transport in conjugated polymers, Adv. Mater. 28 (2017)1702729–1702736, https://doi.org/10.1002/adma.201702729.

[34] Y. Meng, G.X. Liu, A. Liu, H.J. Song, Y. Hou, B.C. Shin, F.K. Shan, Low-temperaturefabrication of high performance indium oxide thin film transistors, RSC Adv. 5(2015) 37807–37813, https://doi.org/10.1039/c5ra04145g.

Y. Yang, et al. Applied Surface Science 481 (2019) 632–636

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