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PPLIED
A
Applied Energy 82 (2005) 266–283

www.elsevier.com/locate/apenergy

ENERGY

Photovoltaic power interface circuit incorporatedwith a buck-boost converter and

a full-bridge inverter

Feel-soon Kang a,*, Sung-Jun Park b, Su Eog Cho c,Jang-Mok Kim c

a Department of Control and Instrumentation Engineering, Hanbat National University,

San 16-1, Duckmyung, Yuseong, Daejeon 305-719, Republic of Koreab Department of Electrical Engineering, Chonnam National University, 300 Yongbong-dong,

Puk-gu, Gwangju 500-757, Republic of Koreac Department of Electrical Engineering, Pusan National University, Changjurn, Kumjung,

Busan 609-735, Republic of Korea

Available online 24 December 2004

Abstract

This paper presents an efficient photovoltaic power interface circuit incorporated with a

buck-boost converter and a full-bridge inverter. It connects up a solar array to power a utility

line. The proposed interface circuit consists of five switches, an input inductor, and LC filters.

The buck-boost converter operates at high switching frequency to make the output current a

sine wave, whereas the full-bridge inverter operates at low switching frequency of 50–60 Hz,

which is determined by the ac utility line frequency; thus, it can reduce the switching losses

incurred by the full-bride inverter. In the output stage, a high power-factor is achieved without

an additional current controller owing to the input inductor current operatly in a discontinu-

ous conduction mode. Consequently, it has a simple and robust circuit configuration. Opera-

tional modes are analysed, and then the validity of the proposed interface circuit is verified

through computer-aided simulations and experiments based on a laboratory prototype of

150 W.

� 2004 Elsevier Ltd. All rights reserved.

0306-2619/$ - see front matter � 2004 Elsevier Ltd. All rights reserved.

doi:10.1016/j.apenergy.2004.10.009

* Corresponding author. Tel.: +82 42 821 1172; fax: +82 42 821 1164.

E-mail address: [email protected] (F. Kang).

mailto:[email protected]

F.-s. Kang et al. / Applied Energy 82 (2005) 266–283 267

Keywords: Buck-boost converter; Digital signal processor; Full-bridge inverter; Photovoltaic system;

Pulse-width modulation

1. Introduction

In recent years, the utilization of natural energy has become an attractive alterna-

tive to fossil fuels because of the latter�s negative impact on the environment. Solar

energy is especially attractive because it is inexhaustible and because its conversion is

not accompanied by the emission of air or water pollutants, or the generation of so-

lid waste.

In photovoltaic power-generation systems, the cost reduction of solar cells and

interface circuit between a solar array and a utility line is still a major issue. To alle-viate the cost problem, several inverter topologies have been presented [1–4]. Among

them, a single-phase utility interactive photovoltaic-system including a current-

source pulse width modulation (PWM) inverter was presented [1]. It can transfer

arbitrary power generated by a solar array to loads or utility lines regardless of

Nomenclature

CDC dc-link capacitor

CF output filter capacitorE stored energy in the input inductor

iDC diode current

iL input inductor current

iLpeak the peak of the input inductor current

iout output current

iP input solar-array current

L input inductor

LF output filter inductorLline line inductance

Pout output power

QA buck-boost switch

Q1, Q2, Q3, Q4 full-bridge switches

Ro minimum output resistance

Ton on-time of switches

Ts switching period

VDC voltage across dc-link capacitorVP input solar-array voltage

Vs ac utility line-voltage

h the angle by which iout lags vSx1 the fundamental output frequency

268 F.-s. Kang et al. / Applied Energy 82 (2005) 266–283

the magnitude of the generated array voltage. There is no need for a current feed-

back control to achieve a high power-factor because the system operates in discon-

tinuous conduction modes (DCMs); nevertheless, it still has a cost problem.

Avoiding the use of a transformer has the additional benefits of reducing cost, size,

weight and complexity of the photovoltaic inverter system. Five new inverter topol-ogies using two converters with buck and boost voltage characteristics, in parallel-

series-connection, were proposed to avoid the drawbacks of commonly-used

voltage-source-inverters [2]. One of the presentable achievements of these five topol-

ogies is an enormous reduction in volume; however it has a low efficiency due to the

switching loss of the power-switching devices.

In this paper, we present a photovoltaic-power interface circuit based on a buck-

boost and a full-bridge configuration. The proposed inverter supplies currents ob-

tained by solar arrays to an ac utility line with high power-factor. The input inductorcurrent is designed to operate in a DCM; thus, it does not require an additional

current controller. Consequently, it has a simple structure compared with

commonly-used inverters for photovoltaic power-generation. Operational modes

are described, and then the validity is verified through computer-aided simulations

and experiments using a 150 W laboratory prototype.

2. Proposed photovoltaic power generator

Fig. 1(a) shows a basic configuration of the proposed interface circuit. It consists

of five switches, an inductor, and LC filters. Among the five switches, only QA oper-

ates at a high switching-frequency to make the output current a sinusoidal wave, and

the others determine the polarity of the ac output voltage with a low switching fre-

quency �50–60 Hz. This switching scheme is useful to reduce the switching loss and

switching interference problem. The proposed photovoltaic interface circuit is based

on the principle of buck-boost power conversion. It has an advantage compared witha boost or a buck power converter with respect to output-voltage generation. In the

case of a buck topology, the output voltage never becomes higher than the input

voltage; therefore, in order to feed such low voltage into the high ac utility line, it

requires an additional boost converter or a step-up transformer. On the other hand,

a boost topology can generate a higher output-voltage than the input; however, a

lower voltage under the input level would not be obtained. But the proposed inter-

face circuit, i.e., a buck-boost topology can generate either a higher or lower than

input voltage according to duty ratio [5,6].Fig. 1(b) shows the operational waveforms for each gate signal (QA, Q1–Q4),

inductor current (iL), diode current (iDC), ac utility voltage (vS) and superimposed

output-current (iOUT). The proposed circuit can provide a sinusoidal output current

without sensing the input inductor current because the inductor is designed to oper-

ate in a DCM; thus, the input inductor current peak automatically follows the ac

utility voltage, but, it requires a feedback signal to control the phase difference be-

tween the ac utility line voltage and the transferred current via the interface circuit.

As shown in Fig. 1(b), during a positive half cycle of the ac utility voltage (vS), thepolarity selection switches, Q1 and Q2, are conducting, and a pulse width modulated

Fig. 1. Configuration of the proposed inverter and operational waveforms: (a) configuration of the

proposed interface circuit; (b) each gate signal, input inductor current (iL), diode current (iDC), and ac

utility line voltage (vS) and output current (iOUT).


switching signal to synthesize a sinusoidal current wave is applied to QA. In contrast,

a case where Q3 and Q4 are conducting, the current obtained by the buck-boost con-

verter is transferred to the negative direction of the utility line voltage.

For the sake of convenience, the proposed interface circuit is divided into three

operational modes as depicted in Fig. 2. It shows the magnified waveforms of the

Fig. 2. Magnified inductor current with QA gate signal.


input inductor current (iL) and diode current (iDC) according to the gate signal QA.

To simplify the mode analyses, we only consider a positive cycle. All switching de-

vices and components are ideal; thus, the effect of stray capacitance and inductance

is ignored. The ripple component of the input solar-array voltage (vP) is assumed to

be very small and equivalent to a constant dc voltage source (VP), and the load is a

pure resistance. Before Mode 1, there is no current flowing through the input induc-tor. To supply a positive output current, Q1 and Q2 are conducting.

Mode 1. (t0–t1). At t0, QA is turned on, and D is reverse-biased. The input array

voltage (VP) is imposed across the input inductor (L); thus, the inductor current (iL)

linearly ramps up at the rate

diLdt

¼ V P

L: ð1Þ

During on-time (Ton), the inductor current reaches

iLpeakðtÞ ¼V P � T on

L: ð2Þ

Hence, during this mode, the stored energy (E) in the input inductor become

1 2
E ¼2LiLpeakðt1 � t0Þ: ð3Þ
Mode 2. (t1–t2). At t1, QA is turned off while voltage across the inductor reverses;

thus iLpeak flows to the output. The inductor current does not flow through the inputsolar-array. All of the energy stored in the inductor is delivered to output loads

before QA becomes conducting. Hence, the power transferred from the solar array

to the output load is given as


P ¼Li2LpeakðtÞ

2T S

: ð4Þ

Assuming that the proposed interface circuit is lossless, and a minimum output resis-

tance Ro, the output power

P out ¼V 2

out ¼LI2Lpeak

: ð5Þ
Ro 2T S
Mode 3. (t2–t3). QA is in the off state, and there is no power transfer to the load

from the input source because the inductor current is designed to operate discontin-

uously. In practice, to make the output current (iOUT) a continuous wave, a low-pass

filter, composed of the inductor LF and the capacitors CF, is required between theutility line and the inverter terminal.

An analysis of the dc-side array current iP is informative with respect to

understanding the proposed interface circuit. In this analysis, LC high frequency

filters are included at the dc-side solar-array as well as at the ac-side utility line, asshown in Fig. 3. Assuming that the switching frequency is very high, i.e. approaching

infinity, the values of the filter components (L and C) required in both the dc-side

and ac-side filters will approach zero to filter out the high switching frequency

components in vOUT and iOUT. This means that the energy stored in the filters is

negligible. The instantaneous solar-power input must equal the instantaneous power

output because the interface circuit itself has no energy-storage elements. By these

assumptions, vS is a pure sinusoidal wave at the fundamental output frequency x1: it

is expressed as

mS1 ¼ mS ¼ffiffiffi2

pV S sinx1t: ð6Þ

If the output is a utility line including a line inductance (Lline) as shown in Fig. 3,

where the ac utility voltage is a sinusoidal wave of frequency x1, then the output cur-

rent transferred by the interface circuit would also be a sine wave and would lag vSfor an line inductance, i.e.

iOUT ¼ffiffiffi2

pIOUT sinðx1t � hÞ; ð7Þ

where h is the angle by which iOUT lags vS. On the dc-side, the LC filter will filter the

high switching-frequency components in iP, and i�P would only consist of the low-frequency and dc components. Assuming that no energy is stored in the filters, then

Fig. 3. Interface circuit with filters.


mPi�PðtÞ ¼ mSðtÞiOUTðtÞ ¼ffiffiffi2

pV S sinx1t

ffiffiffi2

pIOUT sin x1t � hð Þ

j k: ð8Þ

Rearranging (8), yields

i�PðtÞ ¼V SIOUT

V P

cos h� V SIOUT

V P

cosð2x1t � hÞ: ð9Þ

In (9), we know that i�P consists of a dc component iP, which is responsible for the

power transfer from VP on the dc side of the interface circuit to the ac side. At

the same time, iP contains a sinusoidal component of twice the fundamental fre-

quency of the utility line. The solar-array current iP consists of i�P and the high-

frequency components due to switching.

In practical photovoltaic systems, the previous assumption of a constant dcvoltage as the input to the interface circuit is not absolutely valid. In general, the dc

voltage source is obtained by the solar-array, and a large capacitor or battery is used

across the array terminals to filter the dc solar array voltage. The ripple in the

capacitor voltage, which becomes the dc input voltage to the interface circuit, is due

to two causes: (a) the output voltage obtained by the solar-array is not a pure dc

because of non-linear characteristics of the solar array — it largely depends on solar

radiation, temperature, load conditions, and other non-linear factors; and (b) as

derived in (9), the current drawn by the interface circuit from the dc-side is not aconstant dc but has a second harmonic component of the fundamental frequency at

the interface circuit output in addition to the high switching frequency components.

The second-order harmonic current component results in a ripple in the capacitor

voltage, even though the voltage ripple due to the high switching frequencies is

essentially negligible.

3. Simulation and experimental results

To assess the performance of the proposed interface circuit for the photovoltaic

power-generation, computer-aided simulation by PSpice (Professional Simulation

Program with Integrated Circuit Emphasis; MicroSim, ver. 8.0) is implemented first,

and then a 150 W laboratory prototype was manufactured and experimented.

3.1. Simulation results

Table 1 shows the information for simulation. Power MOSFETs are employed as

switching devices. The switching frequency of QA is set to 10 kHz. To reduce the cur-

rent stress of QA when it turns off, a fast-recovery diode (MUR1520) is used. Initialvalues of all passive components are set to zero. In this simulation, we used a con-

stant dc voltage as an input source instead of a solar cell. Therefore, simulation re-

sults maybe little different from those of experiments. The VSIN component of the

PSpice library is used for the utility line. Its internal value was set to 100 V rms,

60 Hz, and a single-phase.

Table 1

Parameters for PSpice simulation

Symbol Part name Description

QA IRFP460 Power MOSFET 500 V/20 A; switching frequency = 10 kHz

Q1–Q4 IRF830 Power MOSFET 500 V/5 A

D MUR1520 Fast recovery 200 V/1 5 A

CDC C lOnF, IC = 0

L L 300 lH, 1C = 0

LF L 3 mH, 1C = 0

CF C 300 nF, IC = 0

VP VDC DC = 51

VS VSIN VOFF = 0, VAMPL = 141, FREQ = 60 TD = 0, DF = 0, PHASE = 0


Fig. 4 shows simulation results of the input inductor current (iL) and output diode

current (iDC): they operate in the discontinuous current conduction mode. So it does

not need to feed back the input current to the controller. The peak of the input cur-

rent will automatically follow well the shape of the output-voltage waveform. But,

the higher current-peak increases the current rating of the switching devices. There-

fore, it is not recommended for high-power applications. In addition, the input

inductor and diode current does not flow at each zero-cross point because of a dead

time, which is given to prohibit series-connected switches from short circuiting.Thus, it becomes a reason for the current distortion. However, the final output cur-

rent turns into a sinusoidal current owing to output LC filter showing good THD

(total harmonic distortion) characteristics.

Fig. 5 shows the variation of output current and voltage across CDC according to

the increase of load power. In the simulation, we changed the value of the output

load to estimate the circuit operation. In Fig. 5, we find that voltage across CDC is

changed with load power conditions. With the increase of transferred current, the

bandwidth of VDC becomes larger because the peak of the input inductor current will

Fig. 4. Simulation results of input inductor current (iL) and diode current (iDC).

Fig. 5. Simulation results of output current (iOUT), grid voltage (vS), and voltage across CDC according to

the load power: (a) 30 W; (b) 60 W; (c) 140 W.



be higher. In practical photovoltaic applications, the solar-array current will be in-

creased or decreased by the intensity of sunlight. As shown in Fig. 5(a)–(c), the pro-

posed interface circuit shows a high power-factor regardless of the load power

conditions. The transferred current (iOUT) is always in phase with the grid voltage

(VS). Supplying energy to the grid with a high power-factor is one of the importantissues in order to increase reliability, stability, and power utility.

3.2. Experimental results

Based on the simulation results, we manufactured a laboratory prototype, and it

was applied to a practical solar-array. A photograph of the prototype is given in

Fig. 6. The circuit components used are listed in Table 2. Power MOSFETs are used

Fig. 6. Photograph of the 150 W laboratory prototype.

Table 2

Component list of the laboratory prototype

Symbol Value and type Features

QA 2SK2198 Power MOSFET 500 V/30 A: Shindengen electric;

switching frequency = 10 kHz

Q1–Q4 IRF830A Power MOSFET 500 V/5 A: International rectifier

D FR605 Fast recovery 600 V/6 A: RECTRON

CDC 10 nF Mylar condenser: Samwha

L 300 lH Ferrite Core PC40/Litz-wired: TDK

LF 3 mH Ferrite Core PC40/Litz-wired: TDK

CF 300 nF Mylar condenser: Samwha

VP DC 51 V Solar array/Si/54.14 W/3 paralleled: LG

VS AC 100 V/760 Hz Grid-connected type


for the main switching devices. A fast-recovery diode is employed to minimize the

current stress of QA when it turns off. For the input inductor, we used ferrite core,

and Litz wire (woven wire) was used to reduce the losses in the inductor. An Si-type

solar array was employed for the input power-source. Three panels are connected in

parallel. The maximum power rating of the used solar-array is about 162 W undersufficient sunlight. The proposed photovoltaic interface circuit was installed between

the solar array and a single-phase utility line. As a controller, a digital signal proces-

sor (DSP) TMS320F241 is used. Fig. 7 shows a control block diagram for the pro-

posed interface circuit. The general perturbation and observation control scheme is

applied to track the maximum power point (MPP). On the whole, it is based on a

proportional integration (PI) control method. QA is applied to the buck-boost switch

via a PWM0 port with anti-windup function, and it has a limit of duty ratio because

it should be operated in the DCM. The operating frequency of QA was set to 10 kHz.Two ports (PWM2 and PWM3) are allotted to control the switches of the full-bridge

inverter. An internal capture function of the TMS320F241 is used to operate the out-

put current in phase with ac utility line voltage. An over-current detection faculty is

added to protect the system under fault situations.

Fig. 8(a) shows gate signals of QA, Q1 (and Q2), and reference signal (Cap0). By

using this reference signal and a zero-cross detecting function (null voltage detecting

function), it can determine the switching sequence of the full-bridge switches. Dead

time between the positive and negative selection switches is set to 5 ls by using aninternal dead-band programming function of TMS320F241 (DBCON). Fig. 8(b)

shows the ac utility line voltage (vS) and the output current (iOUT) transferred via

the interface circuit: both waveforms are in phase showing a high power-factor;

therefore, the DPF (displacement power factor) is exactly unity as shown in

Fig. 7. Control block diagram of the proposed interface circuit.

Fig. 8. Experimental waveforms: (a) gate signals of QA, and (Q1, Q2) with a reference signal (Cap0); (b) ac

utility line voltage (vS) and the supplied current transferred from the proposed inverter system (iOUT); and

(c) input inductor current (iL) and its magnified waveform.



Fig. 8(b). The measured power factor was over 0.98. The output current is closer to

the sine wave compared to the utility voltage. In view of power-factor correction, it is

important that the proposed interface circuit can produce a sinusoidal current wave-

Fig. 9. Dynamic response of the output current (iOUT) in the proposed interface circuit: (a) when sunlight

is being increased; (b) when sunlight is being decreased; (c) magnified waveform of (a); and (d) magnified

waveform of (b).


form because the sinusoidal current can minimize the harmonic power-generation.

That is to say, there is no harmonic power generation although the output grid volt-

age has some harmonics because the current is sinusoidal. Fig. 8(c) shows the input

inductor current operated in a DCM. In Fig. 8(c), the lower current waveform is the

Fig. 10. Variation of voltage across CDC according to the transferred power: (a) 50 W; (b) 80 W; and (c)

150 W.

Fig. 11. Characteristics of the output filter according to the transferred power: (a) 50 W; (b) 80 W; and (c)

150 W.



same as the upper one, but on an expanded time scale. As shown in the upper wave-

form, the peak of the inductor current follows the shape of the output voltage wave-

form well. Thus, it is not necessary to sense the input inductor current.

Fig. 9 shows the dynamic responses of the proposed interface circuit in the case

where sunlight is increased or decreased, respectively. Fig. 9(a) shows the output cur-rent when sunlight is increased. Fig. 9(b) is a case where the sunlight is decreased.

Fig. 9(c) and (d) are the magnified waveforms of Fig. 9(a) and (b), respectively. In

the experiment, we used a 500 W plasma lamp instead of the Sun for the sake of con-

venience. Generally, the output power of a solar array largely depends on the weath-

er conditions, solar radiation, temperature, load conditions, and other non-linear

40 60 80 100 120 140 160 180 200 220

1.0

1.2

1.4

1.6

1.8

2.0

2.2

1

Switc

hing

loss

es [

W]

Output Power [W]

Full-bridge (Q1+Q

2+Q

3+Q

4)

Buck-boost (QA)

Full-bridge + Buck-boost

Fig. 12. Power consumption by switching losses.

0 2 4 6 8 10 12-0.1

0.0

0.1

0.8

0.9

1.0

1.1

Am

plitu

de [

p.u]

Harmonic numbers [N]

50 W

80 W

150 W

200 W

Fig. 13. FFT results according to energy flow.


factors. The output current transferred by the proposed interface circuit maintains a

high power factor whether sunlight increases or decreases. This means that the pro-

posed circuit ensures high power factor regardless of the variation of input solar ar-

ray power.

Fig. 10 shows the voltage (VDC) across CDC with the superimposed grid-voltage(VS). The outlines of the capacitor voltage maintain almost a constant wave shape,

but its bandwidth is increased with the increase of the transferred current. Since the

peak of the input inductor current is being increased, it influences the voltage across

the CDC. These experimental results are similar to those of the simulation results de-

picted in Fig. 5.

The proposed interface circuit can obtain a sinusoidal output current wave with-

out sensing an input inductor current, because the inductor current operates in the

discontinuous-current conduction mode. However, due to this reason, it requires ahigh-performance output filter to make the output current (iOUT) a continuous wave.

In the experiments, a low-pass filter is inserted between the ac utility line and the in-

verter terminal. Fig. 11(a)–(c) show the characteristics of the employed low pass fil-

ter. Regardless of the quantity of the transferred current, it shows good

characteristics in filtering out high-order harmonics.

Fig. 12 shows experimental results for switching losses. The switching loss of

QA employed for chopping purpose is higher than that of the sum of the other

switches because QA is operated at a higher switching frequency of 10 kHzwhereas other full-bridge switches are working at low switching-frequencies. In

addition, the switching loss by QA is not severe owing to the applied soft-switch-

ing method. Because the input inductor current is operated in DCM (discontinu-

ous current conduction mode), QA is always turned to a zero-current state without

a turn-on loss. Regardless of the quantity of the transferred energy, the switching

losses by QA and others (Q1 + Q2 + Q3 + Q4) are measured as 1.22 and 0.96 W,

respectively.

FFT results for the output current (iOUT) are shown in Fig. 11, i.e. good har-monic characteristics. Supplying current to the grid with a promising THD is one

of the important issues to increase the reliability, stability and power utility (see

Fig. 13).

4. Conclusion

In this paper, we proposed a photovoltaic power interface circuit based on thebuck-boost and full-bridge configurations. The proposed circuit consists of five

switches, an input inductor and LC filters. The buck-boost converter operates at a

high switching-frequency to make the output current a sinusoidal wave, whereas

the full-bridge inverter operates at a low switching-frequency of 50–60 Hz; thus, it

can reduce the switching losses occuring in the inverter. Because the input inductor

is operated in the discontinuous-current conduction-mode, a near unity power-factor

can be achieved without an additional input inductor current controller. Conse-

quently, the overall system shows a simple structure. Operational modes were ana-


lysed, and verified through computer-aided simulations and experimental results

using a 150 W laboratory prototype.

References

[1] Michihiko Nagao, Koosuke Harada. Power flow of photovoltaic system using buck-boost PWM

power inverter. Proc IEEE Power Electron Drive Sys 1997:144–9.

[2] Johanna M, Myrzlk A. Novel inverter topologies for single-phase stand-alone or grid-connected

photovoltaic systems. Proc IEEE Power Electron Drive Sys 2001:103–8.

[3] Akkaya R, Kulaksiz AA. A microcontroller-based stand-alone photovoltaic power-system for

residential appliances. Appl Energ 2004;78(4):419–31.

[4] Nonaka S. A novel three-phase sinusoidal PWM voltage source inverter and its application for

photovoltaic power-generation system. Proc IEEE Power Conversion Conf 1997:755–61.

[5] Pressman Abraham I. Switching power supply design. New York: McGraw-Hill; 1991.

[6] Mohan N, Undeland TM, Robbins WP. Power electronics: converters, applications and design. New

York: Wiley; 1995.

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