application note microblaze support ds5203 fpga board

RTI FPGA Programming Blockset

MicroBlaze Support DS5203 FPGA Board

Application Note

1.1 – May 2014

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MicroBlaze Support DS5203 FPGA Board - 2014 3

Contents

Contents

About This Document ................................................................ 4 Document Symbols and Conventions ........................................................................................ 4

Overview ...................................................................................... 5 Software Prerequisites ............................................................................................................................. 6

Example of DS1005 PPC Board with DS5203 FPGA Board: RTI FPGA Programming Blockset Using MicroBlaze ..................... 7 Constructing the MicroBlaze Core with Xilinx Platform Studio ................................................ 8 Constructing the Simulink Model for the DS5203 ...................................................................... 12 Constructing the Software Component .......................................................................................... 16

Importing Software Projects ....................................................................................................... 18 Running and Checking the Model .................................................................................................... 19 Replacing and Restoring Software in the Bitstream .................................................................. 21 Measured Delays ..................................................................................................................................... 23

4 MicroBlaze Support DS5203 FPGA Board - 2014

About This Document

Document Symbols and Conventions

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MicroBlaze Support DS5203 FPGA Board - 2014

Overview

This application note describes how to use a MicroBlaze processor block as part of a Simulink FPGA model with the dSPACE RTI FPGA Programming Blockset.


Software Prerequisites The workflow described in this document requires the following software installations: dSPACE RCP and HIL RLS2013-B including RTI FPGA Programming Blockset 2.6

or later

Xilinx ISE Design Suite 14.6 or later

Xilinx System Generator 14.6 or later

Xilinx Platform Studio and Embedded Development Kit (EDK)

It is recommended to use Windows 7 as operating system.

The following descriptions and instructions are based on RTI FPGA Programming Bockset 2.6 and Xilinx ISE Design Suite 14.6.


Example of DS1005 PPC Board with DS5203 FPGA Board: RTI FPGA Programming Blockset Using MicroBlaze

This section gives a simple example of using the MicroBlaze processor core within the RTI FPGA Programming Blockset. The example application takes an unsigned 32-bit integer input and feeds it into the MicroBlaze via shared memory. The MicroBlaze adds a constant value of 3 to the input and writes the result back via shared memory. Additionally, the MicroBlaze is set up with an interrupt controller. The interrupt controller is connected to the “data new” port of the incoming data port and triggers an interrupt service function inside the MicroBlaze which adds the number of interrupts modulo 1000 to the input data multiplied with 1000. The model is composed of two parts: The processor-model running on the DS1005 processor board and the FPGA model (containing the MicroBlaze) running on the DS5203.

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Shared memories TO and FROM: Depth: 16

Ownership: Locally owned and initialized

Access protection: Unprotected

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Output type: Fixed point

Arithmetic type: Unsigned

Number of bits: 32

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Constant 1, 2 Constant value: 0. This is the address for the value written to the shared

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Arithmetic type: unsigned

Number of bits: 4

Binary point: 0

Sample period: 1e-8.

Constant 3 Constant value: 0. This is the address for the value written to the shared

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Number of bits: 32

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Constant 4 Constant value: 0. This is the address for the value written to the shared

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Output type: Boolean


Now you can add the EDK processor block which represents the MicroBlaze core. Open the Simulink Library Browser.

From the Xilinx Control Logic blockset, add EDK Processor to the model, resize it larger and double-click to open. Select the different tabs and configure as follows. You must click Apply after each modification.

Configure Processor for: HDL Netlisting

Select the system.xmp file created by XPS in the previous step.

Memory Map: Add all. This adds the previously defined shared memories to the MicroBlaze (visible when “look under mask” is done).

Expose the following ports: fpga_0_rst_1_sys_rst_pin, xps_intc_0_Intr_pin, xps_intc_1_Intr_pin

Disable Dual Clocks.

Disable Co-Debug and leave the Initial Program empty for the moment.

On the Basic page, click Sync and then click OK.

Create Constant 5, 6, 7 Constant values 0, 1 and 0 for 5, 6 and 7



Number of bits: 1

Binary point: 0


Connect constant 5 to fpga_0_rst_1_sys_rst_pin no reset

Connect constant 5 to fpga_0_rst_1_sys_rst_pin no reset

Connect constant 6 to proc_sys_reset_0_Dcm_locked_pin

Connect constant 7 to xps_intc_0_Intr_pin (0 = no interrupt)

Connect Register In 1, Data New to xps_intc_1_Intr_pin (interrupt request whenever there is new data)

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Constructing the Software Component This section explains how to implement a software component for the system described above using the Xilinx Software Development Kit (SDK). The program will contain one interrupt service routine, adding the number of calls of the interrupt service function modulo 1000 to the FPGA input multiplied by 1000. The last three decimal digits of the output run in a loop to show that the interrupts function. The other digits represent the original input, demonstrating how data is fed to the MicroBlaze. The program will also contain a main program which receives the FPGA input via shared memory and sends the result back to the FPGA. Create a new directory <FPGAModelDir>/SDK. Start Xilinx. Create a new hardware platform specification: Menu File: new: other: Xilinx, Hardware Platform Specification

Select a project name, e.g., “MB”.

Target hardware specification: <FPGAModelDir>/sysgen/SDK_Export/hw/system.xml

Now the SDK must be informed about the location of the software drivers provided by the XPS export. Menu Xilinx Tools: Repositories: New

Set directory to <FPGAModelDir>\sysgen\SDK_Export\sysgen_repos

After the hardware platform specification has been generated , you can create a board support package together with an example application. The board support package contains some simple access functions for the shared memories and for the interrupt controller. Switch the “project build” configuration to release mode. Menu Project: properties: C/C++ Build: Manage Configurations: Release: set active. Create the example application as follows: Menu File: New, Application Project

Choose a project name, e.g. “MB_app”.

Click Next.

Application template: Peripheral Tests

The example application has been created. To run it, you must replace the source code. In the project explorer, double-click the testperiph.c file in the folder MB_app/src. Replace the code by the following program.


#include <stdio.h>

#include "xparameters.h"

#include "sg_plbiface.h"

#include "xintc_l.h"

volatile u32 * to_pt = (u32 *) XPAR_SG_PLBIFACE_0_MEMMAP_TO;;

volatile u32 * from_pt = (u32 *) XPAR_SG_PLBIFACE_0_MEMMAP_FROM;

u32 counter = 0;

u32 int_counter = 0;

void fpga_int_handler(void * baseaddr_p)

{

int_counter = (int_counter + 1) % 1000 ;

}

int main()

{

xc_iface_t *iface;

// initialize the software driver, assuming the

// Pcore device ID is 0

XC_CfgInitialize(&iface, &SG_PLBIFACE_ConfigTable[0]);

// MicroBlaze & XIntC Interrupt Controller

microblaze_enable_interrupts();

// Register fpga interrupt routine in the vector table

// of XIntC

XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,

XPAR_XPS_INTC_0_SYSTEM_XPS_INTC_0_INTR_PIN_0_INTR,

(XInterruptHandler) fpga_int_handler,

(void *)0);

// Start the interrupt controller XIntC

XIntc_MasterEnable(XPAR_XPS_INTC_0_BASEADDR);

XIntc_EnableIntr (XPAR_XPS_INTC_0_BASEADDR,

XPAR_SYSTEM_XPS_INTC_0_INTR_PIN_0_MASK);

while (1)

{

counter = *to_pt * 1000 + int_counter;

*from_pt = counter;

}

return 0;

}


Save the file. The compilation is executed automatically. The application has been compiled to <FPGAModelDir>\SDK\MB_app\Release\MB_app.elf and is ready to use. Open the EDK block in the FPGA Simulink model.

Select the software tab and browse to the ELF file.

Execute the FPGA build via the FPGA Setup block.

Importing Software Projects

If you want to import SDK software projects into your current workspace, select File – Import – General – Existing Projects into Workspace.

Then select the root directory of the project to be imported.


Running and Checking the Model After the FPGA component was synthesized successfully, the processor component has to be built. Open the processor component of the Simulink model.

Open the processor setup block. On the Model Configuration page, select Processor Build and click Switch Model Mode.

If directory <FPGAModelDir>\*_rti1005 exists, delete it.

Press Ctrl-B to build the model.

The <FPGAModelDir>\*.sdf and *.ppc files are generated.

Now the result can be tested. Open dSPACE ControlDesk and register your DS1005 / DS5203 system.

Drag the SDF file to the DS1005 icon. This loads the file to the DS1005 and programs the FPGA on the DS5203.

Create a simple layout in ControlDesk with two numerical displays and one numerical input.

Connect the numerical input to Model Root/constant/value.

Connect the numerical displays to Model Root/microblazed/In1 and Model Root/unmodified/In1.

Start the animation.

The display should look like this.


In this figure, 12 is the input into the system. It is shown in the numerical input field and in the numerical display for “unmodified”. The numerical display containing 1015 shows the result computed by the MicroBlaze. 1000 is added by the interrupt service function and 3 by the main function. You can now modify the value in the numerical input field and observe the behavior.


Replacing and Restoring Software in the Bitstream If the software component was changed, there is no need to perform the whole FPGA synthesis process again. The FPGA bitstream can be updated with the new ELF file. The original bitstream is backed up and can be restored if desired. Updating the bitstream with a new ELF file First a modified software component has to be created. In Xilinx SDK, in the software component’s file testperiph.c, modify the

interrupt service function. Replace counter = *to_pt * 1000 + int_counter; by counter = (*to_pt + 2) * 1000 + int_counter;

Save the file. This automatically compiles and updates the ELF file.

Now the FPGA bitstream can be updated. It is contained in an INI file. After each complete FPGA build, a new INI file is created at this location. The files are named subsystem_<some hex number>.ini. To provide unique file names, the hexadecimal number is different for each FPGA build. Identify the file name of your current build by looking in the INI file directory, e.g. subsystem_4A284D2DC61ADB.ini. The INI files are located in <FPGAModelDir>/<ModelName>_rtiFPGA/ini. Go to the MATLAB prompt.

Enter rtifpga_scriptinterface('ReplaceElfFile', '<ini path>\ Subsystem_4A284D2DC61ADB.ini', '<elf path>\MB_app.elf'), where <ini path> and <elf path> are replaced by the specific current locations.

Delete <FPGAModelDir>\*_rti1005 or disable the incremental build in MATLAB via menu File: Preferences: Simulink: Launch Simulink Preferences: Configuration Defaults: Simulation Target Build Mode: Clean all

Rebuild the processor component of the model.

Reload the model using ControlDesk. The changed behavior can be observed.

Restoring the original bitstream When a complete FPGA build is done (not only an update of the bitstream as described above), the bitstream containing the software component is backed up in the INI file. It can easily be restored: Go to the MATLAB prompt.


Enter rtifpga_scriptinterface('ReplaceElfFile', '<ini path>\ Subsystem_4A284D2DC61ADB.ini', '') where <ini path> is replaced by the specific current location. It is nearly the same except that you provide an empty ELF-file name.

Delete <FPGAModelDir>\*_rti1005 or disable the incremental build in MATLAB via menu File: Preferences: Simulink: Launch Simulink Preferences: Configuration Defaults: Simulation Target Build Mode: Clean all

Rebuild the processor component of the model.

Reload the model using ControlDesk. The original behavior can be observed.


Measured Delays From the software point of view, some delays where measured using a real-world model on the DS5203. For other performance figures, refer to the Xilinx MicroBlaze Guide.

Operation Delay Data from model to MicroBlaze via shared memory 60 ns Data from model to MicroBlaze via shared memory 80 ns Interrupt from model to Microblaze 1300 ns

application note microblaze support ds5203 fpga board

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