appendix i: important verilog keywords

Appendix I: Important Verilog Keywords

The important Verilog keywords used in this book are listed below.

module assign reg wire

input output parameter endmodule

begin end fork join

always posedge negedge bit

function endfunction case endcase

if else casex casez

for while initial

`define localpar `timescale

inout task endtask

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2022V. Taraate, Digital Logic Design Using Verilog,https://doi.org/10.1007/978-981-16-3199-3

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Appendix II: Frequently Used VerilogConstructs

Verilog is case sensitive, and few of the important Verilog-2005 constructs arelisted below.


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582 Appendix II: Frequently Used Verilog Constructs

Appendix II: Frequently Used Verilog Constructs 583

584 Appendix II: Frequently Used Verilog Constructs

For the syntax of other constructs, please refer Verilog-2005 language referencemanual!

Appendix II: Frequently Used Verilog Constructs 585

Appendix III: Xilinx Spartan Devices

The comparison of the Spartan 3 FPGA devices and the architecture is documentedin this document.

• Xilinx Spartan 3 Devices


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Device

System

gates

Equ

ivalent

logic

cells

(1)

CLB

array(O

neCLB=four

slices)

Distributed

RAM

bits

(K=10

24)

Block

RAM

bits(K

=10

24)

Dedicated

multip

liers

DC

Ms

Max.

user

I/O

Maxim

umdifferential

I/O

pairs

Row

sColum

nsTotal

CLBs

XC3S

50W

(2)

50K

1,72

816

1219

212

K72

K4

212

456

XC3S

200(2)

200K

4,32

024

2048

030

K21

6K12

417

376

XC3S

400(2)

400K

8,06

432

2889

656

K28

8K16

426

411

6

XC3S

1000

(2)

1M17

,280

4840

1,92

012

0K43

2K24

439

117

5

XC3S

1500

1.5M

29,952

6452

3,32

820

8K57

6K32

448

722

1

XC3S

2000

2M46

,080

8064

5,12

032

0K72

0K40

456

527

0

XC3S

4000

4M62

,208

9672

6,91

243

2K1,72

8K96

463

330

0

XC3S

5000

5M74

,880

1104

808,32

052

0K1,87

2K10

44

633

300

Notes:

1.Log

icCell=4-inpu

tlook

uptable(LUT)plus

a‘D

’flip-flop

.‘Equ

ivalentLog

icCells’equal‘Total

CLBs’

�8Log

icCells/CLB

�1.12

5effectiveness.

2.These

devicesareavailablein

Xilinx

Autom

otiveversions

asdescribedin

DS3

14:Sp

artan3Autom

otiveXAFPGAFam

ily.

588 Appendix III: Xilinx Spartan Devices

• Spartan 3 Family Architecture

Appendix III: Xilinx Spartan Devices 589

• Xilinx Spartan 3 package information for Part no XC3S400-4PQ208C

For more information please use the following link.http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf.

• Xilinx FPGA Spartan 3E Devices


http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf

Device

System

gates

Equ

ivalent

logiccells

CLBarray(one

CLB=four

slices)

Distributed

RAM

bits(1)

Block

RAM

bits(1)

Dedicated

multip

liers

DC

Ms

Maxim

umuser

I/O

Maxim

umdifferentialI/O

pairs

Row

sColum

nsTotal

CLBs

Total

slices

XC3S

100E

100K

2,16

022

1624

096

015

K72

K4

210

840

XC3S

250E

250K

5,50

834

2661

22,44

838

K21

6K12

417

268

XC3S

500E

500K

10,476

4634

1,16

44,65

673

K36

0K

204

232

92

XC3S

1200

E12

00K

19,512

6046

2,16

88,67

213

6K50

4K28

830

412

4

XC3S

1600

E16

00K

33,192

7658

3,68

814

,752

231K

648K

368

376

156

Notes:

1.Byconv

entio

n,on

eKbisequivalent

to1,02

4bits.


• XILINX Spartan 3E Architecture

• XILINX Spartan 3E package information


For more information please use the following link.http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf.


http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

Bibliography

1. IEEE Standard. www.ieee.org, http://standards.ieee.org/getieee/1800/download/1800-2012.pdf

2. Guidelines and practices for successful logic synthesis version 1998.08, Aug 1998. Synopsystiming constraints and optimization user guide, version D-2010.03. www.synopsys.com

3. Guidelines and practices for successful logic synthesis version 1998.08, Aug 1998. www.synopsys.com

4. Design compiler® user guide version D-2010.03-SP2, June 2010. www.synopsys.com5. Cummings CE. Synthesis and scripting techniques for designing multi asynchronous clock

designs6. Closing the loop on clock domain functional implementation problems. www.cadence.com7. Power Compiler Reference Manual: Synopsys Inc. www.synopsys.com8. IEEE 1801 low power design standard. www.ieee.org9. RTL schematic capture using Xilinx Vivado tool: www.xilinx.com


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Index

AAcknowledgement or notification, 484Active, 143Active event queue, 144, 246Active power, 541Active queue, 242Adder, 61Adders and subtractors, 72Addition, 278AHB, 563Algorithms, 563Altera, 380ALU, 569ALU architecture, 270Always, 71, 258, 346, 545Always procedural block, 22Analyze, 414AND, 50, 52, 53, 270Antifuse, 372Application Specific Integrated Circuit (ASIC),

403Arbiters, 269, 568Architecture, 375, 406, 439Architecture design, 3Architecture document, 406Architecture level design, 406Area, 545Area constraints, 458Area optimization, 394Area optimization techniques, 455Arithmetic Logic Unit (ALU), 269Arithmetic operators, 25ASIC design, 154, 249ASIC library, 566

ASIC porting, 561ASIC synthesis and optimization strategies,

449assign, 21, 45always, 45Asynchronous, 473Asynchronous counters, 226Asynchronous design, 398Asynchronous or synchronous inputs, 183Asynchronous path, 446Asynchronous pulse generator, 261, 396Asynchronous reset, 179, 251, 252, 398Asynchronous reset ‘reset_n’, 320Attribute, 457

BBack annotation, 376Basic cell or base cell, 404Baud rate control block, 575BCD counter, 193, 210, 353BCD up-down counter, 353Begin–end, 356Behavior, 12Behavior style, 12Better design timing, 340Bidirectional IO, 573Binary and gray counter, 202Binary counter, 193Binary encoding, 324, 391Binary to gray, 86, 502Bit-stream, 377Bitwise operations, 31Bitwise operators, 31Blocking, 341, 342


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Blocking assignments, 144, 156, 158,241–243, 386, 401

Block level, 566Block-level representation, 3Block RAM (BRAM), 374, 379Bluetooth, 560Bottom-Up compilation, 454Buses, 576

CCadence RTL Compiler, 407Capacitive load, 539Capture flip-flop, 431Case, 256, 545Case…endcase, 98, 103Case-endcase construct, 102Cell library, 412Characterize, 462Check_design, 415, 469Check_timing, 469Chip architect, 535Chip level, 566Clock balancing, 546Clock buffer, 546Clock definitions, 436Clock Domain Crossing (CDC), 399, 473, 474,

506Clock gating, 258, 297, 298, 400, 539, 542,

543, 567Clock gating cell, 300Clock gating logic, 297Clocking boundary, 500Clock latency, 301Clock path group, 435Clock skew, 380, 433, 564Clock to output delay, 430Clock to q delay, 430Clock tree, 539, 564Clock Tree Synthesis (CTS), 409, 546, 564CMOS, 536Combinational logic, 96, 241Combinational loop, 152, 392Combinational path, 433Combinational path group, 435Common resources, 297Comparators, 82Compilation time, 460Compile, 418Compile-characterize, 453Compiler, 464Complement, 270Complex Programmable Logic Device

(CPLD), 368Computational blocks, 563

Concentration and replication, 35Concurrency, 24Configurable Logic Block (CLB), 369, 374,

377Configuration data, 377Consolidated control signal, 493Constant folding, 422Constrained random verification, 565Constraints, 408, 449Continuous assignment, 21, 144, 149Continuous assignment construct, 123Control and timing unit, 569Control path, 258, 476, 482, 571Control signal, 476, 482Coverage goals, 565CPLD, 368CPU, 403Create_clock, 415Current_state, 314Cycles, 567

DData and control path optimization, 295Data and control path synchronizers, 473Data arrival time, 303, 428, 431Database, 413Data buffers, 575Data integrity, 476Data path, 254, 258, 430, 476, 511, 540, 571Data path and control path optimization, 77Data path synchronizer, 499Data propagation, 567Data rate, 406Data required time, 431Data storage, 379Data synchronizer, 511DCM, 380DDR, 379DDR II, 560DDR III, 560Dead zone code, 423Debug, 453Debug or testing setup, 565Decrement, 278Default, 341, 342, 545Defining hierarchy, 567Delay Locked Loop (DLL), 377, 380, 383Delay operators, 286Delays, 16Depth, 512Deserializer, 568Design compiler, 411, 413Design constraints, 449, 450Design environment, 451

598 Index

Design implementation, 401Design object, 414, 450Design partitioning, 424, 455, 507, 563Design performance, 225, 444, 455, 541, 563Design Rule Constraints (DRC), 450, 458Design rule library, 409Design rules, 450Design specification, 406Design synthesis and timing closure, 449Design Under Verification (DUV), 353DesignWare, 411Device utilization summary, 377D flip-flop, 178, 250DFT, 154, 406, 566DFT friendly RTL, 567Differential IOs, 564Different phases, 476Digital Clock Managers (DCMs), 374D Latch, 251DMA controller, 568Down counter, 196DRC violations, 468Driver, 82Drivers, monitors, and checkers, 353Drive strength, 451DSP, 560DSP algorithms, 566DSP blocks, 374DSP filtering, 566Dual port memory, 379DUT, 82Duty cycle control, 306Dynamic, 427Dynamic and leakage power, 538Dynamic power, 400, 536, 538, 539Dynamic Voltage and Frequency Scaling, 541

EEDA, 376, 564EDA tool, 4, 449, 540, 565Edge triggered, 249Efficient synthesis, 340Effort level, 401, 418Elaborate, 414Electronic Design Interchangeable Format

(EDIF), 376Embedded multiplier blocks, 380Empty and full flag, 499Empty flag, 522Encoder, 133Encoding methods, 440Encounter from Cadence, 409End-point, 433Equality operators, 28

Ethernet, 560Even or odd parity, 85Events, 567

FFabrication techniques, 406False path, 445, 480Faults, 413Feasibility study, 563FFT, 563Field Programmable Gate Array (FPGA), 369FIFO design, 234, 515FIFO design case study, 511FIFO full flag, 524FIFO memory buffer, 497, 507, 516FIFO top level instantiation, 52850% duty cycle, 308, 416Filed Programmable Device (FPD), 367Finite State Machine (FSM), 313FIR, 563First In First Out (FIFO), 511, 516, 563, 573Flash memory, 372Flip-flops, 173, 178, 249Floor planning, 409Fork –join, 35840 nanometer, 4114:1 mux, 1004:2 encoder, 1334:16 decoder, 13214 nanometer, 411Four value logic, 16FPGA, 368, 559FPGA designs, 353FPGA prototyping, 559Frequency synthesis, 380FSM, 392, 464FSM coding, 316FSM control, 498Full adder, 62, 278Full-case, 159, 275Full-custom, 404Full-custom ASICs, 403Full-subtractor, 65Functional and timing issues, 256Functional and timing proven, 563Functional correctness, 79, 203Functionality, 406Functional simulation, 5, 376Functional verification, 6Functions, 269, 286

GGated clocks, 396, 400, 401Gate level netlist, 4, 408, 427, 453

Index 599

Gate level structure, 14Gate level verification, 408GDSII, 409, 536GDSII file, 409General purpose, 564Geometric, 408Glitches, 179, 252, 254, 314Glitches or hazards, 506, 543Glitch free, 341, 342, 391Glitch free low power designs, 542Global clock buffers, 396Glue logic, 424, 455Gray codes, 503Gray counter, 200, 329, 503Gray counter FSM, 328Gray encoding, 324, 500Gray to binary, 86, 88, 500Group, 456Group_path, 460Guidelines, 241

HHalf-adder, 61Half-subtractor, 64Handshake mechanism, 498Handshaking, 497Handshaking mechanism, 568Handshaking signals, 484Hazards, 152, 181, 567Hierarchical design, 453, 459Hierarchies, 440High speed interfaces, 379High speed IOs, 564Hold, 256Hold time, 408, 427, 429Hold time violations, 508Hold violations, 429, 465

II2C, 560IC Compiler from Synopsys, 409Idle cycles, 514IEEE 1364, 6IEEE 1364-2005, 6, 8, 143IEEE 1801, 548if…else, 106if-else, 45, 98, 256, 545IIR, 563Inactive, 143Inactive queue, 144Increment, 278Incremental compilation, 459Initial, 79, 344, 346Input and output delay, 417

Input argument, 289Input Output Block (IOB), 374, 379Input register path group, 434Input string, 289Input to reg path, 433Instance, 11Instruction register and decoder logic, 569Inter assignment delays, 346Interconnect, 369Inter delay assignments, 79Interface, 406Internal generated clock, 256Internally generated clock signals, 396Intra assignment delays, 348IO blocks, 376IO high perforamnce standards, 374IO interfaces, 564IPs, 406, 560Isolation, 548Isolation cells, 541, 542, 549, 567Isolation control, 549Isolation logic, 541

JJack Kilby, 1Johnson counter, 209JTAG, 371

LLatch-based designs, 251Latches, 173, 249, 251, 341, 342Late arrival, 486Late arrival signal, 443Late arrival signal fixes, 440Latency, 397, 447, 481, 498, 536Launch flip-flop, 431Layout, 405Leakage current, 536Leakage power, 538, 541Legal converging, 484Level sensitive, 249, 251Level shifter, 541, 548, 550, 567Level synchronizer, 253, 476Level to pulse, 484Libraries, 450Library models, 542Link library, 412Linting tool, 399Load, 451Logical flattening, 459Logical operators, 27Logic analyzers, 565Logic capacity, 370Logic cells, 376

600 Index

Logic density, 370Logic duplication, 395, 440Logic partitioning, 443Longer runtime, 454Loss of correlation, 508Low power, 535Low power architecture, 535Low power ASIC designs, 547Low power aware design, 535Low power design, 535Low power management, 536LUTs, 377

MMacrocells, 376Macros, 406Map, 411Map_effort, 459Master mode, 371Master slave flip-flops, 544Maximum area, 404Maximum operating frequency, 430MCP, The, 485Mealy, 314Mealy level to pulse, 323Mealy machines, 334Mealy machine sequence detector, 337Memories, 230Metastability, 397, 399, 401, 476, 520Micro-architecture, 4, 270, 406, 439, 449, 566Micro-architecture design, 406Microprocessors, 403Minimum bus width, 545Min, max corner analysis, The, 436Min or max, 417Mix edge triggering, 260MOD-3 counter, 306Modeling levels, 567Monitor, 143, 145Moore, 314, 334Moore’s law, 1Multi-bit signals, 497Multicycle path, 445, 446, 506Multi phase clock signals, 260Multiple clock domains, 473Multiple clocks, 424Multiple clock sources, 258Multiple control signals, 486Multiple driver assignment, 168Multiple drivers, 168, 394Multiple FPGA, 565Multiple power domain, 535, 560Multiple Vth, 540Multiplex decoding, 567

Multiplexed encoding, 272Multiplexed encoding technique, 441Multiplex encoding, 272, 441Multiplexers, 95, 543Multiplier, 374, 563MUX synchronizer, 485

NNAND, 53NBA, 143NBA queue, 246Negative clock skew, 416Negative edge triggered D flip-flop, 179Nested if-else, 388Netlist, 376Nets, 458Next_state, 314Next State Logic, 316Non-blocking, 341, 342, 386Non-blocking assignments, 145, 243, 246Non-converging, 483Non-synthesizable, 167, 343, 365, 531Non-synthesizable constructs, 16, 132NOR, 49NOT, 46

OOf timing summary, 467ON duty cycle, 306One-hot encoding, 324, 331, 3911:2 decoder, 116Op-code, 269Operand, 278Operand Isolations, 540Optimization, 77, 449Optimization algorithms, 440Optimization constraints, 450Optimize, 411Optimized netlist, 413OR, 47, 270Order of non-blocking assignments, 247Oscillatory behavior, 152Output register path, 434Output to reg path, 433

PPackaging, 406Packets, 563Parallel execution, 563Parallel input parallel output, 217Parallel inputs and multiplexing logic, 270Parallelism, 568Parallel logic, 102, 161Parameter, 235

Index 601

Parameterized memory buffer, 234Parasitic capacitance, 536Parasitic (RC), 408Parentheses, 423Parity, 379Parity detectors, 85Partitioning of design, 270Path groups, 467Performance, 370Performance constraints, 406Performance improvement, 277Phase Locked Loop (PLL), 380Phase shifted signals, 260Phase shifting, 380Photo lithography, 409Physical verification, 409Pipelined design, 568Pipelined logic, 301Pipelined register, 303Pipelined stage, 258, 463Pipelining, 277, 440, 567PIPO registers, 217PLA, 368Place and route, 401, 566PLL, 560Port interfaces, 455Ports, 458Positive clock skew, 416, 431Positive edge triggered D flip-flop, 178Positive slack, 440Post synthesis verification, The, 394Power, 286, 407Power analysis, 542Power compiler, 542, 543Power constraints, 458Power consumption, 261Power density, 535Power domains, 548Power estimation, 535Power gating, 541Power management, 536, 539Power planning, 409Power rails, 548Power Shut-Off (PSO), 541Power state tables, 548Power switches, 548Pre layout STA, 408Prime time, 427Priorities, 457Priority encoders, 135Priority encoding, The, 441Priority logic, 160Procedural blocks always, 149

Processing algorithms, 566Process node, 535Processor, 569Process, temperature, voltage, 451Program and stack pointer, 569Programmable ASIC, 369Programmable interconnects, 376Programmable Logic Devices (PLD), 367Programmable Read Only Memory (PROM),

367Programmable switch, 369Propagation delay, 430, 441, 463Propagation delay of flip-flop, 430Protocol, 269, 568Prototype, 367, 559Pulse stretcher, 484Pulse synchronizers, 485

RRace around conditions, 144Race conditions, 152Random test, 565Read, 414Readability, 313Read_pointer, 520Reduction operators, 38References, 458Register balancing, 303, 440, 444, 463, 567Register duplications, 440Registered inputs, 225Registered inputs and outputs, 272Registered outputs, 225Register retiming, 567Register-to-register path, 270, 303Register-to-register timing path, 463Register Transfer Level (RTL), 4, 407Reg-to-reg path, 225, 303, 433Relational operator, 33Reorder of the blocking assignment, 244Report_constraints, 467Report_constraints_all, 468Report_timing, 460Reset deassertion, 179, 508Reset synchronizer, 508Reset trees, 251Resource allocation, 419Resource sharing, 270, 295, 395Retention, 548Retention cell, 550, 567Retention control, 550Right or left shift, 222Ring counter, 207Ripple counter, 226, 261

602 Index

Ripple counters, 396Robust verification, 552, 567Rock’s law, 2Round robin, 576RTL, 455, 547RTL design, 241, 433RTL design and verification, 8RTL or architecture tweaks, 6RTL to GDSII, 552RTL tweaks, 74

SScan insertions, 413SDC, 436, 445, 480SDC commands, 450SDF, 394Search_path, 413Second Moore’s law, 2Selection logic, 95Semiconductor, 561Sensitivity list, 71, 394Sequence detector, 334Serial data, 575Serial input serial output shift register, 243Serializer, 568Set and reset, 546Set_clock_latency, 438Set_clock_uncertainty, 438Set_dont_touch, 454Set-don’t_touch_network, 545Set_input_delay, 438Set_output_delay, 438Setup, 256Set-up time, 427, 443Setup time violation, 443Setup violation, 460Shift operator, 39, 125Shift register, 220, 378Short circuit power, 538Sign operators, 30Silicon wafer, 404Simple Programmable Logic Device (SPLD),

368Simulation, 226, 344Simulation and synthesis mismatch, 146Simulation result, 230Simulation waveform, 82Simulators, 567Single port memory, 379Single port RAM, 380Single port read write memory, 230Skew, 416, 493Slack, 428, 460Slave mode, 371

SOC, 269, 559SOC components, 568SOC designs, 353, 535SOC validation, 565Speed, 404SPI, 560SPLD, 368SRAM, 371SRAM based FPGAs, 372SRAM cells, 371SRAM memory cell, 371SRAM technology, 371SRPG, 542SRPG cell, 542STA, 154, 376Standard cell libraries, 404Standard cells, 403, 404, 536Start-point, 433State encoding, 340State machines, 424State register, 314State register logic, The, 316State retention, 541, 542State transition, 316, 331Static, 427, 576Static and dynamic power, 541Static Timing Analysis (STA), 427Storage buffers, 511Stratified event queue, 143Stray capacitance, 537Strobe, 145Structural design, 10Structured ASIC, 370Stuck at fault coverage, 566Subroutine, 286Subtraction, 278Subtractors, 64Successive reads, 513Successive writes, 513Switches, 548Switching, 297Switching activity, 538Switching threshold voltages, 540Symbol_library, 413Synchronization, 568Synchronization failure, 476Synchronized asynchronous resets, 399Synchronized reset signal, 179Synchronizers, 424Synchronous, 313Synchronous design, 193, 397, 436Synchronous reset, 179, 181, 251, 254, 399Synopsys, 543Synopsys DC, 449

Index 603

Synopsys_dc.setup, 413Synopsys Design Compiler, 407Synopsys PT, 427, 449Synthesis, 6, 315, 376, 382, 407Synthesis optimizations, 419Synthesizable constructs, 14, 16, 89, 258, 571Synthesizable design, 100Synthesizable RTL, 561Synthesized logic, 320SystemC, 565SystemVerilog, 565

TTarget library, 412Task, 286, 269Technology constraints, 406Technology library, 411Testability, 408Testbench, 82, 132, 203, 343, 365, 531, 567Test plan, 565Test vectors, 565Three procedural block always blocks, 316Threshold voltage, 540Throughput, 536, 563Tight constraints, 428Time budgeting, 251Time constructs, 16Time control, 286Time to market, 404Timing analysis, 314, 427, 453Timing analyzer, 434Timing closure, 427Timing goals, 436Timing issues, 396Timing optimization, The, 457Timing optimization commands, 458Timing or area, power, 376Timing parameters, 436Timing paths, 225, 408Timing performance, 376Timing proven IPs, 561Timing sequence, 230, 480Timing violations, 270, 408, 429, 458Toggle flip-flop, 320Toggle synchronizer, 485Top-down approach, 3Top-down compilation, 454Top-down or bottom-up, 450Top level, 424

Transactions, 567Transitions in the state diagram, 341Translate, 411Transport and inertial, 567Tri state, 60, 37920 nanometer, 411Twisted ring counter, 2092:4 decoder, 125Two-level synchronizer, 399

UUART, 560, 575Unified Power Format (UPF), 535, 547, 548Unintentional latches, 154, 164, 165Unit Under Test, 353Universal logic, 95, 96Up-counter, 194Up-down, 198USB, 560User constraints, 467

VVendor specific power formats, 547Verification, 407, 506Verification planning, 565Verilog-2005, 8Video decoders, 563Violations, 427Virtex, 377Virtual clock, 416Voltage level, 550

WWeight factor, 459, 460Working directory, 413Write command, 418Write_pointer, 520

XXilinx, 380XILINX Spartan, 377XNOR, 58XOR, 56, 270XOR logic gate, 98, 411

Z0 delays, 144

604 Index

appendix i: important verilog keywords

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