appendix b - reduction of digital logic

Appendix B - Reduction of Digital Logic

© 1999 M. Murdocca and V. Heuring

ion) of Boolean ns

anonical SOP (or POS) forms.

translates to a lower gate

uction, Karnaugh map ) reduction.



nction Circuit r the unreduced majority liminated, one AND gate has

as only two inputs instead of uced further? How do we go

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdoc

B.1 Reduction of Combinational Logic and Sequential Logic B.2 Reduction of Two-Level Expressions B.3 State Reduction

ca and V. Heuring Principles of Computer Architecture by M. Murdocca and V. Heuring

function, the inverter for C has been ebeen eliminated, and one AND gate hthree inputs. Can the function by redabout it?

B-1 Appendix B - Reductio


Principles of Computer ArchitecMiles Murdocca and Vincent Heuring

Appendix B: Reduction of DigiLogic


Chapter Contents

n of Digital Logic

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ture

tal

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B-3

Principles of Computer Architecture by M. Murdocca and V. Heuring

Reduction (SimplificatExpressio

• It is usually possible to simplify the c

• A smaller Boolean equation generally count in the target circuit.

• We cover three methods: algebraic redreduction, and tabular (Quine-McCluskey

B-4

Reduced Majority Fu• Compared with the AND-OR circuit fo



enn Diagram jority Function

represents a minterm.

a Karnaugh Map.



y Function ds to that minterm.

ap around”


majority circuit, but this one is in its minimal two-level fo

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rm:


• Cells on the outer edge of the map “wr



The Algebraic Method • Consider the majority function, F. We apply the algebrai

to reduce F to its minimal two-level form:


The Algebraic Method • This majority circuit is functionally equivalent to the prev

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c method

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ious

B-7


Karnaugh Maps: VRepresentation of Ma

• Each distinct region in the “Universe”

• This diagram can be transformed into

B-8

K-Map for Majorit• Place a “1” in each cell that correspon



pings inimal (but logically

allest groups first.



gically Adjacent


• F = BC + AC + AB

• The K-map approach yields the same minimal two-level the algebraic approach.

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form as




Adjacency Groupings for MajorFunction

• F = BC + AC + AB


Minimized AND-OR Majority Cir

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ity

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cuit

B-11


K-Map Grou• Minimal grouping is on the left, non-m

equivalent) grouping is on the right.

• To obtain minimal grouping, create sm

B-12

K-Map Corners are Lo



on’t Cares



key) Reduction


AND followed by OR. Inverters are not included in the twcount). Algebraic reduction can result in multi-level circueven fewer logic gates and fewer inputs to the logic gate

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o-level its with s.


• Tabular reduction begins by grouping minterms for which F is nonzero according to the number of 1’s in each minterm. Don’t cares are considered to be nonzero.

• The next step forms a consensus (the logical form of a cross product) between each pair of adjacent groups for all terms that differ in only one variable.



K-Maps and Don’t Cares • There can be more than one minimal grouping, as a res

cares.


3-Level Majority Circuit • K-Kap Reduction results in a reduced two-level circuit (t

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ult of don’t

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hat is,

B-15


Truth Table with D

• A truth table representation of a single function with don’t cares.

B-16

Tabular (Quine-McClus



of Choice ntial prime implicants and , producing the eligible set.



ruth Table into play for multiple hared among the functions.


function, although not necessarily minimally.

• A table of choice is used to obtain a minimal cover set.


functions, in which minterms can be s



On considère la fonction = 1 pourles mintermes

Implicantspremier

Mintermes

0000 0001 0011 0101 0110 0111 1010 1011

000‐ √ √

011‐ √ √

101‐ √ √

0‐‐1 √ √ √ √

‐‐11 √ √ √ ‐1‐1 √ √


Table of ChoiceOn élimine les don’t care

• The prime implicants form a set that completely covers the

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tous

1101 1111

√

√ √

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B-19


Reduced Table • In a reduced table of choice, the esse

the minterms they cover are removed

• F = ABC + ABC + BD + AD

B-20

Multiple Output T• The power of tabular reduction comes



or a NOT Gate



osition

A D


• The speed of a digital system is governed by:

• the propagation delay through the logic gates and • the propagation delay across interconnections. • We will look at characterizing the delay for a logic gate, a

method of reducing circuit depth using function decomposition.

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nd a




Multiple Output Table of ChoiF0(A,B,C) = ABC + BC

F1(A,B,C) = AC + AC + BC

F2(A,B,C) = B


Speed and Performance

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ce

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B-23


Propagation Delay f• (From Hamacher et. al. 1990)

B-24

MUX Decomp



g Tree



e Table


• Description of state machine M0 to be reduced.


• A reduced state table for machine M1.



OR-Gate Decomposition • Fanin affects circuit depth.


State Reduction

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B-27


Distinguishin• A next state tree for M0.

B-28

Reduced Stat



educed State



te Assignment



Sequence Detector State TransitDiagram


Sequence Detector State Tab

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ion

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le

B-31


Sequence Detector RTable

B-32

Sequence Detector Sta



ables st be applied at the inputs

ts at time t+1.



er


Sequence Detector

Circuit




Sequence Detector K-Maps • K-map

reduction of next state and output functions for sequence detector.


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B-35


Excitation T• Each table shows the settings that mu

at time t in order to change the outpu

B-36

Serial Add



dder Circuit



te Machine



Serial Adder Next-State Functio• Truth table showing next-state functions for a serial add

R, T, and J-K flip-flops. Shaded functions are used in the


J-K Flip-Flop Serial Adder Circ

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ns er for D, S- example.

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uit

B-39


D Flip-Flop Serial A

B-40

Majority Finite Sta

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duced

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nt flip-

B-43 Appendix B - Reduction of Digital Logic

Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring

Majority FSM Circuit


flops; and (b) using T flip-flops.

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Majority FSM State Table • (a) State table for majority FSM; (b) partitioning; (c) re

state table.


Majority FSM State Assignme• (a) State assignment for reduced majority FSM using D

appendix b - reduction of digital logic

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