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APPENDIX A Summary of lnstructions by Alphabetic Code INSTRUCTION Add AND logical A left shift A right shift Clear A and add Clear A and subtract Complement magnitude Copy Divide Enter index Halt and jump Halt Halt and procede Jump when Ais minus Jump when Ais non-zero Jump when A is plus Jump when Ais zero J ump and increment Unconditional jump Jump on index Jump when Q is minus Jump when Q is plus Load logical Load Q-register Load address into X Long AQ left shift Long AQ right shift Multiply No operation OR logical Q left shift Q right shift Read select CODE ADD ADL ALS ARS CLA CLS COM CPY DIV ENX HJP HLT HPR JAM JAN JAP JAZ JIX JMP JPX JQM JQP LDL LDQ LDX LLS LRS MPY NOP ORL QLS QRS RDS DESCRIPTION OF OPERATION (L) + (A)-> A; (L) unchanged (A-numeric) AND (L)-> A-numeric; (L) unchanged Shift (A); left bits lost; sign unchanged Shift (A); right bits lost; sign unchanged (L) -> A; (L) unchanged -(L)-> A; (L) unchanged Complement (A); sign unchanged Copy to or from locations specified by L (A) or (AQ) -;- (L)-> Q; remainder-> A (Address part of ENX) or index -> X Stop computer and jump to address in HJP after pressing start key Stop computer Stop computer and procede to next in- struction after pressing start key If (A) neg., go to address in JAM, other- wise to next instruction If (A) 0, go to address in JAN, other- wise to next instruction If (A) pos., go to address in JAP, other- wise to next instruction If (A) = 0, go to address in JAZ, other- wise to next instruction (X) + D -> X, go to address in JIX Go to instruction in address part of JMP If (X) > D, (X) - D -> X, go to address in JPX otherwise to next instruction If (Q) neg., go to address in JQM, other- wise to next instruction If (Q) pos., go to address in JQP, other- wise to next instruction (L)-> A-numeric; (L) unchanged (L) -> Q; (L) unchanged (Address part of L) -> X; (L) unchanged Shift (AQ); Qt -> Aas; sign Q -> sign A Shift (AQ); Aa. -> Qt; sign A-> sign Q (L) x (Q)-> A or AQ; (L) unchanged Machine takes next instruction in sequence (A-numeric) OR (L) -> A-numeric; (L) unchanged Shift (Q); left bits lost; sign unchanged Shift (Q); right bits lost; sign unchanged Select for reading component specified by L 213

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APPENDIX A

Summary of lnstructions by Alphabetic Code

INSTRUCTION

Add AND logical

A left shift A right shift Clear A and add Clear A and subtract Complement magnitude Copy Divide Enter index Halt and jump

Halt Halt and procede

Jump when Ais minus

Jump when Ais non-zero

Jump when A is plus

Jump when Ais zero

J ump and increment Unconditional jump Jump on index

Jump when Q is minus

Jump when Q is plus

Load logical Load Q-register Load address into X Long AQ left shift Long AQ right shift Multiply No operation

OR logical

Q left shift Q right shift Read select

CODE

ADD ADL

ALS ARS CLA CLS COM CPY DIV ENX HJP

HLT HPR

JAM

JAN

JAP

JAZ

JIX JMP JPX

JQM

JQP

LDL LDQ LDX LLS LRS MPY NOP

ORL

QLS QRS RDS

DESCRIPTION OF OPERATION

(L) + (A)-> A; (L) unchanged (A-numeric) AND (L)-> A-numeric; (L)

unchanged Shift (A); left bits lost; sign unchanged Shift (A); right bits lost; sign unchanged (L) -> A; (L) unchanged

-(L)-> A; (L) unchanged Complement (A); sign unchanged Copy to or from locations specified by L (A) or (AQ) -;- (L)-> Q; remainder-> A (Address part of ENX) or index -> X Stop computer and jump to address in

HJP after pressing start key Stop computer Stop computer and procede to next in­

struction after pressing start key If (A) neg., go to address in JAM, other­

wise to next instruction If (A) ~ 0, go to address in JAN, other­

wise to next instruction If (A) pos., go to address in JAP, other­

wise to next instruction If (A) = 0, go to address in JAZ, other-

wise to next instruction (X) + D -> X, go to address in JIX Go to instruction in address part of JMP If (X) > D, (X) - D -> X, go to address in

JPX otherwise to next instruction If (Q) neg., go to address in JQM, other­

wise to next instruction If (Q) pos., go to address in JQP, other-

wise to next instruction (L)-> A-numeric; (L) unchanged (L) -> Q; (L) unchanged (Address part of L) -> X; (L) unchanged Shift (AQ); Qt -> Aas; sign Q -> sign A Shift (AQ); Aa. -> Qt; sign A-> sign Q (L) x (Q)-> A or AQ; (L) unchanged Machine takes next instruction in

sequence (A-numeric) OR (L) -> A-numeric; (L)

unchanged Shift (Q); left bits lost; sign unchanged Shift (Q); right bits lost; sign unchanged Select for reading component specified

by L

213

214

Store A Store logical

Store Q Store X Storezero Subtract Write select

APPENDIX A (CONTINUED)

STA STL

STQ STX STZ SUB WRS

(A) ~ L; (A) unchanged (A-numeric) ~ L; (A-numeric)

unchanged (Q) ~ L; (Q) unchanged (X) ~ address part of L; (X) unchanged (L) replaced by zeros; sign of L plus (A)- (L) ~ A; (L) unchanged Select for writing component specified

by L

APPENDIX B

Powers of Two

2" n 2-11

1 0 1.0 2 1 0.5 4 2 0.25 8 3 0.125

16 4 0.062 5 32 5 0.031 25 64 6 0.015 625

128 7 0.007 812 5

256 8 0.003 906 25 512 9 0.001 953 125

1024 10 0.000 976 562 5 2048 11 0.000 488 281 25

4096 12 0.000 244 140 625 8192 13 0.000 122 070 312 5

16384 14 0.000 061 035 156 25 32 768 15 0.000 030 517 578 125

65536 16 0.000 015 258 789 062 5 131 072 17 0.000 007 629 394 531 25 262144 18 0.000 003 814 697 265 625 524288 19 0.000 001 907 348 632 812 5

1048 576 20 0.000 000 953 674 316 406 25 2097152 21 0.000 000 476 837 158 203 125 4194 304 22 0.000 000 238 418 579 101 562 5 8 388 608 23 0.000 000 119 209 289 550 781 25

16 777 216 24 0.000 000 059 604 644 775 390 625 33554432 25 0.000 000 029 802 322 387 695 312 5 67108 864 26 0.000 000 014 901 161 193 847 656 25

134 217 728 27 0.000 000 007 450 580 596 923 828 125

268435 456 28 0.000 000 003 725 290 298 461 914 062 5 536 870 912 29 0.000 000 001 862 645 149 230 957 031 25

1073 741824 30 0.000 000 000 931 322 574 615 478 515 625 2 147 483 648 31 0.000 000 000 465 661 287 307 739 257 812 5

4294967296 32 0.000 000 000 232 830 643 653 869 628 906 25 8 589 934 592 33 0.000 000 000 116 415 321 826 934 814 453 125

1 7 1 79 869 184 34 0.000 000 000 058 207 660 913 467 407 226 562 5 34 359 738 368 35 0.000 000 000 029 103 830 456 733 703 613 281 25

215

REFERENCES

1. A. W. Burks, H. H. Goldstine, and J. von Neumann, Preliminary Discus­sion of the Logical Design of an Electronic Computing Instrument. PRINCETON, N.J.: Institute for Advanced Study, Ist ed., June 28, 1946.

2. W. H. Ware (ed.), Soviet Computer Technology-1959. Comm. of Ass. for Comp. Mach., March 1960.

3. George Boole, Investigation of the Laws of Thought. NEw YoRK: Dover Publications, 1854, reprint in 1951.

4. D. Hilbert and W. Ackerman, Principles of Mathematical Logic. 1928 in German; reprinted in English translation. NEw YoRK: Chelsea Publish­ing Company, 1950.

5. Claude E. Shannon, A Symbolic Analysis of Relay and Switching Cir­cuits. Trans. NEw YoRK: AIEE, 1938, 57, pp. 713-723.

6. E. W. Veitch, A Chart Method for Simplifying Truth Functions. Proc. ACM Meeting, May 1952, pp. 127-133.

7. M. Karnaugh, The Map Method for Synthesis of Combinational Logic Circuits, Trans, NEw YoRK: AIEE, Nov. 1953, 72, pp. 593-599.

8. W. V. Quine, The Problem of Simplifying Truth Functions, Am. Math. Monthly, Oct. 1952, 59, No. 8, pp. 521-531.

9. D. A. Huffman, The Synthesis of Sequential Switching Circuits, PHILA­DELPHIA: Joumal of the Franktin Institute, 1954, 257, Nos. 3 and 4, pp. 161-190, and 275-303.

10. George H. Mealy, A Method for Synthesizing Sequential Circuits. NEW YoRK: Bell System Technical Joumal, September 1955, 34, pp. 1045-1079.

11. E. F. Moore, Gedanken Experiments on Sequential Machines. PRINCE­TON, N.J.: Princeton University Press, Automata Studies, 1956, pp. 129-153.

12. Morris Rubinoff, Remarks on the Design Sequential Circuits. University of Pennsylvania, The Moore School of Electrical Engineering, March 15, 1957.

13. A. M. Turing, On Computable Numbers with an Application to the Ent­scheidungs Problem. Proc. of the London Math. Soc., Ser. 2, Vol42, 1936, pp. 230-265; Correction, lbid., Vol43, 1937, pp. 544-546.

14. N. Wiener, Cybernetics, CAMBRIDGE, MAss.: The Technology Press, 1948, and reprints.

15. A. Church, The Calculi of Lambda-Conversion, PRINCETON: Princeton University Press, 1941, Annals of Mathematics Studies, No. 6.

16. A. A. Markov, Theory of Algorithms (Russian), Moscow: USSR Academy of Sciences, Steklov Mathematical Institute, 1954.

216

REFERENCES CONTINUED 217

17. S. C. Kleene, Representation of Events in Nerve Nets and Finite Auto­mata, PRINCETON: Princeton University Press, Automata Studies, edited by C. E. Shannon and J. McCarthy, 1956, pp. 3-41.

18. A. A. Liapunov, Mathematical Investigations Related to the Use of Elec­tronic Computing Machines, Mathematik USSR 2a Sorok Let 1917-57, Moscow, 1959, pp. 857-877; translated by Friedman, Comm. of Ass. for Comp. Mach., February 1960, pp. 107-118.

19. J. McCarthy, A Basis for a Mathematical Theory of Computation, Prel. Rpt., Proc. of Western Joint Comp. Conf., May 1961, pp. 225-238.

20. H. H. Goldstine and von Neumann, Planning and Coding of Problems for an Electronic Computing Instrument, PRINCETON, N.J.: Inst. for Adv. Study, 1947.

21. S. Gorn, Standardized Programming Methods and Universal Coding, Journal of the Ass. for Comp. Mach., July 1957.

22. United Aircraft Corporation, SHARE Assembler, UA SAP 1 and 2, HART­FORD, CoNN., March 1956 and following additions.

23. Edward H. Friend, Sorting an Electronic Computer Systems, Journal of the Ass. for Comp. Mach., Vol 3, July 1956.

24. R. D. Elbourn and W. H. Ware, The Evolution ofConcepts and Languages of Computing, Proc. of the IRE, May 1962, pp. 1059-1066.

25. P. Naur (ed.), et al., Report an the Algorithmic Language ALGOL 60, Comm. of the Ass. for Comp. Mach., Vol 3, May 1960, pp. 299-314; or Numer. Math. 2, 1960, pp. 106-136.

25a. P. Naur (ed.), et al., Revised Report an the Algorithmic Language AL­GOL 60, Comm. of the Ass. for Comp. Mach., Vol6, January 1963, pp. 1-17.

26. J. W. Backus, The Syntax and Semantics of the proposed International Algebraic Language of the Zurich ACM-GAMM Conference, Proc. of In­ternational Conference on Information Processing, 1959, MuNICH: Olden­bourg, 1960,pp. 125-131.

27. H. Bottenbruch, Structure and Use of ALGOL 60. Journal of the Ass. for Comp. Mach., Vol 9, No. 2, April1962, pp. 161-221.

28. H. R. Schwarz, An Introduction to ALGOL. Comm. of the Ass. for Comp. Mach., Vol. 5, No. 2, February 1962, pp. 82-95.

29. A. Newell, J. C. Shaw, and H. A. Simon, Empirical Explorations of the Logic Theory Machine: A Case Study in Heuristic. Proc. ofWestern Joint Comp. Conf., February 1957, pp. 218-239.

30. A. Newell and F. M. Tonge, An Introduction to Information Processing Language V, Comm. of the Ass. for Comp. Mach., April1960, pp. 205-211.

31. A. J. Perlis, J. W. Smith, and H. R. Van Zoeren, Interna! Translator IT, A Compiler for the 650. PrTTSBURGH, PA.: Carnegie Institute of Technol­ogy, Computation Center, June 1958.

32. Robert W. Floyd, An Algorithm for Coding Efficient Arithmetic Opera­tions, Comm. of the Ass. for Comp. Mach., January 1961, pp. 42-51.

33. H. Rutishauser, Automatische Rechenp/an-fertigung bei programge­steuerten Rechenmaschinen. ZuRICH: Mitt. f. Angew. Math. der ETH No. 3, 1952.

34. A. A. Grau, Recursive Processes and ALGOL Translation. Comm. of the Ass. for Comp. Mach., January 1961, pp. 10-15.

BIBLIOGRAPHY

Aiken, Synthesis of Electronic Computing and Control Circuits. CAMBRIDGE, MAss.: Harvard Press

Caldwell, Switching Circuits and Logical Design. NEw YoRK & LoNDON: Wiley

Eng. Res. Ass., High-Speed Computing Devices. NEw YoRK: McGraw-Hill Hamming, Numerical Methods for Scientists and Engineers. NEw YORK:

McGraw-Hill Hildebrand, Introduction to Numerical Analysis. NEw YoRK: McGraw-Hill Householder, Principles of Numerical Analysis. NEw YoRK: McGraw-Hill Keister, Ritchie, Washburn, The Design of Switching Circuits. PRINCETON,

N.J.: D. Van Nostrand Larrivee and Stibitz, Mathematics and Computers. NEw YoRK: McGraw-Hill McCracken, Digital Computer Programming, NEw YoRK: Wiley Pfister, Logical Design of Digital Computers. NEw YoRK: Wiley Halston and Wilf, Mathematical Methods for Digital Computers. NEw YoRK:

Wiley Richards, Arithmetic Operations in Digital Computers. PRINCETON, N.j.:

D. V anNostrand Scarborough, Numerical Mathematical Analysis, BALTIMORE: John Hopkins

Press Scott, Analog and Digital Computer Technology. NEw YORK: McGraw-Hill Shannon and McCarthy, Automata Studies. PRINCETON: Princeton University

Press Wilkes, Automatie Digital Computers. NEw YoRK: Wiley Handbook of Automation, Computation and Control. Vol. 2 Computersand

Data Processing, NEw YoRK: Wiley

218

INDEX

Absolute value, 30, 38 Access, 6, 7

random, 5 time, 6, 7-8

Accumulatorregister, 78, 80-82 Ackerman, W., 45, 216 Adders, 74-80, 83-85

half, 74 full, 75 serial binary, 77 parallel binary, 78 coded decimal, 85

Adder-subtracter, 83 Adding with accumulator, 80-82 Address, 111-112

absolute, 114 execution, 125 multi (two, three, four), 111-112 register, 71 single (one), 112 switch, 72 symbolic, 114

Address field, 111 Addressing, 111

direct, 117 indirect, 125

Address modification, 123; See also Indexing

Aiken,218 Algebraic language, 114 ALGOL, structure of, 181-189 Alphanumeric digits, 29 ANDgate, 49 AND operation (or conjunction), 46 Application equations, 66 Arithmetic instructions, 117 Arithmetic operations, 117 Arithmetic operator (in ALGOL), 183 Arithmetic registers, 70-72

A-register, 78, 80-82

Arithmetic registers (Cant.) Q-register, 92-93, 107 Shifting, 92-93, 1 07

Assembly program, 138 Asynchronaus computers, 13 Automatie, 177

assembly, 114 coding, 178 compiling, 178 decomposition, 203-209 execution, 127-128 listing, 199-203

Backus, J. W., 181, 217 Base (of number systems), 16 Basiccomputer elements, 49-51 Basiccomputer operations, 110 Basicprogram elements, 134 Basicprogram functions, 115 Binary arithmetic, 74-106

addition, 74-75 division, 103-106 multiplication, 88-93 subtraction, 30, 75-77

Binary choice, 3 Binary-coded-decimal (BCD), 26; See

also Codes Binary complements, 30 Binary-decimal conversion, 26 Binary digit, 18 Binary machines, 26 Binarynumber system, 16-19 Binary-octal conversion, 19 Binary point, 33 Bit, 18

parity, 28 time, 94

Boole, George, 45, 216

219

220 INDEX CONTINUED

Boolean algebra, 45 AND operation, 46 connectives in, 46-4 7 duality in, 45 NEGATION operation, 47 OR operation, 46 postulates of, 46 proof by perfect induction in, 48 theorems of, 4 7-48

Boolean functions, 4 7-48 of two and more variables, 48 simpli:fication of, 55-56

Boolean variables, 45-46 Borrow, binary, 30 Bottenbruch, H., 189, 217 Bound variable, 135 Branching, See Jump instructions Burks, A. W., 2, 216 Byte, 30

Calculus of propositions, 44 Caldwell, S., 56, 218 Call-time, 125 Catalog of instructions, 213-214 Carry, 78

initiation, 81 propagation, 78,80 signal, 81-82 speed-up, 80 time, 81

Cellar, 204 Channel, 9

basic, 10 controller, 10 general, 10

Character, 29-30 Characteristic equation, 53-54, 67 Check bit, 28 Choice symbol (in language

grammar), 182 Church, A., 132, 216 Circuits, 56-70

analysis, 59 arithmetic, 75-107 combinational, 56-58 logical, 56-70 multi-output, 59-62 sequential, 63-65 synthesis, 56, 63

Circulating registers, 78, 93-95

Circulating storage, 13 Clock pulse, 7, 130 Closed subroutine, 140 COBOL, 191 Codes, 26-29

alphanumeric, 29 basic 8-4-2-1, 26 excess-three, 27 Gray,61 instruction, 113-114 minimizing one's, 27 numeric, 28 self-complementing, 27 weighted, 26-27

Command, 111 Compiler, 192-195

design, 193 future, 209-211 major functions, 194

Complement representation of negative numbers, 30-33

Complements, binary, 30-32 in binary codes, 87-88

Computable algorithm, 195 Concatenation operation, 184 Conditionals, 115 Console, 11 Control unit, 72 Conversion of numbers, 22-26 Core memory, 5 Counter, 64

instruction, 64 odd-sequence, 65-69

Datamovement, 110 Data word, 28 Debugging, 137 Decimal complements, 30 Decimal machines, 26 Decision elements, 49

algebraic expressions for, 52 characteristics of, 49 needfor, 49

Declarator (in ALGOL), 183 Decoding, 61 Decomposition process (of

compilers), 203-209 Delimiter (in ALGOL), 183 De Morgan's theorem, 48 Diagramming (of program), 133-136

INDEX CONTINUED 221

Difference, See Subtraction Differenceequation, 77 Digitalcomputer, attributes of, 1-11

computationalrapidity of, 7-8 family tree of, 11-15 general configuration of, 8-11 large memory capacity of, 4-7 logical diagram of, 71 principle of logical

operation,3,44-45 universality, 1-3

Digitalcomputer descriptors, 11-15 asynchronous, 13 binary,26 buffered, 14 decimal, 26 dynamic,13 fixed-point, 33 floating-point, 37 parallel, 13 serial, 13 static, 13 synchronous,13 variable word length, 14

Digit multiplier, 102 Digits, alphanumeric, 29

binary, 18 numeric, 27-28

Diodes,56 Divide check, 106 Division, 103-108 Doublingcircuit, 99-100 Drum,magnetic,5, 7 Duality (in Boolean algebra), 45

Elbourn, R. D., 180, 217 Electronic gates, 56 Encoding, 60 End-aroundcarry, 32 Equivalence (Boolean

connective), 47 Error-detecting, 28 Excess-three code, 27 Exclusive OR, 80 Execution address, 125 Execution cycle, 128 Execution of instructions, 127-130 Exponent (in floative point), 37

Expressions (in ALGOL), 186 arithmetic, 186 Boolean, 187 designational, 187

Extemal memory, 5

Flip-Flop, 50 characteristic equations, 53-54 set-reset, 53 trigger, 53-54

Fixed-point number range, 33-35 Fixed storage, 135 Floating-point representation, 3 7-39

normalization in, 37 number range of, 38

Flowchart, 135-136 Floyd,RobertW., 199,217 Forbidden combinations, 26 FORTRAN, 192 Four-address instruction, 111 Fractional conversion, 25-26 Fractional number range, 33 Free variable, 135 Friend, Edward H., 167, 217 Full-adder, 75

Generalpurpose computer, 1-3; See

also Universality Generator, subprograms of IT

compiler, 196 Germanium diodes, 56 Goldstine, H. H., 2, 13, 133, 216, 217 Gom, S., 133, 217 Grau, A. A., 211, 217 Gray Code, 61-62

Half-adder, 74 Hamming,175,218 Halt-instructions, 121 Hierarchy of ALGOL

constituents, 182 Hierarchy of store, 4-5 Hilbert, D., 45, 216 Hildebrand,133,218 Hindrance concept, 56 Householder, 133,218 Huffman, D. A., 70, 216

222 INDEX CONTINUED

IBM caxd, 40-42 Identifier(in ALGOL), 184

axray, 185 Iabel, 185 procedure, 185 switch, 185 variable, 184

lmplication (Boolean connective), 47 Indexing, 123-125 Indirect addressing, 125-126 Induction variable, 134 INHIBIT gate, 49 Initialcomputer input, 39-42 Input equations for memory

elements, 53-54 Input-output devices, 5; See also

External memory Input-output instructions, 126-127 Instruction, address of, 138

address paxt of, 112 coding of, 113 execution of, 127 format of, 111 index part of, 113 general classes of, 115 modification of, 122; See also

Indexing operation paxt of, 112 repertoire of, 116

Instruction counter, 64 Instruction cycle, 128 Instruction types, 117-127

arithmetic, 117 control, 120, 122 editing, 126 indexing, 123, 124 jump, 121 Ioad, 117 logical, 120 pseudo, 139 shift, 119 store, 117

Integer conversion, 22-25 Interna! computer speed, 7-8 Interpretive code, 114 Inverse (Boolean negation), 4 7 Inversion of matrix, 163-164 IT-compiler, 195-199 Iterative calculation for squaxe

root, 14 7-150

Jiggling scan, 210 Jumpinstructions, 121

conditional, 121 onindex, 123 unconditional, 120

Karnaugh, M., 56, 216 Kleene, S. C., 132, 217

Language, classes, 180 design, 179 grammax, 180 information processing, 193 machine, 113 mechanical, 179 problem-oriented, 177 source, 177 specification, 180 symbolic, 114

Last-in-first-out principle, 204 Liapunov, A. A., 132, 217 Library (of subroutines), 184 Linking to subroutines, 140 Listing process (of

compilers), 199-203 Logical connectives, 46-4 7 Logical diagram, 70 Logical elements, 49-50 Logical instructions, 120 Logical operator (in ALGOL), 183 Looping, 134

iterative, 147-150 repetitive, 141-146, 150-172

Machine arithmetic, 77-108 additition with

accumulators, 80-82 binary addition, 77-80 binary division, 103-107 binary multiplication, 93-97 binary subtraction, 83-85 decimal (binary coded)

addition, 85-86 decimal division, 108 decimal multiplication, 98-103 decimal subtraction, 88 non-restoring division, 104 parallel, 78 serial, 77 restoring division, 104

INDEX CONTINUED 223

~achnrrechecking, 137 ~achnrrelanguage, 113 ~acro fiow chart, 136 ~agnetic drum, 5, 7 ~agnetic tape, 5-7, 9-10 ~antissa (in fioating point), 37 ~arkov,A. A., 132,216 ~athematical science of

computation, 132 ~atrixoperations, 159-164

inversion, 163-164 multiplication, 159-162

~cCarthy, J., 132, 217 ~ealy, George H., 70, 216 ~emory, 4-7, 49-51

extemal, 5-7 intemal, 5-7 needfor, 4 temporary, 49-51

~ethods, mathematical for computer, 131-133

~ed nurober conversion, 26 ~odel, mathematical, 3 ~odification of addresses, 123; See

also Indexing ~odulus, 33 ~odulus addition, 34 ~oore, E. F., 70, 216 ~ultiaddress instruction, 111-112 ~ultiplication, 88-103

binary, 93-97 decimal (BCD), 98-103 logic, 88-93 machine, 93-103

Naur, P., 181-217 NEGATION operation, 47 Negative numbers, complement

representation, 30-33 machnrre operation with, 83-85

Newell, A., 193, 217 Nine's complement, 30 Non-restoring division, 104 Normalization, 37 NOTgate, 49 Nurober codes, 26-29 Nurober systems, 16-19

binary, 16-19 decimal, 17 duo-decimal, 17

Nurober systems (Cant.) octal, 19-22 quinary, 17 temary, 17

Numerical analysis, 132-133 Numerical solution of differential

equations,169-172

Octal-binary conversion, 19 Octal nurober system, 19-22

addition in, 20 multiplicationin,21 subtraction in, 22

Odd-even check, 28 Odd-sequence counter, 65-69 One-address instruction, 112-113 One's complement, 30 Open subroutine, 140 Operating Systems, 1 78 Operation part ( of

instruction), 111-112 ORgate, 49 OR operation ( or disjunction), 46 Order, 111 Order of arithmetic operators, 189;

See also Precedence rule Output-inputdevices, 5; See also

Extemal memory

Parallel adders, 78-80 Parallel multiplication, 97 Parallel operation, 78-80, 97 Paritybit, 28; See also Checkbit Partial product, 89 Perlis, A. J ., 195, 217 Pfister,~ .• 70, 218 Positional notation (in nurober

systems), 16 Polynomial evaluation, 150-153

fiow chart for, 151 symbolic code for, 152

Princeton-type macbnrres, 13 Procedures (subroutines of

ALGOL), 185 body,185 declaration, 185 heading,185 identifier, 185 statement, 186

224 INDEX CONTINUED

Product, See Multiplication, Partial product

Production symbol (in language grammar), 182

Productofsums,56 Programming, 131-175, 177-211

arithmetic problems, 141-146 automatic, 177-211 diagramming for, 133-136 iterative processes, 14 7-149 mathematical methods

for, 131-133 matrix operations, 159-164 numerical solution of differential

equations,169-172 polynomial evaluation, 150-153 principles of, 133-141 rocket trajectory, 172-175 searching and sorting, 165-169 solution of simultaneaus linear

equations,153-158 writing the code for, 136-141

Propositions, calculus of, 44 Pseudocode, 205 Pseudoinstruction, 139 PSYCO, 211 Punched card, 42 Push-down list, 204

Quine, W. V., 56, 216 Quintupling circuit, 101-102 Q-register, 92-93, 107 Quotient, See Division

Radix, 16 Ralston, 175, 218 Random access, 5 Real time operation, 11 Relays, 56 Register, accumulator, 78, 80-82

address, 71 arithmetic, 71 index, 123-125 instruction, 71 intermediate storage, 71, 78 Q-register, 92-93, 107 shifting, 92-93, 107 storage address, 71

Relational operator (in ALGOL), 183 Remainder, 107

Repertoire (of instructions), 116 Replication, 115 Reset-set flip-flop, 53 Restoring division, 104 Richards,108,218 Rocket trajectory, 172-175 Routine,114,136,194

assembly, 114 closed sub-, 140 compiling, 194 interpreter, 114 open-sub-, 140 sub-, 136 translating, 194

Rubinoff, Morris, 70, 216 Runge-Kuttaintegration, 169-172 Rutishauser, H., 204, 217

Scale factoring, 35-37 Scarborough,133,218 Scanning process, 203

left-to-right, 204 right-to-left, 204

Schwarz, H. R., 189-217 Self-complementing codes, 27 Separator(in ALGOL), 183 Sequencing of program, 134-135; See

also Jump instructions Sequential circuits, 63 Sequential operator (in ALGOL), 183 Serial addition, 77 Serial multiplication, 93-95 Set-Reset flip-flop, 53 Shannon, Claude E., 45-216 Shift counter, 72 Shift instructions, 119 Shiftingregisters, 92-93, 107 Sign digit, 33-34 Simple arithmetic problern in

ALGOL, 189-190 Simplification of Boolean

functions, 55-56 Single address instructions, 112 Single-error detection, 28; See also

Checkbit or Paritybit SOAP, 197 Sourcelanguage, 177 Source pro gram, 177 Space bit, 94 Specification (for language), 180

INDEX CONTINUED 225

Specificator (in ALGOL), 183 Squareroot, 147-149 Stack,204 Statements (instructions of

ALGOL), 187 assignment, 187 conditional, 188 for statement, 187 go to statement, 187 procedure, 186

Store, See Memory Store instructions, 117 Structure of ALGOL, 181-189 Subroutine, 136

closed, 140 library of, 136 linking to, 140 open, 140

Subscripted variables (in ALGOL), 185

Subtraction, binary, logic, 75-77 Machine operation, 83-85

Sum, See Adders Sum of products, 56 Summation procedure in

ALGOL, 191 Switch (address), 72 Switch declaration (in ALGOL), 189 Switch as declarator (in

ALGOL), 183 Switching algebra, See Boolean

algebra Symbolic instruction, 138 Symboliclocation, 13~ Symbolic logic, 45 Synchronouscomputer, 13 Syntactical states, 211 Syntax rules for

ALGOL, 181-187,206

Table of combinations, See Truth table

Tape, See Magnetic tape Tautology(Boolean connective), 47 Temporary storage elements

(enabling elements), 49 algebraic expressions for, 53-54 characteristics of, 50 needfor, 49

Ten's complement, 30 Three-address instructions, 112 Timing, 57, 93 Toggle switch, 50 Transfer instructions, See Jump

instructions Transmission concept, 56 Trigger flip-flop, 53-54 Truncation error, 147 Truth table for, doubling, 99

circuit with even one's output, 57 flip-flops, 53 full adder, 75 full subtractor, 76 gates, 52 quintupling, 101 trigger circuits, 67

Turing,A. M., 131,216 Two address instructions, 112 Two's complement, 30 Type declaration (in

ALGOL), 183-189

Union operation, 184 United Aircraft Corp., 139-217 Universal Turing machine, 131 Use of if-statement in ALGOL, 188 Unweighted codes, 27

excess-three code, 27

Variable storage, 135 Variable word length computers, 14 Veitch,E. W., 56,216 Von Neumann, J.,

2,13,133,215,217

Ware, W. H., 14, 180, 216, 217 Weighted codes, 26-27

basic BCD weight 8421, 26 minimizing 1's weight 7421, 27 self-complementing weight

2421,27 Wiener, N., 132, 216 Word (data and instruction), 28, 111 Word length, 111-113