answers - ies masterfor switches a and b, at a time if only one switch is on, the light will be on....

1. (a)

2. (c)

3. (a)

4. (b)

5. (c)

6. (b)

7. (a)

8. (a)

9. (b)

10. (a)

11. (b)

12. (a)

13. (d)

14. (a)

15. (a)

16. (b)

17. (d)

18. (d)

19. (a)

20. (d)

21. (a)

22. (c)

ESE-2019 PRELIMS TEST SERIESDate: 11th November, 2018

23. (d)

24. (b)

25. (c)

26. (c)

27. (d)

28. (a)

29. (c)

30. (c)

31. (b)

32. (d)

33. (b)

34. (c)

35. (c)

36. (b)

37. (c)

38. (a)

39. (d)

40. (c)

41. (c)

42. (c)

43. (d)

44. (d)

45. (c)

46. (c)

47. (d)

48. (c)

49. (b)

50. (c)

51. (c)

52. (a)

53. (c)

54. (d)

55. (d)

56. (b)

57. (b)

58. (b)

59. (a)

60. (b)

61. (b)

62. (b)

63. (d)

64. (c)

65. (b)

66. (c)

ANSWERS

67. (b)

68. (a)

69. (d)

70. (c)

71. (d)

72. (b)

73. (c)

74. (a)

75. (b)

76. (b)

77. (a)

78. (b)

79. (b)

80. (d)

81. (d)

82. (c)

83. (d)

84. (b)

85. (a)

86. (d)

87. (d)

88. (c)

89. (a)

90. (c)

91. (d)

92. (b)

93. (c)

94. (a)

95. (a)

96. (b)

97. (a)

98. (c)

99. (c)

100. (a)

101. (a)

102. (a)

103. (b)

104. (b)

105. (d)

106. (a)

107. (d)

108. (a)

109. (b)

110. (c)

111. (b)

112. (a)

113. (d)

114. (a)

115. (c)

116. (c)

117. (a)

118. (b)

119. (c)

120. (b)

121. (d)

122. (d)

123. (c)

124. (b)

125. (a)

126. (c)

127. (c)

128. (a)

129. (c)

130. (a)

131. (c)

132. (b)

133. (d)

134. (a)

135. (b)

136. (a)

137. (c)

138. (c)

139. (d)

140. (a)

141. (a)

142. (c)

143. (c)

144. (c)

145. (a)

146. (a)

147. (a)

148. (a)

149. (a)

150. (c)

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(2)

1. (a)

TTL Connection (NAND gate)

AB Q1

Q2

16K5K

1K

Q3

Q4

O/P

Phase splitter Totem pole

V = 5VCC

130

Input transistor reduces propagationdelay : When A = B = 1, Q1 is in cutoff state

When any of A and B is low, Q1 is in activemode, Ic1 (collector current of Q1) quicklyremoves charges stored in Q2 during itsprevious saturation state. Thus storagecharge delay decreases.

2. (c)

Current hogging is a condition that occurs indirect coupled transistor logic family. Thiscondition is marked by large amount of currentflow through one of the many parallel circuitsdue to its low resistance. It can be understandby below example.

Load

VCC

Q3

NAND gate

Q4

VCC

NAND gate

A

B

NOR gate

Q1

Q2

IL

VCC

V0V´0

If A = B = 0, V0 = 1Ideally Q3 and Q4 have same VBE but practicallynot.

Let 3 4BE BEV 0.69V, V 0.7V

Q3 will be ON first due to low value of VBE andsaturates.Since (VCE)sat is very low, so upper NAND gateof load will provide low resistance path andhence a large fraction of load current flows

Rawat\TEST SERIES 2019_SANJAY\EC\ESE\EC-Test-7 (4 Nov 2018)

through it.Q4 will not get enough base current to be turn-ON.This situation is called current hogging.

3. (a)

The expression inside the parentheses must beevaluated before all the operations The nextoperation that holds precedence is thecomplement, then follows AND, and finally theOR.

4. (b)

F = A B . AB

By distributive law

F = A AB B AB

By DeMorgans theorem, AB A B

F = A A B B A B

or F = AA AB BA BB

= 0 AB AB 0

or F = AB AB A B

It can also be solved by making truth table.

A B A B AB AB A B AB

0 0 0 0 1 0

0 1 1 0 1 1

1 0 1 0 1 1

1 1 1 1 0 0

A B

5. (c)

For switches A and B, at a time if only oneswitch is ON, the light will be ON.Therefore,

A B Output X

0 0 0

0 1 1

1 0 1

1 1 0

X = AB AB A B

6. (b)

AND using NOR

X = AB AB A B

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[EC], ESE-2019 PRELIMS TEST SERIES PAPER-II (TEST-08) (3)

A

B

A

B

A B AB

7. (a)

f = A BC AB ABC

By Demorgan ’s theorem

A BC = A BC

f = ABC AB ABC

= ABC AB ABC

= AABBC AABC

= 0 + 0f = 0

8. (a)

f = A B A C AB AC

= AA AC AB BC AB AC

= A C A A AB BC AB

= A C 1 AB BC

[ A A 1 and by redundantliteral rule AB BC BA BC BA ]

f = A C AB BC

= A AB C BC

= A A A B C 1 B

f = A B C

9. (b)

M11

1011Minterm is ABCD

Since 11 11m M

M11 = ABCD

= A B C D

[By DeMorgan’s theorem]

10. (a)

I/P

delay of NOT gate

I/P

O/P

Due to NOT gate, a slight delay (in ns) isintroduced in the output from the NOT gate.Since AND gate output is HIGH when bothinputs are HIGH, so output will be pulseduring positive transition of input as shownabove.

11. (b)

For S-R flip-flop

n 1Q = S RQ

These equations can be verified by truth tables.For example, for D-flip flop

n n 1D Q Q0 0 00 1 01 0 11 1 1

n 1Q D

12. (a)

For 6 bit DAC, the number of steps = 2N – 1 = 26

– 1 = 63.As step size is 50 mV then full scale output will be

63×50 mV = 3.15V.Percentage resolution

R = 50mV 1100 1003.15 63

= 1.587%13. (d)

Since, NAND and NOR are universal gates, anytype of gate can be designed using these gatesonly.

AND gate : X AB AB AB

AB AB

OR Gate : X A B A B AB

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(4)

A

B

A

B

A B A B

NOT gate

A A

Similarly, using NOR gate only, AND, OR andNOT gate can be obtained.

14. (a)

As 00000001 is equivalent to 1, so step size is 0.05V.

00101010 7 6 5 4

3 2 1 00 2 0 2 1 2 0 2

1 2 0 2 1 2 0 2

5 32 2 2 32 8 2 42 i.e. 42 steps

Therefore, 00101010 corresponds to42 × 0.05 = 2.10 V.

15. (a)

f = ABEF BAEF ABEF

= AB EF EF ABEF

as EF EF = 1

= AB ABEF

Now by distributive property

f = AB AB AB EF

= AB EF as AB AB 116. (b)

SRAM (Static RAM) uses internal latches tostore binary information. DRAM (DynamicRAM)- Information is stored in the form ofelectric charges on capacitor (MOS transistors).ROM or PROM Information is stored in theform of intact or blown fuses.

17. (d)

RTL digital logic family.Features :

1. Requires minimum number of transistors2. First digital integrated circuits used RTL.3. Based on saturated logic (saturation, cutoff).4. It uses CE configuration of transistor.

Disadvantages :1. Slow speed i.e. high propagation delay2. Low fan in and fanout (3)3. Poor noise immunity or low noise margin.4. Expensive as fabrication of resistance an

IC is costly affair.5. Speed < 4 MHz.

18. (d)

By truth table.

1 2 3A B Q Q Q X

0 0 OFF OFF ON 0

0 1 OFF ON OFF 1

1 0 ON OFF OFF 1

1 1 ON ON OFF 1

X A B

19. (a)

By truth table.

2 3 0

0

A B Q Q V

0 0 OFF OFF 1

V AB0 1 OFF ON 1

1 0 ON OFF 1

1 1 ON ON 0

Note that Q1 is always ON and works as aresistance ( 100K)When any of the Q2 and Q3 are ON they canbe replaced by a resistance of 1K .

When any of the input is low, 0 CCV V High

When both inputs are high, 2Q and 3Q areON, then

VCC = 5V

100 K

1 K

V0

1 K

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0V = 2 5 0V

102

NMOS :When Vinput > Vthreshold ONVinput < VThreshold OFFSymbol :

or

20. (d)

Consider the circuit for TTL NAND gate.

AB Q1

Q2

16K5K

1K

Q3

Q4

O/P

Phase splitter

Totem pole

V = 5VCC

130

D

I/P Stage

The Q3 and Q4 are never ON together.Truth Table:

1 2 3 4A B Q Q Q Q X

0 0 ON OFF ON OFF 1

0 1 ON OFF ON OFF 1

1 0 ON OFF ON OFF 1

1 1 OFF ON OFF ON 0

Phase splitting is provided by transistor Q2voltage regulation is provide by outputcapacitor.

21. (a)From given Ckt

Output at 160KW 16kHz

10

Output at 16Kx 1kHz16

Output 1Ky 40Hz25

Output at 40Z 5Hz8

22. (c)From figure we can see it is a 3-bit Johnsonring counter and it requires (2n = 2 × 3 = 6states) to reach its initial.Method (2) :Solving by each clock pulse.

0 1 2Q Q Q1 1 0 initial value

Clock1 1 1 1Clock 2 0 1 1Clock3 0 0 1Clock 4 0 0 0Clock5 1 0 0Clock 6 1 1 0

23. (d)The circuit is a –ve edge triggered clock ripplecounter and it is a Down counter the clockpulsesare shown below.

1 2 3 4 5 6 7 8

0

0

0

1

1

1

0

1

1

1

0

1

0

0

1

1

1

0

0

1

0

1

0

0

0

0

0

For x = 0 0Q is connected to clock of TT1 Flip-

flop 1Q is connected to clock of TT2 Flip-flop.Hence Down counter.For x = 1 Q0 is connected to clock of T1 Flip-flop. Q1 is connected to clock of T2 flip-flophence Up counter.

24. (b)

I0I1

I16

o/p16×1MUX

Mode 16Counter

4 data select lines

From the figure we can see that Mod 16 willhave 16 outputs. For each output of the Mod-

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16 counter one data input is selected.

25. (c)We know for R-2R DAC output voltage.

V0 =n 1

ref fin

i 1

V R2 bi2 R

For Rf = R = 1We get

V0 =n 1

ref iin

i 1

V 2 b2

= 3 2 1 0

4 4 4 40 2 1 2 0 2 1 25

2 2 2 2

=0 1 0 15

16 4 8 16

=1 154 16

=55

16

=2516

= 1.5625

26. (c)

We know resolution = reffn

V2

= 652

= 0.0156

% resolution= refn

V 1002

= 0.0156 × 100 =

1.56%

27. (d)It requires large no. of comparators.

28. (a)Both are correctAs the input is analog signal it is approximatedby a step in a sample and hold Ckt at the inputside.

29. (c)

30. (c)Serial in serial out shift register - (2n – 1)serial in parallel out shift register - nParallel in serial out shift register - (n – 1)Parallel in parallel out shift register - no clockpulse required.

31. (b)A D-Flip-flop changes its state at the positiveedge triggered part of the clock pulse where asthe D-latch will change its state the leveltriggered part of the clockpulse and also remainsoff once the clock pulse is removed.

32. (d)Without solving we can say that it is a Johnsoncounter as inverted output is connected to inputof flip-flop.

Initial Value

By Solving

Initial Value

Clock 012345678

Q 011110000

R 001111000

S 000111100

T 000011110

Y=QT 100000001

Serial in = T 111100001

As it under goes 2n states = 2 × 4 = 8 states. Itis johnson ring counter.

33. (b)Given i/p is 0000 0001 = 0.05i.e. 1 step = 0.05 V

11001010 = 7 6 3 12 2 2 2

= 128 + 64 + 8 + 2= 138 + 64= 202 steps

o/p voltage = 202 × 0.05 = 10.10 V

34. (c)

• When switch is open, corresponding input will

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be high.• When switch is closed, corresponding input will

be low.For option (c)

1 2S S A

1 1 0

Then, S1S2 = 1.1 = 1S2.A = 1.0 = 0

Y = 1 2 2 1 0 1 0S S S A

35. (c)

1 1 1

1 1 1

1 1

CD CD CDCD

AB

AB

AB

AB

Y = AC BC AD

36. (b)D can be written as

D = AB ABoutput, f can be written as

f = D.0 D.C DC

So, f = AB AB C

= ABC ABC

37. (c)

C = A B and D = A B

This is the expression of half subtractor.

38. (a)To reset all the flip-flopsQ1 = 1, Q2 = 0, Q3 = 1

(101)2 = (5)10

The given circuit is a Mod-5 counter becauseafter the counter state is 101, the counter resetsand starts counting again from 000.

39. (d)The above flip-flop indicate a trailing edgetriggered JK flip-flip.

40. (c)The ring counter utilizes one flip-flop for eachstate in its sequence. So, for modulus-12 ringcounter i.e. for 12 different output state it needs12 flip-flops.

41. (c)In a Johnson counter, the complement of theoutput of the last flip-flop is connected back tothe input of the first flip-flop.

CLKQ0 Q1 Q2 Q3

0 1 1 1CLK5

0 0 1 16

i.e. 0011

42. (c)• A ripple counter counts in a straight binary

sequence. So n FFs will have 2n outputconditions.

• Modulus or, Mod of a counter is the totalnumber of states through which the countercan progress.

• For ripple counter, Mode-N = 2n

i.e. 16 = 2n

n = 4• But for ring counter, number of different

states is equal to number of Flip-flopsMode-N = n = 16

Where, n is the number of FFs required formode-N counter.

43. (d)Sequence of conversion time :Flash type < SAR Type < Dual-slope type

44. (d)For EN = 0 (Chip of MUX is inactive)S0S1 = 11, D = 0, but there is no output i.e. theo/p is a high input impedance state i.e. (0000)but as these bubbled outputs then it should be(1111).

45. (c)Given Ckt is a Adder

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by adding the bits

3 2 1 0A A A A1 0 0 1

3 2 1 0B B B B1 1 1 0

We get

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

1001 A A A A1110 B B B B

C 1 0111Y Y Y Y

C Y Y Y Y 10111

46. (c)By solving the states from CLK diagram

Initial Valueunused states

Initial Value

Initial Value

Clk 01234567

Q10001000

0 Q11000100

1 Q11100010

2 Q01110001

3

3714

Unused states

1

2

4

8

Hence, Mod 4 counter

47. (d)From the given circuit diagramwhenever Z = 0 Mux gets enabledZ = 1 Mux gets disabled.

1 0

2

0

2

0

y zx y z S S F x,y,z0 0 0 1 0 I 00 1 0 0 0 I 01 0 0 1 0 I 01 1 0 0 0 I 1 x,y,z

48. (c)Drawing the truth table for 4 × 1 MUX.

x y F0 0 10 1 01 0 01 1 1

F(x, y) = m 0,3

49. (b)

+

–

I

V1 RinV2

I

vo

For virtual ground

V1 = V2

I = 0

For I to be zero

Rin should be .

50. (c)In both M1 and M2, Drain and Source areshorted.

VGS= VDS

VDS > VGS – VT Hence both in saturation.

51. (c)

Kn = P oxC W2 L

Kn =

6300 100 10 22 1

Kn = 30 mA/V2.

52. (a)

For the given phase shift oscillator, frequencyof oscillation is given by

fc = 1

3 2 RC

R = 3 –5

1(2 )( 3) 10 10

R =100 50

2 3 3

53. (c)

According to barkhausen criteria

oT(j ) = –1

oT(j ) = A o( j ) 0( j )

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A o( j ) 0( j ) = – 1

04 60º ( j ) = 180º

0( j ) = 0.25 120º .

54. (d)

Stability factor is given by :

S =B

C

1I1–I

IB =

CC BEV V (on)1300 k

IB =

CC BEV V (on)1300 k 1300 k

Here IB is independent of IC

B

C

II

= 0

S =

11– (0)

= 1

= 101.

55. (d)

Considering hybrid parameter conversion

hfc = – (1 + hfe)

given hfe = 199.

hfc = – (1 + 199)

= – 200.

56. (b)

IBQ =CC BE

B

V V (on)R

IBQ = 3

24 0.7700 10

= 33.286 A .

=3

C

B

I 2 10I 33.286

60.

57. (b)

VREF = 5V, 1R 1K , 2R 2K ,

Switching voltage

VS =

1REF

1 2

RV

R R

VS =

1 (5) 5/3 V.2 1

58. (b)

How pass RC filter

Vout

C

RV in

Half power frequency is 3dB cutoff frequencygiven by

f =1

2 RC

10 × 103 = 4

12 10 C

C =

–8102

= 1.59 nF.

59. (a)

Equivalent model for the zener diode can bedrawn as :

rz

Vzo

I2

VzZener voltage

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(10)

Given for = IZ = 28 mA

VZ = 9.1V.

Using kVL

VZ = VZO + IZ rZ

9.1 = VZO + 28 × 10–3 × 5

[ given IZ = 28 mA, Zr 5 ]

VZO = 9.1 – (0.028) (5)

= 8.96 V

VZ at IZ = 10 mA

VZ = VZO + IZ rZ

= 8.96 + (10) × 10–3 × 5

= 8.96 + 0.05

= 9.01 V

VZ at IZ= 100 mA

VZ = VZO + IZ rZ

= 8.96 + (100) × (10–3) × (5)

= 8.96 + 0.5

= 9.46 V.

60. (b)

–+5k

10k

10V

RS

iz

+

–

Vx +–

For zener diode to operate in break down region.

VX > 5V

VX =s

105

10 R

s

105 5

10 R

s

10 15 R

Rs 5k .

61. (b)

+

–

VEC2

IoI =1 mAref

V = 10VCC

+

–VEB+

–

VEC1

IC1 IC2

As VEB1 = VEB2

IB1 = IB2

As base current neglected

IC1 = Iref

= 1 mA

IC1 = 1B1I …(i)

IC2 = 2 B2I …(ii)

dividing (i) and (ii)

C1 1

C2 2

II

IC2 = 2

C11

I

IC2 = 1

C11

2 I

IC2 = (2) (I) = 2mA

62. (b)

VGS = –1V

VP = –2V

IDSS = 5mA

ID = 2

GSDSS

P

VI 1V

= 21(5) 1

2

= 21(5) 1

2

= 54

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ID = 1.25 mA

63. (d)

VG = 0

VD = 5

VGS = 0 – VS = –VS

VDS = 5 – VS = 5 – VS

Clearly VDS > VGS – VT

Hence in saturation

ID = IQ = Kn (VGS – VT)2

(1) = (VGS – VT)2

(–VS – 1)2 = 1

–VS – 1 = ±1

VS = –2, 0V

VGS > |VT| hence

VS = –2

VGS = 0 – (–2) = 2V

VDS = VD – VS = 5 – (–2)

= 7 V

64. (c)

VGS = VDD – 0

= 2V

Assuming in saturation

ID = kn (VGS – VT) 2

ID = (0.1) (2 – 1)2

= 0.1 mA

VDS = VDD – IDRD

= 2 – (0.1) (2)

= 2 – 0.2

VDS = 1.8 V

VDS VGS – VT

Hence our assumption of considering insaturation is correct.

65. (b)

nk = µn cox

= n ox

ox

( )t

= 4 12

10(500 10 ) 8.85 10 3.9

100 10

= 5 × 8.85 × 3.9 × 10–6

= 172.57 µA/V2

66. (c)

VGS – VTN = 2 – 1 = 1V, VDS = 0.1 V (given)

VGS – VTN > VDS

transistor is in linear region.

id = kn [2(VGS – VT) VDS – VDS2]

id = 2nGS T DS DS

k W 2 V V v v2 L

id = 6

280 10 10 2 2 1 0.1 0.12 1

id = 6800 10 0.2 0.01

2

id = 6800 0.19 10 76 A

2

67. (b)

Ideal OP Amp has following characeristics

1. Infinite input impedance

2. Infinite gain for the differential input signal.

3. Zero gain for the common-mode outputsignal.

4. Zero output impedance

5. Infinite Bandwidth.

6. Infinite input impedance.

68. (a)

Positive feedback can’t be used in voltagefollower circuit as it will saturate the output toits extreme value.

option (b) and (d) are not correct.

vo–

+–

vs

+

v1

from circuit v0 = v1

andv1 = vs [virtual ground]

vo = vs

Hence voltage follower.

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(12)

option c

vo–

+–

vs

+

R

Rv1

I

v1 = 0

I = svR

vout = svIR R

R

vo = – vs [not correct]

69. (d)

Here OP amp is in +ve feedback so output willbe dependent only on v in across it +ve & –veterminal.

v2

–+v1

v1 = 2V, v2 = 0

v in,op amp = 2V

As gain is for ideal op-amp it will takemaximum possible +ve value of output i.e. 15V.

70. (c)

Circuit diagram is

–+

iinio

RL

R1 R2

io

iin

+ –

0V+

–

v1

I1

v1 = –iin R1

I1 = 1 in 1

2 2

0 v i RR R

using KCL at v1 node

io + I1 + iin = 0

io + iin + 1

in2

R iR

= 0

1o in

2

Ri i 1R

as the output current is independent of R2,output impedence is infinite.

71. (d)

v1 –

2mA+

3k

+–

+ 5V–

vo0V

I

R

v1 = 5V

vo = v1 – IR

= 5 – (2) (3)

= 5 – 6 = –1V

72. (b)RC coupling provides excellent frequencyresponse. Thus, there is minimum possible non-linear distortion. P 3Inductor (L) used in inductive coupling, appearsto be short-circuited for dc currents and thusthere is hardly any dc drop across inductor. Thuslow collector supply voltage can be used ininductive coupling. Q 4Transformer coupling prov ides excellentimpedance matching and High voltage gain. R 1Direct coupling has outstanding ability to amplifyvery low frequency signals (including dc signals). S 2

73. (c)Small-signal equivalent of the JFET amplifiercircuit.

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rd v0V vGS = ig Vm GS

+ +

_ _

vi

S

G

+

50 k 50 k

D

Output voltage, V0

= m GS dg V r 50k 50k

= m ig v 10k 25k

= i502m k v7

= – 14.28 v i

Voltage gain, vA = 0

i

v 14.28v

74. (a)D.C analysis:

20V

2k400k

V =0.7VSE

+

–

IB =20 0.7400 k

=19.3400

mA = 48.25 µA

IC = BI 125 48.25 A

= 6.03 mADynamic Base resistance,

r =T

B

V 25mVI 48.25µA

= 0.52 K 0.5 K

A.C analysis: Small-signal equivalent of the givenamplifier circuit

v0

ib

+ +

_ _vi 2 kZi

0.5 k400 k

ib

Input impedance, Zi = 400k 0.5k

= 0.5 kTo find Z0: Make v i = 0

i = 0b

400 K 2 Kib

V0

Z0

+

–

Here ib = 0 and thus, ib = 0

Output impedance, Z0 = 2 k

75. (b)Small signal equivalent of the given amplifiercircuit is drawn as

vi

+

–90M

G

VGS

+

–10M

gmVGS

id1k

50k 10k v0

+

–

id

vi

+

–90m

G

VGS

+

–10m

1k

10kv0

+

–

–+

S

50k

VGS

id

µ = g × 50km

1

Apply KVL in loop ‘1’,µVGS – id (50k + 1k + 10k) = 0

id = GsV61k

sv

1k = i sv v61k

vs = i100 v61

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and id = si

v 100 v1k 61k

v0 = d i100i 10k v 10k61k

= i1000 v61

A.C. voltage gain,

Av = i1000 v 16.461

76. (b)

For n – cascaded (interacting) stages, overall *Hf

is calculated from

n

2*H H

1 121 f f

* 1 nH Hf f 2 1

Similarly *Lf can be calculated from

n

2*L L

1 121 f f

* 1 nL Lf f 2 1

For non-interacting n-cascaded stages, overallfH is given by

H

1f = 2 2 2

1 2 n

1 1 11.1f f f

77. (a)

Plot of common-emitter short circuit current gain(hfe) versus frequency:

0 3dB

f fT

f

0 2

Beta cut-off frequency is the frequency at whichthe current gain reduces to 1/ 2 of its low

frequency value. It is given by 1f

2 C C r

(statement ‘1’ is true)Unity-gain bandwidth (fT) is the frequency atwhich fe drops to unity. It is given by

0

T 0µ

f f2 C C r

= m

µ

g2 C C

0 mg r

(Statement ‘2’ is true)

Relation between Alpha cut-off frequency

f and Beta cut-off frequency f is

0f 1 f (Statement ‘3’ is false)

78. (b)Frequency response of a BJT amplifier is shownbelow:

Avo

lowbandband 3dB

High frequency band

fLfH

|V /v |0 i

Gain in the low frequency band falls off due tothe presence of coupling capacitors and Bypasscapacitor.Gain in the high frequency band falls off due toparasitic capacitances of the BJT.

79. (b)Common-collector amplifier is also known asemitter follower because its voltage gain is closeto unity. Thus, the emitter follows the input signal.(Statement ‘1’ is true)The input impedance of emitter follower is veryhigh (hundreds of ki lo-ohms) and outputresistance is very low (tens of ohms)

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Thus, the common collector circuit is used as avoltage buffer, which performs the function ofresistance transformation (from high resistanceto low resistance) over a wide range offrequencies, with voltage gain close to unity.(Statement ‘Z’ is false and statement ‘Z’ is true).

80. (d)

The circuit diagram of a cascode amplifier isshown below:

VCC

R5

vi

v0

R1

R2

R3

R4 R6

VCC

CC

It has a common emitter input stage followed bya common base output stage. (Statement ‘1’ istrue)

It has very high input impedance. (Statement ‘2’is true)

It has a low voltage gain (same as that of CEamplifier) to ensure that input Miller capacitanceis at a minimum, with the CB stage providing agood high frequency operation. (Statement ‘3’ istrue)

81. (d)

Miller’s Theorem:

1 2

1zz

1 K

2

zz 11k

1 2

Similarly, for given circuit,

Z' = 1

j C and K = – 99

Thus, Z1 = 1

j C 1 K and 21Z

1j C 1K

1C C 1 K 10 F 1 99 1mF

and C2 = 1 1C 1 10 F 1K 99

= 10.1 µF

82. (c)

Use of negative feedback in amplifiers leads to(i) Reduction in frequency distortion. (Statement

‘1’ is false)(ii) Reduction in non-linear distortion and noise.


(iii) Gain reduces by a factor of 1 A and

bandwidth increases. (Statement ‘3’ is true)

83. (d)

Gain with feedback, fAA

1 A

Differentiating above equation with respect to A,we get

fAA

= 2 21 A 1

1 A 1 A 1 A

f2

f f

A A 1 AA A A1 A

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f

f

AA

=1 A

1 A A

f1A

1 A

=1 10%11 1500

25

0.167%

84. (b)Voltage sampling decreases output resistanceand current sampling increases output resistance.Series mixing increases input resistance andshunt mixing decreases input resistance.

Voltage-series feedback ifR increases and

ofR decreases

Voltage-shunt feedback ifR and ofR decreases

Current-series feedback ifR and ofR increases

Current-shunt feedback ifR and ofR increases.

85. (a)

Lower cut-off frequency with feedback, fLf

fLf = Lf1 A =

2kHz1 90 0.1

= 0.2 kHz= 5000 kHz

Higher cut-off frequency with feedback, fHf

FHf = fH 1 A

= 500 k × (1+ 90 × 0.1)= 5000 kHz

Bandwidth of the feedback amplifier

= Hf Lff f

= (5000 – 0.2) kHz= 4999.8 kHz

86. (d)

Input and output impedances of passive filtersare both a problem, specially below Radiofrequency. Its input impedance is low, that loadsthe source, and it varies with the frequency. Theoutput impedance is relatively high, whichrestricts the load impedance that the passivefilter can drive. (Statement ‘1’ and ‘2’ are true)

There is no isolation between the load impedanceand the passive filter. (Statement ‘3’ is true)Passive filters use passive components such asresistors, capacitors and inductors. In the R–Frange, it works quite well, but with the lowerfrequencies,inductors create problems. A Finductors are physically larger and heavier, thusexpensive (Statement ‘4’ is true)

87. (d)

Butterworth filter: It is also called as “maximally flat” or “flat-

flat” filter. It has flat passband and flatstopband.

This filter approximates the ideal filter wellin the passband.

It has characteristics somewhere betweenthose of Chebyshev and Bessel filters

It has moderate roll-off and slightly non-linearphase response.

Chebyshev Filter It has a ripple passband but a flat stopband.

It is also called as Equiripple filter.

It gives a sharper cut-off than Butterworthfilter in the passband.

It is used where sharp roll-off is required.

Bessel Filter It provides ideal phase characteristic with an

approximately linear phase response uptocut-off frequency.

It has the best stopband response whencompared to Butterworth and Chebyshevfilter. Its cut-off characteristics is not verysharp.

Elliptic Filter It has a ripple passband as well as ripple

stopband.

It has the sharpest roll-off of all filters in thetransition region.

88. (c)P. The circuit shown is a first-order Low-passfilter. The high cut-off frequency, (fH) is given by

fH = 1 7.96 kHz

2 RC

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Q. The circuit given is a second-order Low-passfilter and its high cut-off frequency is given by

fH = 1 1kHz

2 RCR C

R.The circuit shown is a first order high-passfilter and its low cut-off frequency is given by

fL = 1 7.96 kHz

2 RC

S.The circuit shown is a second-order high passfilter and its low cut-off frequency is given by

fL =1 1kHz

2 RCR C

89. (a)For 555 timer, used as an astable multivibratorcircuit,

Duty cycle, D = HighTT

=

A B

A B

0.693 R R C100%

0.693 R 2R

= 1k 80k 100%1k 2 80k

= 50.3%

90. (c)

Pin diagram of 555 Timer IC (available as an 8-pin mini DIP), with its pin functions, is shownbelow

+ V SupplyCC 1

2

3

4 5

6

7

8Ground

Trigger

Output

555 Timer

Reset

Discharge

Threshold

Control voltage

91. (d)The circuit given represents an Op-Amp SquareWave generator. It is also known as Free-runningor Astable multivibrator. (Statement ‘1’ and ‘2’are true).The output of the above circuit is a square waveand its time period is given by

T = 3f

2 3

R12R Cln , where1 R R


92. (b)When zero or negative control input voltage isapplied, the transistor is OFF. The capacitorcharges up from the Op-Amp output, through Cand Rin, to V–. The charge rate is given as

Charge rate = in

VR C

If the control voltage is not changed, the capacitorC will eventually charge up and hold the outputat +Vsat .When a positive control input is applied, thetransistor is ON. If this voltage is large enoughto drive the transistor into saturation, thencapacitor is short circuited and thus dischargesrapidly.

Vsat

v0

Controlinput

t

t93. (c)

R–

+ V0R

R

Log

LogAntilog

VS1

VS2

R

R

V2

V1

V3

V1 = K1 l n Vs1 and V2 = K1 l n VS2

V3 = 1 S1 1 S2K n V K n VR1R 2

l l

= 1 S1 S2K ln V V

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V0 = Antilog {K1 l n (Vs1·VS2)}= Antilog {ln (Vs1·VS2)}= (Vs1·VS2)

94. (a)

G(s) =

50 0.01N

s s 1 0.05s 0.5

= 10N

s s 1 s 10

Transient response will be decided by poles ats = 0 and –1, pole at s = –10 does not haveconsiderable effect.

Thus, by keeping DC gain constant

G(s) =

10N10N 10s s 1 s 10 s s 1

= N

s s 1

For N = 1

Characteristic equation is

s2 + s +1 =0

Thus, n 1

n2 1

or 1 0.52

There fore option (a) is correct

95. (a)

For unit step input, steady state error is givenby

ess = s 0 p

1lim sE s1 k

Where kp = s 0lim G s

It can be seen that

kp = if system is type -1 or above

kp when system is type - 0

Thus,

Gc(s) = s

s

makes forward path transfer

function of type – 1 hence

kp = and ess = p

11 k = 0

96. (b)

Characteristic equation is

1 + G(s) H(s) = 0

s2 + 100kDs + 100 kP = 0

n P10 k

n D2 100k

for 1 (critical damping)

n P D2 20 k 100 k

or D Pk 0.2 k

97. (a)

For given system

G(s) = P D

2100 K K s

s

P D2

D P

100 K K sY sR s s 100K s 100K

For system to be either uncontrollable orunobservable, there should be pole- zerocancellation.

thus, for KP = 0

D2

D

100 K sY sR s s 100K s

Pole- zero cancellation exists.

98. (c)

24 s 1s type 2 system

s s 2

G

KP = 2s 0

4 s 1lims s 2

(step error constant)

Kv = s 0

4 s 1lims s 2

( Ramp error constant)

a s 0

4(s 1)K lim 2(s 2)

[Parabolic error constant]

Input X can be written as

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x = 1 2 32 35 3 4 5 X s 3x s 4x s2s 2s s

x1 is a unit step input

x2 is a ramp input

x3 is unit parabola input

Now,

ess (step) = p

1 01 K

ess (ramp) = v

1 0K

ess (parabolic) = a

1 1K 2

Therefore,

ess = 14 22

99. (c)

P D2

D P

100 K K sY sR s s 100K s 100K

and G(s) = P D

2100 K K s

s

Parabolic error constant

Ka = 2s 0lim s G s

= 2P D

2s 0

100 K K slim s

s

= 100 KP

As Ka = 1000

100KP = 1000

or KP = 10

100. (a)

When r(t) = 0

2

2

K s 3Y s s 1

1 K s 3 sN ss s 1

or

3 2

Y s K s 3 sN s s Ks K 3 1 s 3 K

Given n(t) = u(t)

N(s) = 1s

Steady state output due to n(t) ;

s t s 0y lim y(t) lim sY(s)

yss = 3 2s 0

Ks s 3lims Ks K 3 1 s 3 K

= 0

101. (a)

From the Nyquist plot, it can be seen that, thepoint –1 + j0 is encircled by

G j locus once clockwise and once counterclockwise.

N = 0

By Nyquist criteria

z = N + P

where z = number of closed loop poles in RHSof s-plane

P = Number of open loop poles in RHS of s-plane.

since, z = 0 (system is stable)

0 = 0 + P = P 0

102. (a)

In system -I, the Nyquist plot of G(s) enclosespoint (–1 + j0) once clockwise and once anticlockwise, so N = 1 – 1 = 0

By Nyquist criteria

z = N + P = 0 + 0 = 0 (stable)

In system II, the Nyquist plot of G(s) enclosespoint (–1+ j0) twice in clockwise manner, soN = 2

Thus,

z = 2 + 0 = 2 (unstable)

103. (b)

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The characteristic equation is

1 + G(s) = 1 + k 1 s 0s 1

or s + 1 + k (1 –s) = 0

or s(1 – k) + 1 + k = 0

s = 1 k1 k

For k > 1, s is positive, i.e. closed-loop polelies in the RHS of s-plane.

104. (b)

For the given system

C

C s G sD s 1 G s G s

Fora ramp disturbance d(t) = at

D(s) = 2as

Therefore,

2s 0 s 0 C

sG s aC lim sC s lim .1 G S G s s

=

s 0 C

a.G slims sG S G s

= s 0 C

alims G s

If GC(s) contains double intergrators

21i.e. contains s

,

C 0

105. (d)

Closed loop transfer function

2

c s ks bR s s as b

The open loop transfer function is

G(s) = 2k s b

s as b k s b

or G(s) = 2k s b

s a k s

steady state error

ess = v s 0

1 1k lim sG s

= s 0

1 a kk s b blim

s a k

Thus

ssa Ke

b

106. (a)

If 1, 2 or 4 , then there will be pole-zerocancellations, so system wil l be eitheruncontrollable or unobservable or both.

107. (d)

G(s) = 2

s 2

s 7s 12

2

2

1 2+Y s s s=–7 12U s 1– –s s

Drawing signal flow graph

1 2 1/s 1/s

Y(s)U(s) x = x1 2. x1

–7 1x2.

–12

1 2 1 1 2x x u 7x 7x x u

2 1 1x 2u2u 12x 12x

y = x1

Therefore

1 1

2 2

x x7 1 1x x12 0 2

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y = 1

2

x1 0

x

Thus,

A = 7 1

12 0

108. (a)

Let x1 = y, x2 = 1dy xdt

2

2 2xd y t 4dy t5r t y t

dtdt

= 5r(t) –x1 – 4x2

Thus,

1 2x x

2 1 2x x 4x 5r

and y = x1

Therefore

1

1

22

dxx0 1 0dt rxdx 1 4 5

dt

y = 1

2

x1 0

x

109. (b)The peak overshoot depends only on thedamping ratio and not on the magnitude ofinput.

110. (c)Increasing the gain will influence the closed looppoles to drift right side. So its poles will moveto right side of s-plane and so system becomesunstable.

111. (b)The root locus is symmetrical about real axisonly.

112. (a)

113. (d)

B

C

AR

B CAR

Transfer function = G1 GH

Here G = A(B–C), H = 1

OR =

A B C1 A B C

= AB AC1 AB AC

114. (a)For R(s) = 0, the above system can be redrawnas.

G (s)2 C(s)N(s)

H(s)

G (s)n G (s)1

C sN s =

2n 1

2 1

G s 1 G s G s1 G s H s G s

i.e. C(s) =

2 n 1 2

1 2

G s G s G s G s N s1 G s G s H s

To eliminate the effect of Noise N(s) on C(s)

2 n 1 2G s G s G s G s = 0

nG s = 1

1G s

115. (c)

–H2–H1

2R 1/2 CG1Forward Path,

P1 = 112×G × 2 = 1G,Δ =1

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Individual loops :L1 = –H1, L2 = –H2,

Non-touching loops,L1L2 = –H1×–H2 = H1H2

Using Mason’s gain formula

CR =

1 1

1 2 1 2

P1 L L L L

= 1

1 2 1 2

G1 H H H H

CR = 1

1 2 1 2

G1 H H H H

= 1

1 2

G1 H 1 H

116. (c)

1010 C1R1 × 10R2 –+

C2

1

1

C 10 10 100R

2

2

C 10 10R 1 10 11

If the forward path gain is reduced by 10% ineach of the system then

90 C1R1 × 9R2–

+C2

1

1

C ´ 90R

2

2

C 9 9´R 1 9 10

Variation in C1 Variation in C2

1 1

1 1

1

1

C CR R

Variation 100CR

90 100 100 10%100

2 2

2 2

2

2

C CR R

Variation 100CR

9 1010 11 100 1%10

11

117. (a)Convert the feedback sytem to unity feedbacksystem, the new Ge is

Ge =

G s1 G Hs s

eG s =

2

2

s 2s s 1

s 2K1s s 1

= 3 2s 2

s s s 2 KK

Now Ge has no pole at origin so type is 0.

118. (b)E(s) = R(s) –C(s)H(s)

=

R G Hs s sR s 1 G Hs s

=

R s1 G Hs s

ess = s 0

LimsE s

=

2

1ss11

s 12s 6s 3

=1 3

1 413

119. (c)A transfer function is Laplace transform of outputdivided by Laplace transform of input. It isindependent of input. It is done with zero initialcondition.

120. (b)In an open loop system, the control action isindependent of the desired output. There is nofeedback available.

121.(d)

G(s) H(s) =K(1 s)(1 – s)

given K < 0 – |K|

G(s) H(s) =–|K| (1+ s)

(1 – s)

G(s) H(s) =(1+ s) |K|

(s – 1)

Put s j and H(s) = 1

G( j ) H( j ) =(1 j ) | K |

( j – 1)

By putting different values of , we get

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= 0 1 180 = 0.01 1 –178.85 = 0.1 1 –168.57 = 1 1 –90 = 10 1 –11.521 = 100 1 –1.145 = 1000 1 –0.1145 = 1 0

G (j ) G(j )

= 0 = u

jVGH plane

122. (d)

OLTF is given by G(s) =d

21

K(1 sT )s (1 sT )

Putting s j

G(j ) =d

21

K(1 j T )(1 j T )

Magnitude, |G(j )| = 2

d2 2

1

K 1 ( T )

1 ( T )

Phase angle

G(j ) = 1 1d 1180 tan ( T ) tan ( T )

0G(j ) = 180

G(j ) = 180

Since at

G(j ) = – 90°, whichis possible only if

1 1d 1tan T tan T > 0

or, 1dtan T > 1

1tan T

Td > T1

123. (c)

By definition of F.T.

if x(t) = 0j te

x( ) =

0j t j te e dt

=

j( )t0e dt

=

0j( )t

0

ej( ) which is

not defined.Therefore we can use the property of impulsefunction, such as

j t0 e d = 0j te

...(1)

0 0t t x t dt x(t )

Thus,

0j tj t

01 ee d

2 2 ...(2)

The relation of x(t) and x is

x(t) =

j t1 x e d2 ...(3)

Comparing (2) and (3)

0j t

0e2

0j t0e 2

124. (b)

1

z 1x z , z 0.5z 0.5 1 0.5z

As ROC is z 0.5 , the signal is right sided.

So express x(z) as a power series in z–1.

Now, by power series expansion method

11 0.5z

1 2 2 3 31 0.5z (0.5) z (0.5) z ....1

11 0.5z10.5z

21 20.5z 0.5 z

2 20.5 z

2 32 30.5 z 0.5 z

3 30.5 z

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Thus,

x(z) = 1 + 0.5z–1 + (0.5)2 z–2 + (0.5)3 z–3 + ....

= x(0) + x(1)z–1 + x(2)z–2 + x(3)z–3 + ....

2x 0 1, x 1 0.5, x 2 0.5 , ....

or x(2) = 0.25Alternatively:

n

1

z 1x z 0.5 u nz 0.5 1 0.5z

x(2) = (0.5)2 = 0.25

125. (a)

Given that,

zlim H z 1

therefore, H(z) has no poles at infinity.

Also, h(n) is right-sided, hence system has tobe causal.

126. (c)

As h(n) is causal, the numerator anddenominator polynomials of H(z) have the sameorder. Given that H(z) has two zeros, thereforethere are two poles.

As one pole is complex in nature, so x(n) to bereal, other pole is conjugate pair of other and

lies on the circle defined by 3z4

.

Given that, ROC is right sided and causal, so

ROC is 3z4

. Thus ROC includes unit circle,

hence system is stable.

127. (c)

x(n) can be written as

x(n) = ...... + (n 4) (n 3)

(n 2) (n 1) (n)

x(z) = ...... + 4 3 2z z z z 1

(By time shifting property)

or x(z) = 2 3 41 z z z z ..........

x(z) Converges if z 1

ROC z 1

128. (a)

1 2 4x(z) sin z 1 3z 2z

=

3 5 7 91

2 411

z z z zz3! 5! 7! 9! 1 3z 2z

z ....11!

Also,

n

n 0x(z) x(n)z

Therefore,

1 3 2x(11)

11! 9! 7!

129. (c)

By definition of z-transform

x(z) =

n

nx(n)z

=

n n n

na u(n) a u(n 1) z

=

n n n n

n na u(n)z a u(n 1)z

Since, u(n) =

1, n 00, n 0 and

u(n – 1) =

1, n 10, n 1

x(z) =

n n1 1

n 0 n 1az az

=

1

1 11 az

1 az 1 az for 1az 1

or z a

1

11 azx(z) 1,1 az

ROC is entire z-plane.

130. (a)

stu 0

L x(t) x(s) x(t)e dt

Thus, discontinuities and impulse that occur att = 0 in the interval of integration is included.Hence x(s) depends on x(t) for t 0 .

For a unilateral laplace transform, there is aunique inverse transform of x(s). This isbecause, ROC must always be in right-halfplane. Therefore, there is no need to specifyROC explicitly.

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131. (c)

Impulse response means, response when initialstate is zero

By Laplace transform, of given differentialequation

s2Y(s) + Y(s) = X(s)

Y(s) [s2 + 1] = X(s)

2

Y(s) 1H(s)X(s) s 1

Taking inverse laplace transform

h(t) = sin t

132. (b)

h(t) = u(t) – u(t – Ts)

Using time shifting property

ssT1 1H s es s

ssT1H s 1 es

133. (d)

Since,

cos2t = cos²t – sin²t

= 1 – 2sin²t

sin²t = 1 (1 cos2t)2

L[sin²t] = 2 21 1 s2 s s 2

=2 2

21 s 4 s2 s(s 4)

= 21 42 s(s 4)

= 22

s(s 4)

134. (a)y(t) = 0x cos tt

Y j = 0 01 1X j X j2 2

Y j = 0 for 0 012

.

The Nyquist rate for y(t) is

N = 0 0

122 = 03

135. (b)

Vrms =

1

22 2

10

dt dt2t 2 2

2using formula

Vrms =

T2

0

V dtt

T

Vrms =

1321

0

t 12 t3

=

12 0 2 13

=223

136. (a)The convolution of input (i/p) function with impulseresponse gives the output (o/p) of the system.

Output, y(t) = h ut t*

= t

0h .u dt [by definition]

137. (c)For a conjugate symmetric function

x(t) = *x t

Now, x(t) X(f)

*x t *X f

*X f = *X f

or, *x t *X f

Now as x(t) is given to be a conjugate symmetric

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function

x(t) = *x t

Therefore X(f) = *X f

Above condition will be true only when X(f) isreal.

138. (c)

I(s) =

2s 1 s

Poles are located at s = 0 and s = –1

System is stable.

Applying final value theorem we get

t

Limi t = s 0

Lim sI s

= s 0

2Lims.s s 1

= 2

139. (d)According to the Parseval’s theorem

E =

2v dtt

=

21 dV2

E =

21 dV

2

=

12j d

1

1 de2

=

1

1

1 1d Joules2

140. (a)For the bounded input, the output will be bounded.So, the system is stable-S.

As y(n) = x(n+1), n 1y(–1) = x(0)

So, the system is not causal - not R.From given i/p - o/p relationship we can see that

1 2 1 2ay by ax bxn n n n

So the system is linear - PFor a time invariant system

0y n n = 0x n n

But here

0y n n = 0x n n 1

So the given system is time variant - not Q. Sosystem is - P, S but not Q, R.

141. (a)

Impulse response h(t) = t 1 t 3

Step response= Impulse response

= h dtt

= dtt 1 t 3

= u ut 1 t 3

Step response can be drawn as

2

1

1 2 3 tFrom above we can see that at t = 2, stepresponse value is 1.

142. (c)As given system is discrete-time LTI system, takethe z-transform of the difference equation.

2 12Y z Y 2X z Xz z z z

12Y Xz z z 22 z

or, H z =

1

2z 2Y z

X 2 zz

H(z) =

2

z z2

z2

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ASTER


Now, for a system to be stable its pole should liewithin the unit circle of z-plane and stability hasno dependence upon zeros location.

zero =2

poles =2

2

< 1

or, < 2 [any value of ]

143. (c)

By definition of F.T.

if x(t) = 0j te

x( ) =

0j t j te e dt

=

j( )t0e dt

=

0j( )t

0

ej( ) which is

not defined.Therefore we can use the property of impulsefunction, such as

j t0 e d = 0j te

...(1)

0 0t t x t dt x(t )

Thus,

0j tj t

01 ee d

2 2 ...(2)

The relation of x(t) and x is

x(t) =

j t1 x e d2 ...(3)

Comparing (2) and (3)

0j t

0e2

0j t0e 2

144. (c)SRAMs are faster than the DRAMs, becauseSRAMs generally use bistable latch as storageelement, whereas DRAMs uses capacitor asstorage element which requires periodicrefreshing.

145. (a)The unused CMOS inputs should never be leftunconnected or, floating because CMOS inputshave very high impedance and even a verysmall amount of circuit noise will result in avery high voltage at this input. This may damagethe circuit by rupturing the insulation layer andalso the persons handling such devices.For storage of such devices, conductive foamor, aluminium foil should be used which willensure shorting of IC pins together.

146. (a)

Non-linearity leads to variable gain, which leadsto amplitude distortion, with variation of oover wide range distortion may be high whichresults in limited bandwidth usage.

147. (a)

Common base (CB) amplifier has very low inputimpedance and very high output impedance.

CB circuit is used as a constant current sourceor current buffer i.e. it accepts an input signal ata low input resistance and delivers a nearly equalcurrent at very high output resistance at thecollector.

148. (a)

For an All-pass filter,

out

in

vv =

1 j2 fRc1 j fRC

= 21 2 tan 2 fRC

An All-pass filter is that which passes allfrequency components of the input signal withoutattenuation but provides predictable phase shiftsfor different frequencies of the input signal. Thus,it is also called as Delay equalizers or Phasecorrectors.

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149. (a)

Most contaminants in MOS fabrication are mobilepositively charged ions. They get trappedbetween the gate and the substrate in an n-channel enhancement MOSFET, whereas theyare trapped on the other side of the substrate inthe case of p-channel enhancement MOSFET.

Due to the contaminants, a p-channelenhancement MOSFET based transistor can beturned on prematurely.

150. (c)• Phase angle of a system is independent of

gain of the system. Thus, assertion is true.• Variation in gain varies the gain crossover

frequency. Thus, it affects the phase marginof system, which is calculated at the gaincrossover frequency. Reason is false.

answers - ies masterfor switches a and b, at a time if only one switch is on, the light will be on....

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