Annual report 2019MICAS - Electrical EngineeringKU Leuven

2

Cover: the variety of MICAS: 1 A 0.59-THz beam-steerable coherent radiator array in 40-nm CMOS. 2 Flexible pMUT 3 A 5GS/s 7.2 ENOB Time-Interleaved VCO-based ADC

v.u. : Wim Dehaene, Kasteelpark Arenberg 10, 3001 Leuven, Belgium

3

1

2

3

Annual report 2019MICAS - Electrical EngineeringKU Leuven

Dept. Electrical Engineering - MICAS Kasteelpark Arenberg 10 - box 2443

3001 Leuven, Belgium tel +32 16 321077

www.esat.kuleuven.be/micas

4

Table of contents

MICAS : MICroelectronics And Sensors Annual Report 2019

1. Analog circuits & power management 12

1.1 Monolithic high voltage power conversion using stacked isolated SC cores 1.2 Dynamic Load Stacking towards highly efficient capacitive energy storage1.3 Switched-capacitor DC-DC converters for high voltage conversions steps1.4 Power DAC for high-speed wireline communication1.5 Development of optical front-end circuits for the LISA space telescope1.6 Optical receivers in nanoscale CMOS with Schottky diodes1.7 Circuit design for ultrasonic haptic feedback with thin-film technology1.8 Multimodal integration of EEG and fNIRS

2. RF, mm-wave & THz circuits 22

2.1 mmWave circuits in 16nm FinFET2.2 Design of A Compact NMOS/PMOS E-band Power Amplifier in 22nm FD-SOI 2.3 Transformer-Coupled Power Amplifiers in III-V 2.4 True Power Detection at mm-Wave Frequencies for Power Amplifiers2.5 Stability Analysis Techniques for mm-Wave Closed-loop Systems2.6 High-performance PMF Communication Systems2.7 Comparison of modulation formats for PMF communication2.8 Stereo-lithographic 3D printing for millimeter and THz frequencies2.9 A High-Speed 390GHz Transmitter in 28nm CMOS2.10 A Packaged Fully Digital 390GHz Harmonic Outphasing Transmitter2.11 Receivers for THz Imaging and Sensing in CMOS2.12 Receivers for THz phase imaging2.13 Design of THz signal sources in CMOS2.14 A 0.59-THz Beam-Steerable Coherent Radiator Array in 40-nm CMOS

5

3. Mixed-signal design & data converters 38

3.1 Advanced Architectures for Time-based Analog-to-digital Converters3.2 High-Performance Analog-to-Digital Converters for 3D-stacked CMOS

Image Sensors3.3 Wideband Continous-Time Delta-Sigma ADC for Wireless Communications3.4 Hybrid Voltage-Time Two-Step ADC With Ring Oscillator Based TDCs3.5 High-Speed/BW High-Resolution Hybrid CMOS ADCs for Wireline/Wireless

Communication Systems3.6 Wide Range, High Speed Clock and Data recovery3.7 Device Modeling and Circuit Design with a-IGZO TFTs3.8 Design of Digital-Based High-Performance Analog Sensor Interfaces3.9 Novel Circuit Architectures for Scalable and Adaptive Sensor Readout3.10 Design of Ultra-Small-Area Low-Power Front-End in Scaled CMOS

Technologies3.11 Radiation Tolerant CMOS Image Sensors

4. Computer Aided Design and Test 52

4.1 Testing and Design for Testability of Latent Defects in Mixed-Signal Integrated Circuits

4.2 Data Learning-Based Defect Activation and Detection in Analog and Mixed-Signal Circuits

4.3 Characterization and Modelling of Superconducting Qubits

5. Digital circuits 58

5.1 Streaming processing for energy-efficient signal processing5.2 Thin-Film Logic Families for VLSI Circuits on Plastic5.3 Ultra-low voltage variation resilient digital circuit design5.4 Energy efficient digital circuits through near/sub-threshold operation5.5 Ultra Low Energy SRAM in 22nm FDSOI using local block level cell monitoring

and tuning5.6 In-Ga-Zn-Oxide based 2T0C gain-cell memory using single-Vt for DRAM

application

6. Machine learning 66

6.1 Hardware acceleration of machine learning algorithms for ultra-low power keyword spotting

6.2 Ultra low power sensory agents through runtime instincts6.3 Hardware-aware machine learning6.4 Efficient processor for Sum-Product Networks6.5 Depth-first CNN inference for efficient high-resolution imagery6.6 Acceleration of pixel processing CNNs6.7 Precision-scalable MAC architectures for embedded DL processing6.8 Rapid hardware-algorithm design space exploration framework

for embedded DL

6

6.9 Exploring mixed-signal NN accelerators6.10 Scaling study of Digital Compute in Memory6.11 Energy-efficient System-on-Chip for Predictive Maintenance6.12 Training and implementation techniques for efficient embedded neural

network processing

7. Biomedical systems 80

7.1 Robust non-contact physiological measurements7.2 Surface Nanostructuring of Parylene-C for Blood contacting implants7.3 Implantable sensor network for monitoring the bladder wall7.4 Dextran as a resorbable and mechanically stiff coating for flexible neural

probes7.5 Integrated CMOS and flexible probe neural microinterfaces7.6 Active ultra-flexible, high-density probes for chronic deep brain neural

interfacing7.7 Ultrasound wave communication through the human body7.8 A Multi-channel CMOS Potentiostat for Monitoring Bioelectrochemical

System 7.9 Implantable measurement system for bladder monitoring and stimulation7.10 An i3T50 CMOS analog front end chip for an implantable eye lens control

system

8. MEMS, sensors & nanotechnology 92

8.1 MEMS technology for flex and stretch monolithic silicon systems8.2 Self-oscillating, thermally actuated piezoresistive MEMS coupled resonators8.3 Gas sensors based on coupled resonators coated with metal organic

frameworks8.4 High performance MEMS sensors based on a novel piezoresistive

transduction principle8.5 Integrated multi-sensor platform for bioprocess monitoring8.6 Microbial chip to capture, analyse and steer communities8.7 Microelectronics for Microorganisms8.8 Piezoelectric micromachined ultrasound transducer (pMUT) for underwater

communication8.9 Structural supercapacitors: composite materials for high-density energy

storage

9. Educational reseach & projects 104

10. Awards and prizes in 2019 108

Volgt na def.

volgorde

7

11. Infrastructure & support 112

11.1 Computer and software infrastructure11.2 Valorization management11.3 IC-Lab HF: broadband, optical, mm-wave and THz measurement lab11.4 IC-Lab LF: the low frequency measurement lab11.5 Technology Lab: chip bonding facilities11.6 Technology Lab: dicing and grinding facilities11.7 Technology Lab: chip repair facilities11.8 MICAS Cleanroom in the Leuven Nanocenter11.9 Micro- and Nanosystem fabrication11.10 Administrative staff ESAT-MICAS

12. Doctoral theses in 2019 124

13. Spin-offs 130

13.1 AnSem13.2 ICsense13.3 Zenso13.4 MinDCet13.5 MAGICS Instruments13.6 HAMMER-IMS13.7 Tusk IC

14. Emeriti 136

Willy SansenBob Puers

15. Bibliography 140

15.1 Journal articles15.2 Conference Proceedings15.3 Abstracts/Presentations/Posters

8

Preface

The MICAS yearbook 2019 is a fact! 2019 was again a year of pushing the state-of-the-art in different fields of circuit design. Typical for MICAS, in this book you will see projects ranging all the way from ‘farfetched ideas with great opportunities, but still far from the market’ to ‘matured concepts, optimized further to make them ready for tech transfer to the industry’ and everything in between. The MICAS research pipeline keeps flowing, to dream up your products of the far future, and collaborate with you on the products of tomorrow.

As always, also in 2019, MICAS took pride in fabricating – not just simulating - the ideas we develop. This means making chips, such that we can actually measure and prove our ideas in the lab. MICAS is all about chips! We are proud to have access to very advanced technologies. In this book, you will hence see numerous die pictures of chip designs all the way down to 16 nm silicon technology. We also keep investing in our lab, to enable measurements down to pico-ampere currents or up to THz frequencies.

In 2019, MICAS organized the first International Workshop on Polymer Microwave Fiber Technology. These two days of the PMF workshop brought the fine-fleur of the microelectronics community involved in this new communication technology to Leuven. Such event clearly shows that technology of which the cradle stood in MICAS, is finding its way to an international public.

9

Finally, MICAS would not be MICAS without its industrial and academic collaboration partners. We are funded by local, national and European funding organizations like VLAIO, FWO and the European Commission. In addition, our industrial cooperation was again very intensive in 2019. With more than 40 different research projects running in our lab, we want to thank you all for the collaborations and the trust you put in our team. Funding is of course essential, but external collaborations especially ensure that we focus on the most relevant topics and try to solve the micro- and nanoelectronic problems that matter for tomorrow. Without your support, the book your holding in your hands would be much thinner.

We hope that you enjoy the MICAS yearbook, edition 2019. We are already filling up the 2020 edition.

Wim DehaeneOn behalf of the entire MICAS staffFebruary 2020

Inaugural Lecture, June 2019, Michael Kraft (MICAS), Valentijn De Smedt (ADVISE, Techn.Campus Geel), Nigel Smart (COSIC).

10

MicasTeam

Prof. W. Dehaene Low-power digital, time-based processing

Prof. M. KraftMicro- & nanosystems, microsensors, BioMEMS

Prof. G. GielenCAD, analog, mixed-signal

Prof. B. PuersMEMS, packaging, biomedical

1 3

2 4

4

7

3

11Prof. P. ReynaertRF, mm-wave, THz

Prof. F. Tavernier Optical, high-speed, power management

Prof. M. SteyaertRF, power management, analog, mixed-signal

1

2

6

5

5

7

8

6 Prof. M. VerhelstProcessors, sensor fusion, machine learning

8

12

1. Analog circuits &power management

13

Analog is the bread and butter of the MICAS research group with more than 4 decades of outstanding research in this domain, often boldly pursuing unconvential paths.

14

Electronic devices spend most of their lifetime in standby mode. Summing the power consumed in standby by these devices, results in a total amount of energy that is much larger than the energy consumed during activity. All these electronic devices are powered by the mains through a power management circuit which is optimized for the active mode, but that is inefficient in standby mode. This research will improve the standby mode by implementing a fully integrated AC-DC converter optimized for this standby mode.

Based on a first prototype, it is concluded that the approach using capacitive voltage division severely limits the output power due to its high input impedance. Therefore, another design approach, in which a multi-ratio switched capacitor converter will be used for AC-DC conversion, is investigated. As a first step, a high-voltage wide-range switched capacitor (SC) DC-DC converter is implemented. This converter uses the new idea of stacking isolated SC cores, in which the different converter cores can be connected in series at their inputs and in parallel at their outputs. This way, a fully integrated high voltage wide-range converter that converts input voltages up to 42V into 3V is realized while the design effort is limited to the single core. More specifically, the performance of the stacked converter is identical to the single converter’s performance while the generated power is summed, and a higher voltage can be converted. Isolated SC cores are designed to avoid shorts during stacking. The DC-DC converter is fabricated in a 0.35μm CMOS technology and achieves an output power of 2.1mW.

Elly De Pelecijn• Promotor Prof. M. Steyaert michiel.steyaert@kuleuven.be• Research topics Monolithic Power Management, AC-DC & DC-DC Conversion, Switched-Capacitor Circuits

1.1 Monolithic high voltage power conversion using stacked isolated SC cores

Related publication: E. De Pelecijn and M. Steyaert, “A 7.5 - 42V Input High-VCR Monolithic DC-DC Converter Using Stacked Isolated SC Cores.” 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), Macau, 2019.

Concept of stacked power conversion (left) and chip micrograph of published design (right).

15

Small sensors nodes or IoT devices can only achieve ultimate portability by extracting their required energy from the environment by means of energy harvesters. However, there exists a big gap between the required power of such a node and the harvested power. Therefore, storing the harvested energy on a capacitor when the node is idle, allows to bridge this power gap and enables the widespread use of energy harvesters in sensor nodes. Such capacitive energy storage, however, sets challenging requirements for DC-DC converters. Therefore, the aim of this research is to design highly efficient fully integrated converters dealing with the wide voltage range across the storage capacitor.

Voltage Domain Stacking (VDS) is a highly efficient technique which splits the total load power into multiple approximately equal parts and stacks them on top of each other. Although being highly efficient, VDS fails to cope with a wide input range which is required for capacitive energy storage. To unlock high efficiencies for capacitive energy storage, this work proposes a new technique: Dynamic Voltage Domain Stacking (DVDS). Based on the voltage across the storage capacitor, more or less loads are stacked in series or placed in parallel to allow multiple VDS-like connections during one discharge cycle, significantly boosting the efficiency. Besides the load switching hub, which connects the loads either in series or parallel, two DC-DC converters are implemented: first, a ladder converter (1 in the figure below) to compensate for power imbalance between the stacked loads and second, a gearbox-type converter (2) to guarantee continuous operation. A dedicated FSM controls the state of both converters as well as the load switching hub.

Tim Thielemans• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be• Research topics Switched Capacitor DC-DC

converters, Integrated Power Management

1.2 Dynamic Load Stacking towards highly efficient capacitive energy storage

Working principle of the proposed DVDS-system for capacitive energy storage.

16

In recent integrated technology nodes, supply voltages have dropped below 1V. At such low voltages, delivering power with an external DC-DC converter results in high intake currents, both causing losses and inducing a voltage drop in the power delivery network. To minimize these effects, many pins of the chip need to be dedicated for supply, decreasing the available pins for I/O.

As an alternative, the DC-DC converter can be placed on-chip so that external voltage increases and hence the intake current decreases. This reduction in current scales proportionally with the voltage conversion step and, for this purpose, this conversion step should be high. At the same time, the converter should have a high efficiency and power density to limit the introduced losses and cost, respectively.

For integrated power conversion, switched-capacitor DC-DC converters are well suited because they only use switches and capacitors that are readily available in standard CMOS technologies. However, for a high conversion step and a high power density conventional topologies have limited efficiency. This is because the voltage across their capacitors is high, which requires less dense capacitors, therefore resulting in significant losses.

This research proposes a cascading technique that splits a converter into two series subconverter stages as shown in the figure below, each with a lower conversion step that the total converter. Hence the capacitors of the subconverter experience low voltages and can therefore be implemented with high-density capacitors despite the high conversion step.

Tuur Van Daele• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be• Research topics Switched-capacitor DC-DC

conversion, Wide-bandgap technology

1.3 Switched-capacitor DC-DC converters for high voltage conversions steps

Concept of cascading DC-DC converter.

Related publication: T. Van Daele, E. De Pelecijn, T. Thielemans, M. Steyaert and F. Tavernier, “A Fully-Integrated 6:1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm2”, PRIME, 2019.

17

A typical transmission chain for wireline communication consists of a digital front-end (DFE) connected to a line driver. The DFE consists of a DSP and ADC/DAC which provide a multi-carrier high PAPR wideband signal for the line driver. Furthermore, it performs channel estimation and correction. The line drivers are typically manufactured in III-V semiconductor technologies which offer higher breakdown voltages compared to standard CMOS. However, it is shown that high voltage stacked line drivers can be implemented in wireline transceivers [1].

Due to high PAPR signals line drivers are mostly operating at back-off where efficiency is shown to be below 3% as these are typically Class A biased for high linearity. By integrating DAC and line driver in a current switching scheme with high voltage current cells the efficiency can be significantly increased while eliminating an intermediate analog signal. This also lowers the boundary for further integration with the digital processing part to obtain a single-chip solution.

A 9-bit segmented DAC with offset correction is implemented in 28nm standard CMOS technology using a supply voltage of 8.1V simulated to output 10Vpp differential across a 50ohm load resistor.

Jan Cools• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Segmented DAC, Current switching,

wideband, Stacking, Standard CMOS

1.4 Power DAC for high-speed wireline communication

Related publication: Gurné T., Strackx M., Tytgat M., Cools J., Reynaert P., “A 20Gbps 1.2GHz Full-Duplex Integrated AFE in 28nm CMOS for Copper Access.”in Proceedings of ESSCIRC, 47, pp. 107-110, Leuven, 2017.

Layout of 28nm 9-bit Power DAC.

18

Gravitational waves are used to observe and study systems that are almost impossible to detect by any other means. The Laser Interferometer Space Antenna (LISA) concept is based on measuring changes in the distance between test masses contained in three identical spacecraft orbiting around the Sun. The laser link that enables communication between these satellites places stringent noise requirements on the receiver chain of each satellite to ensure desired performance.

The readout chain consists of a quadrant photodiode and transimpedance amplifier/pre-amplifier (placed on the optical bench of the receiver unit) followed by the back-end electronics (ADC and phasemeter). The transimpedance amplifier dominates the electronic noise in the system which leads to the low-noise requirement. The key difference between the optical front-end unit in this system and commercially used optical receivers is the nature of the input signal. Due to the concept of laser interferometry, which relates the phase difference between the two interfered light beams to the relative displacement between two free-falling masses, the incoming signal consists of strong DC-signals mixed with a weak AC-signal. Hence, each of these signals have to be amplified with different gains. This is possible by having a spectral filter at the input of the transimpedance amplifier. A prototype of such a transimpedance amplifier was taped-out using 65nm CMOS technology and will be analyzed in radiation environments to determine critical areas that would require radiation hardening by design.

Ciana Barretto• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be• Research topics Analog IC Design, Optical Receiver, Radiation-Hardening By Design

1.5 Development of optical front-end circuits for the LISA space telescope

Block diagram of the receiver (a) and topology of the TIA (b).

19

There has been an increasing trend to integrate optics on chip, similar to the electronicintegration which revolutionized the world decades ago. Different platforms are beingexplored to integrate optical components such as optical waveguides, modulators and photodetectors. Most of these platforms are focused solely on optics, however, meaning an additional electronic chip is necessary for the optical signals to be processed.

In this research, we try to integrate the optics and electronics for optical receivers in abulk CMOS process. While other platforms offer more performance both for optics and electronics, CMOS is more standardised and widespread, resulting in enormouslow-cost-potential. Schottky photodiodes have enabled us to detect sub-bandgap photons and thus operate in the same spectrum as silicon photonics. After characterisation of these novel devices, various 1310/1550nm prototype receivers have been fabricated, demonstrating data rates of multiple gigabits per second.

Wouter Diels• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. M. Steyaert• Research topics Opto-electronics, Low-noise baseband circuits

1.6 Optical receivers in nanoscale CMOS with Schottky diodes

Chip photograph of a fully-integrated1310/1550nm optical receiver in 28nm bulkCMOS.

Related publication: Diels W, Steyaert M, Tavernier F, “Optical Receiver with Schottky Photodiode and TIA with High Gain Amplifier in 28 nm Bulk CMOS”, in Proceedings of ESSCIRC 2019.

20

Haptic feedback is a key technology to improve the user experience of touch screens, automotive and augmented reality applications. Rather than common techniques which incorporate sensors and actuators within keypad, touchscreen or gloves to generate haptic feeling, this project creates this feeling in mid-air without the need for physical contact with the haptic enabled product. The generation of this haptic feedback can be obtained with phased controlled arrays of ultrasonic transducers in a thin-film technology.

This research focuses on the development of circuits to drive the large arrays of ultrasonic transducers. In order to drive these arrays, in-matrix circuits has to be developed. Rather than using conventional CMOS technologies, a cheaper thin-film technology is chosen. However only n-type devices are available in this technology which in addition suffer from worse mobility. These challenges require a different design approach compared to the conventional CMOS technologies.

Pelgrims Jonas• Promotor Prof. W. Dehaene wim.dehaene@esat.kuleuven.be• Research topics Large area electronics, Circuit level

digital in thin-film, Ultrasonic haptic feedback

1.7 Circuit design for ultrasonic haptic feedback with thin-film technology

A figure of the thin-film concept with ultrasonic arrays and in-matrix TFT circuits.

21

Research on low power, portable EEG recording devices have recently gained huge momentum. These devices are already being used for continuous monitoring of brain activity for both therapeutic and neuroscientific research. Near Infrared Spectroscopy (NIRS), a brain imaging technique of growing interest, however, lags far behind when ambulatory monitoring is concerned. It has been recently shown that EEG combined with functional-NIRS (fNIRS) has far greater prospect in decoding brain activity. EEG measures post synaptic potentials associated with neural activation while fNIRS measures local haemodynamic changes associated to the same. These two modalities complement each other in their ability to resolve information about the spatial and temporal characteristics of neural activity. The goal of this project is to design and manufacture a low power integrated solution for state of the art multi-parameter brain activities monitoring, by means of combining EEG and fNIRS analog front-end (AFE), digital interface and (sensor) controller functionality. This chip is a test-chip for a new fNIRS architecture and only includes fNIRS read-outs.

The slope-based light-to-digital converter (LDC) is made for PPG/NIRS recording, which applies a dual-slope readout architecture to gain resolution. Compared with the traditional TIA-based readout architecture, the LDC method is promising as it reduces the system complexity by direct conversion, while improving the dynamic range (DR) and noise performance via the time domain charge counting mechanism. Compared to the prior art, the LDC achieves the highest maximum DR and the lowest power consumption with a large range of reconfigurability. The biomedical acquisition has been done to record robust PPG, NIRS and SpO2 signals.

Qiuyang Lin• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. C. Van Hoof• Research topics Analog Biomedical Circuit, Optical input EEG fNIRS

1.8 Multimodal integration of EEG and fNIRS

Chip micro diagram.

Related publication: Q. Lin et al., “A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors,” 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019, pp. C58-C59.

22

2. RF, mm-wave &THz circuits

23

MICAS has always been one the leading institutes to show the usage of CMOS for RF and mm-wave communication, resulting in the mobile age of today.

24

The desire for ever increasing data rates is leading to the use of the spectrum above 100GHz for communication. The increased transmission loss that comes with these higher frequencies will unfortunately result in smaller communication distances. To achieve sufficient coverage a large amount of transceivers will be necessary. To keep the costs low integration of the high speed baseband and DSP circuits with the mmWave circuits in a nm-scale CMOS technology is desired.

In this research we investigate the design of a D-band power amplifier in a 16nm FinFET process. A 16nm FinFET process posses extra challenges on the design of a mmWave power amplifier compared to the previous planar technologies. A first challenge is to overcome the added parasitic losses when transistors are scalled up to deliver RF-power. A second challenge is the maximal output power of the power stage limited by the matching of a large output capacitance.

The reseach has resulted in a D-band 3-stage power amplifier employing a 2-way power combining technique to further boost the output power. The power amplifier achieves a peak gain of 25.6dB, a Psat of 15dBm and a peak PAE of 12.8% for an area of 0.062mm2.

Bart Philippe • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics mmWave circuits, FinFET, D-band,

Power amplifiers

2.1 mmWave circuits in 16nm FinFET

Related publication: B. Philippe, P. Reynaert “A 15dBm 12.8%-PAE Compact D-Band Power Amplifier with Two-Way Power Combining in 16nm FinFET CMOS”, ISSCC, Feb. 2020.

Die photo of a D-band power amplifier in a 16nm FinFET CMOS technology.

25

For mm-Wave 5G backhaul networks, directive array-based antennas can provide high gain around 30dBi in a small space. This enables the output power requirements of PAs to be in the range of 15-18dBm. These output power levels are realizable in Silicon based technologies. The 22nm FD-SOI CMOS technology presents unique opportunity for the industry as a cheaper alternative to Finfet, as well as allowing higher integration density compared to SiGe. Nevertheless, there are several key challenges to implement a mm-wave PA in 22nm FD-SOI, such as a lower breakdown voltage and large back-end parasitics compared to older CMOS nodes.

In this work, A differential PMOS cascode PA with a differential NMOS cascode driver stage is proposed. This way, the output stage benefits from the large voltage handling capability of PMOS transistors to achieve high output power with 2V supply, while the driver benefits from the higher fmax of NMOS transistors to achieve high gain.

Umut Çelik• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Power Amplifiers, mm-Wave, 5G

2.2 Design of A Compact NMOS/PMOS E-band Power Amplifier in 22nm FD-SOI

Related publication: U. Çelik and P. Reynaert, “An E-Band Compact Power Amplifier for Future Array-Based Backhaul Networks in 22nm FD-SOI,” 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Boston, MA, USA, 2019, pp. 187-190.

The die photo of the PA. Highlighted core area is only 0.052mm x 0.38mm.

26

The high available bandwidth at millimeter wave frequencies enables high data rate wireless communication for future fifth generation(5G) systems. The Ka-band is a potential candidate for the implementation of these systems which makes broadband power amplifiers(PA) that can cover the entire band highly attractive. However, the main challenge in designing a PA over a broad frequency range is using compact matching structures, which translates to a low fabrication cost.

PA’s in GaAs technology have superior performance at millimeter wave frequency compared to CMOS technology. However, the higher cost of GaAs compared to CMOS technology is one of the main limiting factors. To overcome this downside, we propose a broadband and compact transformer-coupled PA, instead of using bulky transmission lines, reducing the overall area and hence the cost.

Transformer-coupled PA’s have become common in CMOS technology and numerous publications have demonstrated this. Transformers are very attractive as they provide very compact impedance transformations and differential-to-single ended conversion. They also provide easy DC biasing through a center tap, which is an AC ground in differential mode, eliminating the need for very bulky bias lines for supply and biasing.

Qunaj Valdrin• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Power Amplifiers,

mm-wave Circuits, III-V

2.3 Transformer-Coupled Power Amplifiers in III-V

Related publication: Qunaj Valdrin and Reynaert Patrick, “A Compact Ka-Band Transformer-Coupled Power Amplifier for 5G”, BCICTS 2019 Qunaj Valdrin and Reynaert Patrick, “Compact Transformer-Based Matching Structures for Ka-Band Power Amplifiers”, APMC 2019.

Die micrograph of the PA protoype in GaAs.

27

The upcoming introduction of fifth generation (5G) wireless systems pioneers a new level of mobile performance with ultra-high speeds and low latency. Recently, millimeter wave (mm-Wave) phased array systems have become the center of focus for these wireless 5G systems, but also imaging applications and radar systems are of interest. Specifically, the rise of self driving cars using mm-wave radar systems for sensing is a significant commercial driving force.

Integrated power detection for low-cost mm-wave phased array systems is of critical importance in modern transceiver systems. Power detectors are used to monitor the delivered power to each antenna element, enabling the control of the output power for each PA through a variable gain amplifier, thus allowing to optimize the power consumption of the system. The power detector can also be used to detect failures associated with packaging or board assembly, thus allowing the detection of antenna failures. Subsequently, the beam can be adjusted to compensate for the defective element. This enables fully-integrated automated built-in self-test (BIST)functionality, which is critical for low-cost mm-wave systems. In addition, the BIST systems needs to have minimal impact on the overall mm-wave system performance.

There are numerous techniques that have been proposed for mm-wave power measurement applications. One type of detector only measures voltage to determine the mm-wave output power. In this case, a voltage rectifier can serve as a power detector. However, by only taking the output voltage into account, the detector only gives the true output power for a fixed load. In this design both voltage and current are measured, and used to determine the true mm-wave output power.

Qunaj Valdrin• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Power Detection, Power Amplifiers,

mm-wave Circuits

2.4 True Power Detection at mm-Wave Frequencies for Power Amplifiers

Related publication: Qunaj Valdrin, Reynaert Patrick, “An E-band Fully-Integrated True Power Detector in 28nm CMOS”, RFIC 2019.

Die micrograph of the E-band power amplifier with integrated power detector.

28

In the pursuit for higher data rates, mm-wave communication has gained interest. Thanks to the smaller wavelength at these frequencies, antennas can be placed on-chip to increase the level of integration. However, parasitic coupling could occur between antenna and mm-wave front-end. Therefore it is crucial to examine stability in simulation. Due to the large S-parameter files, a transient would explode the simulation time. Methods, such as mu- and k-factor analyses, are only defined for two-port networks and could be inoperative due to possible multi-loops.

Considering these drawbacks, a fast closed-loop method is advised, which uses a small-signal current source to emulate small perturbations and verify stability of the dc solution at different circuit nodes. A closed-loo transfer function can be found on which admittance analysis and pole-zero fitting reveal possible oscillations. This technique is used on the design of a 120 GHz LNA with on-chip antenna, which exhibits oscillations.

Simon Ooms• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics millimeter-wave, Dielectric fiber

communication, CMOS

2.5 Stability Analysis Techniques for mm-Wave Closed-loop Systems

Related publication: S. Ooms and P. Reynaert, “Stability Analysis of Parasitic Coupling Between on-Chip Antenna and mm-Wave Front-End”, Radio and Wireless Symposium, Jan 2020, Accepted.

Stability analysis in closed-loop, admittance and pole-zero analysis predict unwanted oscillations.

29

Previous research on dielectric waveguide communication has mainly focused on improving the elements of the physical link. In contrast, this work aims to improve communication range and data rate from a system-level perspective. As a first step, a CMOS ASK transceiver is developed and optimized for the targeted fiber. Using off-chip couplers results in high bandwidth and low coupling loss, allowing for high data rate and large communication range. Enhanced linearity of the transceiver enables higher-order modulation schemes such as 4-ASK. In addition, application of equalization techniques such as FFE (Feed-forward Equalization) or DFE (Decision Feedback Equalization) becomes feasible, further enhancing the bandwidth of the link.

Finally, the use of advanced error-correcting codes relaxes the SNR (Signal-to-Noise Ratio) requirements for a given Bit Error Rate by several dB, at negligible coding overhead. This, in turn, leads to an increased communication range.

Kristof Dens • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics mm-Wave circuits, Dielectric

waveguides

2.6 High-performance PMF Communication Systems

Proposed ASK transceiver (top left), Effects of error correction (right) and equalization (bottom).

30

Dielectric waveguides promise high speed digital communication using millimeter wave signals. In order to increase the data rate without increasing the RF bandwidth, a higher order modulation format can be used. This comes at the cost of increased sensitivity to noise and requires more complex circuitry. By studying the performance at different modulation depths for a same data rate, a better understanding of the system trade-offs can be achieved and the limits in performance can be pushed further.

This work will involve the effect of modulation depth on signal degradation, the impact of the carrier frequency, and the possibility of compensation algorithms in order to improve the received signal quality. Doing so can allow future work to understand better the trade-offs in the design space and their impacts on link performance.

Joren Vaes • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Dielectric waveguides, High-speed

communications

2.7 Comparison of modulation formats for PMF communication

Top: Impact of the carrier is shown.

Bottom: Different modulations for same datarate.

31

Over the last decade, 3D printing and has made significant waves in the manufacturing communities. Many techniques exist, such as FFF/FDM, laser-sintering, etc.

A technique that has recently decreased in cost significantly is based on UV-curable photo-polymers that are exposed by a laser or through an LCD screen. This offers very high resolution (<50μm) compared to other methods such as FDM. Such high resolution opens options for use as lenses or guided channels for millimeter-wave and THz signals.

Such lenses require accurate material parameters. This is an issue, as the material properties depend on curing and manufacturing process. Research is needed in how to model the material properties, and then how to use the technology for millimeter-wave applications.

Joren Vaes• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Dielectrics, millimeter-wave, THz

2.8 Stereo-lithographic 3D printing for millimeter and THz frequencies

A 3D-printed waveguide flange coupler for dielectric fiber measurements.

32

There is an increasing demand for higher data rates in wireless communication systems to accommodate the immense growth in global data traffic. The large available bandwidth and small wavelength at mm-Wave and THz frequencies provides the opportunity to achieve high data rates while keeping the chips compact. Integrating the circuits in a CMOS technology offers an economic advantage, but makes the design more challenging due to the limited fmax at these high frequencies.

A 390GHz transmitter is proposed with a switch-based modulator capable of generating OOK, BPSK and BPOOK modulated signals and a frequency tripler to generate the 390GHz signal. The BPOOK modulation employs duobinary encoding to halve the bandwidth compared to OOK and BPSK. The chip is fabricated in 28nm CMOS and achieves a measured output power of -5.4dBm at 390GHz. A maximum data rate of 28Gbps is achieved with BPOOK modulation and 18Gbps with OOK and BPSK.

Carl D’heer • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics mm-Wave & THz CMOS Design, High-speed communication

2.9 A High-Speed 390GHz Transmitter in 28nm CMOS

Block diagram of the 390GHz transmitter and micrograph of the fabricated chip.

33

The need for higher datarates pushes carrier frequencies to frequencies above Fmax. One of the possible transmitter architectures above Fmax is the multiplier-last architecture. This architecture inherently suffers from amplitude and phase distortion which makes it only suitable for very simple modulation schemes like BPSK and OOK. This work proposes a harmonic outphasing topology as way to overcome the amplitude distortion of multiplier-last architects. When combined with phase per-distortion, complex modulated signals can be generated above Fmax. A prototype was designed and fabricated at 390GHz. An on-chip phase modulator capable of generating 8 different phases and 4 distinct amplitude levels generates two outphasing signals from 5 digital bit streams. Once up-converted, these signals are tripled to 390GHz and recombined. The Transmitter was fully packaged with a micromachined waveguide flange as output.

Alexander Standaert • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics Dielectric waveguides, Millimeter wave, Dielectric properties and characterization

2.10 A Packaged Fully Digital 390GHz Harmonic Outphasing Transmitter

Related publication: Standaert A., Reynaert P., A Packaged Fully Digital 390GHz Harmonic Outphasing Transmitter in 28nm CMOS, ASSCC2019 Proceedings.

Chip picture of the 390GHz harmonic outphasing transmitter.

34

The maximum frequency of oscillation (fmax) of CMOS transistors has saturated around 350GHz. Fundamental THz oscillation and amplification are thus not possible in CMOS technology. However, the numerous advantages (cheap in high volume, integration with digital logic, possibility of going to large arrays) still make CMOS an interesting candidate for THz imaging and sensing. Due to the fmax limitation, non-conventional circuit techniques have to be used to transmit and receive THz signals.

A promising candidate for receiving above-fmax signals is the super-regenerative receiver. The central block of this circuit is the super-regenerative oscillator (SRO). This is an oscillator which is quenched periodically, enabling and disabling oscillation. The THz input, downconverted by mixing with a local oscillator, boosts the SRO’s startup. Consequently, the SRO’s envelope is dependent on the THz input power. The circuit is being designed in 28nm CMOS technology.

Ariane De Vroede• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics THz CMOS electronics, Imaging and sensing

2.11 Receivers for THz Imaging and Sensing in CMOS

Block diagram of the super-regenerative receiver.

35

The THz frequency band (0.3THz - 3THz) gains huge attention for imaging and radar applications. The main advantages of this band compared to the lower and upper bands are higher imaging resolution and capability of penetration through some organic materials (paper, clothes, plastic), respectively. Furthermore, the non-ionizing nature of the THz waves makes them safe for operation with biological tissues. However, design of the integrated circuits operating in the THz range in CMOS technologies proves to be very challenging because of the lack of transistors’ gain and increased parasitics. Those lead to low transmitter output power and high receiver noise figure, resulting in a low overall SNR and consequently long imaging time.

The first part of this research involved developing techniques for power and gain enhancement in CMOS circuits operating between 100GHz and 200GHz. Since transistors in the THz band operate above fmax, meaning cannot provide power gain, those circuits are key components for enabling fast and accurate imaging systems. The proposed techniques resulted in a 40nm CMOS power amplifier, achieving 14.8dBm of output power and 20.3dB of gain at 140GHz (Simic, RFIC 2018).

The second part of the research investigates suitable receiver topologies for THz amplitude and phase detection above 500GHz. This would enable applications such as topography, object localization and full dielectric characterization. The goal is improving receivers’ sensitivity, while preserving phase information. The key for that is implementing coherent receiver architecture and increasing LO power for the THz down-conversion mixer.

Dragan Simic • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics mm-wave & THz circuits, Imaging

2.12 Receivers for THz phase imaging

Die photo of the designed 140GHz power amplifier.

36

The frequency range between 300GHz and 3THz was out of reach for both electronics and optics in the past, becoming what has been known as the “THz gap”. The applications for this frequency range are many, ranging from tomography imaging to gas indentification and detection through spectroscopy. Recent increases in the performance of CMOS processes enabled use for the lower half of this band where both transmitters and receivers have already been demonstrated. But CMOS processes presents many challenges in circuit design and packaging, coming from the low transistor fmax, and the lossy silicon substrate.

On the circuit side, operating above fmax means no amplification and forces the development of new circuit topologies and techniques to extract power generated at mm-Wave frequencies. This requires providing transistors with optimum impedances to increase the efficiency of harmonic power generation and extraction, and also combine coherently the power of many sources to increase the overall link budget of THz systems. On the packaging side, traditional techniques such as wirebonding and flip-chip have too much parasitics and are thus not viable. The most common solution to get the signal off-chip is through the use of integrated antennas as this is made possible by the small wavelength at these frequencies.

In 2019 we demonstrated a 660-to-676GHz 4×2 Oscillator-Radiator Array in 40nm CMOS. The oscillators add their output coherently in free-space achieving state-of-the-art power of -16dBm total radiated power and 7.4dBm EIRP.The circuit has a phase-noise of -93dBc/Hz at 10MHz offset when measured at 670GHz.

Gabriel Guimaraes • Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics THz Sources, Oscillators and On-chip Antennas

2.13 Design of THz signal sources in CMOS

Related publication: G. Guimaraes, P. Reynaert. “29.6 A 660-to-676GHz 4×2 Oscillator-Radiator Array with Intrinsic Frequency-Filtering Feedback for Harmonic Power Boost Achieving 7.4dBm EIRP in 40nm CMOS” - 2020 ISSCC.

The 670GHz 4x2 oscillator-radiator in 40nm chip photograph.

37

In THz active imaging systems, a signal source with high output power is required to provide illumination on the object. Since the THz frequency range lies beyond fmax of CMOS transistors, generating high power radiation is very challenging, and the power from one THz radiator is limited. To further increase the radiated power, a coherent radiator array with free-space power combining is needed. Beam-steering function is very useful in THz imaging system. Electronic beam-steering is compact and fast comparing to the mechanical scanning approaches. In this project, a 0.59THz beam-steerable radiator array is designed, fabricated, and measured. The chip is in 40nm CMOS technology. The size of the chip is 1mm × 0.68mm. The chip is an coherent radiator array composed of 36 radiator elements. By controlling the phase of the radiator elements, beam-steering function is realized.

Kaizhe Guo• Promotor Prof. P. Reynaert patrick.reynaert@kuleuven.be• Research topics THz Radiator, Oscillator, Phased

Array

2.14 A 0.59-THz Beam-Steerable Coherent Radiator Array in 40-nm CMOS

Related publication: K. Guo, P. Reynaert, “A 0.59THz beam-steerable coherent radiator array with 1mw radiated power and 24.1dbm EIRP in 40nm CMOS”. ISSCC, Feb 2020.

A 0.59-THz beam-steerable coherent radiator array in 40-nm CMOS.

38

3. Mixed-signal design& data converters

39

Mixed-signal design requires thorough cross-domain knowledge in order to grasp all opportunities arising from digitally-enhanced analog as well as analog-enhanced digital. The breath of the MICAS research team allows to truly exploit this.

40

The trend towards smaller transistors coupled with lower supply voltages has made digital circuits faster and more energy efficient, but analog circuits do not enjoy the same benefits. Time-based circuits are gaining popularity as an alternative to traditional voltage-based analog circuits to overcome this limitation. Due to their highly digital nature, time-based circuits can benefit from technology scaling just like digital circuits.

This research focuses specifically on the design of time-based ADCs. We have developed a VCO-based design which uses advanced time-domain sampling techniques combined with digital post-processing to deliver significantly higher speed and resolution than previous time-based designs, while still maintaining reasonably low power consumption. The prototype shown below contains 8 time-interleaved VCO-based ADC channels with on-chip digital calibration. It achieves 7.2ENOB at 5GS/s while consuming just 22.7mW, resulting in a Walden FOM of 30.5fJ/cs. This ADC very competitive with state-of-the-art traditional ADCs, and yet requires only a fraction of the area.

As part of this ADC, we developed a wideband frequency divider (DC to 20GHz input) with very low power consumption. This concept was further explored as a separate chip and combined with self-biasing and self-tuning techniques to obtain an extremely wideband, PVT-tolerant frequency divider. The prototype shown below is expected to work with input frequencies from DC to 60GHz without any external tuning.

Maarten Baert• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Analog-to-digital converters,

Frequency dividers, Time-based architectures

3.1 Advanced Architectures for Time-based Analog-to-digital Converters

Related publication: M. Baert and W. Dehaene, “A 5GS/s 7.2ENOB Time-Interleaved VCO-based ADC Achieving 30.5fJ/cs,” ISSCC, Feb. 2019.M. Baert and W. Dehaene, “A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/cs,” JSSC (early access).

Die photo of high-speed VCO-based ADC (left) and PVT-tolerant wideband frequency divider (right).

41

CMOS image sensors (CIS) are everywhere today, in mobile phones, tablets, surveillance, autonomous cars and biometrics devices. They are a common part of today’s modern society, and a further development in the field of imagers is undeniably to be expected in even more applications, such as real-time robotics, industry 4.0, ambient-assisted homes, etc. Additionally, consumer and industry demands are increasingly getting larger and more demanding in terms of spatial resolution, frame rate, dynamic range and power, as well as robustness. This poses a challenge for research to continuously innovate and to improve all these imager performances simultaneously.

Generally, a CIS imager system consists of optics, a pixel array, pixel readout circuitry with the analog-to-digital converters (ADCs), and a digital processing unit. Besides the pixel size and noise, the analog-to-digital conversion is typically responsible for the overall performance limitations in CMOS imagers and also largely determines the power consumption, especially for higher specifications. Therefore, our main research focus lies in optimizing the analog-to-digital converters in 3D-stacked CMOS image sensor devices for achieving a Figure-of-Merit (FoM) around 0.5e-nJ. In order to achieve such good FoM, an incremental delta-sigma (IDS) is an excellent candidate because of its oversampling and noise-shaping capability. State-of-the-art IDS for image sensors, however, only achieve moderate speeds. In this research, novel IDS architectures are being researched in order to achieve faster conversion speeds without increase in power consumption.

Nicolas Callens• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics CMOS Image Sensors, High-Performance ADCs, High-Performance Readout Circuits

3.2 High-Performance Analog-to-Digital Converters for 3D-stacked CMOS Image Sensors

State-of-the-art of CMOS image sensors.

42

Due to the demands of present and new applications, the global mobile data traffic is predicted to be growing continuously the following years. With the radio frequency range limited, the radio spectrum is becoming more and more crowded due to this rapid growth. For the long-term evolution advanced (LTE-A) receiver system, the antenna receives not only the in-band signals but also various blockers, including the out-of-band blockers (OBB), the in-band blockers (IBB) and the narrow-band blockers (NBB). The near blockers can be more than 40dB larger than the in-band signals. All these blockers must be properly dealt with, or they bring detrimentally can impact the receiver system performance. Forexample, the signal transfer function (STF) of the traditional CIFF-B continuous-time ADC has peaking, which amplifies the blockers and significantly reduces the dynamic range of the in-band signal. The zero-cancellation technique eliminates the peaking, while maintaining high power efficiency.

Hui Liu• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Mixed-Signal Design,

Delta-Sigma ADC

3.3 Wideband Continous-Time Delta-Sigma ADC for Wireless Communications

Related publication: L. Hui, X. Xing, and G. Gielen, “An 85-MHz-BW ASAR-Assisted CT 4-0 MASH Delta-Sigma Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS,” TCAS-I, July 2019.

Spectrum characteristics and signal transfer function of wideband ADC in wireless communications.

43

CMOS technology scaling results in higher switching speeds, which enables a finer resolution in the time domain. On the contrary, due to reduced supply voltages in scaled technologies, the dynamic range in the voltage domain decreases, resulting in an ever-decreasing signal-to-noise ratio (SNR). Therefore, in order to solve the design difficulties imposed by the digital driven technologies, time-based ADCs become more and more interesting.

A single-channel hybrid voltage-time two-step ADC that is both simple and low power is designed. The proposed ADC splits the full time domain conversion into two sub pipelined steps with 1-bit redundancy. As a result, the complexity of the TDC is reduced significantly. At the same time, the linearity requirements for the VTC are relaxed. The ADC combines the high accuracy of the voltage domain technique and the high speed and high efficiency of the RO based TDCs. Moreover, due to the use of time domain conversion, it is robust to low voltage operation and technology scaling. Fabricated in 28nm CMOS, the ADC achieves 39.9dB SNDR and 47.8dB SFDR at 4GS/s with a Nyquist input.

Yifan Lyu• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be• Research topics High speed analog-to-digital

converters, Time domain conversion

3.4 Hybrid Voltage-Time Two-Step ADC With Ring Oscillator Based TDCs

Related publication: Lyu Yifan, Tavernier Filip, “A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage–Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs”, in ESSCIRC 2019, Krakow.

Hybrid Voltage-Time Two-Step ADC With Ring Oscillator Based TDCs in 28nm.

44

High Performance ADCs are highly demanded in wireline/wireless communication systems. However the need for high speed is always accompanied by high power consumption and/or accuracy degradation since since analog devices with large bandwidth are needed or complicated techniques are utilized to achieve high speed. Benefits of technology scaling and the flexibility of digital circuits raise the challenges of implementing various ADC architectures with traditional brute-force analog techniques.

The first part of this research involved understanding the fundamental speed-limiting factors in SAR ADCs as a good base candidate. This understanding led to the proposal of novel circuit techniques to push the sample rate and bandwidth of medium resolution single-channel SAR ADCs beyond their architectural limits, while ensuring minimum performance degradation over the whole band of operation. The proposed techniques resulted in a 28nm CMOS prototype, achieving 7b, 1.25GS/s and 5GHz input sampling ability, with only 1.3dB SNDR degradation between low frequencies and Nyquist and a total of only 3.9dB degradation at Nyquist from its nominal quantization level (Ramkaj, ESSCIRC 2017, Ramkaj, JSSC 2018).

The second part of this research was to further introduce novel hybrid system and circuit techniques that would put the resolution in the equation, targeting high sample rate, high-resolution and low-power altogether, breaking the traditional speed-resolution-power barrier. A 28nm 5GS/s > 6GHz BW 12b CMOS prototype was realized with a FoMs of 160.5dB and a FoMw of 46.1 fJ/conv-step achieving at least 6.3dB better FoMs among ADCs with sample rate above 3GS/s, as well as 2.5x higher sample rate than the closest competitor with similar FoMs, redefining the state-of-the-art in RF ADCs (Ramkaj, ISSCC 2019, Ramkaj, JSSC 2020).

Athanasios Ramkaj• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. M. Steyaert, M. Pelgrom• Research topics High-speed/BW high-resolution A/D,

Analog/mixed-signal circuits, Ultra-wideband frontends

3.5 High-Speed/BW High-Resolution Hybrid CMOS ADCs for Wireline/Wireless Communication Systems

Related publication: A. T. Ramkaj, et al., ”A 5GS/s 156.8mW 9.4 ENOB Passive-Sampling Time-Interleaved 3-Stage Pipelined-SAR ADC with Analog-Digital Corrections in 28nm CMOS,” in ISSCC 2019 and JSSC 2020.

Die micrograph of the 28nm time-interleaved ADC chip with a zoomed-in sub-ADC layout view.

45

This work focuses on high speed Clock and Data Recovery (CDR) circuits. For very high data rates baud rate clock recovery is not possible as is it is limited by the speed of technology. Therefore quarter rate CDRs are used which recovers a clock at one fourth the data rate. In traditional quarter rate CDRs a delay line or an injection locked oscillator is used to generate multiple phases of the recovered clock for sampling the data in a time interleaved manner. A delay line or an injection locked oscialltor is not very wideband reconfigurable which goes against the goal of a wide range CDR. Instead we use a transmission line in the data path to generate multiple phases of the incoming data to be sampled by a single phased clock. The transmission line is sampled at multiple locations to get data and edge samples which are then used in a digital phase detector. To handle different data rates, only the input clock frequency is changed and the smaples going into the digital phase detector are multiplexed according to the data rate.

The implemented CDR is based on a phase rotator for NRZ data.In this project the designed tracking is continuous from 1Gb/s to 25Gb/s and at 100Gb/s. The performance has been verfied uptill 25Gb/s where as measurements are stll in progress to verify the operation at 100Gb/s.

Ibrahim Kazi• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be Prof. P. Reynaert• Research topics Delay Lines, CDR, Digital Intensive

3.6 Wide Range, High Speed Clock and Data recovery

Measurement setup for the CDR using a probe station.

46

Thin film electronic devices have traditionally been used in displays as a pixel switch. They are increasingly being considered as active devices to make more complex electronic circuits and systems for large area applications on flexible substrates. Many successful mixed signal circuit implementations have been reported recently. However, the main challenge in pushing the state of the art in a-IGZO TFT based circuit design is the lack of accurate device models for circuit simulation. As the semiconductor physics of a-IGZO differs significantly from the conventional Si-MOSFETs, the device model must first be elaborated in terms of fundamental device physics equations. Next, the parameters of the equations must be fitted from device measurements.

Simulations require both DC as well as AC modelling of the device. Although the DC model can be fitted well with Current-Voltage (IV) measurements, the AC modelling requires the knowledge of the 2-Port parameters of the device at various bias conditions. Measuring the 2-Port parameters (Y-parameters) is a challenge as it is very difficult to achieve the textbook conditions required to measure small signal voltage/currents on the two ports. Hence a method and measurement setup has been developed, to take a set of measurements that can be combined with some electrical network theory to estimate Y-parameters for a set of bias conditions over a wide frequency range.

With the set of measurements the physical equations can be fitted to yield an accurate device model that can be implemented in verilog-a and used along with commercial SPICE simulators for circuit simulation. With an accurate device model, the circuit simulation can predict the performance of the circuit/system being designed more accurately thus allowing us to make more complex circuits and systems pushing the state of the art.

Mohit Dandekar• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Amorphous Metal Oxide TFT, Large Area Electronics, Device Modeling, Circuit Design

3.7 Device Modeling and Circuit Design with a-IGZO TFTs

Related publication: “Flexlines Workshop Presentation”, 2019 Micro Nano Conference, Dec. 10, 2019, Utrecht - The Netherlands.

Fig. 1A - 2-Port Measurement Setup.

Fig. 1B - Layout of 70mm/5um TFT.

Fig. 1C - Common Source 2-Port.

47

Highly robust, compact and precise sensor systems are becoming increasingly important in many fields such as automotive. In order to fully take advantage of CMOS process scaling, time-based sensor readout interfaces have been explored as a valid alternative to the conventional amplitude-based solutions.

This research focuses on the design of a novel highly-digital area- and energy-efficient closed-loop time-based CMOS single-ended resistive-sensor-to-digital readout circuit. The architecture, shown in the figure, employs a single VCO and a digital feedback loop for the read-out of external single-ended resistive sensors such as an NTC thermistor. In addition to inherent 1st-order quantization noise shaping due to the oscillator, a second loop in SMASH configuration creates 2nd-order noise shaping, as shown in the measurement results in the figure below. Also the chip micrograph is shown.

Elisa Sacco• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Sensor readout interface, Mixed-

signal design, Highly-digital A/D converters

3.8 Design of Digital-Based High-Performance Analog Sensor Interfaces

Related publication: E. Sacco, J. Vergauwen and G. Gielen, “A 16.1-b ENOB 0.064mm2 Compact Highly-Digital Closed-Loop Single-VCO-based 1-1 SMASH Resistance-to-Digital Converter in 180nm CMOS,” proceedings IEEE ASSCC, 2019.

Resistive sensor readout block diagram, chip micrograph and measurement results.

48

Due to the ever ongoing miniaturization of electronics, they can be made small enough to be implanted in the human body while being only minimally invasive. Since the power readout systems is crucial and biosignals in general are sparse in nature (over time, the signals only vary sporadically), taking advantage of these properties may lead to both a reduction in data, as well as to a reduction in power consumption of the readout circuitry. In this research we investigate event-driven ADCs. This type of ADCs only takes a sample when there is a change in the signal (see Fig. 1b). By doing this, sparse signals will automatically be compressed and the power consumption of the readout circuits will depend on the signal activity. Today, event-driven ADCs are, however, not as power-efficient yet as the frequently used SAR ADC. This research aims at fully exploiting the asynchronous event-driven nature of the signals to reduce the power and area consumption of smart sensor interfaces.

Jonah Van Assche• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Sensor readout interfaces, Intelligent sensor interfaces,

Scalable analog circuits

3.9 Novel Circuit Architectures for Scalable and Adaptive Sensor Readout

Signal waveforms showing the difference between event-driven and standard signal sampling.

49

For large-coverage and high-spatiotemporal-resolution brain recording, the readout channel area needs to be significantly reduced while still maintaining low power and signal quality. AC coupling with pseudo-resistors has widely been used to try to achieve those requirements. However, pseudo-resistors are highly PVT-sensitive, have a very small linear range and even small leakage currents can lead to large offsets in the readout chain. Duty-cycled resistors have been proposed to relax some of those issues. Nonetheless, large passives are still needed to achieve a sub-Hz high-pass corner frequency. DC-coupling solutions with mixed signal-feedback were also explored, where the corner frequency is well-tuned in the digital domain. The main drawback of such approaches is the limited offset rejection, requiring large input dynamic range, resulting in significant power or area for the low-noise feedback DACs.

To leverage the simplicity of AC-coupled solutions, which inherently provide rail-to-rail offset rejection, the research investigates a reset scheme to bias the front-end input, overcoming the aforementioned issues. The proposed analog front-end shown below is implemented in a 22nm FDSOI process. It features an event-driven input biasing network, an incremental operation with reset timing control to minimize corrupted data samples, and a reconstruction block for signal post-processing. Avoiding the complexity of most conventional designs, the simple implementation of direct converstion achieves good trade-offs between power, noise, bandwidth and area.

Xiaohua Huang• Promotor Prof. C. Van Hoof chris.vanhoof@imec.be Prof. G. Gielen• Research topics Low-power low-noise circuit design

and system development for biomedical applications

3.10 Design of Ultra-Small-Area Low-Power Front-End in Scaled CMOS Technologies

(a) Gm & Cin

(b) CMFB

(c) Integration cap

(d) Comparator

(e) Feedback IDAC

Ultra-small low-power front-end for brain recording.

50

Current CMOS image sensors have a limited radiation tolerance owing to radiation induced degradation in the pixel dark current and noise levels which massively degrades the dynamic range of pixel intensity. This research aims to look at different ways to do radiation hardening by design, and to apply these techniques to image sensors in commercially available CMOS processes.

The goal is to develop active pixel sensor (APS) topologies and readout architectures with high total radiation dose tolerance and single-event latch-up immunity. Test pixels are designed in a 65nm CMOS process to characterize the radiation hardness of different photosensitive devices with varying layouts. To maximize the quantum efficiency of the devices, backside illumination will be employed, and the substrate of the chip will be thinned and passivated. Thermal annealing experiments will also be done to characterize the recovery from radiation induced damages.

Rico Jossel Maestro• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. P. Leroux• Research topics Radiation hardened electronics,

Image sensors

3.11 Radiation Tolerant CMOS Image Sensors

Layout of chip containing test pixels.

51

4. Computer Aided Design and Test

With a long research tradition in CAD tools and methodologies for design and test of ICs, MICAS investigates the entire span from modeling and simulation methods over circuit optimization and synthesis to reliability/EMC analysis as well as optimum test generation and design for testability. Exploiting classic and AI-based algorithms, both CMOS and emerging technologies are addressed.

54

With the increasing immersion of electronics in our society, more and more tasks depend on ICs. In some cases, such as in autonomous cars, absolute reliability of the circuits is crucial because human lives can be at risk. While recent developments have improved the fault coverage in the testing of mixed-signal integrated circuits, latent defects remain a serious problem that prevent the industry’s goal of reaching zero defect escapes. Such latent defects are already present in the ICs at the moment of fabrication, but do not cause a failure yet at time-zero production testing; unfortunately they become active after some time of usage in the field, causing undesired and jeopardizing failures. This research aims to develop new structures and techniques that allow the detection and the activation of latent defects at production test time without the need to initially (over)stressing the circuits for extended periods. To accomplish this aim, we have first developed a model for latent defects affecting the gate oxide of transistors. This model allows to simulate the effect of such oxide defects in the transistors. The model, as shown in the figure, predicts an effective gate oxide thickness and related device performance, that depends on the size of the defect.

Jhon Gomez• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Analog and Mixed-Signal Testing, Latent Defect Testing, Design for

Testability

4.1 Testing and Design for Testability of Latent Defects in Mixed-Signal Integrated Circuits

Effective gate oxide thickness versus the area and depth of the latent oxide defect.

55

Many safety-critical and mission-critical systems, such as airplanes or (semi-)autonomous cars, are relying on an ever-increasing number of embedded integrated circuits. Consequently, there is a need for complete defect coverage, which can be achieved by detecting hard defects and activating or detecting latent defects. Using the field of data learning, several techniques are used to achieve high coverage.

When testing circuits, a usual test bench contains several procedures to verify the designed operation of analog and mixed-signal circuits. However, due to the continuous nature of these circuits, only of part of the possible working conditions of the circuits is tested. This can mask certain hard defects, and latent defects are even harder to detect, as they only become a hard defect after an unknown amount of operational time. Using data learning, such as machine learning (ML) algorithms, it is possible to extract certain features and to use these to detect more defects at test time.

Nektar Xama• Promotor Prof. G. Gielen georges.gielen@kuleuven.be• Research topics Analog/Mixed-Signal Testing

& Verification, Automatic Test Generation, Latent Defect Testing

4.2 Data Learning-Based Defect Activation and Detection in Analog and Mixed-Signal Circuits

Flow chart depicting incremental measurements with ML (above), also showing how ML is used (below) to improve test coverage.

56

Quantum computing holds promise to solve complex computational problems that are intractable by classical computers. Superconducting circuits arranged in the circuit-quantum-electrodynamics (c-QED) configuration are the most advanced solid-state implementation of a qubit. Although proven to be mature for the implementation of basic quantum algorithms, it presents unique challenges in term of integration into a large array of qubits necessary for error correction. The aim of the research is to provide the necessary inputs for the development of a first compact model of a qubit device. The first part of the work involves basic material and device characterization of superconducting circuits that consist of Josephson junctions and microwave resonators. The second part of the work focuses on the development of a simulation platform that captures the electrodynamics of the circuit.

Rohith Acharya• Promotor Prof. G. Gielen georges.gielen@kuleuven.be Prof. F. Catthoor• Research topics Quantum Computing, Super-

conducting Qubits, QED, Circuit Quantization, Compact Modelling

4.3 Characterization and Modelling of Superconducting Qubits

57

58

5. Digital circuits

59

Digital design at MICAS spans from transistor-level memory design, over custom near-threshold standard cell libraries, to architecture level design on configurable data paths and processors, and this in CMOS as well as in thin-film technology.

60

Recent workloads like neural nets have pushed towards novel hardware architectures to keep performance in check with energy constraints. One of these promising new concepts is a streaming processor, which organizes applications explicitly into streams of data records processed by hardware kernels. By providing a deep reconfigurable pipeline, it efficiently performs compute-intensive tasks while minimizing memory bandwidth.

In 2019, this research further developed a streaming processor with a 2D network of Processing Elements. The design extends earlier research with complex operations and scalable bit resolutions to widen the application range. This allows the new processor to map and concatenate a wide range of kernels found in typical signal processing applications (e.g. matrix-vector products, FFT, convolutional filters…). The processor, implemented in a 28nm technology, is expected to demonstrate significant throughput and energy efficiency improvements over the state-of-the-art.

Sander Smets• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be Prof. T. Goedemé• Research topics Processor design, Digital

accelerator design, Signal processing

5.1 Streaming processing for energy-efficient signal processing

Schematic representation of the streaming processor.

61

Amorphous metal-oxide semiconductors are the main materials enabling thin-film transistor (TFT) technology for large area and flexible electronics. The main properties of this technology making it succesful in the display and imager industry are its lower cost per area and ability of being realized in larger substrate sizes. Furthermore, designing more complex digital and analog circuits has become possible on flexible substrates. In this project, design methods for logic cells as well as high level digital circuits with this n-type only technology are investigated for applications with low power, low cost and high performance.

Different standard cell topologies are investigated. One of the most promising approaches is using a diode-connected load TFT. The second terminal (back-gate) of TFT to control the transistor channel helps to tune threshold voltage. For benchmarking performances of different logic topologies; inverters, ring oscillators and some digital circuits are implemented, e.g. 4-bit adder.

The standard transistor channel length for this technology is 5µm. In order to investigate the scaling limits, digital arithmetic blocks have been designed with shorter channel lengths of 0.8µm and 2µm. Performance analysis of these blocks is helpful in characterization of standard cell libraries which is the key step for digital design flow in the process design kit (PDK). The roadmap of the project is to realize complex VLSI circuits on flexible substrates (e.g. 8-bit microcontroller) by improving the PDK for digital blocks in parallel with the further technology optimizations such as lithography and better semiconductor materials.

Hikmet Çeliker• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be K. Myny• Research topics Thin-film transistors, Digital design,

Standard cell libraries

5.2 Thin-Film Logic Families for VLSI Circuits on Plastic

Die photo of adder.

62

In recent years, the demand for ultra-low power applications has conspicuously grown, powered by the emergence of Internet of Things. In digital integrated circuits design, ultra-low voltage operation has become a very promising method for this purpose. Nevertheless, the ultra-low supply voltage aggravates notoriously the sensitivity to intra-die variations, especially in advanced nm scale technologies.

Traditional digital flows design for the worst-case corner, and apply on top timing derating factors to capture the inter- and intra-die variations. This mechanism when considering the high variation susceptibility becomes too simplistic resulting in significant energy overhead. In-situ time monitoring allows eliminating this additional margin, operating at or near the Point of First Failure (PoFF). However, the substantial timing spread also complicates the critical path identification, since nominally sub-critical paths may become critical when variation is taken into account.

This research delves into in-situ warning detection, error detection and error correction, the latter through time borrowing techniques. After the evaluation of the critical path candidates, the proposed tool automatically designs and integrates the most suitable monitoring strategy according to the requirements and relevance of each critical path. The resultant configuration avoids jeopardizing the operation of following stages and finds the best trade-off between the margin reduction and the monitoring overhead.

Clara NietoTaladriz• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Low-voltage operation, Variation

resilient, Timing-error detection and correction

5.3 Ultra-low voltage variation resilient digital circuit design

Simplified timing diagram of the evaluated in-situ timing monitorization strategies.

63

Today’s versatile application spectrum of battery powered electronic devices demands energy efficient microprocessors across a wide performance range. To that end, our research focuses on the implementation of these devices at ultra-low supply voltage in the near/sub-threshold domain. In this domain, the energy benefits associated with voltage-scaling reach their optimum in the minimum energy point or MEP. This is illustrated below by the measurements of a RISC-V microprocessor implemented in near/sub-threshold. Nevertheless, low voltage operation increases the systems sensitivity to PVT variations and therefore enforces large and inefficient safety margins to ensure reliability. To counteract the energy losses caused by these margins, a novel timing-error detection and correction (EDaC) technique is being developed. This technique avoids the additional hold-constraints inferred by the conventional EDaC systems. Early measurements show that it can remove nearly all voltage margins.

Roel Uytterhoeven• Promotor Prof. W. Dehaene wim.dehaene@esat.kuleuven.be• Research topics Energy efficient digital circuits,

Sub-threshold, Voltage-scaling, Timing-error detection

5.4 Energy efficient digital circuits through near/sub-threshold operation

Related publication: Giraldo J., Verhelst M., “LAIKA: A 5uW Programmable LSTM Accelerator for Always-on Keyword Spotting in 65nm CMOS”, IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germa

Related publication: R. Uytterhoeven and W. Dehaene, “A sub 10pJ/Cycle over a 2 to 200MHz Performance Range RISC-V Microprocessor in 28nm FDSOI,” IEEE European Solid-State Circuits Conference, Dresden, Germany, 2018.

Energy and voltage scaling measurements of the RISC-V microprocessor implemented in FDSOI 28nm.

64

In deep submicron chips for ultra low energy applications, leakage is the dominant component in the energy budget. A straightforward approach to reduce leakage is power gating. However, this is only possible for logic circuits, not for memories, as these would loose the data stored. This work reduces leakage in 6T-SRAM memories in FDSOI technology using two techniques: (1) supply reduction and (2) design margin reduction with bulk biasing.

The memory is partitioned into local blocks (LB) to reduce the parasitic capacitance on long bit- and wordlines, ensuring low energy read and write. This local block architecture can be exploited further: memory activity is situated in one local block. Hence, all other local blocks can be placed in deep sleep retention, with a reduced supply. Since local blocks are small and access times are relatively long, it is feasible to take a single local block out of retention within a fraction of an access cycle.

To guarantee correct retention, memories are designed with a hold margin. Due to the large number of memory cells, this margin becomes very large. However, by tuning each individual local block, containing only a small number of cells compared to the entire memory, the hold margin can be reduced. This requires a cell monitor and tuning facility within each local block. The hold margin is measured on one inverter inside each replica memory cell. For each inverter, the transient switching characteristic is measured using a DC sweep. Each local block contains 32 of these monitor replica cells, which are used to estimate the cells hold margin of that block. The local block is then tuned by selecting one of the two bulk biases.

The prototype is a 1-10MHz SRAM of 1Mbit, comprising 256 local blocks, each with 128 words of 32 bits. This prototype is the result of an ultra low energy RAM generator under development.

Bob Vanhoof• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics SRAM design, SRAM macro design, Ultra low energy design, Variation

resilient design

5.5 Ultra Low Energy SRAM in 22nm FDSOI using local block level cell monitoring and tuning

Each LB of the proposed memory contains 32 replica cells and can be tuned on one of 2 biases.

65

Indium-gallium-zinc oxide semiconductor FET(IGZO-FET) was fabricated showing the extremely low off-state current level ~aA (1X10-18) at off-state. IGZO-based 2T0C composed of only two transistors which can be implemented with single Vth is presented. We built verilog-A compact modeling for IGZO-FET and some Figure-of-merits are suggested to quantize simulation results for memory bit cell toward DRAM application. Under single-Vt condition between read and write transistor, less than 10ns read latency supported by 1V internal voltage, more than 100ms retention time at the 10aF assumed parasitic capacitance of storage node powered by negative word-line voltage and DRAM-comparable block density can be expected from circuit simulation, leading to tackle the imminent hurdles of current DRAM scaling-down.

Conclusion: Toward DRAM application, IGZO-based 2T0C memory device’s circuit simulation was explored targeting for single-Vt implementation in this work. With 0.55V of threshold voltage of read/write transistor, read operation achieved read latency of 8.9ns enabling ~3uA read current per cell at the DRAM-comparable Block array density. In addition, simulated retention time at this condition is expected to have ~ 532ms supported by negative write word line (WWL) of -0.5V. These values are promising for DRAM application in terms of Key index.

Oh Hyungrock• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Single-Vt exploration on 2T-based

IGZO-memory for DRAM application

5.6 In-Ga-Zn-Oxide based 2T0C gain-cell memory using single-Vt for DRAM application

(Fig. 4) (a) schematic (b) layout of 2T0C bit cell.

6. Machine learning

Among the first research labs that started to design custom processors for deep neural networks, MICAS still surfs on the forefront of the new artificial intelligence wave. Research expands further towards alternative emerging learning paradigms, as well as emerging implementation technologies.

68

The use of speech-triggered interfaces in mobile and wearable devices has increased in the last years, allowing the user to leverage natural speech to control electronic products. Popular commercial voice assistants like Siri or Alexa use one or more keywords for the activation of the natural language query system, allowing to reduce expensive cloud accesses while providing always-on operability. The rise use of this technology is coupled with the recent emergence of complex machine learning models which provide high accuracy for AI tasks. Nevertheless, the complexity associated with such algorithms is in conflict with the constrained energy budget of embedded systems.

In this research, we have developed a fully-integrated near-microphone keyword spotting and speaker verification solution, capable of directly interfacing with a microphone and not requiring any external memory. Hierarchical machine learning is applied by creating a cascade of tasks, allowing to activate the different machine learning accelerators and preprocessing units only when they are needed. As such after an always-on sound detector detects sound, it activates a Long Short-term Memory (LSTM) accelerator in charge of spotting one or more keywords. Right after keyword detection, a Gaussian Mixture Model (GMM) accelerator is turned on to verify the identity of the speaker. The resulting 65nm SoC carries-out speaker-specific keyword triggering, while only consuming 10.6μW average or 18.3μW peak for real-time operation, or 10x below speaker-agnostic keyword spotting SotA. The use of a single-chip solution, memory and power optimized accelerators, as well as hardware-aware algorithmic tuning, allows reducing significantly the power required for real-time operation.

Sebastian Giraldo• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Machine learning, Computer

architecture, Digital Design

6.1 Hardware acceleration of machine learning algorithms for ultra-low power keyword spotting

Related publication: Giraldo, JS P., Steven Lauwereins, Komail Badami, Hugo Van Hamme, and Marian Verhelst. “18μW SoC for near-microphone Keyword Spotting and Speaker Verification.” Symposium on VLSI Circuits (VLSI), Kyoto, Japan, 2019.

System overview of speech-triggered SoC and chip photo.

69

The push for miniaturization of IoT systems demands smaller batteries and hence more power efficient sensor systems. This work focuses on adaptive μW multi-sensor systems, that enable an agent to target data that contains valuable information over a long period of time, while consuming minimal energy.

This is achieved through a combination of low power flexible hardware and programmable agent adaptive behavior, which recognizes data of interest and records it with the required signal quality. A Behavioral Tree expresses this optimal adaptive behavior. Online, the Behavioral tree checks sensor data features regularly and adapts the flexible settings (eg. sensor on/off, sample frequency, compression harshness, …), based on the statistics of the incoming data. This behavior is first trained offline. An Evolutionary Algorithm evolves Behavioral Trees, based on a power-performance model of the complete agent, and a previously gathered representative sensing scenario and converges to an optimal tree.

Fig.1 shows the overview of the system concept of the flexible sensor system in combination with the offline behavioral optimization loop.

Jaro De Roose• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Low power digital hardware, Flexible

sensing, Automated optimization

6.2 Ultra low power sensory agents through runtime instincts

Related publication: De Roose J., Xin H., Andraud M., Harpe P.J.A, Verhelst M., “Flexible and self-adaptive sense-and-compress for sub-microWatt always-on sensory recording”. ESSCIRC september 2018 p. 282-285.

System overview with all adaptive settings.

70

Smart portable applications increasingly rely on edge computing due to privacy and latency concerns. But guaranteeing always-on functionality comes with two major challenges: heavily resource-constrained devices; and dynamic application conditions. Probabilistic models present an ideal solution to these challenges: they are robust to missing data, allow for joint predictions and have small data needs. In addition, ongoing efforts in the field of tractable learning have resulted in probabilistic models with strict inference efficiency guarantees.

This research targets the development of hardware-aware machine learning frameworks, which capitalize on the desirable attributes of tractable probabilistic models (such as Arithmetic Circuits and Sum-Product Networks) to encode the device’s hardware properties and constraints from the algorithm level of abstraction. Coupled with efficient local optimization strategies, these frameworks allow the user to select the device settings that meet application requirements and constraints. Showcased on a variety of machine learning benchmarks, including a human activity recognition application, the proposed strategies have shown the potential to achieve significant energy consumption savings with minimum accuracy losses.

We are currently developing a tuning strategy that can dynamically select the optimal device settings to meet real-time user needs.

Laura Isabel Galindez Olascoaga• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Probabilistic models, Arithmetic Circuits and Sum-Product

Networks, Hardware-awareness

6.3 Hardware-aware machine learning

Hardware-aware tractable learning scenario on a human activity recognition use case.

Related publication: Laura I. Galindez Olascoaga, Wannes Meert, Nimish Shah, Marian Verhelst, Guy Van den Broeck, Towards Hardware-Aware Tractable Learning of Probabilistic Models, in Proceedings of Advances in Neural Information Processing Systems 32 (NeurIPS), 2019.

71

Deep Learning has achieved remarkable performance in several perception tasks like computer vision, speech recognition etc. However, it still struggles with higher-level reasoning tasks, due to its inability to handle uncertainties and constraints of a system. Hence, hybrid models are being developed by combining DL with probabilistic-logic reasoning techniques. The focus of this work is the efficient execution of one such model called Sum-Product Networks (SPNs), which is a network with sums and products that can encode probabilistic relations of a system.

Unfortunately, unlike DL, SPN does not lend itself to trivial vectorization because of its irregular graph structure. We propose an efficient VLIW-like SPN processor to handle this irregularity efficiently. It consists of multiple trees of processing elements (PE) that communicate to banked register files, via a crossbar. A custom compiler is developed to efficiently map any SPN to the processor while minimizing register bank conficts.

Nimish Shah• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Digital design, On-chip machine

learning, Computer architecture

6.4 Efficient processor for Sum-Product Networks

Related publication: N. Shah, L. Galindez, W. Meert, M. Verhelst, Acceleration of Probabilistic Reasoning Through Custom Processor Architecture, DATE 2020 Proceedings (To Appear).

Flow from SPN generation to execution.

72

Embedded applications of CNN inference on high-resolution images, such as in camera pipelines, autonomous vehicles and satellite imagery, require a hardware-software combination that provides high performance within the tight accelerator area and power constraints.

These constraints e.g. severely limit both the available off-chip IO bandwidth and the on-chip available cache memory. This makes CNN inference in a classic layer-by-layer approach unfeasible: the IO or cache cost of high-resolution feature maps would be too high. Therefore, CNN inference requires a depth-first approach, which propagates data as soon as possible, limiting the amount of data to be stored simultaneously. Furthermore, to achieve good inference quality and performance, good support for compute efficient CNN constructions like depthwise-pointwise pairs and ShiftNet is also required.

In 2020, we will tape-out an accelerator supporting all of the above, enabling embedded CNN inference on high-resolution images.

Koen Goetschalckx• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Machine learning, Neural networks,

Digital accelerators, Computer vision

6.5 Depth-first CNN inference for efficient high-resolution imagery

Related publication: Koen Goetschalckx, and Marian Verhelst. “Breaking High Resolution CNN Bandwidth Barriers with Enhanced Depth-First Execution.” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2019).

Scheduled ASIP features overview.

73

Pixel processing algorithms for denoiseing, demosaicing or segmentation increasingly make use of CNNs. However, deploying these algorithms on high resolution images, require lots of calculations, making their embedded implementations challenging. The scope of this research is to develop and combine various efficiency enhancement techniques through careful hardware-algorithm co-optimization. Specifically, depth first execution is used to minimize the amount of IO communication, while dynamic, data-dependent, pruning automatically adjust the network for every single input patch.

The figure underneath shows a CNN with two intermediate layers of 64 channels, which are dynamically pruned in 4 groups of 16 channels. A trained, NN-based, decision block dynamically (de)activates groups, to optimize the accuracy - speed trade-off on a patch-by-patch basis. As this principle benefits from small patch sizes, dedicated hardware will be developed to efficiently support this dynamic pruning.

Steven Colleman• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Processor design, Machine learning

Algorithm improvement

6.6 Acceleration of pixel processing CNNs

Dynamic pruning based on input features.

74

The current trend of deep learning (DL) has come with an enormous computational need of billions of Multiply-Accumulate (MAC) operations per inference. Fortunately, reduced-precision computing has demonstrated large efficiency benefits with low impact on accuracy, paving the way towards DL processing in mobile devices and IoT nodes. To this end, various run-time precision-scalable MAC architectures optimized for neural networks have recently been proposed. This research categorized the SotA reduced-precision MAC architectures according to the type of unrolling (spatial or temporal), unrolling dimensions (1D, 2D or 2D symmetric) and accumulation scheme (Sum Together or Sum Apart). Each distinct type was subequently implemented to perform a detailed benchmarking and comparison of these architectures towards identifying the achievable tradeoffs in the vast design space.

Linyan Mei• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Deep learning accelerator, HW-algorithm co-optimization, Scalable architectures

6.7 Precision-scalable MAC architectures for embedded DL processing

Related publication: V. Camus*, L. Mei*, C. Enz, M. Verhelst, “Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing,” in IEEE JETCAS, 2019 (* co-first authors).

Collection of some benchmarked run-time precision-scalable MAC architectures.

75

Embedded Deep Learning (DL) has gained a lot of attention nowadays due to its broad application prospects and vast potential market. To meet the tight energy budget of edge devices and at the same time allow them to deliver sound performance, the embedded DL system needs to be carefully designed. One of the biggest challenges that designers are now facing is to deal with the huge design space. At algorithmic level, the topology of the network, the size of each layer, the precision of computation,etc. can vary largely even when targeting a specific application and required accuracy. At hardware level, the memory system and the Processing Element (PE) array can also vary a lot even when accelerating the same algorithm. On top of that, given the same algorithm and hardware, there are still many possible mapping and scheduling options. Due to the many degrees of freedom, it is infeasible to manually try out all possible combinations. Thus, a rapid algorithm-hardware design space exploration tool is required to help designers make fast decisions and build optimum systems effectively. The regularity and determinism of DL workloads enables us to develop such a framework, which includes a nested-loop based hardware-aware analytical cost model and an exhaustive-search-based schedule generator for now. With different working modes, this framework is capable of helping DL researchers design more hardware-friendly algorithms, helping hardware designers fix design parameters more easily, and helping compilers to find the best mapping scheme.

Linyan Mei, Pouya Houshmand• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Embedded deep learning, Design space exploration

6.8 Rapid hardware-algorithm design space exploration framework for embedded DL

Concept of the hardware-algorithm co-exploration framework for embedded deep learning.

76

The main focus of the research is the exploration of a combination of digital accelerators and analog in-memory-computing (AiMC) solutions for neural network processing in a single system-on-chip.

The data movement across different levels of memory required to carry on the inference in a neural network represents the highest cost in terms of power and delay and affects greatly the performances of the accelerators. Analog in-memory-computing addresses this major issue: given the 2D matrix disposition of the bit cells, the possibility to execute matrix-vector multiplication inside the memory array arises, enabling massive parallel computation at very low cost. Yet, not all neural network workloads map well on such an analog array, as this is strongly dependent on the array architecture and the network layer topology.

In order to maximize the performances of such neural network processing, a mixed signal computing system will be able to choose analog or digital execution. A software framework is developed for the exploration of the design space to develop the most efficient mixed-signal hardware architecture, taking into account all the parameters that may impact its performances such as ADC/comparator characteristics, intrinsic parasitic effects, noise and quantization errors. The framework must moreover be able to optimize how the data transfer between different memory levels and the analog/digital processing core occurs, and exploit the right accelerator for different parts of the workload.

The final goal is to be able to compare with which workloads an AiMC solution is better than a purely digital one so that a processor with both solutions will be able to adapt its workload and assign throughout the calculation the optimal type of computing and the correct amount of resources.

6.9 Exploring mixed-signal NN accelerators

Basic AiMC structure.

Pouya Houshmand• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics In-memory-computing, Neural

network accelerators, Emerging technologies

77

Memory bandwidth and data flow are the leading factors in the energy versus performance trade-off of CPUs, GPUs and NPUs. Furthermore, there is a trend to push deep learning from cloud to edge for reasons of privacy and energy efficiency. To realise the required energy efficiency and latency, technology scaling is definitely part of the solution.

This work investigates the energy benefit of digital computation for neural networks in memory with technology scaling. We consider a near memory computing digital architecture, using SRAM to enhance both energy efficiency and throughput by reading multiple blocks per read cycle and by embedding addition block into the periphery of the bit-cell array (Fig. I). This architecture is designed in 28nm standard CMOS. The Energy and area benefit with respective to technology scaling is shown in Fig.2. The energy efficiency of the proposed architecture is improved by 11 times compared to previous designs.

Mohit Kumar Gupta• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Memory design, Digital Circuits, Machine learning, In memory

computing

6.10 Scaling study of Digital Compute in Memory

Prediction based data compression.

78

Predictive Maintenance techniques for Industry 4.0 are used as an efficient mechanism for early prediction of failures in machines and storage units which can then be flagged for maintenance and failure prevention. In general, sensor data collected at the edge is transmitted to cloud where different machine learning (ML) algorithms are applied. However, transmission of data over long haul results in high power dissipation. This can be prevented by moving the computation closer to the sensor. In our work, a system-on-chip capable of performing machine learning at the edge will be designed and implemented with ultra-low power consumption at relatively good performance. The target ML models include, but not limited to, deep learning models like Convolutional Neural Network (CNN), Fully Connected (FC), Autoencoders, Recurrent Neural Networks (RNN), and traditional ML models like OC-SVM, isolation forests, etc.

The hardware design for the ADS consists of two main units; RISC-V processor and unified ML accelerator as shown in the figure below. RISC-V processor will act as the central control unit for data movement, it will also be used for interfacing to peripherals and to generate handcrafted features like FFT, MFCC, ABS, etc. The processor also provides the SoC with flexibility and programmability making it capable of running multiple ML models. The unified ML accelerator will be the main computation unit which will execute Matrix Matrix/Matrix-Vector multiplication, the basic compute of ML algorithms. Other power optimization strategies like structured sparsity and precision scalability will also be supported.

6.11 Energy-efficient System-on-Chip for Predictive Maintenance

Architecture if the envisioned SoC for predictive maintenance.

Vikram Jain• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Machine learning accelerator, Ultra-low power, Predictive Maintenance

79

Convolutional neural networks (CNNs) have emerged as State of the Art algorithms to implement image processing applications. Yet, CNN’s are usually run on power-hungry high-precision and high-performance CPU’s or GPU’s. This work enables the execution of compute intensive CNNs, like the Yolo network, on embedded systems. This is achieved through1.) Lower precision operation, enabled by a quantization-aware NN training framework. This allows to generate 8-bit, 4-bit and even mixed-precision network realizations, with minimal accuracy loss.2.) An output stationary low-power FPGA implementation, maximizing feature reuse for memory bandwidth optimization and energy optimization.

Both techniques are integrated in a demonstrator achieving real time execution of Tiny-YOLO, a single-shot object detection network.

Ninad Jadhav• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Quantization aware training, Hardware for machine learning

6.12 Training and implementation techniques for efficient embedded neural network processing

80

7. Biomedical systems

81

Biomedical implants form a long term flagship in MICAS’ research applications, merging low power design, micro fabrication and 3D packaging and interconnects. Recently, focus is on flexibility for comfortable monitoring.

82

Two unobtrusive sensing techniques are evaluated: capacitively coupled sensing of the electrocardiogram and respiration, and radar-based sensing of heartbeat and respiration. A challenge for use of these techniques in vehicles are the vibrations and other disturbances that occur in vehicles to which they are inherently more sensitive than contact-based sensors. In this work, optimized sensor architectures and signal processing techniques are proposed that significantly improve the robustness to artefacts.

Experimental results, conducted under real driving conditions on public roads, demonstrate the feasibility of the proposed approach.

Ivan Castro• Promotor Prof. B. Puers bob.puers@kuleuven.be Prof. C. Van Hoof• Research topics Contactless ECG,

Electrocardiography, Unobtrusive health monitoring, Wearable sensors

7.1 Robust non-contact physiological measurements

Related publication: I. Castro, M. Mercuri, A. Patel, R. Puers, C. Van Hoof, T. Torfs, “Physiological Driver Monitoring Using Capacitively Coupled and Radar Sensors, Applied Sciences, MDPI, 2019, 9, 3994, (15p); doi:10.3390/app9193994.

Capacitive sensor system installed in a car used for the on-road evaluation.

83

Parylene-C is a biocompatible and biostable polymer. A very thin layer provides an excellent barrier against the diffusion of water and the corrosion resistance required by all medical implants. However, when exposed to the blood flow, Parylene-C initiates a complex series of events that begins with the adsorption of plasma proteins and can, through the adhesion and activation of platelets, lead to the formation of blood cloths.

Surface nanostructuring of Parylene-C allows to tune the adsorption of proteins from the human blood and improve its blood compatibility. The polymer was modified by consecutive low power O2 and SF6 plasma treatments. The induced physical and chemical modifications, yield superhydrophobic surfaces, with static contact angles as high as 158°. The proposed treatment improves the performances of Parylene-C as a moisture and ions barrier. Protein adsorption tests, and in-vivo experiments suggest good blood compatibility of the treated material.

The simplicity of the deposition process, and of the proposed modification technique, make it of great interest for coating implants chronically exposed to the blood flow, like vascular stents or blood pressure sensors for the direct measurement of arterial pressure, with complex geometries.

Luigi Brancato• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Biocompatibility, Packaging, Soft

and stretchable polymers

7.2 Surface Nanostructuring of Parylene-C for Blood contacting implants

Related publication: Brancato L., Decrop D., Lammertyn J. and Puers R., “Surface Nanostructuring of Parylene-C Coatings for Blood Contacting Implants”, Materials 2018, 11(7), 1109.

Static contact angle of DI water and blood on Parylene-C before and after plasma treatment.

84

Traditional methods of assessing bladder function are based on intraluminal pressure measurements through a catheter, urine flow and volume measurements. These methods are quite limited in their scope, as they provide only a global measurement and no localized bladder information. To obtain a better understanding of the fundamental bladder mechanics, a new method for assessing bladder functionality is explored.

A fully implantable wireless system was developed that monitors acceleration and pressure in the bladder wall. A flexible printed circuit board has been designed for this application, featuring multiple commercially available accelerometers and pressure sensors, along with a wireless communication and power board. The battery-powered system was implanted in pigs and gathered data of several voiding events, which was compared to catheter pressure measurements.

Tristan Weydts• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Implantable systems, Sensor

networks, Urology

7.3 Implantable sensor network for monitoring the bladder wall

Related publication: Weydts T., Brancato L., Soebadi M.A., De Ridder D., Puers R., A novel method to investigate bladder wall behavior by acceleration and pressure sensing. Sensors and Actuators A: Physical; 2018; Vol. 280; pp. 376 - 382.

A. Fabricated implant. B. Placement sensors on bladder. C. X-ray image of implanted device.

85

In the quest for chronically reliable and bio-tolerable brain interfaces there has been a steady evolution towards the use of highly flexible, polymer-based electrode arrays. The reduced mechanical mismatch between implant and brain tissue has shown to reduce the evoked immune response. Unfortunately, the low stiffness of the implants also has practical repercussions, making surgical insertion extremely difficult. In this work we explore the use of dextran as a coating material that temporarily stiffens the implant, preventing buckling during insertion.

Tuning parameters, such as coating thickness and molecular weight of the used dextran, allows customization of the stiffness and dissolution time to precisely match the user’s needs. Finally, the immunological response to the coated electrodes was analyzed by performing a histological examination after four months of in vivo testing. The results indicated that a very limited amount of glial scar tissue was formed. Neurons have also infiltrated the area that was initially occupied by the dissolving dextran coating. There was no noticeable drop in neuron density around the site of implantation, confirming the suitability of the coating as a temporary aid during implantation of highly flexible polymer-based neural probes.

Dries Kil• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Neural engineering,

Microfabrication, Flexible electrodes, Resorbable coating materials

7.4 Dextran as a resorbable and mechanically stiff coating for flexible neural probes

Related publication: D. Kil, M. Carmona, F. Ceyssens, M. Deprez, L. Brancato, B. Nuttin, D. Balschun, R. Puers, “Dextran as a resorbable coating material for flexible neural probes”, Micromachines, MDPI, 2019, 10, 61, (15p); doi:10.3390/mi10010061.

Confocal imaging of the brain slices (a-c) and neural density relative to site of implantation (d).

86

Recent advances in implantable neural interfaces are converging towards close co-integration of CMOS front-ends with flexible neural probes for simultaneous maximization of channel count and biocompatibility in ever-smaller device dimensions. To address these demands, a new neural recording chip developed at MICAS integrates 128 transimpedance neural amplifiers with A/D conversion and auxiliary circuitry to minimize number of external components. Digital logic is further implemented on a miniature ICE40 ultra FPGA, and the whole system requires only 4x6.5mm of PCB footprint along with two micro-coaxial cables for power and data. The system was tested in small scale with up to 8 channels with invertebrate neural preparations, and work on full-scale interconnects and testing in rodents is underway.

Marko Bakula• Promotor Prof. B. Puers bob.puers@kuleuven.be Prof. M. Kraft• Research topics Implantable electronics, Chip

design, Flexible electrodes, High density interconnects

7.5 Integrated CMOS and flexible probe neural microinterfaces

The system’s architecture.

87

Neurological disorders have an adverse impact on the life of nearly 1 billion individuals. Appropriate solutions can be found by performing electrophysiological experiments with animal models, and studying the interactions between individual brain cells. Furthermore, therapies like deep brain stimulation are applied to suppress tremor in Parkinson’s disease. Current silicon-based probes encounter several problems: 1) limited long-term neural interfacing due to the mechanical miss-match with brain tissue, 2) targeting distributed deep brain regions simultaneously and, 3) application to the spinal cord or peripheral nerves is difficult. Those problems will be addressed by developing an active ultra-flexible high-density electrode array for recording and stimulating individual brain cells within distributed brain regions in freely moving animals.

This project is funded by a Baekeland mandate and includes the following partners: ATLAS Neuroengineering, MICAS and NERF.

Rik van Daal• Promotor Prof. M. Kraft michael.kraft@kuleuven.be Prof. F. Kloosterman, Dr. A. Aarts• Research topics Neural implants, Micro- and

nanoscale fabrication, MEMS

7.6 Active ultra-flexible, high-density probes for chronic deep brain neural interfacing

Related publication: van Daal R. et al., “System for recording from multiple flexible polyimide neural probes in freely behaving animals”, 2020 - van Daal R., “Next generation brain implant for distributed recordings of cellular activity in freely behaving rodents”, 2018.

Flexible probe with 16 platinum electrodes and positioning mechanism for 16 probes.

88

Next generation implanted medical devices (IMDs) include the ingestible endoscopic capsule, the retinal prosthesis and closed-loop multi-sensor systems. These devices need to communicate over larger in-body distances, at high data rates and increased reliability, all within a limited energy budget. These specifications are impossible to achieve using the current technology of electromagnetic (EM) wave propagation, due to the water-like environment of the human body. As an alternative, we perform research on ultrasound (US) wave propagation, which poses a lower in-body attenuation at reduced health risks.

We constructed an ultrasound in-body mimicking test setup employing small-scale, omnidirectional transducers and a custom Tx and Rx PCB front-end for amplification and filtering purposes. Using this test setup, multiple channel FIR models on different media were extracted. A resulting multipath delay spread of 40..150us was derived, which corresponds to a coherence bandwidth of 5kHz. To achieve reliable communication, we utilized an OFDM modulation scheme where its parameters are optimized to the knowledge from the channel experiments. In the static beef setup, we were able to establish a US link at 340kbps, BER < 1e-4, 4-QAM subcarrier modulation over a 10 cm long beef channel. In order to achieve BER < 1e-4, the US transducer was actuated with 320mVpdd, corresponding to -24dBm transmit power.

Thomas Bos• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be Prof. M. Verhelst• Research topics In-body communication, Ultrasound

channel modelling, Digital transceivers

7.7 Ultrasound wave communication through the human body

Related publication: Bos T., Dehaene W., Verhelst M., “Ultrasound In-Body Communication with OFDM through Multipath Realistic Channels.”, in Proceedings of 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), doi 10.1109/BIOCAS.2019.8918755.

Custom Tx-Rx chain for small-scale US transducers to design large-distance in-body communication.

89

Electrochemical processes form the basis of many sustainability-related applications, such as wastewater treatment, corrosion monitoring and bio-sensing. Electrochemical reactions are intrinsically complex and slow. Therefore, the R&D in this field requires many time-consuming and cumbersome research experiments. In this project, a micro-electronic integrated system is being developed to sense and stimulate electrochemical processes in a highly efficient and automated way, by implementing a high amount of parallel but individually controllable channels, allowing fast characterization and individual stimulation.

A 64-channel prototype has been developed and tested, which can stimulate current in a wide range of 1pA – 1µA and perform cyclic voltammetry on the targeted chemical reaction. To support the necessary user cases, an improved integrated system is being designed with 1000 parallel channels and the ability to perform both cyclic voltammetry and impedance spectroscopy.

Li Peishuo• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be• Research topics Bioelectrochemical system,

Analog and mixed signal circuits, Control theory

7.8 A Multi-channel CMOS Potentiostat for Monitoring Bioelectrochemical System

Related publication: P. Li, T. R. Molderez, F. Ceyssens, K. Rabaey, M. Verhelst, “A 64-channel, 1.1-pA-accurate On-chip Potentiostat for Parallel Electrochemical Monitoring”, in Proceedings of ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference.

Measurement setup and results (bottom), system architecture (top left) and chip micrograph (top right).

90

Urinary incontinence is a significant health issue with high social and economic impact on society. Existing state-of-the-art therapeutic devices offer continuous but blind open-loop stimulation, not reacting on specific physiological events. This research focuses on the low power electronics design to enable a closed-loop measuring and stimulation system.

The envisioned system is shown below. Multiple sensor nodes communicate wirelessly with a control unit, which drives a neurostimulator. The control unit intelligently decides when to stimulate from the extracted features. To achieve low power, an ASIC will be designed. There are two main objectives. 1) Reliable and low-power continuous measurement of bladder physiological signals. 2) Smart pattern recognition and task hierarchy to avoid unnecessary activation of higher decision systems in the always-on stimulation loop.

Previous bladder monitoring research at MICAS has shown that communication prevents reducing the power budget, and hence enabling long-term operation. Conventional RF radios suffer from strong attenuation due to tissue absorption. The magnetic near-field channel, however, is an interesting alternative which does not degrade significantly from the presence of tissue. The classic solution of adding uplink communication to inductive powering using Load Shift Keying, does not achieve the targeted data rates for deep implants tough. Furthermore, it does not allow for node-to-node communication. Therefore, it is currently investigated how time multiplexing power transfer and communication can benefit the needs of implanted multi-node systems. While the inductive link is usually optimized solely for power transfer, the focus is on techniques that improve communication figures while not sacrificing power transfer efficiency.The expansion of this approach to neural implants is also under investigation.

Maxime Feyerick• Promotor Prof. W. Dehaene wim.dehaene@kuleuven.be• Research topics Biomedical systems, Low power

system/circuits design, Inductive communication

7.9 Implantable measurement system for bladder monitoring and stimulation

Envisioned bladder stimulation system: A) Overview B) Electronics system perspective.

91

Cataract, an eye disease that blurs the human vision can be solved by minimal surgery, replacing the biological lens by e.g. a PMMA/Silicon/acrylic lens. Research about an implantable focal adjustable Liquid Crystal (LC) based lenses could lead to next generation active eye lens devices.

Initial efforts were focused on how to equip an C.O.T.S. based eye lens implant to detect ciliary muscle movement and drive the central placed LC based lens. A ferro magnetic eye marker, mounted on the moving ciliary muscle, detunes the Colpitts oscillator frequency by changing the magnetic properties of its miniature detecting coil. An I3T50 CMOS based chip was developed to further miniaturize the digital control system.

Recent an analog front end chip was designed. It contains a diode and capacitor based, voltage doubler followed by a pre regulator circuit to provide a rectified/doubled and pre regulated version of the 13.56MHz input signal for the 1.8V voltage regulator circuit. A Colpitts based oscillation circuit followed by a DC-coupled Schmitt trigger provides a digital oscillation output signal. Inductive link load modulation and ASK demodulation circuitry allows communication with a host system. The designed chip has additional I/O-pads to measure or inject signals on crucial internal nodes. A picture of the chip layout ,is presented below. The designed chip consumes 560µA @ 1.8V and measures 1.5mm x 1mm.

Patrick Pelgrims• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Implantable biomedical systems

7.10 An i3T50 CMOS analog front end chip for an implantable eye lens control system

I3T50 CMOS Analog Front End layout.

92

8. MEMS, sensors & nanotechnology

93

Consequent to our continuous drive, MICAS’ MEMS research forms a cornerstone in the Leuven Nanocenter, a facility enabling growth of the nano-biosensor work in Leuven, augmenting multidisciplinary research through cooperation and cross-fertilisation with several other groups.

94

Flexible and stretchable silicon substrates might be one of the least exploited or researched sectors in electronics. We believe they allow for a smoother integration of sensors, actuators and their associated electronic circuits. Even more, they create opportunities for new applications. The capabilities of monolithic silicon as a flexible and stretchable material, is investigated, because it is the dominant component in microelectronics and MEMS.

A unique, wafer sized stretchable and bendable monolithic silicon matrix structure has been designed and implemented. The achieved stretchability not only allows for one directional folding, but is capable to bend in multiple directions simultaneously. Moreover, it also enables dynamic mechanical deformation of the structure to cope with a moving environment, like e.g. the wall of a heart muscle.

Currently, the work focuses on the integration of already established micromachining processes. As such, paving the road towards stretchable CMOS/MEMS devices. One of these is a flexible piezoelectric micromachined ultrasound transducer array. The fabrication of it, only requires one additional photomask step, compared to a process that realizes the stiff equivalent transducers. This assures a low additional cost and allows for a high element density. Moreover, their performance is not degraded. As a case study, the flexible transducer array is wrapped around a 5x5x5mm3 3D printed cube. It illustrates how MEMS-technology can leverage the functionality and application domains of current state-of-the-art devices.

Bram Lips• Promotor Prof. B. Puers bob.puers@kuleuven.be Prof. M. Kraft• Research topics Microfabrication technology,

Stretchable interconnects, CMOS integration

8.1 MEMS technology for flex and stretch monolithic silicon systems

Flexible silicon ultrasound transducer array wrapped around a 3D printed cube.

Related publication: Sadeghpour S., Lips B., Kraft M., Puers R., Flexible SOI-Based Piezoelectric Micromachined Ultrasound Transducer (PMUT) Arrays. Proceedings international Conference on Solid-State Sensors, Actuators and Microsystems (Transducers), 2019, pp. 250-253.

95

Recently, coupled MEMS resonators have been developed as new transduction concept and demonstrated that they can improve the sensitivity by 2-3 orders of magnitude compared with conventional sensors using resonant frequency shift as an output metric. They are sensitive to mass or stiffness perturbations exploiting an effect called mode-localization. Additionally, coupled resonators are relatively immune to environmental condition changes, e.g. ambient temperature or pressure variations. These resonators typically use electrostatic actuation and capacitive sensing, and therefore suffer from excessive squeeze-film damping due to the required narrow gap(~5μm) between their electrodes,resulting in low-quality factors when operating in a viscous medium such as air.

To tackle this problem, our research focus on applying thermal actuation to coupled resonators, as it increases the gap distance and avoids squeeze film damping. Likewise, piezoresistive signal read-out can be used instead of capacitive means. Moreover, recent research has shown that thermally actuated resonators can oscillate spontaneously when driven by a constant direct current, which simplify the test configuration.

Aojie Quan• Promotor Prof. M. Kraft michael.kraft@kuleuven.be• Research topics Thermal actuators, Coupled

resonators, Piezoresistive sensing

8.2 Self-oscillating, thermally actuated piezoresistive MEMS coupled resonators

Simulated self-oscillation of thermally coupled resonators.

96

Resonators have been widely used for making gas sensors, as they have potentially many advantages over conventional approaches based on heated metal oxide chemiresistors. They show promise to be more stable and selective, have lower power consumption and are low cost due to higher miniaturization. The usual working principle of resonator-based gas sensors is measuring frequency shift caused by a mass change due to gas molecules depositing. However, there are still many challenges to overcome in the development of gas sensors with higher sensitivity and selectivity.

Our research work aims at developing a formaldehyde gas sensor with high sensitivity and selectivity to other volatile organic compounds (VOCs). Compared to conventional single resonators, coupled resonators exhibit two or three orders of magnitude enhancement in sensitivity due to the mode localization effect. In such a configuration, the vibration amplitude ratio of the two resonators provides the output signal. One resonator can be coated with a metal-organic frameworks (MOFs), which are a group of inorganic-organic hybrid materials composed of single metal ions or polynuclear metal clusters and organic ligands. Zeolitic Imidazolate Framwork-8 (ZIF-8) is a type of MOFs, which has been extensively reported as sensing materials due to its large cavities and small pore apertures. The ZIF-8 aperture size is comparable to formaldehyde molecules, which can block other larger VOCs molecules, thus being selective to formaldehyde. Therefore, it is a promising approach to combine coupled resonators and ZIF-8 for a novel type of gas sensors.

The project is in collaboration with Prof. Rob Ameloot, Centre for Membrane Separations, Adsorption, Catalysis, and Spectroscopy for Sustainable Solutions at the Department of Microbial and Molecular System.

Chenxi Wang• Promotor Prof. M. Kraft michael.kraft@kuleuven.be• Research topics MEMS, Resonators, Gas sensors

8.3 Gas sensors based on coupled resonators coated with metal organic frameworks

Highlight of MOFs-based resonator for gas sensing.

97

The Internet of Things and the trillion-sensor vision drive the need for ever more sensitive, compact and energy efficient sensor systems. Integrating new materials with MEMS sensor structures allow to develop such sensors. Piezoresistive sensors in particular could benefit from this integration. These sensors are based on the piezoresistive effect, where a mechanical strain changes the electrical resistivity. Current piezoresistive sensor use doped silicon as piezoresistive material. Integrating new piezoresistive materials not only increases the piezoresistive response but simultaneously shows large piezo-refractive and piezo-dielectric coefficients. This enables the development of a new generation of ultra-sensitive multimodal microdevices including pressure sensors, accelerometers and resonators for applications in IOT, automotive and biomedical fields.

In this work piezoresistive properties such as gauge factor, noise and temperature coefficient of resistance of the new material are optimized. Starting from these material properties and the desired sensor specifications prototypes are designed with multi-physics simulations. Furthermore, the new piezoresistive material is integrated in industry-relevant fabrication platforms and allows use to fabricate and test several prototypes. The focus lies on both high perfomance MEMS sensors and further downscaling.

Michiel Gidts• Promotor Prof. M. Kraft michael.kraft@kuleuven.be• Research topics Piezoresistivity, MEMS sensors, Microfabrication

8.4 High performance MEMS sensors based on a novel piezoresistive transduction principle

Multimodal piezoresistive sensor.

98

Precise control of multitude parameters influencing the biotechnological process such as pH, temperature, concentration of nutrients (e.g. glucose) and metabolites (e.g. lactate), oxygen level and biomass concentration are crucial to meet the rising requirements in production and research. To monitor these key parameters, numerous analytic techniques have been employed.

Among of these techniques, multi-parameter sensor platforms offer promising solution to simultaneously monitor a wide range of parameters owing to its smaller size, cheaper cost and simplicity compared to multiple single sensors.

In this research, the integration of multiple electrochemical biosensors based on amperometric, potentiometric, impedimetric/conductometric detection techniques, as well as physical sensor on a single chip will be demonstrated. Sensor prototypes will be fabricated on a single chip, comprising platinum and gold electrodes on a glass substrate using standard microtechnology techniques.

This platform may not only capable to perform real time multi-parametric electrochemical measurements with different techniques but also can be autonomous to continuously monitor and analyse both in time and space, potentially employing wireless data transmission.

Nurul Izni Rusli• Promotor Prof. M. Kraft michael.kraft@kuleuven.be• Research topics Micro- and nanoelectronics,

Biosensors, MEMS technologies

8.5 Integrated multi-sensor platform for bioprocess monitoring

Photograph of integratedmulti-sensor chip.

99

A microbial community is a complex network, consisting of several populations, which can interact with each other by antagonistic or cooperative processes. To understand the full extend of these interactions, a real time analysis of bacteria on a single cell level is required. Commercial single cell analysis techniques like Flow Cytometry and Micro Raman Spectroscopy do not offer real time monitoring of cultures. Impedance spectroscopy on the other hand has the potential of analysing individual bacteria in real time.

Impedance spectroscopy is a technique where the electrical impedance between two electrodes is measured over a range of frequencies. The presence of bacteria near such an electrode inflicts small changes in the impedance measured at this electrode. The characteristics of these changes give information about cell properties such as size, viability, etc.

The aim of this research is to design and fabricate a microelectrode array chip that is capable of analysing bacteria in parallel using impedance spectroscopy. The design of the electrodes is a crucial aspect in this research, since they are to interact with individual bacteria whose size ranges below 1µm. A second aspect is the design of the read out circuitry which has to be capable of detecting small impedance changes. By integrating the microelectrode array with a CMOS chip, the interconnect lengths can be minimized. This allows a higher throughput of signals, which is needed for the real time analysis of bacteria in a parallel way.

Ruben Van den Eeckhoudt• Promotor Prof. M. Kraft Michael.kraft@kuleuven.be Prof. F. Tavernier• Research topics MEMS, Bio-MEMS, Impedance Spectroscopy,

Electrohydrodynamics, Microelectrode Arrays

8.6 Microbial chip to capture, analyse and steer communities

Conceptual drawing of the microelectrode array chip, integrated with CMOS circuitry.

100

Electrical active microorganisms are an environmentally friendly alternative for energy generation or chemical production from waste carbon streams. The electrical settings of these microbial electrochemical systems (MES) determine the efficiency. Little is known about these optimal settings and their relation with environment conditions as experiments are time-consuming and lab equipment (potentiostat) is expensive. This results in suboptimal production.

This PhD project aims at increasing our knowledge about MES by 1) using intelligent search algorithms for electrical setting experiment exploration and by 2) increasing the number of parallel stimulation and measurement channels while simultaneously drastically lowering the cost-per-channel for generating a dataset suitable for machine learning. To achieve this, a 128-channel potentiostat has been designed and verified with MES measurements. Processing the measurement data is currently in progress.

Tom Molderez• Promotor Prof. M. Verhelst marian.verhelst@kuleuven.be Prof. K. Rabaey (CMET, UGent)• Research topics Instrumentation & Measurement, Control Theory, Sensors

8.7 Microelectronics for Microorganisms

Related publication: T. Molderez, Z. Xu, M. Verhelst, K. Rabaey, “A Current-Driven Six-Channel Potentiostat for Rapid Performance Characterization of Microbial Electrolysis Cells”, in IEEE Transactions on Instrumentation and Measurement, vol. 68, no. 12, Dec. 2019.

(a) 128-channel potentiostat, (b) the circuit schematic and (c)-(d) 128x parallel chronoamperometry.

101

(a) 128-channel potentiostat, (b) the circuit schematic and (c)-(d) 128x parallel chronoamperometry.

The ultra-miniaturization and easy integration of pMUTs with CMOS technology allows ipso facto the utilization of ultrasound in different applications. In some cases, surprisingly, a whole new market has been introduced. Following the introduction of IoT as a technological revolution of computing and communications to interconnect with terrestrial applications, Underwater Sensor Networks (USN) were adopted to tackle many scientific and industrial underwater activities.

We at KU Leuven, have provided all facilities to design and fabricate highly efficient pMUT arrays to generate high output pressure/volt for underwater communication. Our PZT-based single pMUT has a world record displacement response of 8.6μm/V, which in an array configuration is capable of generating more than 1.5kPa/V @ 1cm. Moreover, a general platform to fabricated flexible silicon-based pMUT arrays has been demonstrated, which is applicable in miniaturized USNs and medical imaging, such as intravascular imaging.

Sina Sadeghpour• Promotor Prof. B. Puers bob.puers@kuleuven.be• Research topics Microelectromechanical systems

(MEMS), Piezoelectric materials, Ultrasound transducers

8.8 Piezoelectric micromachined ultrasound transducer (pMUT) for underwater communication

Related publication: Sadeghpour, S., M. Kraft, and R. Puers. “Design and fabrication strategy for an efficient lead zirconate titanate based piezoelectric micromachined ultrasound transducer.” Journal of Micromechanics and Microengineering 29.12 (2019): 125002.

(a) PMUT with a 8.6μm/V response; (b) OOK underwater communication by an array;(c) flexible pMUT.

102

High-density energy and power electrical storage technologies are crucial for the elaboration of electric vehicles with increased driving ranges by re-using braking energy. The use of a capacitor offers numerous advantages compared to the traditional Li-ion batteries. The (dis)charging is extremely fast, the lifetime is quasi unlimited (no degradable electrolyte) and a capacitor is light and contains no rare chemical elements. However, the variable voltage over time and the limited energy density currently prevent the capacitor of being a large-scale alternative to electrochemical batteries. Nevertheless, due to the high-power currents generated during braking, the recovered energy can only be efficiently stored by a capacitor and perfectly suits urban driving conditions or traffic congestion.

This research is addressing both difficulties and aims at establishing cheap, light, reliable and flexible capacitive energy storage. Multifunctional composite materials offer a unique integration method, which allows to embed the functional capacitor materials into structural carbon fiber reinforced polymers. In this concept, the composite material is not only the structural component, but it also realizes the storage capacitor. Potential materials to be addressed are carbon fibers as electrode material and ceramic nanoparticles embedded in a high-capacitive polymer as a dielectric in order to create a near-percolation network.

Additionally, this research aims at assessing the importance of controlling the manufacturing parameters and consequently to predict its effect on the mechanical (stiffness, strength) and electrical (capacitance, breakdown strength) properties by both experiments and simulations. These structural capacitors are essential to the reduction of fossil-based fuels by saving on both structural weight and energy requirement

Ruben Windey• Promotor Prof. F. Tavernier filip.tavernier@kuleuven.be Prof. M. Wevers• Research topics Structural supercapacitors,

Percolative dielectrics, Composites, Multiscale modeling

8.9 Structural supercapacitors: composite materials for high-density energy storage

Layup and materials for the structural high-voltage capacitor researched within this project.

103

104

9. Educational research& projects

105

MICAS staff members believe that passion for engineering and science is something we need to pass on to our kids from a young age. That is why MICAS is leading projects that bring STEM to schools in such a way that youngsters can engage with engineering in the regular educational curriculum.

106

Educational projects

Our passion for engineering the technology of the future extends to supporting the next generation of STEM professionals (Science, Technology, Engineering and Mathematics) to discover, follow and develop their own passions in STEM-fields. Complementary to its long history in teaching engineering students and supervising doctoral studies in electrical engineering, MICAS has also been developing expertise in teaching STEM in secondary education for many years now. This has resulted in multiple doctoral studies focusing on integrated STEM-education and in productive collaborations within KU Leuven and between universities and university colleges in Belgium, i.e. the project “STEM@school” and its continuation and expansion “iSTEM inkleuren”. In the latter, the comprehensive research expertise and field experience from MICAS and its academic partners is combined into a single strategic cell with partners of all Flemish universities and university colleges. This cell is under general management from MICAS and aims to disseminate its research-based insights and to support teachers in secondary education in developing their own educational materials for iSTEM (integrated STEM). To do so, the collaborators in this cell employ the “iSTEM educational approach” and make use of, and further refine, the “CODEM for iSTEM methodology” – which is the result from one of MICAS’ doctoral studies in educational research. Coaches from this strategic cell assist Teacher Design Teams in their design process using this methodology. The experience and expertise gained in a TDT guided by a coach then allows such teams to continue to develop and improve their practices on their own. They can then share their work and experience with more and more schools in learning networks, thus contributing to the end goal of realizing a network of self-sustainable TDTs developing and sharing their own learning materials throughout Flanders. This network will lift STEM education to a higher level; develop the means to support education to achieve a basic STEM literacy for all; and realize a stimulating, engaging and high quality education for future STEM professionals. All while using the iSTEM educational approach and the CODEM for iSTEM methodology tailored to their needs.

107

A Teacher Design Team at work using the CODEM for iSTEM methodology. They first perform a context analysis of their target group and select a relevant theme and a motivating challenge (societal, ecological, personal, …). Then the sub-problems are identified and the puzzle of matching the many discipline-specific curriculum standards with the project’s learning goals is solved – a worthy engineering challenge in itself. The teachers then design learning activities, which hone the students’ problem solving skills, as well as their technical and scientific skills and understanding to realize a viable solution to the stated challenge. Throughout this process, the relevance of STEM and the role of each of the STEM-disciplines and its content matter, skills and attitudes becomes clear for the students.

Our MICAS collaborators Prof. dr. ir. Wim Dehaene, Marie-Paule Buyse and dr. Stijn Ceuppens working on the educational projects.

108

10. Awards and prizes in 2019

109

110

Awards and Prizes in 2019

Ariane De Vroede won the IEEE Region 8 Student Paper Contest with her paper “A 94 GHz Voltage-Boosted Energy Harvester in 45 nm CMOS Achieving a Peak Efficiency of 21.2% at – 8.5dBm Input Power”, presented during Eurocon 2019 in Novi Sad, Serbia, from July 1st till July 3th 2019. [photo 1]

Bob Puers, lecturer of the microelectromechanical systems training, became Teacher of the year during High Tech Ins@tute’s annual get together in Eindhoven.His training scored a 9.8 with praising comments and even a 10 for him as a lecturer. [photo 2]

Laura Galindez won two awards, the NeurIPS 2019 travel award and the ICML 2019 travel grant. [photo 3]

1

2 3

111

4

Thomas Bos (promotors Prof. Wim Dehaene, Prof. Marian Verhelst) received the 2019 BioCAS Young Researcher Poster Award (Bronze) with his paper entitled “Ultrasound In-Body Communication with OFDM through Multipath Realistic Channels”. [photo 4]

Tuur Van Daele received for his paper “A fully-Integrated 6:1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm2” the bronze leaf certificate at the PRIME2019 conference.

112

11. Infrastructure & Support

113

MICAS continually invests substantially in its computing and measurement infrastructure. In our new measurement lab, we are able to measure everything from DC to THz frequencies.

114

At MICAS a Local Area Network (LAN) is provided with a minimum connection speed of 1Gbit/s to all available servers and workstations. A central file server with multi TB hard disk cabinets and RAID 10 architecture hosts all the design and EDA software as well as the user accounts. The total storage capacity at ESAT exceeds 500TB.

Performant Multicore CPU numbercrunchers with more than 0.5TB of RAM provide the processing power to tackle even the most demanding simulation runs.

EDA tools from vendors such as Cadence, Mentor Graphics, Synopsys, Keysight, a.o. are used for simulation, layout and verification. Other tools such as Comsol Multiphysics and Coventorware are used to support the design of MEMS.

Linux RedHat 7 is used as our preferred operating system.

11.1 Computer and software

infrastructure

W. DehaeneB. Geeraerts

View of the 19” racks in our computerroom, stacked with different servers.

115

MICAS has a long-standing tradition of research valorization through research projects with the industry and through spin-off creation. Our “research pipeline”, consisting of long-term fundamental research, strategic basic research and applied industrial research, is targeted on creating maximum leverage and societal-economic impact for the research.

Our model of research valorization towards the industry is based on a continuous interaction with current and potential partners and on a profound knowledge of their research needs. Finding a good match between those needs and what MICAS can offer leads to the definition of a research collaboration. That collaboration can take the form of a purely bilateral contract, a participation in a project with co-funding by regional or European agencies, or any other form through which MICAS research results can enable significant innovation in the product pipeline of the partner.

In 2019, 42 different research projects have been running at MICAS, keeping a healthy balance between fundamental, applied and industrial research.

David Maes is our Research Valorization Manager. He is responsible for setting up collaboration projects with the industry, forming the bridge between our research and the industrial needs. He also stimulates and guides all other forms of research valorization at MICAS.

11.2 Valorization management

D. Maes

In the MICAS IC-Lab, researcher Simon Ooms demonstrates the results of our research to our industrial partners.

PMF 2019, The First International Workshop on Polymer Microwave Fiber Technology, was organized by MICAS and brought together academia and industry to stimulate the market adoption of our research.

116

(top) High speed data across plastic waveguide demo setup.(bottom left) IC-Lab HF. (bottom right) Network Analyzer setup.

IC-Lab HF contains wideband measurement equipment such as signal analyzers, arbitrary waveform generators, oscilloscopes and vector network analyzers. An extensive list of high performance instruments is available to ensure the best possible measurement accuracy. Also it provides means to test the latest communication standards such as 5G, LTE Advanced, WiMAX, and WLAN.

Recent activities include the measurement of transmitters/receivers, oscillators, AD/DA converters, THz antennas, high speed optical receivers and high speed data communication across plastic waveguides.

Instrumentation facilities include:• Vector network analysis up to 325GHz• Spectrum analysis up to 1.1THz• Signal generation up to 1.1THz• Power measurements up to 2THz• Probe Stations and mmW-probes up to 1.1GHz• Parbert System: 16 bit data Generator/ 12 bit Analyzer up to 27Gb/s• Arbitrary Waveform Generators up to 50GS/s• Real-Time Oscilloscopes up to 60GHz• Phase Noise measurements up to 18GHz• Various Horn Antennas for wireless chip measurements and antenna characterization• E-Band Communication Test Equipment• Various high-speed optical transmitters

11.3 IC-Lab HF: broadband, optical, mm-wave and THz measurement lab

M. SteyaertP. ReynaertF. Daenen

117

(left) IC-Lab LF. (right) Low Frequency measurement setup.

IC-Lab LF contains specialized equipment in the range from DC to several GHz. The main focus of this lab is on low noise, high resolution signal generation and power source analysis.

Recent activities include power analysis & EMI performance of integrated power converters and power control circuits.

Instrumentation facilities include:• Accurate inductor measurement system• AC Source Analyzer up to 750VA• Power Analyzers up to 600VA• Precision Source Measure Units• Impedance Analyzer up to 110MHz• Ultra low distortion signal sources < 0.001% THD• High Magnification Digital Microscope up to 2500x• Laser Cutter for chip repair• High performance thermal imaging camera with 3um/pixel resolution• Thermostream for fast precision temperature testing• Controlled Humidity and Temperature Chamber

11.4 IC-Lab LF: the low frequency measurement lab

M. Steyaert P. ReynaertF. Daenen R. Vanlaer

118

The MICAS Technology Lab provides in-house facilities to bond, flip-chip and package chips and sensors.

Aluminum and Gold wire bonders are available to package chips in a package or directly on a PCB. The latest bonder is a fully automatic wire bonder that can be configured for either gold wire ball-stitch or aluminium wire stitch-stitch bonding. With these machines we can perform complex wire bonding and ball/stud bumping on a broad variation of chips and devices.

Flip Chip packaging is possible by bumping Au studs onto a chip, combined with an accurate flip-chip bonding device to place the pre-bumped sample directly on a PCB. Compared to traditional bonding this process allows very low-impedance connections between the chip and the measurement board which results in increased performance.

11.5 Technology Lab: chip bonding

facilities

P. Reynaert M. Steyaert N. Gaethofs R. Vanlaer

F. Daenen

Thermosonic high-speed, ball-and-stitch wire bonder.

119

The MICAS Technology Lab provides in-house facilities to perform high precision sample preparation.

With an accurate dicing saw, individual chips can be separated from each other on the wafer. The dicing process is accomplished by mechanically sawing the scribe lines on the wafer. A second dicing machine is available and optimized for cutting glass material with high precision.

A specialized cnc controlled grinding machine is able to perform decapsulation, silicon thinning, polishing and cleaning of integrated circuits. This machine is often used for sample preparation prior to backside circuit editing with the focused ion beam system. Typically the bulk silicon at the back of the die is removed until a remaining thickness of around 50 to 100um is left.

11.6 Technology Lab: dicing and

grinding facilities

M. Steyaert P. Reynaert N. Gaethofs R. Vanlaer

F. Daenen

Dicing and Grinding machine.

120

The MICAS Technology Lab provides services for state of the art circuit modification and chip repair.

An Nd-YAG laser is available for top metal silicon surgery. The laser light is focused through a microscope in order to selectively remove certain parts from an IC. The laser emits green light (532nm) which can be used for cutting metal lines and trimming resistors. An attenuator and variable aperture lens are used to control the energy level of the laser for precise operation.

For advanced chip modification, a specialized Focused Ion Beam System (FIB) is available. Several materials can be removed and deposited with nanometer accuracy so that circuits can be modified without the need for re-processing. A unique feature of the system is the increased working distance so that electrical components around the chip won’t hinder the repair operation. Therefore the FIB is able to make modifications not only on single dies or on chip packages but even on dies directly mounted onto a PCB.

11.7 Technology Lab: chip repair

facilities

M. Steyaert P. Reynaert F. Daenen

Dual Beam System optimized for chip repair. FIB was used to fine tune a microstrip line.

121

Micas has a well-equipped 450m2, ISO class 6 cleanroom facility in the KU Leuven Nanocenter for R&D and small-scale production of micro- and nanosystems, MEMS and lab-on-chip devices. It includes more than 35 major tools including lithography, dry and wet etching and thin film deposition.Highlights include a deep reactive ion etcher (DRIE), a Raith e-beam system for direct writing of patterns with a resolution down to 10nm, a Nanoscribe GT 2-photon lithography system for realizing 3D structures with a voxel size of 200 x 200 x 600nm, two atomic layer deposition reactors, evaporation and sputtering tools.There is also a range of inspection equipment available, including a SEM, a Dektak profile meter, a Femtotools micro-force probe and diverse tools for optical characterization by microscopy, reflectometry and ellipsometry.Next to our own research in sensors and actuators for various applications the cleanroom is also used by other research groups interested in developing devices or setting up experiments at the micro- and nanometer scale.Third-party users include several local and international companies and research centers, and research groups from KU-Leuven’s physics, bio-engineering and chemistry departments. To limit costs and increase flexibility, third party users can be allowed to operate the equipment themselves after training.

The deposition and etching room.

M. KraftF. CeyssensM. De CoomanT. Brockhans

11.8 MICAS Cleanroom in the

Leuven Nanocenter

122

With more than 80 users from many research groups, the activities in micro- and nanoscale fabrication is very diverse and interdisciplinary. We currently fabricate around 70% on silicon 4-inch wafers and 30% using flexible substates.Some recent highlights include:• A SOI wafer-based fabrication process, which is suitable for various inertial sensors

and resonators. The structural layer can vary from 5-100mm. Release and die separation is done in a HF vapor etcher to avoid stiction and dicing.

• Fabrication of PZT layers with a high piezoelectric coefficient for highly efficient PMUTs (piezoelectric micromachined ultrasound transducers). Applications include under water communication and medical imaging. • Fabrication of dense electrode arrays on flexible substrates for neurorecording and stimulation.• Process development to integrate novel piezoresistive materials on (111) wafers.• Fabrication of metal-organic framework (MOF) with atomic layer deposition.• Metal electrode fabrication for bio-sensing applications based on electrochemical measurement and electrical impedance spectroscopy.

The cleanroom is equipped with all infrastructural requirements to facilitate researchunder clean, controlled and safe conditions, and is compliant with ISO class 6.

11.9 Micro- and Nanosystem

fabrication

M. Kraft F. CeyssensM. De CoomanR. Ameloot

The Micas lithography room.

123

D. VermettenC. MertensA-M. Ruijmen

Micas wouldn’t be running as smoothly as it does, if it didn’t have the excellent support of the Micas secretariat by Danielle Vermetten (administrative support) and the Financial Services by Chris Mertens and Anne-Marie Ruijmen. They all have been with Micas for many years and definitely are an essential part of the Micas operations.

11.10 Administrative staff ESAT-MICAS

Anne-Marie: finances Danielle: secretariat Chris: finances

124

12. Doctoral theses in 2019

125

126

Badami, K., Verhelst, M. (sup.), Meert, W. (cosup.) (2019). Power Efficient Analog and Mixed-Signal Architectures for Sensing Systems. [photo 1]

Brancato, L., Puers, R. (sup.) (2019). Towards Improving Biocompatibility in Implantable Monitoring. [photo 2]

Castro Miller, I., Van Hoof, C. (sup.), Puers, R. (cosup.) (2019). Robust Capacitively-coupled Electrocardiography and Bioimpedance for Unobtrusive Health Monitoring. [photo 3]

Ceuppens, S., De Cock, M. (sup.), Dehaene, W. (cosup.), Deprez, J. (cosup.) (2019). Learning of physics and mathematics concepts in an integrated STEM curriculum. [photo 4]

Contino, A., Groeseneken, G. (sup.), Sorée, B. (cosup.) (2019). Modeling of Graphene for Interconnect Applications.

1

3

2

4

127

De Meester, J., Dehaene, W. (sup.), Langie, G. (cosup.), De Cock, M. (cosup.) (2019). Designing iSTEM Learning Materials for Secondary Education. [photo 5]

De Roose, F., Dehaene, W. (sup.), Genoe, J. (cosup.) (2019). Advanced Mixed-Mode Design in Thin-Film Technologies on Flex. [photo 6]

De Wit, M., Reynaert, P. (sup.) (2019). CMOS Millimeter Wave Circuits for Dielectric Waveguide Communication. [photo 7]

Florent, K., Groeseneken, G. (sup.), Van Houdt, J. (cosup.) (2019). Evaluation of Alternative Vertical Transistors for 3D NAND Applications.

Goovaerts, L., Dehaene, W. (sup.), De Cock, M. (cosup.), Struyven, K. (cosup.) (2019). Development and Assessment of iSTEM Competencies. [photo 8]

5 6

7 8

128

9

10

Janneck, R., Heremans, P. (sup.), Genoe, J. (cosup.) (2019). High Performance, High-Level Integration of Organic Transistors.

Keulemans, G., Puers, R. (sup.) (2019). Miniature Pressure Sensors for the High Temperature Domain. [photo 9]

Kil, D., Puers, R. (sup.) (2019). Design and Microfabrication of Flexible Neural Probes for Chronic Applications. [photo 10]

Marin Niño De Zepeda, J., Gielen, G. (sup.), Dehaene, W. (cosup.) (2019). Time-Based Techniques for the Design of Area-Efficient and Robust CMOS Sensor Interface Circuits. [photo 11]

Putcha, V., Groeseneken, G. (sup.) (2019). Reliability Characterization of Gate-stacks for III-V Channel MOSFETs.

11

129

Theunis, R., Dehaene, W. (sup.), Leroux, P. (cosup.) (2019). Wireless indoor ranging systems. [photo 12]

Weydts, T., Puers, R. (sup.) (2019). Exploration of Bladder Wall Physiology by an Implantable Accelerometer Network. [photo 13]

Zhang, Y., Reynaert, P. (sup.) (2019). Co-design of Mm-wave Interfaces, Duplexers and CMOS Transmitters. [photo 14]

12 13

14

130

13. Spin-offs

131

The state-of-the-art research at MICAS has resulted in 7 successful spinoff companies over the last 20 years, jointly resulting in 200+ new high-tech jobs.

132

13.1 AnSemAnSem was founded in 1998 as a spin-off from the MICAS research group of the K.U.Leuven. AnSem is a fabless analog ASIC design service company, designing and delivering state-of-the-art analog, RF and mixed-signal integrated circuits to customers worldwide. It takes control over the complete ASIC development an supply flow, being a true one-stop-shop for its customers. AnSem is ISO 9001:2015 and ISO13485:2016 certified and is predominantly active in healthcare, communications, industrial and aerospace markets. AnSem became the R&D center of excellence for turnkey, custom and smart analog front-end chips and sensors for Cyient, after the acquisition in April 2018. In the meantime it has invested a lot in test and production test and expanded to about 100 employees divided over the 3 sites: Leuven, Enschede and Duisburg.

More information: www.ansem.com

13.2 ICsenseICsense was founded in 2004 as a spin-off from the MICAS group of KU Leuven and is Europe’s premier IC design company. ICsense’s core business is ASIC development and supply and custom IC design services. ICsense has the largest fab-independent European design group of 85 people with world-class expertise in analog, digital, mixed-signal and high-voltage IC design. The company develops and supplies customer exclusive ASIC solutions for the automotive, medical, industrial and consumer market compliant with ISO9001, ISO13485, IEC61508-ISO26262. ICsense is part of the Japanese TDK group since 2017, but more than 50% of its business is outside of TDK.

More information: www.icsense.com

133

13.3 ZensoZenso NV was founded in 2007 as a MICAS spin-off, designing and producing electronic circuits and systems. Zenso NV is active in the medical sector, as well as in the industrial, automotive and consumer sectors. Zenso is ISO9001 and ISO13485 for medical design certified. The core services it offers are centered around: feasibility studies, electronic system and PCB design, software development, system integration, prototyping & series production, test & validation, CE testing (safety, immunity, emission, radio) and technical writing.

More information: www.zenso.be

13.4 MinDCetMinDCet was founded in 2011, as a spin-off from the MICAS research group. MinDCet is an ISO9001 certified, fabless, mixed-signal IC design company, developing Power Management ICs. MinDCet develops highly/fully integrated and discrete DC-DC converters, motor drivers, high-speed GaN and laser drivers, control systems, class-D amplifiers, power and battery management. Currently, MinDCet is active in the following markets: automotive, industrial, aerospace & space, biomedical, high-reliability & harsh environments.

More information: www.mindcet.com

134

13.6 HAMMER-IMSHammer-IMS is a high-tech company in the field of industrial sensing. It is a spin-off company of research laboratory ESAT - MICAS of KU Leuven University. The company, founded in 2016, is based in Hasselt, Belgium. Hammer-IMS supplies contactless measurement systems for measuring thickness, weight and anomalies of semi-finished products in production lines. Hammer-IMS applies its disruptive M-Ray technology in its products and solutions. This technology combines millimeter waves (=high-frequency electromagnetic waves) with innovative algorithms to a powerful alternative for today’s nuclear and radioactive measuring equipment.

More information: www.hammer-ims.com

13.5 MAGICS InstrumentsMAGICS Instruments (MAGICS®) is a fabless IC development company with its headquarter located in Belgium, specialized in the design of harsh environment integrated circuits and machine learning based intelligent sensors. MAGICS provides solutions for intelligent sensing and smart robotics for extreme environments (e.g., nuclear, space, off-shore, and high-energy physics), leveraging the company’s world-class expertise in the design of high-performance, low-power, and radiation-hardened analog, mixed-signal, time-mode and high-voltage ASICs.

More information: www.magicsinc.com

135

13.7 Tusk ICTusk IC is a mmWave design house, offering extensive research and industry experience in the field of mmWave IC design. Founded in 2018 as a spin-off from the MICAS research group, Tusk IC provides state-of-the-art custom mmWave solutions, high-frequency measurements and IP development for CMOS, SOI and SiGe mmWave circuits from 10GHz to 300GHz+ and beyond. From 5G to car radar for autonomous vehicles, wireless VR to contactless sensing: the millimeter wave spectrum will enable a wide range of revolutionary applications. Tusk IC is where these millimeter waves meet silicon.

More information: www.tusk-ic.com

14. Emeriti

138

Willy Sansen is the founder of MICAS, established in 1984. He has been retired as an emeritus professor since October 2008. He has continued a number of activities such as courses, consulting with companies and service work within the IEEE.

In 2019 he has continued to teach analog IC design, as a follow up of his book “Analog Design Essentials”. Courses are held all over the world, including China (see photograph). The content of his courses is updated, after each major conference in the field.

In addition Willy Sansen is a member of Technical Advisory Boards of several companies and of Boards of Directors. For example in 2019, he has left the Board of Tyndall in Cork, Ireland.

Last but not least Willy Sansen is a member of several IEEE conferences and meetings. As a past president of the IEEE Solid-State Circuits Society, he is a member of its ADCOM. He has played an instrumental role in the inclusion of the ESSCIRC/ESSDERC conference in the IEEE and was until recently Chairman of its Technical Program Steering Board.

Willy Sansen

Willy Sansen explaining about Analog design in Nanjing, China.

139

Bob Puers has become an emeritus professor since October 2018. He is best known for his pioneering role in MEMS and medical implants in Micas, and for his drive in the creation of the Leuven Nanocenter and its cleanroom.

In 2019 he was still active to finish his ERC advanced grant (MicroThalys) on flexible implantable devices for health monitoring and stimulation. It produced three doctoral dissertations this year, directly related to this project. He was granted a follow-up ERC Proof of Concept (PoC) project (Himiser) to develop an active neural brain implant.

He became a member of the reflection group of the emeriti forum of KU Leuven, defining the content of the emeriti meetings each month for discussions on actual themes. He also chairs Doctoral thesis defenses for the Faculty of Engineering.

He acted as a member of the Board of Directors of MinDCet (Leuven), and Zenso (Leuven), two of the Micas spin-off companies.

Bob Puers

Bob Puers giving a seminar in the Beihang University, Campus Qingdao, China.

140

15. Bibliography

141

142

15.1 Journal articlesAgarwal, T.K., Rau, M., Radu, I., Luisier, M., Dehaene, W., Heyns, M. (2019). Performance Comparison of s Si, In0.53Ga0.47As, Monolayer BP- and WS2-Based n-MOSFETs for Future Technology Nodes-Part II: Circuit Level Comparison. IEEE TRANSACTIONS ON ELECTRON DEVICES, 66 (8), 3614-3619.

Agarwal, T.K., Rau, M., Radu, I., Luisier, M., Dehaene, W., Heyns, M. (2019). Performance Comparison of s Si, In0.53Ga0.47As, Monolayer BP, and WS2-Based n-MOSFETs for Future Technology Nodes-Part I: Device Level Comparison. IEEE TRANSACTIONS ON ELECTRON DEVICES, 66 (8), 3608-3613.

Agbo, I., Taouil, M., Kraak, D., Hamdioui, S., Weckx, P., Cosemans, S., Raghavan, P., Catthoor, F., Dehaene, W. (2019). Sense amplifier offset voltage analysis for both time-zero and time-dependent variability. MICROELECTRONICS RELIABILITY, 99, 52-61.

Baert, M., Dehaene, W. (2019). A 5GS/s 7.2 ENOB Time-Interleaved VCO-based ADC Achieving 30.5fJ/cs. Ieee Journal Of Solid-State Circuits.

Balaji, Y., Smets, Q., Szabo, A., Mascaro, M., Lin, D., Asselberghs, I., Radu, I., Luisier, M., Groeseneken, G. (2019). MoS2/MoTe2 Heterostructure Tunnel FETs Using Gated Schottky Contacts. ADVANCED FUNCTIONAL MATERIALS, 30 (4), Art.No. ARTN 1905970.

Bankman, D., Yang, L., Moons, B., Verhelst, M., Murmann, B. (2019). An Always-On 3.8 mu J/86% CIFAR-10 Mixed- Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54 (1), 158-172.

Bao, X., Bao, J., Ocket, I., Liu, S., Schreurs, D., Kil, D., Liu, Z., Zhang, M., Puers, R., Nauwelaers, B. (2019). A Simplified Dielectric Material Characterization Algorithm for Both Liquids and Solids. IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 61 (5), 1639-1646.

Bastos, J.P., Uytterhoeven, G., Qiu, W., Paetzold, U.W., Cheyns, D., Surana, S., Rivas, J., Jaysankar, M., Song, W., Aernouts, T., Poortmans, J., Gehlhaar, R. (2019). Model for the Prediction of the Lifetime and Energy Yield of Methyl Ammonium Lead Iodide Perovskite Solar Cells at Elevated Temperatures. ACS APPLIED MATERIALS & INTERFACES, 11 (18), 16517-16526.

Baumgratz, F.D., Saavedra, C., Steyaert, M., Tavernier, F., Bampi, S. (2019). A Wideband Low-Noise Variable Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 66 (7), 1104-1108.

Biswas, D., Everson, L., Liu, M., Panwar, M., Verhoef, B-E., Patki, S., Kim, C.H., Acharyya, A., Van Hoof, C., Konijnenburg, M., Van Helleputte, N. (2019). CorNET: Deep Learning Framework for PPG-Based Heart Rate Estimation and Biometric Identification in Ambulant Environment. IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 13 (2), 282-291.

Biswas, D., Simoes-Capela, N., Van Hoof, C., Van Helleputte, N. (2019). Heart Rate Estimation From Wrist-Worn Photoplethysmography: A Review. IEEE SENSORS JOURNAL, 19 (16), 6560-6570.

Bizindavyi, J., Verhulst, A.S., Verreck, D., Soree, B., Groeseneken, G. (2019). Large Variation in Temperature Dependence of Band-to-Band Tunneling Current in Tunnel Devices. IEEE ELECTRON DEVICE LETTERS, 40 (11), 1864-1867.

Butzen, N., Steyaert, M. (2019). Design of Single-Topology Continuously Scalable-Conversion-Ratio Switched-Capacitor DC-DC Converters. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54 (4), 1039-1047.

Camus, V., Mei, L., Enz, C., Verhelst, M. with Mei, L. (joint first author) (2019). Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing. Ieee Journal On Emerging And Selected Topics In Circuits And Systems, 9 (4), 697-711.

Caselli, M., Tonelli, M., Boni, A. (2019). Analysis and design of an integrated RF energy harvester for ultra lowpower environments. INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 47 (7), 1086-1104.

Çelik, U., Reynaert, P. (2019). An E-Band Compact Power Amplifier for Future Array-Based Backhaul Networks in 22nm FD-SOI. IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers, 187-190.

Ceuppens, S., Bollen, L., Deprez, J., Dehaene, W., De Cock, M. (2019). 9th grade students’ understanding and strategies when solving x(t) problems in 1D kinematics and y(x) problems in mathematics. PHYSICAL REVIEW PHYSICS EDUCATION RESEARCH, 15 (1), Art.No. ARTN 010101.

Ceyssens, F., Carmona, M.B., Kil, D., Deprez, M., Tooten, E., Nuttin, B., Takeoka, A., Balschun, D., Kraft, M., Puers, R. (2019). Chronic neural recording with probes of subcellular cross-section using 0.06 mm (2) dissolving microneedles as insertion device. SENSORS AND ACTUATORS B-CHEMICAL, 284, 369-376.

143

Ceyssens, F., Sadeghpour, S., Hiroyuki, F., Puers, R. (2019). Actuators: Accomplishments, opportunities and challenges. SENSORS AND ACTUATORS A-PHYSICAL, 295, 604-611.

Ceyssens, F., Welkenhuysen, M., Puers, R. (2019). Anisotropic etching in (3 1 1) Si to fabricate sharp resorbable polymer microneedles carrying neural electrode arrays. JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 29 (2), 027001-027001.

Chen, M., Chun, H.S., Castro, I.D., Torfs, T., Lin, Q., van Hoof, C., Wang, G., Lian, Y., van Helleputte, N. (2019). A 400 G Omega Input-Impedance Active Electrode for Non-Contact Capacitively Coupled ECG Acquisition With Large Linear-Input-Range and High CM-Interference-Tolerance. IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, 13 (2), 376-386.

Chen, S., Noori, S., Villena, M.A., Shi, Y., Han, T., Zuo, Y., Pedeferri, M., Strukov, D., Lanza, M., Diamanti, M.V. (2019). Memristive Electronic Synapses Made by Anodic Oxidation. CHEMISTRY OF MATERIALS, 31 (20), 8394-8401.

Chen, W-C., Ker, M-D. (2019). Area-Efficient On-Chip Transient Detection Circuit for System-Level ESD Protection Against Transient-Induced Malfunction. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 19 (2), 363-369.

Ciofi, I., Roussel, P.J., Baert, R., Contino, A., Gupta, A., Croes, K., Wilson, C.J., Mocuta, D., Tokei, Z. (2019). RC Benefits of Advanced Metallization Options. IEEE TRANSACTIONS ON ELECTRON DEVICES, 66 (5), 2339-2345.

De Pelecijn, E., Steyaert, M. (2019). A Fully Integrated Switched-Capacitor-Based AC-DC Converter for a 120 VRMS Mains Interface. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54 (7), 2009-2018.

De Wit, M., Zhang, Y., Reynaert, P. (2019). Analysis and Design of a Foam-Cladded PMF Link With Phase Tuning in 28-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54 (7), 1960-1969.

Fakharuddin, A., Qiu, W., Croes, G., Devizis, A., Gegevicius, R., Vakhnin, A., Rolin, C., Genoe, J., Gehlhaar, R., Kadashchuk, A., Gulbinas, V., Heremans, P. (2019). Reduced Efficiency Roll-Off and Improved Stability of Mixed 2D/3D Perovskite Light Emitting Diodes by Balancing Charge Injection. ADVANCED FUNCTIONAL MATERIALS, 29 (37), Art.No. ARTN 1904101.

Fakharuddin, A., Shabbir, U., Qiu, W., Iqbal, T., Sultan, M., Heremans, P., Schmidt-Mende, L. (2019). Inorganic and Layered Perovskites for Optoelectronic Devices. ADVANCED MATERIALS, 31 (47), Art.No. ARTN 1807095.

Franco, J., Wu, Z., Rzepa, G., Ragnarsson, L-A., Dekkers, H., Vandooren, A., Groeseneken, G., Horiguchi, N., Collaert, N., Linten, D., Grasser, T., Kaczer, B. (2019). On the Impact of the Gate Work-Function Metal on the Charge Trapping Component of NBTI and PBTI. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 19 (2), 268-274.

Frans, Y., Dehaene, W., Motomura, M., Bae, S-J. (2019). Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC). IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54 (1), 3-5.

Georgitzikis, E., Malinowski, P.E., Li, Y., Maes, J., Moreno Hagelsieb, L., Guerrieri, S., Hens, Z., Heremans, P., Cheyns, D. (2019). Integration of PbS quantum dot photodiodes on silicon for NIR imaging. IEEE Sensors Journal.

Goetschalckx, K., Verhelst, M. (2019). Breaking High-Resolution CNN Bandwidth Barriers With Enhanced Depth-First Execution. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 9 (2), 323-331.

Goossens, T., Geelen, B., Lambrechts, A., Van Hoof, C. (2019). Vignetted-aperture correction for spectral cameras with integrated thin-film Fabry-Perot filters. APPLIED OPTICS, 58 (7), 1789-1799.

Goossens, T., Van Hoof, C. (2019). Exit pupil localization to correct spectral shift in thin-film Fabry-Perot spectral cameras. OSA Continuum, 2 (7), 2217-2226.

Goovaerts, L., De Cock, M., Struyven, K., Dehaene, W. (2019). A concrete proposal to introduce control theory to 16 year old pupils. European Journal of STEM Education, 4 (1).

Guo, K., Zhang, Y., Reynaert, P. (2019). A 0.53-THz Subharmonic Injection-Locked Phased Array With 63-mu W Radiated Power in 40-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54 (2), 380-391.

Han, T., Shi, Y., Yu, Z., Shin, B., Lanza, M. (2019). Potassium Hydroxide Mixed with Lithium Hydroxide: An Advanced Electrolyte for Oxygen Evolution Reaction. SOLAR RRL, 3 (10).

Janneck, R., Karagiannis, D., Heremans, P., Genoe, J., Rolin, C. (2019). Influence of Solute Concentration on Meniscus-Guided Coating of Highly Crystalline Organic Thin Films. ADVANCED MATERIALS INTERFACES, 6 (19), Art.No. ARTN 1900614.

144

Janneck, R., Nowack, T.S., De Roose, F., Ali, H., Dehaene, W., Heremans, P., Genoe, J., Rolin, C. (2019). Integration of highly crystalline C8-BTBT thin-films into simple logic gates and circuits. ORGANIC ELECTRONICS, 67, 64-71.

Jech, M., Ullmann, B., Rzepa, G., Tyaginov, S., Grill, A., Waltl, M., Jabs, D., Jungemann, C., Grasser, T. (2019). Impact of Mixed Negative Bias Temperature Instability and Hot Carrier Stress on MOSFET Characteristics-Part II: Theory. IEEE TRANSACTIONS ON ELECTRON DEVICES, 66 (1), 241-248.

Jing, X., Illarionov, Y., Yalon, E., Zhou, P., Grasser, T., Shi, Y., Lanza, M. (2019). Engineering Field Effect Transistors with 2D Semiconducting Channels: Status and Prospects. ADVANCED FUNCTIONAL MATERIALS, Art.No. ARTN 1901971.

Kil, D., Carmona, M.B., Ceyssens, F., Deprez, M., Brancato, L., Nuttin, B., Balschun, D., Puers, R. (2019). Dextran as a Resorbable Coating Material for Flexible Neural Probes. MICROMACHINES, 10 (1), Art.No. ARTN 61.

Lanza, M., Wong, H-S.P., Pop, E., Ielmini, D., Strukov, D., Regan, B.C., Larcher, L., Villena, M.A., Yang, J.J., Goux, L., Belmonte, A., Yang, Y., Puglisi, F.M., Kang, J., Magyari-Kope, B., Yalon, E., Kenyon, A., Buckwell, M., Mehonic, A., Shluger, A., Li, H., Hou, T-H., Hudec, B., Akinwande, D., Ge, R., Ambrogio, S., Roldan, J.B., Miranda, E., Sune, J., Pey, K.L., Wu, X., Raghavan, N., Wu, E., Lu, W.D., Navarro, G., Zhang, W., Wu, H., Li, R., Holleitner, A., Wurstbauer, U., Lemme, M.C., Liu, M., Long, S., Liu, Q., Lv, H., Padovani, A., Pavan, P., Valov, I., Jing, X., Han, T., Zhu, K., Chen, S., Hui, F., Shi, Y. (2019). Recommended Methods to Study Resistive Switching Devices. ADVANCED ELECTRONIC MATERIALS, 5 (1), Art.No. ARTN 1800143.

Lee, J-H., Ke, T-H., Genoe, J., Heremans, P., Rolin, C. (2019). Overlapping-Gate Organic Light-Emitting Transistors. ADVANCED ELECTRONIC MATERIALS, 5 (1), Art.No. ARTN 1800437.

Li, X., Geens, K., Guo, W., You, S., Zhao, M., Fahle, D., Odnoblyudov, V., Groeseneken, G., Decoutere, S. (2019). Demonstration of GaN Integrated Half-Bridge With On-Chip Drivers on 200-mm Engineered Substrates. IEEE ELECTRON DEVICE LETTERS, 40 (9), 1499-1502.

Li, X., Zhao, M., Bakeroot, B., Geens, K., Guo, W., You, S., Stoffels, S., Lempinen, V-P., Sormunen, J., Groeseneken, G., Decoutere, S. (2019). Buffer Vertical Leakage Mechanism and Reliability of 200-mm GaN-on-SOI. IEEE TRANSACTIONS ON ELECTRON DEVICES, 66 (1), 553-560.

Liu, H., Xing, X., Gielen, G.G E. (2019). An 85-MHz-BW ASAR-Assisted CT 4-0 MASH Delta Sigma Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 66 (7), 2405-2414.

Lyu, Y., Tavernier, F. (2019). A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage– Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs. IEEE Solid State Circuits Letters, 163-166.

Makarov, A., Kaczer, B., Chasin, A., Vandemaele, M., Bury, E., Jech, M., Grill, A., Hellings, G., El-Sayed, A M., Grasser, T., Linten, D., Tyaginov, S. (2019). Bi-Modal Variability of nFinFET Characteristics During Hot-Carrier Stress: A Modeling Approach. IEEE ELECTRON DEVICE LETTERS, 40 (10), 1579-1582.

Makarov, A., Kaczer, B., Roussel, P., Chasin, A., Grill, A., Vandemaele, M., Hellings, G., El-Sayed, A-M., Grasser, T., Linten, D., Tyaginov, S. (2019). Stochastic Modeling of the Impact of Random Dopants on Hot-Carrier Degradation in n-FinFETs. IEEE ELECTRON DEVICE LETTERS, 40 (6), 870-873.

Malinowski, P.E., Ke, T-H., Akkerman, H., Nakamura, A., Breemen, A.V., Velpen, D.V., Vandenplas, E., Hagelsieb, M., Verscheuren, L., Genoe, J., Dehaene, W., Jisk, A., Steudel, S., Gelinck, G., Heremans, P. (2019). Organic Photolithography for Displays with Integrated Fingerprint Scanner. SID symposium digest of technical papers, 50, Art.No. 1, 1007-1010.

Marin, J., Sacco, E., Vergauwen, J., Gielen, G. (2019). A Robust BBPLL-Based 0.18-mu m CMOS Resistive Sensor Interface With High Drift Resilience Over a-40 degrees C-175 degrees C Temperature Range. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54 (7), 1862-1873.

Moeyersons, J., Smets, E., Morales, J., Villa, A., De Raedt, W., Testelmans, D., Buyse, B., Van Hoof, C., Willems, R., Van Huffel, S., Varon, C. (2019). Artefact detection and quality assessment of ambulatory ECG signals. COMPUTER METHODS AND PROGRAMS IN BIOMEDICINE, 182, Art.No. UNSP 105050.

Mohammed, M., Verhulst, A.S., Verreck, D., Van de Put, M.L., Magnus, W., Soree, B., Groeseneken, G. (2019). Phonon-assisted tunneling in direct-bandgap semiconductors. JOURNAL OF APPLIED PHYSICS, 125 (1), Art.No. ARTN 015701.

Moors, K., Contino, A., Van de Put, M.L., Vandenberghe, W.G., Fischetti, M., Magnus, W., Soree, B. (2019). Theoretical study of scattering in graphene ribbons in the presence of structural and atomistic edge roughness. PHYSICAL REVIEW MATERIALS, 3 (2), Art.No. ARTN 024001.

Osca, J., Alomar, M., Serra, L. (2019). Spatial coupling of quantum-anomalous-Hall and chiral-Majorana modes. EUROPEAN PHYSICAL JOURNAL-SPECIAL TOPICS, 227 (15-16), 2025-2035.

145

Osca, J., Serra, L. (2019). Complex band-structure analysis and topological physics of Majorana nanowires. EUROPEAN PHYSICAL JOURNAL B, 92 (5), Art.No. ARTN 101.

Osca, J., Serra, L. (2019). Magnetic orbital motion and 0.5e(2)/h conductance of quantum-anomalous-Hall hybrid strips. APPLIED PHYSICS LETTERS, 114 (13), Art.No. ARTN 133105.

Petraglia, F., Scarcella, L., Pedrazzi, G., Brancato, L., Puers, R., Costantino, C. (2019). Inertial sensors versus standard systems in gait analysis: a systematic review and meta-analysis. EUROPEAN JOURNAL OF PHYSICAL AND REHABILITATION MEDICINE, 55 (2), 265-280.

Philippe, B., Reynaert, P. (2019). An F-Band n-Probe Standing Wave Detector for Complex Reflection Coefficient Measurements in 40-nm CMOS. IEEE Transactions on Microwave Theory and Techniques.

Piedrahita Giraldo, J.S., Lauwereins, S., Badami, K., Verhelst, M. (2020). Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10-μW Keyword Spotting and Speaker Verification. Ieee Journal Of Solid-State Circuits.

Qiu, W., Xiao, Z., Roh, K., Noel, N.K., Shapiro, A., Heremans, P., Rand, B.P. (2019). Mixed Lead-Tin Halide Perovskites for Efficient and Wavelength-Tunable Near-Infrared Light-Emitting Diodes. ADVANCED MATERIALS, 31 (3), Art.No. ARTN 1806105.

Ramkaj, A., Steyaert, M., Tavernier, F. (2019). A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple- Latch Feedforward Dynamic Comparator in 28-nm CMOS. IEEE Solid State Circuits Letters, 2 (9), 167-170.

Resta, G.V., Leonhardt, A., Balaji, Y., De Gendt, S., Gaillardon, P-E., De Micheli, G. (2019). Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 27 (7), 1486-1503.

Sacco, E., Marin, J., Vergauwen, J., Gielen, G. (2019). Performance Limitation Analysis of Highly-Digital Time- Based Closed-Loop Sensor-to-Digital Converter Architectures. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 66 (7), 1114-1118.

Sadeghpour Shamsabadi, S., Kraft, M., Puers, R. (2019). Design and fabrication strategy for an efficient lead zirconate titanate based piezoelectric micromachined ultrasound transducer. Journal Of Micromechanics And Microengineering, 29, Art.No. 125002. (professional oriented)

Sadeghpour Shamsabadi, S., Meyers, S., Kruth, J-P., Vleugels, J., Kraft, M., Puers, R. (2019). Resonating Shell: A Spherical-Omnidirectional Ultrasound Transducer for Underwater Sensor Networks. SENSORS, 19, Art.No. 757.

Saffari, H., Moghadam, R.A., Kraft, M. (2019). Wideband RF MEMS switch using two dimensional actuations. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 100 (2), 369-376.

Simicic, M., Weckx, P., Parvais, B., Roussel, P., Kaczer, B., Gielen, G. (2019). Understanding the Impact of, Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 27 (3), 601-610.

Simoes-Capela, N., Schiavone, G., De Raedt, W., Vrieze, E., Van Hoof, C. (2019). Toward Quantifying the Psychopathology of Eating Disorders From the Autonomic Nervous System Perspective: A Methodological Approach. FRONTIERS IN NEUROSCIENCE, 13, Art.No. ARTN 606.

Smets, E., De Raedt, W., Van Hoof, C. (2019). Into the Wild: The Challenges of Physiological Stress Detection in Laboratory and Ambulatory Settings. IEEE JOURNAL OF BIOMEDICAL AND HEALTH INFORMATICS, 23 (2), 463- 473.

Standaert, A., Reynaert, P. (2019). A 400-GHz 28-nm TX and RX With Chip-to-Waveguide Transitions Used in Fully Integrated Lensless Imaging System. IEEE TRANSACTIONS ON TERAHERTZ SCIENCE AND TECHNOLOGY, 9 (4), 373-382.

Thibaut, L., Knipprath, H., Dehaene, W., Depaepe, F. (2019). Teachers’ Attitudes Toward Teaching Integrated STEM: the Impact of Personal Background Characteristics and School Context. INTERNATIONAL JOURNAL OF SCIENCE AND MATHEMATICS EDUCATION, 17 (5), 987-1007.

Tian, S., Chen, J., Lian, X., Wang, Y., Zhang, Y., Yang, W., Wu, G., Qiu, W., Chen, H. (2019). Engineering the underlying surface to manipulate the growth of 2D perovskites for highly efficient solar cells. JOURNAL OF MATERIALS CHEMISTRY A, 7 (23), 14027-14032.

Vermeulen, B.F., Ciubotaru, F., Popovici, M.I., Swerts, J., Couet, S., Radu, I.P., Stancu, A., Temst, K., Groeseneken, G., Adelmann, C., Martens, K.M. (2019). Ferroelectric Control of Magnetism in Ultrathin HfO2\Co\Pt Layers. ACS APPLIED MATERIALS & INTERFACES, 11 (37), 34385-34393.

Villena, M.A., Hui, F., Liang, X., Shi, Y., Yuan, B., Jing, X., Zhu, K., Chen, S., Lanza, M. (2019). Variability of metal/h-BN/metal memristors grown via chemical vapor deposition on different materials. MICROELECTRONICS RELIABILITY, 102, Art.No. UNSP 113410.

146

Wu, Z., Franco, J., Vandooren, A., Kaczer, B., Roussel, P., Rzepa, G., Grasser, T., Linten, D., Groeseneken, G. (2019). Improved PBTI Reliability in Junction-Less FET Fabricated at Low Thermal Budget for 3-D Sequential Integration. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 19 (2), 262-267.

Xiang, Y., Verhulst, A., Yakimets, D., Parvais, B., Mocuta, A., Groeseneken, G. (2019). Process-Induced Power- Performance Variability in Sub-5nm III-V Tunnel FETs. IEEE TRANSACTIONS ON ELECTRON DEVICES, 66 (6), 2802-2808.

Xiao, Q., Wang, Y., Dricot, S., Kraft, M. (2019). Design and experiment of an electromagnetic levitation system for a micro mirror. MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 25 (8), 3119-3128.

Xin, H., Andraud, M., Baltus, P., Cantatore, E., Harpe, P. (2019). A 0.1-nW-1-mu W Energy-Efficient All- Dynamic Versatile Capacitance-to-Digital Converter. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 54 (7), 1841-1851. 1

Yamashita, Y., Stoffels, S., Posthuma, N., Geens, K., Li, X., Furuta, J., Decoutere, S., Kobayashi, K. (2019). Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process. IEICE ELECTRONICS EXPRESS, 16 (22), Art.No. ARTN 20190516.

Yan, J., Croes, G., Fakharuddin, A., Song, W., Heremans, P., Chen, H., Qiu, W. (2019). Exploiting Two-Step Processed Mixed 2D/3D Perovskites for Bright Green Light Emitting Diodes. ADVANCED OPTICAL MATERIALS, 7 (15), Art.No. ARTN 1900465.

Yang, W., Chen, J., Lian, X., Li, J., Yao, F., Wu, G., Qiu, W., Jin, C., Heremans, P., Chen, H. (2019). Black Phosphorus Quantum Dots Induced High-Quality Perovskite Film for Efficient and Thermally Stable Planar Perovskite Solar Cells. SOLAR RRL, 3 (8), Art.No. ARTN 1900132.

Yuan, S., Swartenbroekx, J., Li, Y., Zhu, J., Ceyssens, F., Zhang, R., Volodine, A., Li, J., Van Puyvelde, P., Van der Bruggen, B. (2019). Facile synthesis of Kevlar nanofibrous membranes via regeneration of hydrogen bonds for organic solvent nanofiltration. JOURNAL OF MEMBRANE SCIENCE, 573, 612-620.

Zdrali, E., Etienne, G., Smolentsev, N., Amstad, E., Roke, S. (2019). The interfacial structure of nano-and micronsized oil and water droplets stabilized with SDS and Span80. JOURNAL OF CHEMICAL PHYSICS, 150 (20), Art.No. ARTN 204704.

Zhai, D., Schiavone, G., Van Diest, I., Vrieze, E., DeRaedt, W., Van Hoof, C. (2019). Ambulatory Smoking Habits Investigation based on Physiology and Context (ASSIST) using wearable sensors and mobile phones: protocol for an observational study. BMJ OPEN, 9 (9), Art.No. ARTN e028284.

Zhang, Y., Song, S., Vullings, R., Biswas, D., Simoes-Capela, N., van Helleputte, N., van Hoof, C., Groenendaal, W. (2019). Motion Artifact Reduction for Wrist-Worn Photoplethysmograph Sensors Based on Different Wavelengths. SENSORS, 19 (3), Art.No. ARTN 673.

Zhu, K., Liang, X., Yuan, B., Villena, M.A., Wen, C., Wang, T., Chen, S., Hui, F., Shi, Y., Lanza, M. (2019). Graphene-Boron Nitride-Graphene Cross-Point Memristors with Three Stable Resistive States. ACS APPLIED MATERIALS & INTERFACES, 11 (41), 37999-38005.

15.2 Conference Proceedings Agub, U.R., Zebedee Aquino, J., Beano, J., Monsayac, R., Alvarez, A., De Leon, M.T., Vincent Densing, C., Hizon, J.R., Jossel Maestro, R., Rosales, M. (2019). A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications. In: IEEE Region 10 Annual International Conference, Proceedings/TENCON: vol. 2018-October, (1352-1356). ISBN: 9781538654576.

Ahmmed, P., Dieffenderfer, J., Valero-Sarmiento, J.M., Pamula, V.R., Van Helleputte, N., Van Hoof, C., Verhelst, M., Bozkurt, A. (2019). A Wearable Wrist-Band with Compressive Sensing based Ultra-Low Power Photoplethysmography Readout Circuit. In: 2019 IEEE 16TH INTERNATIONAL CONFERENCE ON WEARABLE AND IMPLANTABLE BODY SENSOR NETWORKS (BSN). Presented at the IEEE 16th International Conference on Wearable and Implantable Body Sensor Networks (BSN), Univ Illinois Chicago, Chicago, IL, 19 May 2019-22 May 2019.

Aspell, P., Dabrowski, M., Tavernier, F., Leroux, P. (2019). VFAT3: A Trigger and Tracking Front-end ASIC for the Binary Readout of Gaseous and Silicon Sensors. In: 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC). Presented at the 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), Sydney, Australia. ISBN: 978-1-5386-8494-8.

147

Baert, M., Dehaene, W. (2019). A 5GS/s 7.2 ENOB Time-Interleaved VCO-Based ADC Achieving 30.5fJ/conv step. In: 2019 IEEE International Solid-State Circuits Conference Digest of Technical Papers: vol. 62, (328-330). Presented at the 2019 IEEE International Solid-State Circuits Conference, San Francisco, 17 Feb 2019-21 Mar 2019.

Balde, A.V., Owen Cabuyadao, J., Densing, C.V., Richard Hizon, J., Rosales, M., Maestro, R.J., Theresa De Leon, M. (2019). Low Power Converter for Capacitive Sensors Using Capacitance-to-Pulse Width Modulation. In: IEEE Region 10 Annual International Conference, Proceedings/TENCON: vol. 2018-October, (570-573). ISBN: 9781538654576.

Bury, E., Chasin, A., Chuang, K-H., Vandemaele, M., Van Beek, S., Franco, J., Kaczer, B., Linten, D. (2019). Arraybased Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the {V-G,V-D} bias space. In: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 31 Mar 2019-04 Apr 2019.

Butzen, N., Steyaert, M. (2019). Advanced Multiphasing: Pushing the Envelope of Fully Integrated Power Conversion. In: 2019 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC). Presented at the 40th Annual IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 14 Apr 2019-17 Apr 2019.

Cabrera, G.P., Credo, J., Evidente, G.I., Malatbalat, R.R G., Mindoro, S.L., Ricardo Sanico, A., Alvarez, A., Densing, C.V., Jossel Maestro, R., Rosales, M., De Leon, M.T. (2019). A 2.4 GHz Energy-efficient Short-range Receiver with Wake-up and Multiple Gain Settings for Wireless Sensor Networks. In: IEEE Region 10 Annual International Conference, Proceedings/TENCON: vol. 2018-October, (26-31). ISBN: 9781538654576.

Camus, V., Enz, C., Verhelst, M. (2019). Survey of Precision-Scalable Multiply-Accumulate Units for Neural- Network Processing. In: 2019 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2019), (57-61). Presented at the 1st IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hsinchu, TAIWAN, 18 Mar 2019-20 Mar 2019.

Caselli, M., Boni, A. (2019). 3-D Maximum Power Point Searching and Tracking for Ultra Low Power RF Energy Harvesters. In: 2019 16TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD 2019), (121-124). Presented at the 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, SWITZERLAND, 15 Jul 2019-18 Jul 2019.

Catalano, A.P., Riccio, M., Codecasa, L., Magnani, A., Romano, G., d’Alessandro, V., Maresca, L., Rinaldi, N., Breglio, G., Irace, A. (2019). Model-order reduction procedure for fast dynamic electrothermal simulation of power converters. In: Lecture Notes in Electrical Engineering: vol. 512, (81-87). ISBN: 9783319930817.

Çelik, U., Reynaert, P. (2019). An E-Band Compact Power Amplifier for Future Array-Based Backhaul Networks in 22nm FD-SOI. In: 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), (187-190). Presented at the RFIC 2019, Boston, MA, USA, 02 Jun 2019-04 Jun 2019. ISBN: 978-1-7281-1701-0.

Chaudhuri, B.P., Ceyssens, F., Celen, S., Bormans, G., Kraft, M., Puers, R. (2019). In-Vivo Intradermal Delivery of Co-57 Labeled Vitamin B-12, and Subsequent Comparison with Standard Subcutaneous Administration. In: Proceedings of Engineering in Medicine and Biology Society (EMBC), Annual International Conference of the IEEE, (1670-1673). Presented at the IEEE EMBC 2019, Berlin, 23 Jul 2019-27 Jul 2019.

Cools, J., Gurné, T., Reynaert, P. (2019). A Broadband 13 Vpp 40% PAE Stacked Line Driver in 28 nm Bulk CMOS. In: 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS): vol. 25, (445-448). Presented at the International Conference on Electronics, Circuits and Systems (ICECS), Bordeaux, France, 09 Dec 2018-12 Dec 2018. ISBN: 978-1-5386-9562-3.

Cornelis, J., Smets, E., Van Hoof, C. (2019). Accelerometer-based sleep/wake detection in an ambulatory environment. In: HEALTHINF 2019 - 12th International Conference on Health Informatics, Proceedings; Part of 12th International Joint Conference on Biomedical Engineering Systems and Technologies, BIOSTEC 2019, (375-379). ISBN: 9789897583537.

De Roose, F., Celiker, H., Genoe, J., Dehaene, W., Myny, K. (2019). Dual-gate self-aligned a-InGaZnO transistor model for flexible circuit applications. In: 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), (25-29). Presented at the Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, ITALY, 25 Mar 2019-29 Mar 2019.

148

De Roose, F., Genoe, J., Kronemeijer, A.J., Myny, K., Dehaene, W. (2019). Memory Solutions for Flexible Thin-Film Logic: up to 8kb, > 105.9kb/s LPROM and SRAM with Integrated Timing Generation Meeting the ISO NFC Standard. In: L.C. Fujino, J.H. Anderson, L. Belostotski, D. Dunwell, V. Gaudet, G. Gulak, J.W. Haslett, D. Halupka, K.C. Smith (Eds.), 2019 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC): vol. 62, (206-+). Presented at the IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, 17 Feb 2019-21 Feb 2019.

De Vroede, A., Ooms, S., Philippe, B., Reynaert, P. (2019). A 94 GHz Voltage-Boosted Energy Harvester in 45 nm CMOS Achieving a Peak Efficiency of 21.2% at -8.5 dBm Input Power. In: IEEE EUROCON 2019 -18th International Conference on Smart Technologies. Presented at the Eurocon, Novi Sad, Serbia, 01 Jul 2019-04 Jul 2019.

Doevenspeck, J., Degraeve, R., Fantini, A., Debacker, P., Verkest, D., Lauwereins, R., Dehaene, W. (2019). Low voltage transient RESET kinetic modeling of OxRRAM for neuromorphic applications. In: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 31 Mar 2019-04 Apr 2019.

Evidente, G.I., Lorenzo Mindoro, S., Alvarez, A., Densing, C.V., Jossel Maestro, R., Rosales, M., De Leon, M.T. (2019). An Ultra-Low Power Direct Active-RF Detection Wake-Up Receiver with Noise-Cancelling Envelope Detector in 65 nm CMOS Process. In: IEEE Region 10 Annual International Conference, Proceedings/TENCON: vol. 2018-October, (12-15). ISBN: 9781538654576.

Feyerick, M., De Roose, J., Verhelst, M. (2019). Exploration and Design of Low-Energy Logic Cells for 1 kHz Always-on Systems. In: Proceedings of the 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE, (1697-1702). Presented at the 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Firenze, Italy, 25 Mar 2019-29 Mar 2019. ISBN: 978-3-9819263-2-3.

Georgitzikis, E., Malinowski, P., Li, Y., Lee, J., Süss, A., Frazzica, F., Maes, J., Gielen, S., Verstraeten, F., Boulenc, P., Mao, M., Guerrieri, S., Maes, W., Hens, Z., Heremans, P., Cheyns, D. (2019). Organic- and QD-based image sensors integrated on 0.13 μm CMOS ROIC for high resolution, multispectral infrared imaging. In: 2019 International Image Sensor Workshop (IISW), (Paper No. R43). Presented at the International Image Sensor Workshop, Snowbird, Utah, USA, 23 Jun 2019-27 Jun 2019. https://imagesensors.org/2019-papers/.

Gielen, G. (2019). The fantastic voyage towards ultra-miniaturized sensing circuits. In: 2019 IEEE 8TH INTERNATIONAL WORKSHOP ON ADVANCES IN SENSORS AND INTERFACES (IWASI), (35-35). Presented at the 8th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Otranto, ITALY, 13 Jun 2019-14 Jun 2019.

Gielen, G., Marin, J., Sacco, E. (2019). Improving the robustness and drift resilience of CMOS BBPLL-based time-based sensor interfaces. In: 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, (117-120). ISBN: 9781538695623.

Gielen, G., Xama, N., Ganesan, K., Mitra, S. (2019). Review of Methodologies for Pre- and Post-Silicon Analog Verification in Mixed-Signal SOCs. In: 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), (1006-1009). Presented at the Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, ITALY, 25 Mar 2019-29 Mar 2019.

Guimaraes, G., Reynaert, P. (2019). Analysis of substrate mounted dielectric lenses for silicon-based THz sources. In: 2019 12TH GLOBAL SYMPOSIUM ON MILLIMETER WAVES (GSMM 2019), (78-80). Presented at the 12th Global Symposium on Millimeter Waves (GSMM), Tohoku Univ, Sendai, JAPAN, 22 May 2019-24 May 2019.

Ha, H., Sijbers, W., Van Wegberg, R., Xu, J., Konijnenburg, M., Vis, P., Breeschoten, A., Song, S., Van Hoof, C., Van Helleputte, N. (2019). 22.5 A Bio-Impedance Readout IC with Digital-Assisted Baseline Cancellation for 2-Electrode Measurement. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference: vol. 2019-February, (368-370). ISBN: 9781538685310.

Halbach, A., Gijsenbergh, P., Jeong, Y., Billen, M., Chare, C., Gao, H., Torri, G.B., Cheyns, D., Rottenberg, X., Rochus, V. (2019). Modelling of display-compatible piezoelectric micromachined ultrasonic transducers for haptic feedback. In: 2019 20TH INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME). Presented at the 20th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), Hannover, GERMANY, 24 Mar 2019-27 Mar 2019.

149

Hellings, G., Roussel, P., Wang, N., Boschke, R., Chen, S-H., Simicic, M., Scholz, M., Stoedel, S., Myny, K., Linten, D., Hellings, P., Ashif, N.R M D. (2019). Concise Analytical Expression for Wunsch-Bell 1-D Pulsed Heating and Applications in ESD using TLP. In: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 31 Mar 2019-04 Apr 2019.

Higashi, Y., Florent, K., Subirats, A., Kaczer, B., Di Piazza, L., Clima, S., Ronchi, N., McMitchell, S.R C., Banerjee, K., Celano, U., Suzuki, M., Linten, D., Van Houdt, J. (2019). New Insights into the Imprint Effect in FE-HfO2 and its Recovery. In: IEEE International Reliability Physics Symposium Proceedings: vol. 2019-March. ISBN: 9781538695043.

Juillard, J., Brenes, A., Gouspy, M., Kraft, M. (2019). Towards the optimization of excitation waveform for electrostatic resonant sensors with enhanced frequency stability. In: J. Juillard, E. Lefeuvre, F. Mailly, Y. Mita, P. Nouet, F. Pressecq, P. Schneider, S. Smith (Eds.), SYMPOSIUM ON DESIGN, TEST, INTEGRATION & PACKAGING OF MEMS AND MOEMS (DTIP 2019). Presented at the 21st Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP), Paris, FRANCE, 12 May 2019-15 May 2019.

Konijnenburg, M., Van Wegberg, R., Song, S., Ha, H., Sijbers, W., Xu, J., Stanzione, S., Van Liempd, C., Biswas, D., Breeschoten, A., Vis, P., Van Hoof, C., Van Helleputte, N. (2019). 22.1 A7 69μW Battery-Powered Single-Chip SoC with BLE for Multi-Modal Vital Sign Health Patches. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference: vol. 2019-February, (360-362). ISBN: 9781538685310.

Li, C.H., Chiu, T.Y., Wu, W.M. (2019). CMOS devices and circuits for THz applications. In: Asia-Pacific Microwave Conference Proceedings, APMC: vol. 2018-November, (1151-1153). ISBN: 9784902339451.

Li, P., Molderez, T., Ceyssens, F., Rabaey, K., Verhelst, M. (2019). A 64-channel, 1.1-pA-accurate On-chip Potentiostat for Parallel Electrochemical Monitoring. In: ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), (Paper No. 4), (317-320). Presented at the European Solid State Circuits Conference (ESSCIRC), Cracow, Poland, 23 Sep 2019-26 Sep 2019. ISBN: 978-1-7281-1550-4.

Lin, Q., Xu, J., Song, S., Breeschoten, A., Konijnenburg, M., Chen, M., Van Hoof, C., Tavernier, F., Van Helleputte, N. (2019). A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors. In: IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Presented at the 2019 Symposium on VLSI Circuits, Kyoto. ISBN: 978-4-86348-720-8.

Makarov, A., Kaczer, B., Roussel, P., Chasin, A., Grill, A., Vandemaele, M., Hellings, G., El-Sayed, A-M., Grasser, T., Linten, D., Tyaginov, S. (2019). Modeling the Effect of Random Dopants on Hot-Carrier Degradation in FinFETs. In: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 31 Mar 2019-04 Apr 2019.

Mei, L., Dandekar, M., Rodopoulos, D., Constantin, J., Debacker, P., Lauwereins, R., Verhelst, M. (2019). Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. In: 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), (6-10). Presented at the 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hsinchu 30060, Taiwan.

Piedrahita Giraldo, J.S., Lauwereins, S., Badami, K., Van hamme, H., Verhelst, M. (2019). 18μW SoC for nearmicrophone Keyword Spotting and Speaker Verification. In: 2019 Symposium on VLSI Circuits. Presented at the Symposia on VLSI Technology and Circuits, Kyoto, Japan.

Qunaj, V., Reynaert, P. (2019). An E-band Fully-Integrated True Power Detector in 28nm CMOS. In: IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers. Presented at the 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Boston.

Ramkaj, A., Pena Ramos, J.C., Lyu, Y., Strackx, M., Pelgrom, M., Steyaert, M., Verhelst, M., Tavernier, F. (2019). A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS. In: ISSCC, (Paper No. 3.3), (62-64). Presented at the International Solid-State Circuits Conference (ISSCC), San Francisco, 17 Feb 2019-21 Feb 2019.

Ramkaj, A., Steyaert, M., Tavernier, F. (2019). A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple Latch Feedforward Dynamic Comparator in 28-nm CMOS. In: European Solid-State Circuits Conference, (167-170). Presented at the European Solid State Circuits Conference (ESSCIRC), Krakow, Poland, 23 Sep 2019-26 Sep 2019.

150

Sacco, E., Vergauwen, J., Gielen, G. (2019). Architectural Analysis of a Novel Closed-Loop VCO-Based 1-1 Sturdy MASH Sensor-to-Digital Converter. In: 2019 16TH INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD 2019), (261-264). Presented at the 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, SWITZERLAND, 15 Jul 2019-18 Jul 2019. (URL)

Sacco, E., Vergauwen, J., Gielen, G. (2019). From Open-Loop to Closed-Loop Single-VCO-Based Sensor-to-Digital Converter Architectures: theoretical analysis and comparison. In: 2019 IEEE 8TH INTERNATIONAL WORKSHOP ON ADVANCES IN SENSORS AND INTERFACES (IWASI), (29-34). Presented at the 8th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Otranto, ITALY, 13 Jun 2019-14 Jun 2019.

Sadeghpour Shamsabadi, S., Kraft, M., Puers, R. (2019). Coupled Piezoelectric Bulk-Micromachined Ultrasound Transducer (cPB-MUT): An Ultrasound Transducer with Enhanced Pressure Response in Liquid and Dense Medium. In: IEEE International Ultrasonics Symposium (IUS). Presented at the 2019 IEEE International Ultrasonics Symposium (IUS), Glasgow, Scotland, 06 Oct 2019-09 Oct 2019. (professional oriented)

Sadeghpour Shamsabadi, S., Kraft, M., Puers, R. (2019). Design and fabrication of a piezoelectric micromachined ultrasound transducer (pMUT) array for underwater communication. In: Proceedings of Meetings on Acoustics: vol. 38, (Paper No. 045006). Presented at the ICU 2019, Bruges, 03 Sep 2019-06 Sep 2019.

Sadeghpour Shamsabadi, S., Kraft, M., Puers, R. (2019). HIGHLY EFFICIENT PIEZOELECTRIC MICROMACHINED ULTRASOUND TRANSDUCER (PMUT) FOR UNDERWATER SENSOR NETWORKS. In: IEEE conference on solid State Sensors and Actuators (Transducers), (162-165). Presented at the The 20th International Conference on Solid- State Sensors, Actuators and Microsystems (Transducers 2019), Berlin, 23 Jun 2019-27 Jun 2019. (professional oriented)

Sadeghpour Shamsabadi, S., Lips, B., Kraft, M., Puers, R. (2019). FLEXIBLE SOI-BASED PIEZOELECTRIC MICROMACHINED ULTRASOUND TRANSDUCER (PMUT) ARRAYS. In: International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS), (250-253). Presented at the 2019 20th IEEE International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS 1029), Berlin, 21 Jun 2019-27 Sep 2019. https://ieeexplore.ieee.org/abstract/document/8808793. (professional oriented)

Sallam, M.O., Vandenbosch, G.A E., Gielen, G., Soliman, E.A. (2019). Modal Characteristics of Plasmonic Transmission Lines in Multi-Layered Media using the Method of Moments. In: 2019 13TH EUROPEAN CONFERENCE ON ANTENNAS AND PROPAGATION (EUCAP). Presented at the 13th European Conference on Antennas and Propagation (EuCAP), Krakow, POLAND, 31 Mar 2019-05 Apr 2019.

Sanchez, Z.R., Jason Vasquez, S., Alvarez, A.B., Vincent Densing, C.J., Hizon, J.R E., Jossel Maestro, R.M., De Leon,M.T G., Rosales, M.D. (2019). A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65 nm Technology. In: IEEE Region 10 Annual International Conference, Proceedings/TENCON: vol. 2018-October, (1870-1875). ISBN: 9781538654576.

Shah, N., Galindez Olascoaga, L.I., Meert, W., Verhelst, M. (2019). ProbLP: A framework for low-precision probabilistic inference. In: Proceedings of the 56th Annual Design Automation Conference 2019, (190:1-6). Presented at the Design Automation Conference, Las Vegas, United States, 02 Jun 2019-06 Jun 2019. New York, NY, USA. ISBN: 978-1-4503-6725-7.

Smets, S., Goedeme, T., Mittal, A., Verhelst, M. (2019). 2.2 A 978GOPS/W Flexible Streaming Processor for Real-Time Image Processing Applications in 22nm FDSOI. In: Digest of Technical Papers - IEEE International Solid-State Circuits Conference: vol. 2019-February, (44-46). ISBN: 9781538685310.

Smets, S., Goedemé, T., Mittal, A., Verhelst, M. (2019). A 978GOPS/W Flexible Streaming Processor for Real Time Image Processing Applications in 22nm FDSOI. In: 2019 IEEE International Solid-State Circuits Conference Digest of Technical Papers, (Paper No. 2.2), (44-46). Presented at the 2019 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 17 Feb 2019-21 Mar 2019.

Van Daele, T., De Pelecijn, E., Thielemans, T., Steyaert, M., Tavernier, F. (2019). A Fully-Integrated 6:1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm(2). In: 2019 15TH CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME), (49-52). Presented at the 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, 15 Jul 2019-18 Jul 2019.

Vandemaele, M., Kaczer, B., Tyaginov, S., Stanojevic, Z., Makarov, A., Chasin, A., Bury, E., Mertens, H., Linten, D., Groeseneken, G. (2019). Full (V-g, V-d) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs. In: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 31 Mar 2019-04 Apr 2019.

151

Vlasselaer, J., Meert, W., Verhelst, M. (2019). Towards resource-efficient classifiers for always-on monitoring. In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics): vol. 11053 LNAI, (305-321). ISBN: 9783030109967.

Wang, C., Liu, H., Wang, Y., Song, X., Bai, J., Kraft, M. (2019). Genetic algorithm for electro-mechanical cooptimization of a MEMS accelerometer comprising a mechanical motion pre-amplifier with a 2nd-order sigma delta modulator. In: J. Juillard, E. Lefeuvre, F. Mailly, Y. Mita, P. Nouet, F. Pressecq, P. Schneider, S. Smith (Eds.), SYMPOSIUM ON DESIGN, TEST, INTEGRATION & PACKAGING OF MEMS AND MOEMS (DTIP 2019). Presented at the 21st Symposium on Design, Test, Integration and Packaging of MEMS and MOEMS (DTIP), Paris, FRANCE, 12 May 2019-15 May 2019.

Wu, Z., Franco, J., Claes, D., Rzepa, G., Roussel, P.J., Collaert, N., Groeseneken, G., Linten, D., Grasser, T., Kaczer, B. (2019). Accelerated Capture and Emission (ACE) Measurement Pattern for Efficient BTI Characterization and Modeling. In: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 31 Mar 2019-04 Apr 2019.

Yu, K.O., Jossel Mindoro Maestro, R., De Leon, M.T G. (2019). A Study on the Effectiveness of Using a Hybrid Topology in Improving the Power Efficiency and Voltage Regulation over a Wide Input Range of DC-DC Converters. In: IEEE Region 10 Annual International Conference, Proceedings/TENCON: vol. 2018-October, (2104-2109). ISBN: 9781538654576.

Zhu, K., Liang, X., Yuan, B., Villena, M.A., Wen, C., Wang, T., Chen, S., Lanza, M., Hui, F., Shi, Y. (2019). Tristate resistive switching in heterogenous van der Waals dielectric structures. In: 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS). Presented at the IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, 31 Mar 2019-04 Apr 2019.

15.3 Abstracts/Presentations/PostersCeyssens, F., Bovet Carmona, M., Kil, D., Deprez, M., Tooten, E., Nuttin, B., Balschun, D., Kraft, M., Puers, R. (2019). Insertion and chronic performance of ultra-fine neural electrode arrays in vivo. Presented at the f-Tales workshop on Neuro-Sense and Sensibility, Leuven, Belgium.

Dabrowski, M.M., Carini, G., Chen, H., Gao, S., Zhang, J., Lopriore, E., Pinaroli, G., Tavernier, F., Leroux, P. (2019). Single-to-Differential Converter in 65 nm CMOS for the analog readout chain in DUNE Liquid Argon TPC. Presented at the 2019 IEEE Nuclear Science Symposium (NSS) and Medical Imaging Conference (MIC), Manchester, United Kingdom, 26 Oct 2019-02 Nov 2019.

de la Hucha Arce, F., Moonen, M., Verhelst, M., Bertrand, A. (2019). Comparison of bit depth allocation problems for signal estimation in wireless sensor networks. Presented at the 2019 Symposium on Information Theory and Signal Processing in the Benelux (SITB19), Ghent, Belgium, 28 May 2019-29 May 2019.

Galindez Olascoaga, L.I., Meert, W., Verhelst, M., Van den Broeck, G. (2019). Towards Hardware-Aware Tractable Learning of Probabilistic Models (workshop version). Presented at the 3rd Tractable Probabilistic Modeling Workshop colocated with the 36th International Conference on Machine Learning (TPM-ICML 2019), Long Beach, California, United States.

Michon, F., Aydin, C., van Daal, R., Den Bakker, H., Sun, J.Y H-J A N G., Haesler, S., Kloosterman, F. (2019). 3Dprinted implants that facilitate chronic recordings and reuse of neuropixels probes in freely behaving rodents. (Abstract No. 430.14 / CC72). Presented at the Society for Neuroscience, Chicago, Illinois, USA, 19 Oct 2019 23 Oct 2019.

Michon, F., van Daal, R., Aydin, C., Den Bakker, H., Sun, J-J., Kraft, M., Haesler, S., Kloosterman, F. (2019). 3Dprinted implants that facilitate recordings and reuse of Neuropixels probes in freely behaving rodents. Presented at the NERF retreat 2019, OPEK, Leuven, Belgium.

Ooms, S., Reynaert, P. (2019). Thz Communication Over Polymer Fibers Using Mm-wave Chipsets in Standard CMOS Technologies. Presented at the Huawei 2019 Novel Photonics Technologies Workshop, Munich.

Ooms, S., Reynaert, P. (2019). Using PMF for galvanic isolated communication and control links. Presented at the FIRST INTERNATIONAL WORKSHOP ON POLYMER MICROWAVE FIBER TECHNOLOGY, Leuven.

Shah, N.S., Galindez Olascoaga, L.I., Meert, W., Verhelst, M. (2019). PRU: Probabilistic Reasoning processing Unit for resource-efficient AI. Presented at the Hot Chips: A Symposium on High Performance Chips, Palo alto, California, United States, 18 Aug 2019-20 Aug 2019.

Sun, J-J., Coleman, J., van Daal, R., Kloosterman, F. (2019). A lightweight hyperdrive for optogenetics in freely behaving rats. Presented at the NERF Retreat 2019, OPEK, Leuven, Belgium.

152

Sun, J-J., Coleman, J., van Daal, R., Kloosterman, F. (2019). A lightweight hyperdrive for optogenetics in freely behaving rats. Presented at the RIKEN - KU Leuven Joint Symposium 2019, IMEC, Leuven, Belgium.

Vaes, J., Reynaert, P. (2019). PCB-embedded dielectric waveguides: An alternative for chip-to-chip and moduleto-module communications. Presented at the FIRST INTERNATIONAL WORKSHOP ON POLYMER MICROWAVE FIBER TECHNOLOGY, Leuven, 04 Mar 2019-05 Oct 2019.

van Daal, R., Ceyssens, F., Kloosterman, F., Kraft, M., Aarts, A. (2019). Flexible depth probes: towards higher channel counts and smart insertion strategies. Presented at the NERF Retreat 2019, OPEK, Leuven, Belgium.

van Daal, R., Sun, J-J., Ceyssens, F., Puers, R., Kraft, M., Kloosterman, F. (2019). Flexible high-density electrode arrays for chronic recordings of cellular activity in freely behaving rodents. Presented at the f-TALES Neuro-Sense and Sense-Ability, Leuven, 01 Apr 2019-02 Apr 2019.

Vermeulen, B., Swerts, J., Couet, S., Popovici, M., Ciubotaru, F., Adelmann, C., Radu, I., Stancu, A., Temst, K., Groeseneken, G., Martens, K. (2019). Ferroelectric Control of the Magnetic Anisotropy of an Ultrathin Co\Pt Bilayer. Presented at the MMM / Intermag 2019, Washington DC.

Vermeulen, B., Swerts, J., Couet, S., Popovici, M., Radu, I., Roussel, P., Temst, K., Groeseneken, G., Martens, K. (2019). Large Room Temperature VCMA in Co\Pt Bilayers Deposited on ALD-grown SrTiO : the Impact of the Interface. Presented at the MMM / INTERMAG 2019, Washington DC.

Vermeulen, B., Swerts, J., Couet, S., Popovici, M., Wu, J., Kim, W., Sankar Kar, G., Roussel, P., Van de Vondel, J., Temst, K., Groeseneken, G., Martens, K. (2019). Temperature dependence of VCMA in SrTiO3\Co\Pt trilayers: insights into the mechanism. Presented at the 63rd Annual Conference on Magnetism and Magnetic Materials, Las Veygas.

Wouters, J., Kalender-Atak, Z., Minnoye, L., Spanier, K., De Waegeneer, M., González-Blas, C.B., Mauduit, D., Davie, K., Hulselmans, G., Najem, A., Dewaele, M., Rambow, F., Makhzami, S., Christiaens, V., Ceyssens, F., Ghanem, G., Marine, J-C., Poovathingal, S., Aerts, S. (2019). Single-cell gene regulatory network analysis reveals new melanoma cell states and transition trajectories during phenotype switching.

Dept. Electrical Engineering - MICAS Kasteelpark Arenberg 10 - box 2443 3001 Leuven, Belgium tel +32 16 32 10 77 www.esat.kuleuven.be/micas