AnnouncementsThursday class TAPrelab 5

Decide on System ImprovementsRedesign using GaN Devices

Midterm after Experiment 5Open note, book, instructor

Today: Experiment 5No report; deliverables are layout files and BOM

Lab 5: PCB Layout

MSP430

Power Module

More information on motor drive in Experiment 5

Design ModificationYou may order additional parts, at reasonablecost/benefit

Will need to provide a listing of parts from digikeywith final Exp 5 files

Reuse components from lab kit wherepossibleUse SMD ceramic, low ESR caps for powerstage and gate drive decoupling

Circuit Enclosure

Circuit Enclosure Mounting

Circuit Connections

Prelab for Experiment 5: Redesign with GaN

EPC EPC2001C7 mOhm100V/36AQg = 9 nCCoss = 375 pF (80V)

GaN Systems GS61008T7.4 mOhm100V/80AQg = 12 nCCoss = 250 pF (80V)

GaN Devices

Vertical Silicon Power MOSFET Lateral GaN HEMT

No body diode (reverse conduction due to Vgd > Vgd,th 2V)Use antiparallel (schottky) diode or precise dead time

Significantly faster switching

Designing with GaN

Because of high electric breakdown fieldand high electron velocity, GaN devices withcomparable Ron can be significantly smallerand switch must faster.

Need very good layout to prevent ringingfrom causing overvoltage and device failure.

More information:

http://potenntial.eecs.utk.edu/About.php?topic=PowerSemiconductors

GaN Design Issues1. Reverse conduction mechanism2. Sensitivity to parasitics3. Gate robustness4. Small size > Thermal, soldering

difficult

Motor ControlMotor control is open loopUser throttle monotonically increases power

Controlled as BLDC motorTwo options to change throttle

Alter boost output voltageAlter duty cycle of motor drive

Motor Driver: Trapezoidal Control

Trapezoidal Control: HF PWM

Sinusoidal (Vector) Control

A Note: Reflected Voltages

Control Scheme Filtering

MSP430

Power Module

Motor Control Bandwidth ThrottleRelease

No Filter

Motor Control Bandwidthfc = 15 mHz

Motor Control Bandwidthfc = 8 mHz + antiparallel diode

Motor DrivePower Stage

IRAM power module (recommended)Integrated devices, drivers

Build your own power stageController

Allegro A4915Toshiba TB6551FAGOther options

Example Schematics in Starter Files forExperiment 5

PCB Layout for Experiment 5Include test points forvoltages/currents to aid debuggingWhere possible, give yourself“backup options”Make sure parts you select areavailable and have sufficient stock

even if some get ordered in theinterim

Basic PCB Layout ConceptsKelvin ConnectionParasitic Capacitances and DecouplingLoop Inductances / Complete RoutingDecouplingGround Plane / Return CurrentsPartitioning

Trace Parasitics

Kester, W. “Tips about printed circuit board design: Part 1 Dealing withharmful PCB effects”

Kelvin Connection

Texas Instruments, “LMP8640/ Q1/HV Precision High Voltage Current SenseAmplifiers”

DecouplingAlways add bypass capacitor at power supplyfor any IC/referenceUse small valued (~100nf), low ESR and ESLcapacitors (ceramic)Limit loop for any di/dt

Decoupling Capacitance

Analog Devices, “Decoupling Techniques,” MT 101

High Impedance Nodes and Capacitive Coupling

Analog Devices, “Decoupling Techniques,” MT 101

Capacitive Shielding

Analog Devices, “Decoupling Techniques,” MT 101Analog Devices, “A Practical Guide to High Speed Printed Circuit Board Layout”

Loop Inductances

Ground PlaneBenefits:

Common referenceShieldingHeat dissipationReduced inductance (increased capacitance)

Resist urge to cut ground plane as much aspossible; consider paths of return currentswhen cuts are unavoidable

Cuts in Ground PlaneGoals:

minimize inductance/loopsMinimize ground interference

Routing cuts should be kept short and out of thepath of any significant (high frequency) returnpathsCuts can be used effectively for ground isolation,and to reduce noise coupled betweendigital/analog/power circuitryReducing parasitic capacitance in sensitive signallocations (i.e. op amp circuitry)

Ground Plane Cuts

Ground return currentpath

Ground Plane Cuts

Ground return currentpath

Signal routing with ground plane cuts

Ground Plane Example

Maxim, TUTORIAL 5450, “Successful PCB Grounding with Mixed Signal Chips Follow the Path of Least Impedance”

Ground Plane Example

Maxim, TUTORIAL 5450, “Successful PCB Grounding with Mixed Signal Chips Follow the Path of Least Impedance”

Ground Plane Example

Maxim, TUTORIAL 5450, “Successful PCB Grounding with Mixed Signal Chips Follow the Path of Least Impedance”

Ground Plane Example

Maxim, TUTORIAL 5450, “Successful PCB Grounding with Mixed Signal Chips Follow the Path of Least Impedance”

Half Bridge Loop Inductance

Bridge Layout

Half Bridge Layout: Another Example

Lateral Vertical “Optimal”

D. Reusch & J Strydom, “Understanding the Effect of PCB Layout on Circuit Performance in a High Frequency Gallium NitrideBased Point of Load Converter”

Layout Impact Measurements

Smallest Loop Area results inSmaller overvoltageLower switching loss

D. Reusch & J Strydom, “Understanding the Effect of PCB Layout on Circuit Performance in a High Frequency Gallium NitrideBased Point of Load Converter”