anita rf conditioning and digitizing

ANITARF Conditioning and Digitizing

Gary S. VarnerUniversity of Hawai

,i, Manoa

ANITA Collaboration MeetingUC, Irvine

24,25 November 2002

2Gary S. Varner, ANITA Collaboration Meeting @ UC Irvine, November 2002Gary S. Varner, ANITA Collaboration Meeting @ UC Irvine, November 2002

Topics

• RF Signals– Noise Limited

• RF Electronics– Optimum SNR– Triggering– HS Transient Digitizers

• Prototypes– STRAW2– DRS– Advanced ATWD

• R&D Plans (for discussion)


Askaryan Signature

• Significant signal power at large frequencies

• Strong linear polarization (near 100%)

0 2 4 6 8

Time (ns)


Single Point Measurement

• Maximize R for better pointing… trigger latency

)/(4.01

1

1 00

0

TeV

W

R

KAE T

R

Empirically determined

DecoherenceFreq.

Material, aperture

• Squeeze all possible info.


RF Transient Recorder Specs

>= 1GHz analog input bandwidth (300-1200MHz) multi-GSa/s sampling rate (Nyquist limit ideal) minimum phase distortion for clean polarization maximum dynamic range (>= 9 bits) internal Analog to Digital Conversion (ADC) short record length (100-200ns if optimally matched)

self-triggering with fine threshold adjustment bi-polar triggering deadtimeless conclude multi-hit buffering

needed


Proposed Signal Flow

LNA Gain

Digitize

Trigger

[GHz]

[GHz]

.3 1.2

.3 1.2


Straw-man Instrumentation

Trigger/Digitizers


• In principle, can do brute force with off-the-shelf ADCs/backend processing (POWER! But other issues)

• A number of SCA designs:– DSC (samples obtained, to be tested)– KEK AMC– STRAW2 (SalSa prototype)– Advanced ATWD (Kleinfelder [UCI])

• Space/Balloon Transient RF specific:– >1GHz analog input bandwidth– Self-triggering– Low power

Possibilities


High-speed Digitizers

• DRC/DRS close

High Speed Digitizer Comparison

10

100

1000

10000

10 100 1000 10000

Analog Bandwidth [MHz]

Sam

plin

g R

ate

[MS

a/s]

ZEUS[12]

RD2[13]

Kleinfelder[14]

Haller[15]

ADeLine1[11]

DSC/DRS[16]

AD9410[17]

CLC5957[18]

TLV5580[19]

ADS5102[20]

MAX1449[21]

Desired Max.Operating Region

• Analog BW not eval.


Domino Ring Sampler (DRS)

input

• Free running domino wave, stopped with trigger

• Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution

• 1024 bins 150ns waveform + 350ns delay

• Free running domino wave, stopped with trigger

• Sampling speed 2 GHz (500ps/bin), trigger gate sampling gives 50ps timing resolution

• 1024 bins 150ns waveform + 350ns delayInformation courtesy of Stefan Ritt (PSI):

For further info.: http://meg.web.psi.ch/doc/talks/s_ritt/may02_triumf/meg.ppt

• If can keep the sampling jitter small enough (or can measure), no need for a TDC!

• Switched Capacitor Array (SCA)


Domino Sampling Chip

C. Brönnimann et al., NIM A420 (1999) 264

Existing:• 0.5 – 1.2 GHz sampling

speed• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 60 $/channel

Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout

Existing:• 0.5 – 1.2 GHz sampling

speed• 128 sampling cells• Readout at 5 MHz, 12 bit• ~ 60 $/channel

Needed:• 2.5 GHz sampling speed• Circular domino wave• 1024 sampling cells• 40 MHz readout


STRAW2 Specifications

> 1GHz ind. Adj.256 ind. Adj.32 OR of 1616 multiplicity

1-2 GHz high+low12 32 bits/ch.

<=16 ms cascadeADC (SAR) bits

Digitize deadtime

High level thresholdLow level threshold

High level logicLow level logic

Comparator typeMonitor scalers

Trigger type

# SCA/channel# of channels# of RF inputsSampling rate

Analog Triggering

STRAW2 Design Parameters

Input bandwidth

• Unique in this design is the triggering requirements – High freq and bipolar

• Large latency strategy:– Multiple buffering


STRAW2 Architecture

• 0.25m TSMC process


Ring Oscillator in 0.25m CMOS

Simulated Frequency Adjustment range

0

0.5

1

1.5

2

2.5

1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8

Vadjust [V]

Sam

pli

ng

Fre

q [

GH

z]


Analog Input Bandwidth!

• Many examples of high sampling rate, but:– PMT readout– Wireless (2.5GHz)

– Very narrow BW

– Naïve calculation • phase• inductance

– 3-D Simulation• PCB, Package, bond wires• BGA necessary?• What is fundamental limit

.4.62

13 GHz

RCf dB

Component Length/area Unit Factor FunitTotal [fF]

Input traces 5 cm 0.2 pF/cm 1000 w.a.g.bonding wire 150 mil 0.3 pF/wire 300 w.a.g.

input pad 60 um^2 187 fF/pad 187 Tannerinput protection 594 1.1 pF/ckt 1100 SPICE

stripline area 2500 um^2 43aF/

um^2 107.5 MOSISstripline fringe 5 mm 60 aF/um 300 MOSISSwitch Drains 256 switches 5.6 fF/drain 1433.6 SPICEOpen Switches 6 open 87 fF/gate 522 SPICE

TOTAL 4.9501 pF


RF Coupling Simulation

die

on-chip 50 stripline

• Utilizes the LC program (FTDT algorithm)– Cray developed, available for free under Linux

Bonding wires

.4.62

13 GHz

RCf dB

.4.6

2

13 GHz

RCf dB

.4.6

2

13 GHz

RCf dB

.4.6

2

13 GHz

RCf dB


S-Parameters

STRAW2 Packaging S-Parameters

0

0.2

0.4

0.6

0.8

1

1.2

0 0.5 1 1.5 2 2.5 3

Frequency [GHz]

S11

S21

VSWR:

1.8 [1GHz]

1.9 [2GHz]


Logging Performance

Storage Cell Simulation

y = 6.2891x - 2364.8R2 = 0.993

0

100

200

300

400

500

600

700

350 400 450 500

Stored Waveform (Vin) [mV]

Dif

f se

nse

d V

olt

age

(Vo

ut)

[m

V]

Rload = 40k

Gain:

mVC

kTv

storerms 23.0


Self-Triggering


Simulation Results

• Use simulated high freq. Response from beamtest data:– works


32x256 SCA bank

DACs ADC

Trigger

scalers

STRAW2 Chip

Submitted for Fab.: 4 Nov.

16 Channels of256 deep SCA buckets

Self-Triggered Recorder Analog Waveform (STRAW)

Optimized for RF inputMicrostrip 50

Record length:128-256ns

Self-Triggering:

Target input Bandwidth:>700MHz

-LL and HL (adj.) for each channel

Sampling Rate:1-2GSa/s (adj.)

-Multiplicity trigger for LL hits

On-chip ADC:12-bit, >2MSPS

External option:MUXed Analog out

Sampling Rates>~8GSa/s possiblew/ 0.25m process

8192 analog storage cells

Die:~2.5mm2


Cosmic-ray Radio Testbed

• Stage 2: Replace TDM with STRAW2– ~200 total antenna signals – get rid of delay cables


Evaluation

Trigger/Digitizers


Readout Board/RF prototype

Strong disincentive to purse a “full

card” development to start with

10k$ parts!


Details…documentation

Push to document these details


• R&D into critical (non-standard) components:– Strong need in other (e.g. precision timing)

applications– Not needed for self-triggering/high analog BW (PMTs)– Emphasis on low-power

• Plans:– STRAW2 Testing (packaged parts ship 12/19)– ANITA evaluation board/backup ADCs– Adv. ATWD Prototype (common START ready for fab.)

• Discussion: (see next slide)

Preliminary Summary


• Time scale for custom component development– STRAW2 appropriate triggering architecture?

• Really need trigger waveform recording?

– Sample depth/rate and bandwidth for ATWD?– Multi-buffering scheme acceptable?– Still consider RF down-conversion/comm. ADCs?

• Many disadvantages (large BW DCV, power)• Viable fallback?

• Plans:– STRAW2 Testing (packaged parts ship 12/19)– ANITA evaluation board/backup ADCs– Adv. ATWD Prototype (proto. Waiting for $$)

Discussion Items


3 Designs Similar

• 16 cells

• All paracitics included

• Domino speed: 1.5-2.2 GHz

• 16 cells

• All paracitics included

• Domino speed: 1.5-2.2 GHz

10 GHz?

Simulated Frequency Adjustment range

0

0.5

1

1.5

2

2.5

1.2 1.7 2.2 2.7

Vadjust [V]

Sa

mp

lin

g F

req

[G

Hz]

TSMC 0.25m

AMC:


KEK AMC

• Analog Memory Cell (AMC) – Common

platform– Original

AMC follow-on

– Super Belle and JHF

0.5m:LSB ~200ps

0.35m:LSB ~100ps?

anita rf conditioning and digitizing

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