analyzing noise for the muon silicon...

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Analyzing Noise for the Muon Silicon Scanner Miguelangel Marchán, University of Illinois at Chicago – GEM Program Michael Utes, Fermi National Accelerator Laboratory Background The development of a silicon muon tomography detector is a joint project between Fermilab and National Security Technologies, LLC. The goal of this detector is to detect nuclear materials better than technology in the past. Using silicon strip detectors and readout chips used by experiments at CERN we have been developing the detector. This summer we have been testing components of the detector and have been analyzing noise characteristics. Each SKIROC Chip has 64 channels and each carrier board has six SKIROC chips for a total of 384 channels. Using the SKIROC chips we are able to convert the analog signals from the sensors into digital signals. These signals are read as ADC (Analog to Digital Converter) counts. We took runs with the help of software such as Bitvise and Terraterm to analyze the pedestal noise while increasing the bias on the sensors starting from 25V to 200V. Data files were created for each run. The files contain information such as chip header address, trigger number, and ADC values. Increasing bias voltage reduces detector capacitance which then reduces random noise. Using C code and Root, we wrote a macro that would analyze data files and plot noise vs voltage. The first set of data that was used was taken in early July. The second set of data files that were used were taken in late July. Using Root, We compared the plots of both these sets of data. Error distribution plot (top) and Voltage vs Error Mean (bottom) of data from early July Silicon detector strips with SKIROC chips and various electronic components ADC count histogram plot of all available channels at 0V Error distribution plot (top) and Voltage vs Error Mean (bottom) of data taken in late July Conclusion For the data files from early July, the error distribution plot has a nice gaussian fit. For the newer data files the error distribution plot has more peaks than it should and so the gaussian fit seems off. One of the possible reasons for this is that the first 10 channels in the first sensor had an extra ground bond while this was not the case when the first set of runs were taken. The overall noise performance is good and shows that the detector should perform well with bias above 180 volts. Analyzing Error Distributions Results Taking Pedestal Runs References Christian, David. “Silicon Tracking Detectors.” 2014, Print Spieler, Helmuth. “Semiconductor Detector Systems.” Oxford: Oxford UP, 2005. Print

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Page 1: Analyzing Noise for the Muon Silicon Scannereddata.fnal.gov/lasso/summerstudents/papers/2017/Miguelangel-Ma… · such as Bitvise and Terraterm to analyze the pedestal noise while

Analyzing Noise for the Muon Silicon ScannerMiguelangel Marchán, University of Illinois at Chicago – GEM ProgramMichael Utes, Fermi National Accelerator Laboratory

Background

The development of a silicon muon tomography detector is a joint project between Fermilab and National Security Technologies, LLC. The goal of this detector is to detect nuclear materials better than technology in the past. Using silicon strip detectors and readout chips used by experiments at CERN we have been developing the detector. This summer we have been testing components of the detector and have been analyzing noise characteristics.

Each SKIROC Chip has 64 channels and each carrier board has six SKIROC chips for a total of 384 channels. Using the SKIROC chips we are able to convert the analog signals from the sensors into digital signals. These signals are read as ADC (Analog to Digital Converter) counts. We took runs with the help of software such as Bitvise and Terraterm to analyze the pedestal noise while increasing the bias on the sensors starting from 25V to 200V. Data files were created for each run. The files contain information such as chip header address, trigger number, and ADC values.

Increasing bias voltage reduces detector capacitance which then reduces random noise. Using C code and Root, we wrote a macro that would analyze data files and plot noise vs voltage. The first set of data that was used was taken in early July. The second set of data files that were used were taken in late July. Using Root, We compared the plots of both these sets of data.

Error distribution plot (top) and Voltage vs Error Mean (bottom) of data from early July

Silicon detector strips with SKIROC chips and various electronic components

ADC count histogram plot of all available channels at 0V

Error distribution plot (top) and Voltage vs Error Mean (bottom) of data taken in late July

Conclusion

For the data files from early July, the error distribution plot has a nice gaussian fit. For the newer data files the error distribution plot has more peaks than it should and so the gaussian fit seems off. One of the possible reasons for this is that the first 10 channels in the first sensor had an extra ground bond while this was not the case when the first set of runs were taken. The overall noise performance is good and shows that the detector should perform well with bias above 180 volts.

Analyzing Error Distributions

Results

Taking Pedestal Runs

References Christian, David. “Silicon Tracking Detectors.” 2014, PrintSpieler, Helmuth. “Semiconductor Detector Systems.” Oxford:Oxford UP, 2005. Print