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Analyse van een besturingssysteem voor stappenmotoren in een "open-loop"-systeem Citation for published version (APA): Verbaarschot, B. (1986). Analyse van een besturingssysteem voor stappenmotoren in een "open-loop"-systeem. (TH Eindhoven. Afd. Werktuigbouwkunde, Vakgroep Produktietechnologie : WPB; Vol. WPA0349). Technische Universiteit Eindhoven. Document status and date: Gepubliceerd: 01/01/1986 Document Version: Uitgevers PDF, ook bekend als Version of Record Please check the document version of this publication: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement: www.tue.nl/taverne Take down policy If you believe that this document breaches copyright please contact us at: [email protected] providing details and we will investigate your claim. Download date: 27. Jul. 2020

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Page 1: Analyse van een besturingssysteem voor stappenmotoren in ... · Analyse van een besturingssysteem voor stappenmotoren in een "open-loop"-systeem Citation for published version (APA):

Analyse van een besturingssysteem voor stappenmotoren ineen "open-loop"-systeemCitation for published version (APA):Verbaarschot, B. (1986). Analyse van een besturingssysteem voor stappenmotoren in een "open-loop"-systeem.(TH Eindhoven. Afd. Werktuigbouwkunde, Vakgroep Produktietechnologie : WPB; Vol. WPA0349). TechnischeUniversiteit Eindhoven.

Document status and date:Gepubliceerd: 01/01/1986

Document Version:Uitgevers PDF, ook bekend als Version of Record

Please check the document version of this publication:

• A submitted manuscript is the version of the article upon submission and before peer-review. There can beimportant differences between the submitted version and the official published version of record. Peopleinterested in the research are advised to contact the author for the final version of the publication, or visit theDOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and pagenumbers.Link to publication

General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright ownersand it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.

• Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal.

If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, pleasefollow below link for the End User Agreement:www.tue.nl/taverne

Take down policyIf you believe that this document breaches copyright please contact us at:[email protected] details and we will investigate your claim.

Download date: 27. Jul. 2020

Page 2: Analyse van een besturingssysteem voor stappenmotoren in ... · Analyse van een besturingssysteem voor stappenmotoren in een "open-loop"-systeem Citation for published version (APA):

AFDELING DER WERKTUIGBOUWKUNDETECHNISCHE UNIVERSITEITEINDHOVEN

VAKGROEP PRODUKTIETECHNIEK EN AUTOMATISERING (WPA)

A~ALYSE VAN EEN BESTURINGSSYSTEENVOOR STAPPENMOTOREN IN EEN"OPEN...LOOP"""SYSTEEM.door B. Verbaarschotrap,. 1\1. wrA. 01'"

Verslag Tan een 1.1 -opdrachtuitgevoerd in opdracht van

ir. R. BUlhoofd Engineering.alker-Hagou BY.Bladel/Holland·en

prof.ir. J.M. Tan Bragt

Onder begeleiding Tanire P••• (OUIlaDSmedewerker vakgroep WPA

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~~~

'* e.\7~",c.c.£ ~~o.-~ ~~'t>~~ ~ ~d~~~~eue,...

~~ C.O.V. k4!.t: ~sle ~oJ1 ~~ ,,~~ ~ de.

ef' - 0, ~ .. COH~~Y)~E. woraJ.e- ~t:d..d.. Oe.a.e ~~..

k..:.~~ 2.~ ~U:.o..OooV\ cM~ ~~~ ol~ ~"-040~ ~

c:Lz. c.o~U"loAcl1-~~o

O~ "'~ oJ..~e-e.e- 2.oJ.. k'12. o.tw~~~ ~"oot ~V\ I ~­

~ ~ ee...... :,~~ o.U ve. i ~ b\~ ...5' ~ "'-d: (.UC.e;lle..-eA:.v\

ko.- UOC>I'oloe-. Hc.k ~~~t'\O~ "'ee (.CW'~f>~~~"

~o.. \)0..0.4 l:e cJ.cC)t'l.o~I~ ,,~ ~~~CA..~ .et..r we!

\.')CO..- 2.0~ ~ U:..ct~ ~c..- bo~ "'~~~'-""OV'c::Lt

CO~~·

AL", ~",,~.\.e """l. L.k b\::V.leY\ ~ he,t. cJ.,bo., WoJ..k.~ .. ~ou.

o",,~~i.\OLe.1de Ioe..~b..u-'~~~~t:~ -~ op~ c::kL~~~~ 'o\.~

0"'"~~~~pt-"""O~ c~\U.Mba ~~~ n\U \oe.~

~ e~ p~~ ~ ~eA:~ re.de.~\c.e. "'Q'u~\ceux~~c:l,)c:J,.J.!a ko.-

~f"~ u~oot.~ "e.t. ~~e.-. ~ ~ c:onu.l:ie.~Y~~.

f.::>c. o~t6te. \o~~~ ~bte.w- U ~ p"'oc..e:,~c.c.F~t::eiJ::.

E", "Zo..l ",o..~~ Of->~~ \Jo)O'fdc- b:>~ clo.t cke:u:.~­

~t. ~ \.Uo.,~ O\)~oft:cl~.

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-53 -

a 'Ou.':'cJ..e to ""'-C>c.h:......~ thc::::Dn..~

(LV\. do. p""eu:.. b ..c.e .

B.C. Kv.o T""u~,,""'~-'\.to..\. fY'"\ctA.Q" <'01"-..\:'(0.: ~\:~?\.h0 ~o,~ c.........t\.

~\:.<"O\e. ~~~.

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APPENDIX:•

- 5t.t -

8253Programmabl. 'n'er".1 "'mer

.dtfanced MOS/LS.

DISTINC'nVE CHARACTERISTICS

• Bo1l'1 Binary « BCD counling• Single +5V IUPPIy• Three independenl16-bit countelS• DCtoSMHz• Programmable counter modes• Bus oriented 110

BLOCK DIAGRAM

GENERAL DESCRlPT10N

'"'-1253 is aprograrmnabl. counterl1irner dllpdeIlgned forlite with eoeOA~SA mic:roproce8aor. 1My lite NMOStechnology with a lingle +5V IUppIy end lie drecl replace­rnerlls for 1tQl., 8253,uss·5.

Each device is organized IS three independent 16·bitcounters. etch counter having a rate 01 up to 5.OMHz. Allmodes 01 operation lie software programmable. For im­proved performance devices Me AmlI513 System TImingController.

CONNECTION DIAGRAM - Top VIewo-N·1. P·M·1

-AI..OAt

..,.,

..,-.NaIll: Pin 1 Iallllllred lor aMnlalIon.

PIN NAMES

D7-IXl D8III buI (8-bll)

CUtN eour. dock iIpuIs

GATEN eour. galt iIpuIs

OUTN eour. CllIlPUlS

AD ANd OllU!lltr

WR WriIe COl'/lI'I'IIIIl or cIata

CS 0lip1Mcl

AO-A1 CourtIer ItIect

vee +5Vob

GND Gnlund

ORDERING INFORIIAl1ON

Orclering Numbers

tRo .aoona tRO·2OOne tN) .12Ona..... Type AmbIentT~ tcY • IlOna tcy." tcY -aoona

MoIdecI DIP P8253 P8253-5 fII253·2

HermRcDlPO"C '" TA '" ...7O'C

D8253 Dll253-5 Dll253·2

HemwlicDIfl -4O'C '" TA '" +15"C ID82S3 1D8253-5

HennMicDlP -55"C '" TA '" + 125"C MDll253B

FUNCOONAL DESCRIPTION

General

'The 8253 is • programmable intervallirnertcounler epeclficatYdesigned for use with tie 8060A Microc:omputllr systems. lisfunction is thet 01 ageneral-purpose. roollitiming element that c:anbe tre8t8Clas an array 01 110 ports in the system eoftware.

'The 8253 aolYes one 01 the moat oomrnon problems in anymcrocomputer aystem. lie generation 01 accurate time delaysunder 80fIware control. Instead 01 aetling up liming loops inIY'18ITlS software. the programmer configures the 8253 to melchhis requirements. initiuzes one 01 tle countelS 01 tie 8253 withlie desired quanlity, tlen upon command the 8253 wi" count oulthe delay and intemJpt the CPU when it has completed its tasks.h is 1I8Sy to ... tlal the software overhead Is minimal andthat multiple delays c:an easily be maintained by assignment 01priority levels. '

Other counterltimer func:lions that aie /llll'lod8Iay in natura, butalso common to mosl microcompu1ers c:an bei~ withthe 8253.

• Programmable Rete Generator• Event Ceunter• Binary Rete Multiplier

• Real-Time Clock• Digital One-Shot- ~Iex Motor ConlroIer

Data Bua Buffer

This 3-atate. bidirectional. 8-blt buffer is U88d to interface the8253 to the system data bus. Data is transmitted or received bythe buffer upon execulion 01 INput or OUTput CPU instructions.'The Data Bus Buffer has three basic tunclions.

1. Programming the MOOF.S 01 the B2532. Loading the count registers3. ReaQng the count valu.

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"'.

A1

MODE Cof*ol WordCounllll'rn

cs RD ~ A1 AIJ

0 1 0 0 0 l.-l CounIar No. 0

0 1 0 0 _1 l.-l CounIer No. 1

0 1 0 , 0 l.-l ColIn_ No. 2

D 1 0 , 1 Wr1lI MODE Word

0 0 1 0 0 . flIeed Caunter No. D

0 0 1 0 1 ANd c:eu- No. 1

D 0 1 1 0 "-' ClIIunter No. 2

0 0 1 1 1 ND-OperDon 3-S- .J, X X X X DieIble 3-6teIe J0 1 1 X X ~3-S1811 j

rMODE Control WordI No.' 1 1

I CcM.-O

'_2 MODE Control Word1 1CaunIer 1

i No.1MODE ConlroI Word

1 1CclunlIIr 2

No.4 LS8 Counl RegiAIr By-.0 1CclunIer 1

I_Ii MSB Count Regi'" By-. 0 1CaunIer ,

lID. I LS8 Count Regislar By-. 1 0Courter 2

IMIl 7 MSB· Caunl RegiIIer By-.1 0Counlllr 2

,Count RegiAIr By-.IItID.I LS8 Counllr 0 0 0

L..·•MSB Count RegieltIr .,..

0 0Counlllr 0

.... The8lCCllllv'-*"-t1"chCllUl*r'.CllIUr't~I'II8Ir8!hetItlk 01 poogrMIIIling lie12538vwy~nwn.r.-'muimum1IIfec:tiveuee Ollie cIeWle wli~••till,..". 181u1y LIIlIzed.....~

.. tI1lIIt 0CIUf1llIr eppIicaIions It~ MC8SI8ry to read the-'01 \he count In progrRS and make.~tionaldecision..... on this quantity. Event counters .. probably the moslIIIlwnon 8pplication that UI8S thil Iunclion. The 8253 contains- f1a1 wiD allow the programmer to -.it)' read the contents 01.., lillie Ihrw COUl'IltIr8 wItloul cIatultling lie llCkIaI count in......

: N counters - down COUntenl. ThuI vMIi Io8ded Inlo thelIIlII"' I'Igister wII lCluaiIy be ".cr III.d. I..oMing .. Illf08S_ I count rwgister wi. rasuII in lie /IIIIlilnum count (218 forIlflIrY or 1()4 for BCD). In MODE 0 \he new count wiN IllIt raslart.....1fie load..been completed. It w1111Xl1pl one 01 two bytesdIPllflCing on how the MODE cantroI Wllfds (ALO. RL1) areprogrammed. Then proceed wlth lhe ....... operation.

Ptoifiemmlftg Format

1253 READ/WRITE PROCEDUREWrite 0perwtI0nI

The systems IClftwln must progrwn each counter 01 the 825'wlth lhe mode and~y desired. The programmer must ..,.aut lID lhe 8253 a MODE cantroI word and lhe progt8ll1ftllllnumb8r 01 count regisSllr bytes (1 or 2) prlorto actually~"IeIec:ted counter.

The~ ord« 01 .. programming is~ tled:JIe. Wrt1I~,,­oIlhe MODE control word c.n be in .""~ d __1eIection••.g., coul'lte! #0 Cka not heY.lID be first or~"lest. Each c:ounter'l MODE cantroI word AIgister '*•___8ddreIs 10hIlls Ioecing II~y I8qI.Hll'IC8i~CSCO, SC1) . .

The taUng allhe Count RegiSter wlth lhe aclual counl .".however, mm be done In exactly the~ progra""'*"tie MODE control word (ALD, RL1). This Ioaclng d the~count register is Ilia MqUence lndepeodent ~ke the MODE r#"WI word 1oa6ng. but When. MIected count Ngisler" to"bided it~ be IoalSeC With ~e rumtler d bytes P't>ll.i~In I'le MODE control word (RLO, RL'). The one or two~Ill'"loaded in lhe count "'lliIter do not have to follow the~MODE oontrol word. They can be progrIlIMl8lS at fI'I'/fclIowin9 the MODE control word Ioecl"ll_1Dng ...~IlUtI'lbef d br* II Iaeded In 0I'def.

M.M .n-e~ _ normeIy corwleCteClllD lhe adlhls bill. Theirfunction is to .eIec1 aniI d the tvee counters lID be operalieCI 01'1

and lID address lhe control word register lor MODE 18Iedion.

CS (ChIp Select)

A "low" on this input ei1abI. lhe 8253. No reacIng or writing willoccur unless lhe deYices is eelected. The CS input hal no effectupon the 8CUII apendion 01 tie ClCllIf*Ir.

Control Word RegIatIr

The ConIroI Word Register is NleCted when AD. A1 _11.• then8CCePlS Intormation 110m the a.ta buI bufler and a1(QI It In •register. The inIomIatiOI'II1O*l in this regisler controls the oper'IIIiOnIII MODE of NCh ClClUI'1Ier. IMcliOII 01 binary or BCD eourw.Ing and the toadirlg 01 81th oount ,.... •

The Control Word Aegiar C8l tIf'Iy be WIllen ln1ID; no ...aperation 01 Its CCII*nIS II 1VIiIIbIe.

eoum. H. CounlIIr '1, c:oum.r.2These three functional blocks _ ider1tical1n operation 10 only•RlgIe Counter will be dellCllbecl. Each Counter~ d •lingle, 16-bit. prasettable. DOWN counter. The counter c:an~erate In either binary or BCD and Its input, gale and outpuI ..configured by'" Ielection 01 MODES stored in the Control WllIlIRegister.

The counters _ fully W1cIepenclent and each can have S8P8ral1MODE configuration and counting operation. binary or BCD.Also. there are special features in the control word thaI handle ..Ioeding 01 lhe count value 10 lhIt -mw_ overhead can IIIminimized lor Iheae tunctions.

The ruding 01 \he canIents d eadl ccuntIir ill available lID ..programmer with limple READ operations for event OCIU~lIPP~cations. and special commands and logic _ included in..8253 so that the c:ontents oIaach counte' can be read "on !he Iy'wiIhoUt heving lID inhlbiI the clock inpUt

AeecSlWrite Loglc

The ReaO.IWri1e Logic accepts~ from 1he svstern tll!s and in

un gener&la control lignal$ lor lWtnI o-ce operation. It is t ClIIunt RegiIW~enabled or disabled by CS 10 Il'lal no opera1On can occur to Ii, MSBLSB eo.. nchange the lundion WlIess the deYice ha&~ I8lec1lld by the :..._------ _

CounI""-- "'-system logic. ~ .,,-

iiD (Reed) Nllle: Formallhown ill ••••..,. t1 JDmng !he 8253-' doesA "low" on \his input irlIorms the 8253 ht \he CPU is ir1lUtlIng nollmply IleI it Is !he only Iarmld 1Iall*l be UNd.data in lie larm 01 • counlln value. : AIlemN Prognmmlng FonMIa

WR (WI1tIe)

A "loW" on this input informs the 8253 Il'lal the CPU11 DUlpUttingdata in the form 01 MODE inlorrnation or~ oounlIra.

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CUt 1--";;-;;";;;"--1

-...._---- ..-..

-... •• .,D! «*0 .......~ .1l!53.$ aIoCiIllr1M. IlllIIIl ......... II 8111 (1/ ....

'ThIn art two metladIIlhel..prClglatMlet.."..to,.., tie ,"""..... the 1253VIIIue 0I1he COUI'lI8rI. The tnt me1hod involvl6\he I.e 0I1imple AI of the MODES lor _ch counter are programmed by thel/Oreedoperalionsoftlel8llctlldcounter. By controIing\heAO, tyStems eottware by IIimple I/O operations.A1 qMs to the 8253 the p1llg1W\'11T1e1''''' eeIect \he 0DUf'IIer to be .e.cn~ of lie 8253 is incIvidualIy programmed by writing aMad (remerrber thet no"" ~tion of tie mode regis18r is oontroI word into the Control Word Register (AD, A1 .. 11).dowed AD, A1 -11). The orIy~rementwltll this method is thatIn order to usure • ItIbIe ccunt realing \he ICtual opeI1Ition of c:ontroI Won! FanMtlie I8Iected counter InUIt lie Inhlbhld lither by conlrcAng theGate input or by extemlllogic hal iMibi\s the docIl input. The 07 De OS DC D3 . 02

.conl8ntS of .... counter --.::lId wiI be avlUble • toIIcMs: &C1 100L...;;~.,.I...;~-L..._.......L.._--L._""'__"--_"""'----'

Iirat I/O Reed CXInIains .. least tigniticanl byte (l..5B).

aecond 110 Read ClOnIIinI .... most lignific:anl byte (USB). a.ftnitlOn of Control

Due to the intema110gic of..8253 it is 8bsollJte1y necessary to SC - SIIeet Counlw:CCII11)lel41 t1e ~re reati..... pr~'e ~ \We by\e& we pro. SC1 tK:O

0 ·0 0 MODE 0 .

0 0 1 MODE 1

X 1 0 . MODE2

X 1 1 MODE 3

1 0 0 MODE"

1 0 1 MODES

grammed to be read I'ler. tK' byter. musi De read belore any0 0 8eIec:I~OtoatIng WR c:omrnand can be teI'Il to the II8me counter.

...., Operation Chert 0 1 SlIIIcl~l

A1 AO AD1 0 8elICl c:our-r 2

1 1 lIegel0 0 0 Reed Counter No. 0

0 1 0 Re8d Coun1ef No. 1 RL - RMdILoed:1 0 0 ReBd Coun1ef No. 2 flU RLO1 1 0 IIegaI

0 0 Counler L.a1ching operation.

WhIle Counting-

1 0 AIedI\.DId moll IIgnIficInI by1e only.

In order for the programmer to read the contents 01 any counter 0 1 -AIed/l.DlId .... IignllIcenl bylI only.

wi1hout effecting or distlJrIIing 1he counting operation the 82531 1

RMcl'Lo8d .... lignlllcant bylI ftrst. thenhas special intemallogic thai can be accessed ulling simple WR ftDllignllic8nl bylI.commands to the MODE I8gistef BasicaJly, when the program­mer wishelto read .... conl!InlS 01 a selected counter "on the fly" 'he loads 1he MODE register with • special code which latches \he .. - MODE:pr-n count vaJue into • SlDr8ge register 80 that its contents 112 111 110CXInIain an accurate, lIt8bIe~. The programmer then is­IlHIS a nonnaJ read command to \he selected counter and \heconl8ntS of the 1a1l:hed register Is available.

MODE Reg..... lor LeIl:tllng Count

1tIJ, A1 -11Dr De 05 1M D3 (02 D1 DO

SCO

KD:

IIODE D: IntImIpt on Terminal Count

The 0U1pUl wlll be InIIiIlIly low after the mode lilt operation. AflIrthe count illoadecIllto \he lelected count~r, ttle output ..nNnain low and the counter will count. When terminal count.IMChed the 0IJ1PUl will go high and remain high until the ..Itc:teccount register Is reloaded with the mode Of • rww count is loa_The counter continues to clecramenl alter terminal llllUnt "­been re8ched.

SCl. SCO - tpeCify llllUnter to lie latched.

05, D4 - ClO dIIigna- counler~ operation. E±j ItIr*Y CounIIr ,..'X - clan' care. 1--......:..--------------The ume limitation~ totlls mode 01 reading the counteras 1 IlinIIry cc.d DllcInwI (BCD) CoIntr \" Dec:8dM)

the previous method. That ill, It iI mandatory to~ the e.untar.... ....entira read operation • 1JfC98INl'lId. This command his no 'n. count register II not loaded untll the count V81ua iI wrltteo ..rtecA on lhe llllUnter'a mode. (one 01 two bytes, depenling on the mode ..Iecled by lhe FlL

OPERATIONAL DESCRIPT10N bits), tollowedby arislngeclge ancl. faJlingeclge 01 the clock.~IMd 01 the counter prior to that falling clockedgemay yield inVllio

...... data..•

.The~ twnctionII clefinllion 01 .... 8253 ill progrwnmed bylie~ aottwara. A..Iof control words muat be..out bylie CPU to ntialize eectl COUntef 01 the 8253 with tie ~11Id MODE DEFINITIONMODE and quantity lnIormation. n-e control words programlie MODE. L.oecIng eequence and MIeCtion of binary or BCDClllUfIIing.

Onceprogrammecl. lie8253 is raedyto partorm~lming_ks II is II8igned 10 accompish.

The aclUaJ counting operation 01 each counler II ~IyIndependent and 8detilional logic is prOYicled orH:tIip 10 thai theUlUal problems associated with efficient monitoring and man­egement 01 external, 8SYflchronous events or rates to tie micr0­computer aystem have been eliminated.

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-5"1

110O£ I: HIr_..T~ IIrobe

The counter wIIIl18It c:ounlIng "the rlsing edge 01.. triggerilput Itldwill go loW for one cIoc* period when the terminaloountII reached. The counter is retriggerable. The output will not go lowuntil .. fUll count atter .. riling edge 01 any trigger.

._....

menting ttII COUI'll8r by two on the tailing edge 01 each ­pulse. When the counter Rl8Ches terminal count, the .... llf.output is changed and the counter is reloaded with 1Mlui""n the wtlole process is repeated. . .

lithe count is odd and the output is high. the first clock pue. (fillthe count is loaded) decrements the count by one.~clock pulses decrement the clock by two. Alter limMlUt. thllIlIII"""goes low and the lull count il reloaded. The first c:Iadl~(following the reIOId) decrements the counter by~~~nt clock pulse. elIIcntment the count by _ .....~Thero the whole procell • .-pelted. In thiI way. , til-­odd, the output will be Hgh IDr (N + 1~ ODUIIII ...... "(N - 1~ couru.

IIC)OE.: ~T,...,... .......fJlBr the mocllI iI -I, the output wlIl be high. When the oount is.,.ded.1he counter wUl begin counting. On terminal count, the0IIIPlI' wIl go low IDr one Input clock period. lhen will go high.n.• !he count reglstar is reloaded between output pulees the pre­..,,1 period WIll not be lIfIected, but the subsequent s-riod will,.fieCt the new value. The count will be Inhibited wtliIe the I}8te

Rewriting a counter register during counting results in littoIlowing:

1. Write 1st byte IIaps the cunerrt counting.2. Write 2nd byte starts the new count.

MODE 1: Pr'ogrMnmable O,.Shot

The output will go low on the count following the rising edge 01"gate input.

The output will go high on the terminal count. If a IWW count YIIUII loaded while the output is low II will not affect the durRon 01..one-shol putse until thuuCOMdingtrigger The CUlTenlCOUIllGiftbe read at My time wiltlout IIfIectjng the one-shoI pulIe.

The one-shot is reo\rigglM able. hence the outpul wiIIl8IMin low.the full count after any rising Hge oI1h1 ga\tl input.

MOOE 2: Rate Generator

Divide by N aounter. The output will be low lor one period 01..Input clock. The s-riod from one output pulse to the next~the number 01 input counts in the count register. If ttII ClOlIIlregister is reIoeded between output pulses the preeent period"not be aftected. but 1he subsequent period will ,.nea ttII ..veIue.

•The gate input. When loW. will force the output high. wWnwgate input goes higtl, the counter will staI1 from the initial ClllIIThus, 1he ga\tl input can be UMd to aynctv1)nID ..~..

When !his mode is MI, ttII output will nImIin high unlll aIIIr­ODUnt register is 1oaOed. The output '-' can IIlIo lltf ..etwonlZlld by DIwlIre. .

MODE 3: Square W.w Rate~Simllar toMOOE 2eJlCl8P\ that the output win l1Hll8InHghurta­half the count has been completed (tor even numbers) d lID­lor the Olher half 01 the count. This is accompIi&tIed by ,.",..

IIODE o. lmerrupt on Terminal Count.

•• , ..__....J

- __r-----

~ !.'Inal Low

Modes~Or GoIng

Low RIalng High

O' IliIIbIes - EnIilIle5CllUI'Iling CDJnting

') InitiatlIa, - CllUIlIing -2) RMlIIs autpulaf18f next ClOCk

') DlubIes ') AelC*IslllIIIOIng

OOUnl8rEIIIbIe5

2 2) SeIB autpul 2) InIUtes CDJntingmneciately

CDJntingfiWl

') IliIIbIesCXlUIIIing ....... EIIIbIe53 2) &.II autpul

CllUIlIing camlingmnecialelyfiWl

"o.ble& - En8bIesCllUI'Iling ~

5 - ........ -CllUIlIing

MOOE.. Softw....Triggered Strobe.

o..~

~. ;0---1.....

.cKlE 1. Progremmable o,.Shot.

- JULJ"Ln...n.nJ"lIl...n.n..nrLSL

---.....,-

..,-..

_----~!.-~..L.-.l.--li...J..-----

-----......:.---.:........:........!......:-Lr­.'_7L_J--

....~-~ 2. Rate' Generator.

----_......::.......:.......:.......;-0 ••

---,.. J---------.,_5.... 3. Square Wave Generator.

----"------=_.!....~..:......;...... u

•- __n....l_ ---......:.-~>......:.•......:~..:........:'i....-l.•.... U .,-..