Analogue-to-Digital Conversion and Flexible FDM Demultiplexing Algorithms for Digital On-Board Processing of Ultra-Wideband FDM Signals

Heiko Kopmann, Heinz G. Göckler, Mohammed N. Abdulazim

Digital Signal Processing Group (DISPODISPODISPODISPO)

Ruhr-Universität Bochum, D-44780 Bochum, Germany Email: <kopmann, goeckler, abdulazim>@nt.ruhr-uni-bochum.de

1. INTRODUCTION In [9] a scenario of a satellite communication system for internet applications is specified to process a total bandwidth of 40GHz. The mission of the overall system and its basically required performance features are detailed in the compan-ion paper [24], and will not repeated here.

The most demanding subsystem is the digital FDM demultiplexer (FDMUX) in the Forward Link of this system [9]. This single digital FDM demultiplexer shall channelise 84 slot signals to a granularity of 10MHz using a channel spac-ing of 12MHz and starting from a real-valued FDM input signal of an overall bandwidth of 1,008MHz to be digitised at the high sampling rate of fi = 2.4GHz. This usable FDM spectrum to be demultiplexed is centred at fC = fi/4 = 600MHz.

The challenging task to devise such an FDMUX system, being investigated under ESA contract [10], is twofold: 1. Develop an extremely fast and yet precise enough ultra-wideband front-end analogue-to-digital interface. 2. Develop a highly efficient (in terms of computation and power consumption) FDMUX algorithm that, more-

over, flexibly allows for the extension of the granularity bandwidth of 10MHz by 1 up to 9 additional granules, thus encompassing a range of bandwidths of 10MHz to 120MHz [24].

Referring to task 1, present-day state-of-the-art single electronic analogue-to-digital converters (ADC) are either too slow [9], [24], [32], [33], or resolve the signal to be quantised too coarsely. As a consequence, two diverse paths for ADC interface improvement are pursued in the sequel that, in case, can be combined with each other: i) Shifting the ADC into the parallel low-speed (200MHz) branches of the FDMUX (ADC time-interleaved parallelisation [2], [19], [23]), ii) Improving the performance (resolution, accuracy, etc.) of the single high-speed ADC front-end by applying error correction in the digital domain [20].

Concerning task 2, efficient state-of-the-art FDMUX approaches [1], [9], [12], [13], [31] are either infeasible under the above clock constraint (tree FDMUX [1], [12], [13]), or completely inflexible as to channel allocation and bandwidth (complex-modulated polyphase FDMUX [1], [12], [31]). Hence, for the outlined scenario, two efficient and feasible algorithms to FDM demultiplexing are investigated under ESA contract [10] considering a maximum clock speed of about 200MHz (corresponding to present-day CMOS technology). One of these approaches with restricted yet sufficient bandwidth flexibility combines a complex-modulated polyphase FDMUX [1], [12] for coarse demultiplexing with a subsequent tree FDMUX with extended passbands [1], [13] for fine demultiplexing down to the granularity level of 10MHz. The other approach with improved flexibility properties applies mere tree demultiplexing. To be feasible under the speed constraint, this structure has to be parallelised appropriately in compliance with [17].

This paper is organised as follows: First, in section 2, the ADC system input interface is investigated. To this end, a model of clock generation is introduced, which is commonly used to represent clock and aperture jitter of all ADC ap-proaches considered. Next, all relevant errors of a single ultra-fast ADC (fi = 2.4GHz) are discussed, and their impact on the overall ADC performance is analysed. Using these results, the relative improvement that can be obtained by a paral-lel connection of M concurrently operating ADCs of the same type is investigated. Finally, time-interleaved analogue-to-digital conversion (TI-ADC) is introduced, where M ADCs are operated sequentially in the polyphase branches of the FDMUX at a correspondingly reduced rate. Concluding, the various ADC approaches are thoroughly evaluated and compared with each other.

In section 3 we start with the description and investigation of the two stage coarse-and-fine FDMUX approach, where the first stage for coarse demultiplexing exploits the inherently parallel architecture of the DFT polyphase filter bank to warrant signal processing at a sufficiently low clock rate. The second stage applies modified tree demultiplexing [1], [13] to secure the required bandwidth flexibility. Next, the second FDMUX approach is exclusively based on the classi-cal and modified tree demultiplexer architecture [12], [13], respectively, with its wide range of flexibility. System paral-lelisation (mandatory for feasibility but without impact on multiplication rate [17]) is, however, beyond the scope of this present paper. Finally, computational load and flexibility properties of both approaches are discussed and compared with each other.

2. ANALOGUE-TO-DIGITAL CONVERSION

Random fluctuations of the sampling instant τs(t) represent a major error source of analogue-to-digital conversion. Their origin is twofold: i) Noise properties of sample-and-hold (S&H) circuit of the ADC and ii) Phase noise of driving clock. These basic errors, common to all ADC interface approaches considered, are investigated first.

2.1 Modelling of Clock Generation

The distribution of the deviation τs,ADC(t) from the nominal ADC (S&H) sampling instants tk = kTi, k = …, -1, 0, 1, …, is usually assumed to be Gaussian [25], and characterised by its standard deviation στ s,ADC. For the continuous time repre-sentation of the ADC aperture jitter τs,ADC(t) we introduce the power spectral density:

22i

i2

4/)(ˆ

ADCs,ADCs,ADCs, ωωωσω τττ +

=R , (1)

where ω i = 2πfi is the sampling frequency, and its variance represents the finite jitter energy since

1d4/2

1

22i

i =+

∫∞

∞−ω

ωωω

π. (2)

As a result, the power spectral density of the sampled version of the aperture jitter, τs,ADC(tk), is essentially flat [25].

The performance of a clock generator is generally specified by the power spectral density of its phase noise φs,Clk(t) [6], [8], [25], [26], [30]. In order to be able to compare the impact of phase noise (clock jitter) and ADC aperture jitter, the phase noise must be expressed in terms of a clock timing jitter. According to [3], the relationship between τs,Clk(t) and φs,Clk(t) is of non-linear nature. For small variations it can be approximated by the phase delay

iClks,Clks, / )()( ωφτ tt ≈ (3)

with sufficient accuracy, yielding the power spectral density of the clock jitter according to

2i/ )(ˆ)(ˆ

Clks,Clks,Clks,Clks,ωωω φφττ RR ≈ , (4)

and its variance

2i

22 / Clks,Clks,

ωσσ φτ ≈ . (5)

Since the standard deviation σφ s,Clk of phase noise is approximately proportional to ω i [4], [22], [25], [28], the variance (5) of the clock jitter is essentially independent of the sampling frequency. Combining and modifying the phase noise models proposed by LEESON [22], [4], SCHERER [28], [4], MÜLLER [25] and DEMIR et al. [6], we define a generalised phase noise model by the following power spectral density [20]:

])/ (1[])/ (1[

)/ (1)(ˆ

2M

2PLL

2Q

Clk,0Clks,Clks, ωωωωωω

ωφφ +⋅+

+= NR . (6)

The meaning of the above variables will be explained in conjunction with the numerical example discussed subse-quently. The variance of φs,Clk(t) is readily obtained by integration of (6)

)(2

)(d)(ˆ

21

PLLM2Q

PLLM2QMPLLClk,0

2

Clks,Clks,Clks, ωωω

ωωωωωωω

πσ φφφ

+

+== ∫

∞

∞−

NR . (7)

Since aperture jitter τs,ADC(t) and clock jitter τs,Clk(t) are uncorrelated (careful circuit layout provided), the related power density spectra and variances can readily be added to yield the overall error contribution, respectively.

Example: The phase noise power spectral density (6) of a clock generator is depicted in Fig. 1 with the noise power density N0,Clk = -58dBc/Hz close to the carrier frequency, the bandwidth of the clock generator’s phase locked loop fPLL = 1kHz, the resonator cut-off frequency fQ = 1MHz, and the measurement bandwidth fM = 1.2GHz. The associated power spectral density of clock jitter (4), that of aperture jitter (1) with fi = 2.4GHz and στ s,ADC = 1.2ps, and the overall power spectral density of time jitter are shown in Fig. 2. By inserting (7) into (5), the resulting standard deviation of clock jitter is calculated to στ s,Clk = 6.9ps, eventually yielding the overall standard deviation στs = 7.0ps of the ADC interface.

Fig. 1. Phase noise power spectral density of clock generator with N0,Clk = -58dBc/Hz, fPLL = 1kHz, fQ = 1MHz, and fM = 1.2GHz

Fig. 2. Power spectral density of time jitter: Clock gen-erator and ADC; fi = 2.4GHz, στ s,ADC = 1.2ps and other parameters as given in Fig. 1

2.2 Single Ultra-Fast Analogue-to-Digital Conversion The use of a single ultra-fast ADC would represent the most robust and least sensitive approach, if such a device was available. For the error analysis of such an ADC, the error model depicted in Fig. 3 is introduced. Here, the following parameters are considered:

• Gain error g = const. • DC offset o = const. • Time-dependent delay τ (t) = τd + τs(t)

o Time delay τd = const. o Time uncertainty (jitter) τs(t) = τs,ADC(t) + τs,Clk(t) according to section 2.1

• Quantisation error eQ(tk) • Overflow saturation (clipping level at ±1: C = 1)

o Non-linear part of clipper output signal eC(tk) o The linear part of the clipper transfer function is represented by the equivalent gain G(pf) depending

on the peak factor pf (back-off).

In the subsequent section 2.3, the performance of a parallel connection of M concurrently operating ADCs is analysed, including the case M = 1. Hence, in this section, we only recall some fundamental results on the interaction of round-off noise and dynamic range of the ADC interface according to [7].

For this particular analysis of the dynamic behaviour, a normally distributed (Gaussian) ADC clipper input signal u(t) is anticipated. Introducing a parametric peak (back-off) factor pf for u(t) [11], [14], [15], we require:

1uf == CPp , (8)

where Pu is the power of the clipper input signal (Fig. 3). The clipper output signal is decomposed into a dominant lin-ear part being correlated with the clipper input signal, and a non-linear portion (clipping noise) that is uncorrelated with the input signal. For the linear part, we introduce the equivalent gain [7]

1de22

erf)(2/

0

ff

f 2≤=

= ∫

−pp

pG ξπ

ξ , (9)

x tS( ) τ( )t

x tN( ) o

g

e tC( )k

G p( )f

tk

e tQ( )k

y t( )k

ADC

u t( )

Fig. 3. ADC error model

Fig. 4. Equivalent clipper gain G(pf); pf: peak factor Fig. 5.

Clipping noise power PC; pf: peak factor

which is depicted in Fig. 4 as a function of the peak factor pf. The desired clipper output power is scaled by G2(pf), and the clipping noise power is characterised by

)(1)( 11121 f2

2f

f2f

2/

fC

2f pG

ppG

pe

pP p −

−−−= −

π, (10)

which is shown in Fig. 5, [7]. The quantisation noise power due to LSB rounding is given by

wqP 22

Q 231

12−== , (11)

where q represents the quantisation step size, and w the corresponding ADC word length, respectively [11], [12], [14], [31]. Considering only quantisation and clipping errors, the ADC output signal to noise and distortion ratio is given by

CQ

2ff

2

10CQ

uf2

10Y/)(

log10)(

log10PP

ppGPP

PpGSNDR

+=

+= , (12)

where use is made of (8). Introducing (9)-(11) into (12) immediately shows that SNDRY only depends on the peak factor pf and the ADC word length w. In Fig. 6 SNDRY is depicted as a function of pf for w = 6. In this case the SNDR, due to both quantisation and clipping, is maximum at pf = 3.3. Furthermore, the dependence of the optimum peak factor pf,opt on w is shown in Fig. 7. Obviously, the optimum peak factor pf,opt increases monotonically with the ADC word length w, which is compliant with the conclusions drawn from Fig. 6.

Fig. 6. SNDRY(pf) for w = 6; quantisation: dotted, clip-ping: dashed, quantisation and clipping: solid

Fig. 7. Optimum peak factor pf,opt as a function of ADC word length w

2.3 Multiple Concurrent Ultra-Fast Analogue-to-Digital Conversion A single ADC in front of the FDMUX operating at fi = 2.4GHz can be approximated by a parallel connection of M = 2i (i > 0) concurrent ADCs with lower resolution, where each output sample of the ADC input interface (ADI) is given by the arithmetic mean over the M samples nominally taken at the same time instant:

∑−

==

1

0)(1)(

M

mkmk ty

Mty . (13)

The summation of (13) is shifted into the parallel FDMUX branches beyond its serial-to-parallel input interface [17]. Furthermore, the associated division by M is realised by a hard-wired shift by i = log2(M). In the following, the impact of the error sources on the multiple concurrent ADC performance is investigated by evalu-ating (13) in conjunction with the ADC error model introduced in section 2.2, where all parameters are supplemented by a running index m according to (13). As a measure of performance the degradation of SNDR is adopted. In order to determine the SNDR at the ADI output port, we start with calculating the individual ADC output signals. According to Fig. 3, the sampler (clipper) input signal is given by:

mmmmm ottxgtu +−−= ))(()( ,s,d ττ , (14)

where x(t) = xS(t) + xN(t) is the ADC input signal with the usable signal xS(t) and the noise contribution xN(t), respec-tively. The digital output signal of each single ADC follows by sampling at tk, clipping and quantisation

)(]))(()[()()()()( ,s,df,f, kmmkmmkmmkmkmmkm teottxgpGtetupGty ++−−=+= ττ (15)

where em(tk) = eQ,m(tk) + eC,m(tk) is the error sequence due to quantisation and overflow saturation of the m-th ADC.

In the following, a linear approximation (first-order TAYLOR expansion) of the sampling process (also proposed in [29], [5]) is introduced for a simplified analysis. With this approximation, (14) can be rewritten as follows:

, )]()()([

] 2/)()()()()([ )(

d,s,d,

d,2s,d,s,d,

mmmmm

mmmmmmmm

otxttxgotxttxttxgtu

+−′−−≈

++−′′+−′−−=

ττττττττ l

(16)

where the prime denotes the derivative with respect to time t. This approximation holds if the amplitude of time jitter τs,m(t) is small enough compared to the inverse of the maximum frequency component of the input signal. In practical applications, this condition is usually satisfied very well. With (16) we rewrite (15)

)(]))()()(([ )()()()()( d,s,d,f,f, kmmmkkmmkmmkmkmmkm teotxttxgpGtetupGty ++−′−−≈+= τττ . (17)

In the following, we assume xS(t), xN(t), τs,ADC,m(t), τs,Clk,m(t), eQ,m(t) and eC,m(t) to have zero mean and to be uncorrelated with each other. Hence, with Et denoting expectation, the correlation functions of the sampler input signals are obtained:

µµµµ

µµµµµ

ττττ

ττττ

µ

µµ

ootrtrtrgg

ootrtrtrggtuttutr

mmmm

mmmmm

m

mm

++−∆′′∆−+−∆≈

++−∆∆++−∆≈∆+=∆ ′′

)]( )()([

)]( )()([ )( )(E)(

d,d,XXττd,d,XX

d,d,XXττd,d,XX*

tUU

s,s,

s,s, (18)

with

)(- )()( )( XXIFTXX2

XXFTXX trRRtr ∆′′→=→∆ ′′′′ ωωω , (19)

where

)()()(NNSS XXXXXX trtrtr ∆+∆=∆ and )()()(

Clk,s,Clk,s,ADC,s,ADC,s,s,s,trtrtr

mmm∆+∆=∆

µµµ ττττττ

represent the autocorrelation function of x(t) and the correlation functions of τs,m(t) and τs,µ(t), respectively. It follows for the correlation functions of the digital output signals of the individual ADCs:

, )()]( )()([)()(

)()()()()()(E)(

EEd,d,XXττd,d,XXf,f,

EEUUf,f,*

tYY

s,s, lmmllmlmm

llmklkml

trootrtrtrggpGpG

trtrpGpGtyttytr

mm

mmkm

µµ

µµµ

µµµµµ

µµ

ττττ +++−′′−+−≈

+=+= (20)

where rEmEµ(tl) = rEQmEQµ(tl) + rECmECµ(tl) are the correlation functions of em(tk) and eµ(tk).

Finally, the autocorrelation function of the ADI output signal is obtained according to

)()()(1)(NNSS YYYY

1

0

1

0YY2YY ll

M

m

M

ll trtrtrM

trm

+== ∑ ∑−

=

−

=µµ

. (21)

By inserting (20) into (21), the autocorrelation function of the linearly distorted (usable) signal part is calculated to

∑ ∑−

=

−

=+−=

1

0

1

0d,d,XXf,f,2YY )()()( 1)(

SSSS

M

m

M

mlmml trggpGpGM

trµ

µµµ ττ (22)

and that of the noise and distortion contributions to

)()()()()()(CCQQOOJJXXNN YYYYYYYYYYYY llllll trtrtrtrtrtr ++++= , (23)

where rYxYx(tl) represents the noise load of the ADI input signal transferred to the ADI output port, which is given by (22) by replacing rXsXs(tl) with rXnXn(tl),

∑ ∑−

=

−

=+−′′−≈

1

0

1

0d,d,XXττf,f,2YY )( )()()( 1)(

s,s,JJ

M

m

M

mllmml trtrggpGpGM

trm

µµµµ ττ

µ (24)

represents the noise and distortion contribution due to time jitter of the clock generator and S&H circuit,

∑ ∑−

=

−

==

1

0

1

0f,f,2YY )()( 1)(

OO

M

m

M

mml oopGpGM

trµ

µµ (25)

the DC component originating from the DC offsets of the ADCs,

)]1(1[1)()( 1)( QEE

1

0

1

0EE2YY QQQ,Q,QQ

−+== ∑ ∑−

=

−

=M

Mtrtr

Mtr l

M

m

M

ll mρ

µµ

(26)

the noise component due to quantisation and, finally, rYcYc(tl) the clipping component, which is given by (26) by replac-ing the index Q with C. Here, the correlations between the quantisation noise of different ADCs of the same type and the corresponding ones of clipping distortion are uniformly denoted with ρQ and ρC, respectively.

The overall SNDR at the digital output port, the ratio of the usable signal power to the noise and distortion power, can be determined by evaluating the respective autocorrelation functions rYY(tl) at tl = 0:

)0()0(

log10NN

SS

YY

YY10Y r

rSNDR = . (27)

The SNDR of a slot signal (denoted by the running channel index c) must be calculated in the frequency domain by integrating of the corresponding power spectral densities over the bandwidth of the considered channel according to:

∑ ∫

∑ ∫

∫

∫

∞

−∞=

−

−

∞

−∞=

−

−==

λ

λωω

λωω

λ

λωω

λωω

ωω

ωω

i ,u

i l, NN

i ,u

i l, SS

,u

l,NN

,u

l,SS

d)(ˆ

d)(ˆ

log10d)e(

d)e(

log10

YY

YY

10j

YY

jYY

10Y,c

c

c

c

c

c

c

c

R

R

ΩR

ΩR

SNDR Ω

Ω

Ω

Ω

Ω

Ω

c , (28)

where Ω = ωTi is the normalised frequency, and Ω l,c and Ωu,c represent the lower and upper cut-off frequencies of chan-

nel c, respectively. To this end, the continuous time autocorrelation functions (22)-(26) are subjected to the FOURIER transform, where spectral representations are denoted by capital letters. Hence, for the usable signal (22) we get

∑ ∑−

=

−

=

−=1

0

1

0

)(jf,f,2XXYY

d,d,SSSS

e)()( 1)(ˆ)(ˆ M

m

M

mmmggpGpG

MRR

µ

ττωµµ

µωω . (29)

Correspondingly, the power spectral density of the noise and distortion contribution (23) is obtained

)(ˆ)(ˆ)(ˆ)(ˆ)(ˆ)(ˆCCQQOOJJXXNN YYYYYYYYYYYY ωωωωωω RRRRRR ++++= , (30)

with )(ˆXXYY ωR being given by (29) if )(ˆ

SSXX ωR is replaced with )(ˆNNXX ωR ,

[ ]∑∑−

=

−

=

−∗≈1

0

1

0

)(jXX

2ττf,f,2YY

d,d,

s,s,JJe)(ˆ)(ˆ)()(

21)(ˆ

M

m

M

mmm

mRRggpGpG

MR

µ

ττωµµ

µµ

ωωωπ

ω , (31)

)()()( 2)(ˆ 1

0

1

0f,f,2YY OO

ωδπωµ

µµ∑ ∑−

=

−

==

M

m

M

mm oopGpGM

R , (32)

ii

QQEEQYY

2rect)]1(1[

)(ˆ)]1(1[1)(ˆQQQQ ω

ωρωρω

MfMP

RMM

R−+

=−+= , (33)

and finally the overall contribution due to clipping, which is given by (33) by replacing index Q with C, where PQ and PC are the quantisation (11) and clipping (10) noise powers of a single ADC, respectively. Since G(pf,m) is, in compli-ance with (9) and Fig. 4 for pf,opt ≈ 3, very close to unity, we set pf,m = pf ∀m, for convenience. Furthermore, it is as-sumed that the power spectral density of the sampled versions of the quantisation and clipping errors are flat (white).

Since exact values of the ADC parameters om, gm, and τd,m are generally not available, we subsequently rely on the asso-ciated expectations µ and standard deviations σ, assuming a normal distribution for all parameters. Furthermore, since all ADCs of the ADI are of the same type, their random model parameters are all identical. Moreover, the coefficients ρo, ρg, and ρτd are introduced to describe the correlation between the parameters of different ADCs. Hence, the expected SNDRs can be calculated by means of the expected power spectral density of the usable signal (29)

+−++≈

≈

+−

−

=

−

=

−∑ ∑

)1(2gg

2g

2g

2gf

2XX

1

0

1

0

)(jPP2f

2XXYYP

dτ2dτ

2

SS

d,d,SSSS

e))(1(1)()(ˆ

eEE1)()(ˆ)(ˆE

ρσω

µ

ττωµ

σρµσµω

ωω µ

MM

pGR

ggM

pGRRM

m

M

mm

(34)

and the expectation of the power spectral density of the overall distortion (30). The first term of (30) is given by (34) by replacing index S with N. For the terms (31) and (32), respectively, we obtain:

[ ][ ] [ ]

[ ] ,e)(ˆ)(ˆ)(ˆ))(1(

)(ˆ)(ˆ)(ˆ)()(2

1

eE)(ˆ)(ˆE)(2

1)(ˆE

)1(XX

2ττττττ

2gg

2g

XX2

ττττ2g

2gf

2

1

0

1

0

)(jPXX

2ττPf

22YYP

dτ2dτ

2

ADCs,ADCs,ADCs,Clks,Clks,Clks,

ADCs,ADCs,Clks,Clks,

d,d,s,s,JJ

∗++−+

+∗++≈

∗≈

+−

−

=

−

=

−∑∑

ρσω

µ

ττωµ

ωωωρωρσρµ

ωωωωσµπ

ωωωπ

ω µµ

RRRM

RRRpGM

RRggpGM

RM

m

M

mm

m

(35)

[ ] ( ) )(2)1(11)()( ))(1(2)()(ˆE o2o

2of

22oo

2o

2o

2of

2YYP OO

ωπδρσµωδσρµσµπω

−++=+−++= MM

pGMM

pGR . (36)

The error contributions due to quantisation and clipping are immediately applicable in their original stochastic represen-tation (33). Note that in the above derivations the following properties of normally distributed random variables (RV) were used [27]:

Characteristic Function: 2/jXjX

22eEe)( ssss σµϕ −== , (37)

Expectation of a product of jointly normal RV: YXYXXYE σρσµµ += (38)

General discussion and interpretation of the above results: • For M > 1, the usable signal spectrum (34) is linearly distorted as a result of different ADC delays τd,m. In case of

no correlation between the M ADI branches, the overall gain variance is diminished by 1/M. • ADI input noise is transferred to its output port in the same way as the desired signal component. • The expectation of the noise power due to time jitter (35) at the ADI output port is basically determined by the

power spectral density of time jitter convolved with the power spectral density of the ADI input signal times ω 2. For M > 1, this distortion can only be partly diminished by the ADI, since the relative improvement depends on the correlations between the ADI branches. In general, aperture jitter correlation ρτs,ADC is expected to be small, whereas clock jitter correlation will approach unity if, as is common practice, all ADCs are controlled by the same clock generator. As a result, only the impact of aperture jitter can be diminished by at most 1/M.

• For low correlation ρo ≈ 0, which can be taken for granted, and zero mean µo, which is questionable, the reduc-tion of DC-offset power (36) approaches 1/M.

• The noise power contributions due to quantisation (33) and clipping are strongly dependent on the respective cor-relations between the ADI branches. Since DC-offsets om, gains gm and delays τd,m of the parallel ADCs generally exhibit low correlation with each other, correlation coefficients of ρQ ≈ ρC ≈ 0 can be expected (yet still to be verified). In this latter case, the ADI gives rise to an improvement by 1/M.

2.4 Performance Comparison In this section we present an example under the assumption of a constant power spectral density of the ADI input signal in each channel c of bandwidths Bc = fu,c – fl,c and centre frequency fC,c = (fu,c + fl,c)/2. We choose 84 channels with iden-tical power spectral density without noise load and the following channel allocation [1], [24]:

,841, , 90MHzMHz12C, =+⋅= ccf c and bandwidths: ,841, , MHz10 === cBBc .

The error scenario adopted is listed in Table 1. The power spectral density of the ADI input signal is depicted in Fig. 8.

Table 1. Survey of error scenario; fi = 2.4GHz, pf = pf,opt = 3.0 for ENOB = 5.2 (Fig. 7)

Device Type of error Expected value Standard deviation Correlation ADC: Gain µg = 1 σg = 0.037 ρg = 0

DC-offset / Full Scale µo = 0 σo = 0.040 ρo = 0 Aperture delay µτd = 250ps στd = 50ps ρτd = 0 Aperture jitter στs = 1.2ps ρτs,ADC = 0 Quantisation ENOB = 5.2 ρQ = 0 Clipping

ρC = 0

Clock: Phase noise power density for |f| < fPLL N0,Clk = -58dBc/Hz (Fig. 1) Bandwidth of phase locked loop fPLL = 1kHz

Resonator cut-off frequency fQ = 1MHz Measurement bandwidth fM = 1.2GHz

ρτs,Clk = 1

For M = 1, the resulting SNDRs (28) are plotted in Fig. 9 for all 84 channels. As it can seen from Fig. 9, the higher the centre frequency the lower the SNDR (SNDRmin = 24.9dB for c = 84). This frequency dependence of SNDR is exclu-sively caused by the time jitter (cf. Fig. 10), where the impact of the clock jitter is dominant (cf. Fig. 2). Since fM ≈ fu,84, the power spectral density of the noise contribution by jitter is spread, due to the convolution in (35), over a band of at least three times that of the usable bandwidth of about 1GHz. Hence, by letting λ = -9, …, 9 in the denominator summa-tion of (28), all major error contributions are completely included in the determination of SNDR. In Fig. 11, for c = 1 and c = 84, the SNDR is depicted as a function of M. The increase of SNDR by every doubling of M is lower than the maximally possible gain of 3dB (≅1/2 bit). This is due to the anticipated correlation of the clocks (ρτs,Clk = 1). Obviously, the highest relative performance improvement is obtained by the transition from M = 1 to M = 2: 2.5dB (1.4dB) in channel 1 (84). Since, with increasing M, the impact of jitter is retained while all other error contri-butions are diminished, the relative performance gain attainable by a doubling of M becomes smaller and smaller.

Note that all functions including integration are evaluated analytically. To this end, for M > 1 the approximation ex ≈ 1 + x is used in (35). This approximation is permissible for στd << 1/fu,c ∀c, which can usually be taken for granted.

Fig. 8. Power spectral density of the ADI input signal Fig. 9.

SNDRY,c for c = 1, …, 84; M = 1; λ = -9, …, 9

Fig. 10.

Noise and distortion contribution due to time jitter for M = 1; λ = -9, …, 9

Fig. 11. SNDRY,c as a function of M for c = 1, 84; λ = -9, …, 9

2.5 Time-Interleaved Analogue-to-Digital Conversion in the FDMUX Polyphase Branches For this ADC interface approach (TI-ADI), the single ultra-fast ADC is split into a cascade of a fast S&H circuit being still operated at fi = 2.4GHz, and a parallel connection of P by the factor of P slower time-interleaved ADCs, where P is the degree of parallelisation prescribed by the subsequent FDMUX front end serial-to-parallel interface (see section 3). Thus, the various time-interleaved slow ADCs are appropriately distributed over the P parallel branches, and each of them converts just one, decimated by P, polyphase component of the de-interleaved discrete-time high-speed input signal of the FDMUX system. This is achieved by distributing the samples of the fast input S&H circuit in a time-discrete (analogue) manner to the polyphase branches of the FDMUX, where they are re-sampled by slow S&H circuits in conjunction with slow A/D conversion.

Unfortunately, deviations of matching of the time-interleaved branches (gain, DC-offset, delay, etc.) introduce distor-tion, and thus reduce the SNDR [2], [19]. Therefore, the deviations of matching have to be measured or estimated, re-spectively, and to be minimised in the digital domain [23]. These enhancement techniques call for additional computa-tional load. The error reduction procedures will be preferably implemented with respect to the slot signals at the output ports of the FDMUX. This approach has the potential that the errors related to a single granule might be smallest and, hence, error reduction could become very simple. However, these questions still require further active research under [10]. Possibly, it might turn out that error reduction procedures must be allocated immediately behind the slow branch S&H and ADC cascade, which was likewise feasible. A comprehensive error analysis of the ultra-wideband TI-ADIs (corresponding to section 2.3 and [21]) together with error reduction techniques will be published as soon as available. 3. FLEXIBLE FDM DEMULTIPLEXING ALGORITHMS Subsequently, the two approaches to flexible FDM demultiplexing outlined in the introduction are investigated. 3.1 Cascade of Coarse and Fine FDM Demultiplexer with Intrinsic Parallelisation In order to develop a feasible and flexible cascade FDMUX approach comprising a first stage for coarse demultiplexing (DFT polyphase filter bank [12], [31]) and a second stage for fine demultiplexing (tree structure [12], [13]), the follow-ing requirements have to be accounted for: i) Operational sampling rate fop = I·12MHz < 200MHz for signal processing in coarse FDMUX shall be an integer multiple of channel spacing, being desirable for subsequent fine demultiplexing [12] ii) Range of granularity from 10MHz up to 120MHz [1], [24] without applying any kind of slot signal reconstruc-tion [13], and iii) basic oversampling factor of two to warrant efficient low order filtering [12]. Considering ii) as much as possible under the constraint i), with Imax = 16 an operational rate of fop = 192MHz readily follows, yielding the intrinsic decimation factor of coarse FDMUX:

5.12225

MHz192MHz2400

op

i =====LM

ff

D . (39)

Regarding requirement iii) exactly would allow for a maximally usable bandwidth of b = 96MHz encompassing 8 rather than 10 granules, as required under ii). However, following the concept of [13], the nominal passband width b of the

0H

1H

25

MHz192fo,1 =

2

MHz2400fi,1 =

12H

49H

11H

Tree-Module

discarded

discarded

Tree-Module

Coarse FDMUX Fine FDMUX

e-jπk

e-jπk

e-jπk

Fig. 12. Two-stage FDM demultiplexer with intrinsic parallelisation

polyphase prototype filter of the coarse FDMUX can easily be extended by just one granule on either side to comply with ii). This bandwidth extension reduces the width of the FIR filter transition band from 96MHz to 72MHz and, hence, calls for an increase of the filter length by 4/3 over the classical complex-modulated polyphase FDMUX ap-proach with non-overlapping passbands according to [12]. The basic block diagram of the two-stage FDMUX is de-picted in Fig. 12. 3.1.1 Coarse FDM Demultiplexing Starting from the system theoretic approach to coarse FDM demultiplexing, as shown in Fig. 12, we first derive an efficient structure for this first FDMUX stage, and give preliminary design results. Since the rational decimation factor D = M/L = 25/2 of the coarse FDMUX according to (39) cannot be implemented in a straightforward manner [16], [31], the input sampling rate must first be expanded by L = 2 to the interim value of fn = 4.8GHz and then decimated by M = 25 to fop = 192MHz. As a result, the number of channels of the DFT polyphase filter bank is determined by

50MHz96

MHz4800ncoarse ===

bf

N , (40)

where b represents the nominal (non-extended) bandwidth of the prototype filter.

Since the overall input spectrum of the FDM signal is allocated from 96MHz to 1,104 MHz [1], [24], only 11 out of the 50 complex-valued output signals of the coarse FDMUX are useful (slot number 1 to 11); all others are discarded (by saving unnecessary hardware of the IFFT processor as much as possible). In order to meet the requirements regarding flexible channel sizing and following [13], the oversampling factor of the output signals of the coarse FDMUX is re-duced by symmetrically extending each slot transfer function on either side by 12MHz. This leads to overlapping pass-bands of contiguous slot transfer functions, whilst the widths of the transition regions are symmetrically reduced by the same amount. Due to this passband extension, it is possible to merge up to ten 10MHz-granules to slots of correspond-ingly wider bandwidth. Hence, the real FIR prototype lowpass filter has a specified passband width of 120MHz and a transition bandwidth of 72MHz. Requiring a stopband attenuation of as = 50dB (underlying all filter designs in the scope of this paper), the prototype filter length results in N = 199. In order to avoid all unnecessary multiplications by the alternate zero-samples introduced by the L-upsampler, as it is obvious from the detailed block diagram of the coarse FDMUX as shown in Fig. 13 (left), the sequential order of L-upsampling and M-downsampling must be reversed. Since L = 2 and M = 25 are relatively prime [31], this is achieved by applying novel multirate identities [16] - [18] for structural transformation. In the original structure of the FIR poly-phase prototype filter Fig. 13 (left), up- and downsamplers use the standard phase shift of p = 0 [31]. The polyphase components of the prototype lowpass filter are denoted by Hν

(zo), where ν = 0,…,49. To apply the novel multirate iden-tities, the branch filters are grouped with those of even or odd channel indices in conjunction with even and odd multi-ples of the basic time delay zn

-1, respectively.

For channels with even indices all delays are integer multiples of L = 2 and, hence, the upsampler is shifted beyond each delay, and the sequential order of up- and downsampler is reversed [16], [31]. In a last step, each branch filter Hν

(zo) is decomposed into its two polyphase components to allow for an efficient implementation as a polyphase interpolator

Mod

ified

IFFT

)z(H o02 25

25

25

25

)z(H o2

)z(H o48

)z(H o1

)z(H o3

)z(H o49

0 0

0

0

0

0

0

iz oz

2-nz

2-nz

2-nz

1-nz

2-nz

o

o

o

25

)z(H s0,025

25

0

0

iz oz

2

0

)z(H s0,1 2

0

2

0

2

0

)z(H s48,0

)z(H s48,1

)z(H s1,0

25

12

12

2

1

)z(H s1,1 2

1

2

1

2

1

)z(H s49,0

)z(H s49,1

1/50-sz

1/50-sz

1-oz

1-oz

1-oz

1-oz1-

iz

1-iz

1-iz

1-iz

o

Mod

ified

IFFT

)z(H o02 25

25 )z(H o2

)z(H o48

)z(H o1

)z(H o3

)z(H o49

0 0

0

0

0

0

0

iz oz

2-nz

2-nz

2-nz

-nz

2-nz

o

o

o

)z(H o0 )z(H o02 2525

2525

25

25

)z(H o2

)z(H o48

)z(H o1

)z(H o3

)z(H o49

0 0

0

0

0

0

0

iz oz

2-nz

2-nz

2-

n

z

-nz

2-nz

M

o

M

25

)z(H s0,025

25

0

0

iz oz

2

0

)z(H s0,1 2

0

2

0

2

0

)z(H s48,0

)z(H s48,1

)z(H s1,0

25

12

12

2

1

)z(H s1,1 2

1

2

1

2

1

)z(Hs49,0

)z(H s49,1

1/50-sz

1/50-sz

1-oz

1-oz

1-oz

1-oz1-

iz

1-iz

1-iz

1-iz

o

2525

)z(H s0,02525

2525

0

0

i

z oz

2

0

)z(H s0,1 2

0

2

0

2

0

)z(H s48,0

)z(H s48,1 )z(H s48,1

)z(H s1,0

2525

12

12

2

1

)z(Hs1,1

2

1

2

1

2

1

)z(H s49,0

)z(Hs49,1

)z(H s49,1

1/50-

s

z

1/50-sz

1-oz

1-oz

1-oz

1-oz1-

iz 1-iz

1-iz

1-iz

1-iz 1-iz

1-iz

1-iz

o

o

Fig. 13. Structural transformation of the coarse FDMUX

[16], [31]. As a result, the ultimate filter operation rate is additionally reduced to f’op = fop / 2 = 96MHz. The optimised efficient structure for channels with even indices is depicted in the upper right part of Fig. 13.

For channels with odd indices all delays are odd multiples of the basic delay zn-1. Hence, the novel identity 3 of [18] is

applied to obtain the respective structure in the lower right part of Fig. 13. In comparison to the channels with even indices, the resulting down- and upsamplers use a phase shift of p = 12 and p = 1, respectively. As a result, a shimming delay of zn

-1/50 is introduced in each branch with an odd channel index. Finally, in- and output delay chains are replaced by in- and output commutators, where the different phase shifts have to be regarded [1], [16], [17].

The 50 real-valued output signals of the efficient FIR lowpass polyphase prototype filter (Fig. 13 right) are fed into a 50-point IFFT processor, as indicated. Due to the specified channel allocation scheme [1], [24] with slot centre frequen-cies

11,,1,)( 21

,C l=+= cbcf c , (41)

resulting from fC = fi / 2 introduced in section 1, each IFFT input sequence has to be subjected to a multiplication with a complex-valued constant [12]. Note that these multiplications are conceptually combined with the IFFT processor. 3.1.2 Fine FDM Demultiplexing If ten elementary granules are merged to one single slot signal, no fine demultiplexing is needed, since the respective signal can be tapped directly at the output of the coarse FDMUX. Otherwise, the 120MHz-sub-FDM-signal is fed into an individual tree-structured FDMUX for fine demultiplexing, which should deliver several slot signals of different or equal bandwidths. Hence, the respective tree-structure is determined by the particular slot configuration desired. Fig. 14 presents the spectrum of a 120MHz-sub-FDM-signal, where the elementary granules are indicated. The two outer gran-ules are also part of the respective contiguous coarse FDMUX slot signals. Due to this overlapping it is not possible to have two contiguous slots each with a usable bandwidth of 120MHz. In the following, it is shown, how slots of different bandwidth can be formed. As a First of two baseline Approaches, a directional filter according to [12], separates the input spectrum into 4 different spectra of twice 48MHz (granules [gb,gc,gd,ge] and [gf,gg,gh,gi]) and twice 12MHz (granule ga and gj) of usable bandwidth, respectively, using all 4 output ports of the directional filter [12]. The slots of 4 merged granules can be further split by subsequent stages of directional filters down to the granularity level of 10MHz; otherwise, all subsequent stages are switched off to minimise power

fi/2 = 96MHz

ga gb gc gd ge gf gg gjgh gi

-12MHz f108MHz48MHz

fi/2 = 96MHz

ga gb gc gd ge gf gg gjgh giga gb gc gd ge gf gg gjgh gi

-12MHz f108MHz48MHz Fig. 14. Output spectrum of the Coarse FDMUX in conjunction with its allocated granules

consumption. The corresponding structure is depicted in Fig. 15, where the black and dashed connections are valid for this First Approach. With this structure it is possible to form slots of one, two or four granules. In a third stage, every granule is subjected to a final bandlimiting filter operation in conjunction with a shift to zero centre frequency, in order to have a well defined and uniform spectrum for further signal processing, like switching and re-multiplexing.

To enable the merging of three granules to one single slot, the second stage of the structure in Fig. 15 has to be modi-fied. The extension of the slot transfer functions [13] on either side by 12 MHz leads to non-realisable filters, since the transition band vanishes. Instead, the input spectrum is shifted by 6MHz to the left (multiplication by e-jkπ/8) according

Fig. 15. Overall Fine FDMUX structure

fi/2 = 48MHz

gb gc gd ge

-6MHz f42MHz

fi/2 = 48MHz

gbgb gcgc gdgd gege

-6MHz-6MHz f42MHz42MHz Fig. 16. Spectrum for slots of 3 granules

1H

2H

3H

0H

2

Tree-Stage 2

MHz96f TS2i, = MHz48f TS2o, =

[gb,gc,gd]

ge1H

2H

3H

0H

21H1H

2H 2H

3H3H

0H0H

22

Tree-Stage 2

MHz96f TS2i, = MHz48f TS2o, =

[gb,gc,gd]

gee -jπk

e -j 8πk/

Fig. 17. Second stage of tree-structure for slots of 3 granules

to Fig. 16, and the passbands of the slot transfer functions are extended by only 6MHz on either side, This specification leads to a don’t care transition band of 12MHz and provides one slot comprising 3 granules ([gb,gc,gd]) and another one of one granule (ge). The modified structure is shown in Fig. 17. Other slot specifications are attainable by the Second tree-structure Approach. Starting from the spectrum shown in Fig. 14, the specified bands of the slot transfer functions are extended by 12MHz on either side allowing for the grouping of six granules [ga,gb,gc,gd,ge,gf] with one slot. The other four granules [gg,gh,gi,gj] can be further demultiplexed conven-tionally. The resulting structure of this Second Approach is also presented in Fig. 15, where the black and dotted links belong to this second approach. As it is obvious from Fig. 15, the two structures can readily be derived from a common baseline approach by appropriately connecting the various filter cells in conjunction with the required frequency shifts. Finally, similar to the approach of merging 3 granules to one slot, a slot of 5 granules is obtained by shifting the input spectrum of the first stage by 6MHz to the right (multiplication by ejkπ/16) and extending the passband of the transfer functions by 6 MHz on either side, while a slot of 7 granules is obtained by shifting the input spectrum 12MHz to the left (multiplication by e-jkπ/8) and extending the passbands symmetrically by 18MHz.

Table 2 gives an overview of the filter lengths of the directional filters of all stages and for all desired slot configura-tions.

Table 2. Survey of slot configurations Tree-Stage 1 (fop = 96MHz) Tree-Stage 2 (fop = 48MHz) Tree-Stage 3 (fop = 24MHz) Filter length N Number of merged

granules realised Filter length N Number of merged

granules realised Filter length N Number of merged

granules realised First Approach Fig. 15 11 4 11 2 11 1 Fig. 17 23 3 Second Approach Fig. 15 23 6 11 2 11 1 43 7 15 5

3.1.3 Flexibility Since the coarse FDMUX divides the overall bandwidth of the input signal into 11 usable slots of 120MHz bandwidth, it is not possible to specify slots of a total width of up to 10 granules that span two of those 120MHz-slots. As a result, slot configuration is somewhat restricted regarding the allocation of slot centre frequencies, i.e. arbitrary grouping and allocation of slots can solely be achieved within a 120MHz-slot. Moreover, as aforementioned, due to the overlapping the slot transfer functions, it is not possible to form two contiguous slots of each 120MHz usable bandwidth.

As far as the fine FDMUX is concerned, slots of 8 and 9 granules, respectively, cannot be obtained by the presented tree-structures using efficient halfband filters [12], since the required extension of the slot transfer functions would lead to brick wall (zero-width) transition bands and, hence, to non-realisable filters. Instead, less efficient direct filtering has to be applied to form those slots.

In view of the underlying specifications [9], [24] it has to be clarified, whether or not the flexibility requirements (espe-cially the grouping of one up to ten granules) could be mitigated such that, for instance, only 1, 2, 4 or 8 granules are to be merged to one single slot. This slight modification would reduce the expenditure considerably since i) a smaller number of different slot bandwidths has to be foreseen and ii) the multiples of an elementary granule are powers of two and, hence, the slot signals can easily be tapped from the tree-structure [12]. In any case, a coarse FDMUX is needed to reduce the input sampling rate to a tractable value. 3.2 Tree-Structured FDM Demultiplexer to be Parallelised The FDMUX structure envisaged in this section exclusively applies the tree-structure with overlapping passbands, as presented in [13], with up to 8 stages where the number of cascaded stages depends on the desired level of granularity of the respective slot signal to be tapped. The input spectrum is successively split by directional filter cells, and concur-rently decimated by two. To avoid possible disintegration of slot spectra, the slot transfer functions are extended appro-priately, as described in conjunction with fine FDMUX in section 3.1.2 [13]. The successive sampling rate reduction by the factor of 2 in each stage, except the first one in order to obtain an over-sampling factor of at least two, makes the direct implementation of this approach infeasible, since the operation rate adopts a tractable value not until the fifth stage (fop=150MHz). Hence, the first four stages (complex halfband filter fop=2,400MHz, first tree stage fop=1,200MHz, second tree stage fop=600MHz, and third tree stage fop=300MHz) have to be parallelised using a degree of parallelisation of 12, 6, 3 and 1.5, respectively. In [17] a systematic graphically repre-sented method of system parallelisation is available, which can be applied to make this demultiplexing approach feasi-ble. Essential system characteristics, like computational load, are not affected by the parallelisation. 3.3 Comparison In the following the two approaches presented in sections 3.1 and 3.2 are compared with each other regarding flexibility and computational load. 3.3.1 Flexibility The cascade of coarse and fine FDMUX fulfils the specified requirements of flexibility only partially, since not every slot bandwidth with any arbitrary slot centre frequency can directly be tapped from the cascaded stages of the tree-structure. Yet, this restricted type of flexibility has to be purchased at the expense of an intricate adaptive connection scheme of the directional filter cells of the tree-structure (cf. Fig. 15). The use of the coarse FDMUX, which is unavoid-able to make this approach feasible, with its slot bandwidth constrained to 120MHz, additionally restricts the possible slot allocations.

The tree-structured FDM demultiplexer to be parallelised outperforms the cascade of a fine and a coarse FDMUX re-garding flexibility. It allows for almost full flexibility as to channel sizing and slot allocation. In the first stages of the tree-structure the processed bandwidths are much higher than the possible overlapping of the transfer functions of con-tiguous filter cells and, therefore, realisation problems like vanishing transition bands do not occur. This might be a difficulty in the latter stages; however, this problem can be solved with frequency shifts as applied in section 3.1. 3.3.2 Computational Load The computational load of a digital system is measured by the multiplication rate being defined as the sum of all multi-plications times the respective operational rates fop [16]. For the coarse FDMUX the multiplication rate is mainly influ-enced by the multiplications due to filtering and due to the computation of the 50-point-IFFT, which contributes more to the multiplication rate than the filter operations. Since only 11 out of the computable 50 output signals are used, the IFFT structure can be optimised by discarding all unnecessary multiplications and additions to reduce computation. Concerning the fine FDMUX, the filtering operations are decisive (filter lengths are given in Table 2), since only 4-point-IFFTs have to be computed. The multiplication rate increases by extending the slot transfer functions because of the increasing filter length (see Table 2). For the corresponding discussion of power consumption refer to the compan-ion paper [24]. The merely tree-structured FDM demultiplexer to be parallelised according to section 3.2 avoids the disadvantages of the coarse FDMUX and behaves similar to the fine FDMUX. The final overall multiplication rate for both approaches highly depends on the particular slot allocation, which is, due to the desired flexibility, varying in a wide range.

4. CONCLUSION It has been shown that digital on-board processing of ultra-wideband FDM signals of overall bandwidths beyond 1GHz, as specified in [1], [9], [24], is feasible, most likely even with acceptable expenditure and power consumption [24]. Since analogue-to-digital conversion will always represent the bottleneck of the system, the bulk of signal degradation must be allowed for this system input interface. Future work [10] will, on the one hand, be devoted to research into further improvement of the properties of the ADC input interface (ADI) by means of digital signal post-processing [20], [21]. This will, in particular, apply to in-depth investigations of the ADI approach based on time-interleaved ADCs, where many questions concerning its feasibility are still open: Impact of fast input S&H in conjunction with subsequent slow branch re-sampling and analogue-to-digital conversion, measurement and adaptive compensation of delay and gain deviations and DC-offsets, etc. More-over, the analytically derived results presented in this paper have to be verified by extensive simulation, taking into account the actual parameters of emerging ADCs.

In the field of FDM demultiplexing, on the other hand, the two basic approaches discussed in this paper have to be elaborated in more detail, optimised under finite arithmetic conditions, and thoroughly compared with each other. This particularly applies to the mere tree-structure FDMUX approach that could only be treated marginally in this paper, and to its absolutely necessary parallelisation [17]. Nevertheless, some of the specifications [1], [9], [24] should be critically reviewed, in order to hopefully find an additional potential for further reduction of the overall expenditure. Alterna-tively, these savings could be used to improve performance, possibly permitting the application of higher level modula-tion schemes such as M-QAM. REFERENCES [1] M.N. Abdulazim and H.G. Göckler, “Survey of potential algorithms for wideband digital demultiplexing and

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