ANALOG INTEGRATED

CIRCUITS DESIGN

University of Massachusetts

Electrical and Computer Engineering Department

Omid Oliaei

ECE697BB/Oliaei

2

•Real-world signals are Analog.

•Signals generated by sensors are analog

•Digital signal processing of signals requires Analog-to-Digital Conversion.

•Analog signal needs to be amplified and filtered before A/D.

•Amplifiers and Filters are Analog Circuits.

•A/D is a Mixed-Signal Circuit.

Why Analog?

Chapter 1

ECE697BB/Oliaei

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•Digital signals in a digital communication system behave as analogsignals

at certain stages of transmission, receive and processing.

Ex 1. Lossy Cable

Ex 2. Disc Drive

•Signal Attenuation, Noiseand Distortion incurred in the propagation

channel require that the received signal be Amplified, Filteredand

Equalizedusing Analogcircuits.

Ex 3. Wireless Receiver

Ex 3. Optical Receiver

Chapter 1

ECE697BB/Oliaei

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•Why Integrated?

•Larger integration �larger complexity

•Lower parasitics �Higher speed

•Lower cost

•Moore’s Law: Number of transistors doubles every 18 months:

•1960: 25 µm Gate length

•Today: 90 nm and 65 nm in production

•45 nm and 32 nm are in lab. 22nm and 16nm on roadmap.

•Why CMOS?

•Digital (Main Driver)

•Low Power, Simplicity, Scaling, Low cost

•Analog

•Integration with digital

•Improved speed over years

Chapter 1

ECE697BB/Oliaei

5Chapter 1

Analog

Design

Performance

Constraints

Schematic

TestLayout

System Level

Circuit Level

Component Level

Levels of Abstraction

What is Analog Design?

Don’t Forget

Variations

ECE697BB/Oliaei

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CAD TOOLS FOR CIRCUIT DESIGN

•Two Dominant Suppliers:

•Cadence

80% market share

•Mentor Graphics

20% market share

•Simulation:

•System Level:

Matlab, SPW

•High-Level (Behavioral):

Verilog, Verilog_A, Verilog AMS

•Low-Level (Electrical):

SPICE, SPECTRE, ADS, Proprietary Tools

•Cadence and Mentor Graphics Include tools for

•Schematic Capture

•Simulation

•Layout

Chapter 1

ECE697BB/Oliaei

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Schematic Capture

Netlist

Electrical/Behavioral Simulations

Layout: Automatic/Manual

Technology

Device Model

Parasitic Extraction

Design Rules Check (DRC)

Layout Versus Schematic (LVS)

Masks

Fabrication

Design House

Foundry

Customer

Specifications

Test

Production

Chapter 1

ECE697BB/Oliaei

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Analog Design Space

Tra

deo

ffs

•Analog Design is a Multi-Dimensional OptimizationProblem.

•Improving one parameter always results in degradation of some others.

Cost ?

Chapter 1

ECE697BB/Oliaei

9Chapter 2

Basic MOS Device Physics

•Understanding Device Physics is Essential to Analog Design.

•MOS device is symmetric.

NMOS

Bulk

Side Diffusion

(Sio

2)Contact

(Metal)

Ddrawn

eff

LL

L2

−=

5 nm

0.25 µ µµµm

2.2 nm

0.13 µ µµµm

3.5 nm

0.18 µ µµµm

Tox

Ldrawn

ECE697BB/Oliaei

10

•MOS is a four-terminal device.

•Substrate (bulk) of an NMOS is connected to the lowest potential.

•Substrate (bulk) of a PMOS is connected to the highest potential.

•All p-njunctions are reversebiased.

•Conduction takes place beneath gate, between source and drain.

NMOS

PMOS

Chapter 2

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Complementary MOS Process (CMOS):

PMOS

NMOS

Chapter 2

PMOS

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MOS CHANNEL FORMATION

Cut Off

Depletion

Inversion

VG

GND

VG

GND

VG

GND

GND

VTH

Chapter 2

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•Device turn-on is a gradual phenomenon.

•There exists several definitions for VTH.

•One definition: when VG=VTH:

density of electrons on the interfaced equals density of holes in the substrate

•VTHincreases with increasing the substrate doping.

Adjusting V

THby ion implantation:

•P+layer increases VTH

Chapter 2

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PMOS IN INVERSION STATE

•PMOS: Holes flow from Source to Drain.

•NMOS: Electrons flow from Source to Drain.

•Electrons have a higher Mobility. �NMOS is faster than PMOS (~ 3 times).

Chapter 2

SD

ECE697BB/Oliaei

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MOS Symbols

Chapter 2

Arrow indicates current flow from positive voltage to negative voltage polarity.

ECE697BB/Oliaei

16

NMOS

I-V CHARACTERISTICS

Uniform Charge

Distribution

•Larger VDS�Larger Longitudinal Field

•Larger VGS�More Charge Carriers

Chapter 2

More Current

ECE697BB/Oliaei

17

I/V Characteristics (cont.) v

xV

VV

WC

ITH

GS

ox

D)]

([

−−

−=

∫∫

==

−−

=VDS

V

TH

GS

nox

L

x

DdV

xV

VV

WC

dx

I0

0

)](

[µ

Giv

en v

=µE

an

d E

(x)=

−d

V(x

)

dx dxx

dV

xV

VV

WC

In

TH

GS

ox

D)

()]

([

µ−

−=

ID=

µnC

ox

W L[(

VG

S−

VT

H)V

DS−

1 2V

DS

2]

ECE697BB/Oliaei

18

I-V CHARACTERISTICS: Triode Region

Triode Region:

TH

GS

DS

VV

V−

<

I D=

µnC

ox

W L[(

VG

S−

VT

H)V

DS−

1 2V

DS

2]

Almost Linear

nµ

Electrons Mobility

oxsi

ox

tC

ε=

Oxide Capacitance

WDevice Width

LDevice Length

35.0

=siε

DS

TH

GS

LWox

nD

VV

VC

I)

(−

≈µ

Oxide Permittivity

oxt

Oxide Thickness

sVcm

.2

[]

mµ []

mµ

Chapter 2

[]

cmpF/

[]2

/cm

pF

ECE697BB/Oliaei

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TH

GS

DS

VV

V−

>

I-V CHARACTERISTICS: Saturation Region

2 )(

2TH

GS

ox

nD

VV

LWC

I−

′=

µ

V' D

S=

VG

S−

VT

H (

Pin

ch−

off

)

LL

≈′Chapter 2

ECE697BB/Oliaei

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MOS OPERATION REGIMES

Both PMOS and NMOS:

TH

GS

DS

VV

V−

<

Triode Region

TH

GS

DS

VV

V−

=

Pinch-Off

TH

GS

DS

VV

V−

>

Saturation Region

•In saturation, MOS behaves as a current source.

Chapter 2

ECE697BB/Oliaei

21

constant

VDS

GS

Dm

VIg

∂∂= =µn

Cox

W L(V

GS−

VT

H)

gm=

2µn

Cox

W LID

=2

ID

VG

S−

VT

H

Transconductance in Saturation Region

2 )(

2TH

GS

ox

nD

VV

LWC

I−

=µ

Chapter 2

ECE697BB/Oliaei

22

ID=

µnC

ox

W L[(

VG

S−

VT

H)V

DS−

1 2V

DS

2]

ID=

µnC

ox

W L(V

GS−

VT

H)V

DS,

VD

S

ECE697BB/Oliaei

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THRESHOLD VOLTAGE AND BODY EFFECT

()

22

0F

SB

FTH

TH

VV

VΦ

−+

Φ+

=γ

VB < 0 attracts holes and widens depletion region

�Larger VG > 0 to put opposite charge on gate

�Larger VG > 0 to create inversion

�Higher VTH

4.0

3.0

<<γ

Body effect coefficient

FΦ

Fermi level

Source-Bulk voltage

Chapter 2

ECE697BB/Oliaei

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CHANNEL LENGTH MODULATION: SATURATION REGION

L'=

L−

∆L

)1(

1)

/1(

1'

/1

DS

VL

LL

LL

λ+

=∆

+=

)1(

)(

2

2DS

TH

GS

ox

nD

VV

VLW

CI

λµ

+−

=

LL’

DS

TH

GS

ox

n

DS

DS

IV

VLW

C

VIg

DS

λµ

λ≈

−=

∂∂=

2 )(

2

Chapter 2

L1∝

λ,

LIg

DS

DS∝

ECE697BB/Oliaei

25

ECE697BB/Oliaei

26

=T

GS

D

VVI

Iζ

exp

0

SUBTHRESHOLD CONDUCTION

•For VGS<VTH, there exists a weak inversion layer causing a small diffusion current.

•This “leakage”current causes increased power dissipation in digital circuits.

•To operate in weak inversion, transistor must be wide �low speed.

•Application: Ultra Low-Power design.

Chapter 2

ECE697BB/Oliaei

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MOS LAYOUT

Gate

(Poly)

Contacts

(Metal)

Gate

Shared

Chapter 2

Gate Contact

ECE697BB/Oliaei

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PARASITIC CAPACITANCES

Overlap

Bottom-plate

cap

Side-wall

cap

•Junction capacitance increases non-linearlywith reverse bias.

Chapter 2

ECE697BB/Oliaei

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GAT-SOURCE AND GATE DRAIN CAPCITANCES

•Cgsis maximum in the saturation region

• •Device is symmetric in the triode region

Chapter 2

)](

[x

VV

VWC

QTH

GS

ox

ch−

−∝

ox

GS

WLC

C32

≈

ox

GD

GS

WLC

CC

21≈

=

ECE697BB/Oliaei

30

LOW-FREQUENCY MOS SMALL-SIGNAL MODEL

D

o

Ir

λ1=

SB

F

mBS

D

mb

Vg

VIg

+Φ

==

22

γ∂∂

0=

SB

V0

≠SB

V

: Drain-source resistance

: Bulk transconductance

saturation

Chapter 2

ECE697BB/Oliaei

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HIGH-FREQUENCY SMALL-SIGNAL MODEL

Chapter 2Saturation

Triode

Cut Off

ECE697BB/Oliaei

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ECE697BB/Oliaei

33

ECE697BB/Oliaei

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GATE ACCESS RESISTANCE

Two fingers

Reduce resistance

Chapter 2

•Gate resistance effect is significant at RF.

ECE697BB/Oliaei

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COMMON-SOURCE with RESISTIVE LOAD

Av=

−g

mR

D

Deep triode

Saturation

Sat.

Triode

Off

Chapter 3

ECE697BB/Oliaei

36

om

vr

gA

−=

Av=

−g

mro

||R

D

∞→

DR

Chapter 3

COMMON-SOURCE with RESISTIVE LOAD: Model

ECE697BB/Oliaei

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DIODE-CONNECTED MOS

(gm+

gm

b)V

x+

Vx

ro=

Ix

Vx Ix=

1

gm+

gm

b

||ro

≈1

gm+

gm

b

Chapter 3

ECE697BB/Oliaei

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COMMON-SOURCE STAGE with DIODE-CONNECTED LOAD

Av=−

gm

1

1

gm

2+

gm

b2

=−

gm

1

gm

2

1

1+η

Av=

−(W

/L

) 1(W

/L

) 2

1

1+η

Av=

−u

n(W

/L

) 1u

p(W

/L

) 2

•G

ain

in

dep

end

ent

of

bia

s cu

rren

t

•G

oo

d g

ain

acc

ura

cy:

goo

d m

atc

hin

g

•G

ain

in

dep

end

ent

of

bia

s cu

rren

t

•G

ain

set

by t

wo

dif

fere

nt

typ

es o

f tr

an

sist

or

PMOS Diode-Connected Load

Chapter 3

ECE697BB/Oliaei

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COMMON-SOURCE with CURRENT SOURCE LOAD

Av=−

gm

r o1

||r o

2

•Large Output Voltage Compared with Resistive Load

•All Transistors Need to be in Saturation for High Gain

•M1 sets the Minimum Output Voltage

•M2 Sets the Maximum Output Voltage

Saturation

Triode

Av=

−g

mR

ON

2

RO

N2=

1

µnC

ox

W L

2

(VD

D−

Vb−

|VT

HP

|)

Chapter 3

High-Resistance Node

ECE697BB/Oliaei

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COMMON-SOURCE WITH SOURCE DEGENERATIONS

Av=

−G

mR

D

Av=

−g

mR

D

1+

gm

RS

Gm

=g

m

1+

gmR

S

Gm

=g

mr o

RS+

[1+

(gm+

g mb)R

S]r

o

Av=

−G

mR

D||

RO

UT

Including Second-Order Effects

Chapter 3

ECE697BB/Oliaei

41

COMMON-SOURCE OUTPUT RESISTANCE

RO

UT=

[1+

(gm+

gm

b)r

o]R

S+

r o

RO

UT=

r o'≈

r o[1

+(g

m+

gm

b)R

S]

Av=

−G

mR

D||

r o'

Av=

−g

mR

D

1+

gm

RS

=

−R

D

1/g

m+

RS

Simplified Model

Chapter 3

ECE697BB/Oliaei

42

SOURCE FOLLOWER

mb

mmb

m

out

gg

gg

R+

==

11

||1

Av=

gmR

S

1+

(gm+

gm

b)R

S

=R

S

1/g

m+

(gm+

gm

b

gm

)RS

≈R

S

1/g

m+

RS

Small-Signal Model

Output Resistance

•Source Follower Exhibits a high input resistance

and a low output resistance.

Chapter 3

ECE697BB/Oliaei

43

SOURCE FOLLOWER WITH FIXED BIAS CURRENT

•I d1, thus, Vgs1-Vth1, are independent of Vin.

Av=

1 g mb

||r o

1||

r o2

||R

L

1 g mb

||r o

1||

r o2

||R

L+

1 g m

Load Effect on Gain

Application: Buffering a High-Gain Stage

Chapter 3

ECE697BB/Oliaei

44

COMMON-GATE

Rout=

{[1+

(gm+

gm

b)r

o]R

S+

r o}

||R

D

AC coupling

DC coupling

Dmb

mD

DS

So

mb

mo

omb

mv

Rg

gR

RR

Rr

gg

r

rg

gA

)(

)(

1)

(+

≈+

++

++

+=

Small-Signal Model

Gain

Output Resistance

Input Resistance

Rin

=r o

||1 gm

||1 g m

b

Chapter 3

ECE697BB/Oliaei

45

CASCODE AMPLIFIER

Dmb

mo

o

Do

oo

mb

m

Rg

gr

r

Rr

rr

gg

Rout

||)]

([

||}

])

(1{[

22

21

21

22

2

+≈

++

+=

AV≈

gm

1{[r

o1r o

2(g

m2+

gm

b2)]

||R

D]}

AV≈

gm

1[(

r o1r

o2g

m2)|

|(r o

3ro

4g

m3)]

Shielding Effect of Cascode

Chapter 3

ECE697BB/Oliaei

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DIFFERENTIAL VERSUS SINGLE-ENDED

Single-Ended Source

Differential Sources

Advantage: Reduced Sensitivity to Supply Noise

Supply Noise

Clock Noise

ECE697BB/Oliaei

47

PSEUDO-DIFFERENTIAL AMPLIFIER

Disadvantage: Sensitive to Input Common-Mode Voltage

Chapter 4

ECE697BB/Oliaei

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DIFFERENTIAL AMPLIFIER

Tail current: Rejects input common mode

Dm

inin

out

out

diff

Rg

VV

VV

A=

−−=

21

21

Differential-Mode Gain

0=

cA

Common-Mode Gain

2

2

/

4

/

4

2in

ox

n

SS

in

ox

n

SS

ox

n

inDm

VL

WC

I

VL

WC

I

LWC

VIG

−−=

∆∆=

µµµ

∂∂

Chapter 4

ECE697BB/Oliaei

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SMALL-SIGNAL ANALYSIS

Dm

dR

gA

−=

Differential-Mode

SS

mDc

RgR

A+

−=

)2/(1

2/

Common-Mode

Virtual ground

Chapter 4

ECE697BB/Oliaei

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COMMON-MODE RESPONSE

SS

m

Dm

CM

in

YX

RgR

g

V

VV

21

,+

=−

Load Resistor Mismatch

Transistor Mismatch

()

1)

(2

1

21

,+

+−

−=

−

SS

mm

Dm

m

CM

in

YX

Rg

g

Rg

g

V

VV

Chapter 4

ECE697BB/Oliaei

51

DIFF. AMP WITH ACTIVE LOAD

mP

mN

oP

oN

mP

mN

dgg

rr

gg

A−

≈−

=−

)||

||(

1)

||(

oP

oN

mN

dr

rg

A−

=

)](||)

[(7

55

13

31

oo

mo

om

md

rr

gr

rg

gA

≈

Chapter 4

ECE697BB/Oliaei

52

Chapter 5

CURRENT MIRRORS

2

12

2)

(2

TH

DD

ox

nOUT

VV

RR

R

LWC

I−

+≈

µ

Reference Current

Sensitive to V

DD, Vth, W, L

ECE697BB/Oliaei

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CURRENT-BIASED DIFFERENTIAL AMPLIFIER

Chapter 5

ECE697BB/Oliaei

54

CASCODE CURRENT MIRROR

Low-Voltage Cascode

Chapter 5

ECE697BB/Oliaei

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DIFFERENTIAL AMPLIFIER WITH

ACTIVE CURRENT MIRROR

Large-Signal Operation

Chapter 5

ECE697BB/Oliaei

56

I D1=

I D3=

I D4=

gm

1,2

Vin

/2

I D2=

−g

m1,

2V

in/2

I out=

I D2−

I D4=

−g

m1,

2V

in ,⇒

Gm=

gm

1,2

DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD

Small-Signal Analysis

Av≈

Gm

Ro

ut

Rout≈

r o2

||r o

4 ,

(2r o

1,2>>

[1/g

m3]|

|ro

3)

Chapter 5

ECE697BB/Oliaei

57

COMMON-MODE ANALYSIS

4,3

2,1

2,1

21

1

mm

SS

m

CM

gg

Rg

A+

−≈

xF

VV

=

)2

1)(

||(

2,1

4,3

2,1

4,3

SS

mo

om

CM

DM

Rg

rr

gAA

CMRR

+=

=

Common-Mode Gain

Common-Mode Rejection Ratio

Chapter 5

ECE697BB/Oliaei

58

FREQUENCY RESPONSE OF AMPLIFIERS

vi

vo

pio

sRCS

sCR

sC

sV

sV

ω/1

1

1

1

/1/

1

)(

)(

+=

+=

+=

RC

pπ

ω2/

1=

Single-Pole Passive RC

ωωω

jRC

VV

io

+=1

1

)(

)(

: pole frequency

()2

2

1

1

)(

)(

ωωω

RC

VV

io

+=

ωjs=

Z1=

Z

(1−

Av)

Z2=

Z

(1−

A−

1 v)

Miller’s Theorem

XYv

VVA

=vA

Chapter 6

ECE697BB/Oliaei

59

AMPLIFIER FREQUENCY RESPONSE ANALYSIS

C1=

CF(1

−A

v)

C2=

CF(1

−A

−1v)≈

CF

Capacitance Multiplication

Association of Poles and Nodes

ωω

ωp

Nin

sinout

CR

CRA

CRA

sV

sV

21

21

1

1

11

)(

)(

++

+=

Chapter 6

ECE697BB/Oliaei

60

COMMON-SOURCE FREQUENCY RESPONSE

[]1

()

1()

(

)(

)

2+

++

++

++

+−

=DB

GD

DGS

SGD

Dm

SDB

GD

SB

GS

GD

GS

DS

Dm

GD

io

CC

RC

RC

Rg

Rs

CC

CC

CC

RR

s

Rg

sC

VV

f p,i

n=

1

2πR

SC

GS+

(1+

gmR

D)C

GD

[]

f p,o

ut=

1

2π

CG

D+

CD

B(

)RD

[]

Exa

ct A

naly

sis

GDm

zC

g+

=ω

Chapter 6

Ap

pro

xim

ate

An

aly

sis

(Mil

ler)

ECE697BB/Oliaei

61

SOURCE FOLLOWER OR COMMON DRAIN

vo vi=

g m+

sCG

S

s2R

S(C

GSC

L+

CG

SC

GD+

CG

DC

L)+

sg

mR

SC

GD+

CG

D+

CG

S(

)+g m

f p1≈

g m

2π

gm

RSC

GD+

CL+

CG

S(

) ,

assu

min

g

f p2>>

f p1

=

1

2πR

SC

GD+

CL+

CG

S

gm

Chapter 6

ECE697BB/Oliaei

62

SOURCE FOLLOWER INPUT IMPEDANCE

At

low

fre

qu

enci

es,

gm

b>

>|s

CL

|

Zin≈

1

sCG

S

1+

g m/g

mb

()+

1/g

mb

∴ C

in=

CG

Sg

mb

/(g

m+

g mb)+

CG

D

(sa

me

as M

ille

r)

Lmb

GS

m

GS

insC

gsCg

sCZ

+

+

+≈

11

1

At

hig

h f

requen

cies

, g

mb

<<

|sC

L|

Zin≈

1

sCG

S

+1 sC

L

+g m

s2C

GSC

L

Chapter 6

ECE697BB/Oliaei

63

SOURCE FOLLOWER OUTPUT IMPEDANCE

ZO

UT=

VX

/IX

=

sRSC

GS+

1

gm

+sC

GS

≈

1/g

m ,

at

low

fr

equ

enci

es

≈

RS

, a

t h

igh

fr

equ

enci

es

()

mS

mGS

mS

mg

RgC

Lg

RR

gR

/1

,/1

,/1

12

−=

−=

=

Ou

tpu

t ri

ngin

g d

ue

to C

Lan

d i

nd

uct

ive

com

pon

ent

of

ou

tpu

t im

ped

an

ce.

Chapter 6

ECE697BB/Oliaei

64

CASCODE STAGE

f pA=

1

2πR

SC

GS1+

CG

D1

1+

gm

1

gm

2+

g mb

2

f pX=

gm

2+

g mb

2

2πC

GD

1+

CD

B1+

CS

B2+

CG

S2

()

f pY=

1

2πR

DC

DB

2+

CL+

CG

D2

()

Chapter 6

ECE697BB/Oliaei

65

DIFFERENTIAL PAIR

f p1≈

1

2π(r

oN

||r o

P)C

L

f p2=

gm

P

2πC

E

f Z=

2f p

2=

2g

mP

2πC

E

Chapter 6

ECE697BB/Oliaei

66

FEEDBACK PRINCIPLES

Y(s

)=

H(s

)[X

(s)−

G(s

)Y(s

)]

Y(s

)

X(s

)=

H(s

)

1+

G(s

)H(s

)

ββ

ββ

β1

1

1

1≈

+⋅

=+

==

A

A

AA

XYACL

•Gain Desensitization

2

21

1

1

1 R

RR

A

AACL

+=

+⋅

=

β

βββ

•Example

121

RRACL

+≈

Chapter 8

ECE697BB/Oliaei

67

FEEDBACK EFFECT ON BANDWIDTH

+=

p

cl

ff

jAA

1

0

()

++

+=

)1(

11

1

00

0

ββ

ββ

Af

fj

A

AA

p

CL

Chapter 8

ECE697BB/Oliaei

68

FEEDBACK EFFECT ON OUTPUT IMPEDANCE

I X=

VX−

VM

Rout

=V

X−

(−βA

0VX

)

Rout

VX

I X=

Rout,

CL=

Rout

1+βA

0

VX

I X=

Rin

,CL=

Rin(1

+βA

0)

•Input Impedance

•Output Impedance

Chapter 8

ECE697BB/Oliaei

69

AMPLIFIER TYPES

Chapter 8

ECE697BB/Oliaei

70

OP-AMP

-+

-+- +

Differential Output

Single-Ended Output

∞→

vA

Ideal Op-Amp

∞→

inR

0=

out

R

Chapter 9

ECE697BB/Oliaei

71

SINGLE-STAGE OP-AMP

•OP-AMP as a voltage buffer

Chapter 9

ECE697BB/Oliaei

72

CASCODE OP-AMP: SINGLE-STAGE

+ Higher Gain

-Reduced Output Swing

-Output swing dependent on input swing

Telescopic Cascode

Chapter 9

ECE697BB/Oliaei

73

IMPROVED SINGLE-ENDED CASCODE OP-AMP

Chapter 9

Low-Voltage Cascode Current Mirror

ECE697BB/Oliaei

74

TRIPLE CASCODE

•A

vap

p. (g

mr o

)3/2

•S

ever

ely L

imit

ed O

utp

ut S

win

g

•C

om

ple

x b

iasi

ng

Chapter 9

ECE697BB/Oliaei

75

FOLDED-CASCODE AMPLIFIER

PMOS Input

NMOS Input

+ High Gain

+ Output Swing Decoupled from Input Swing

-Reduced Speed

Chapter 9

ECE697BB/Oliaei

76

FOLDED-CASCODE OP-AMP

13

33

1]

)[(

||

oo

mb

mm

vr

rg

gg

A4

43

44

21

+≈

Cascode Gain

Chapter 9

ECE697BB/Oliaei

77

|Av

|≈g

m1{[

(gm

3+

gm

b3)r

o3(r

o1||

r o5)]

||[(

gm

7+

g mb

7)r

o7r o

9]}

FOLDED-CASCODE OP-AMP

Chapter 9

ECE697BB/Oliaei

78

TELESCOPIC VERSUS FOLDED CASCODE

Non-dominant Pole

Non-dominant Pole

Chapter 9

ECE697BB/Oliaei

79

FOLDED-CASCODE OP-AMP IMPLEMENTATION

Current-Mirror

Current-MirrorDevices in Signal Path

Current-Mirror

signal

Chapter 9

ECE697BB/Oliaei

80

SINGLE-ENDED TWO-STAGE OP-AMPS

+ Large Voltage Swing

-Reduced Speed

Single-Ended Output Two-Stage Op Amp

Chapter 9

Active Current Mirror

ECE697BB/Oliaei

81

FULLY-DIFFERENTIAL TWO-STAGE OP-AMPS

+ Larger Voltage Swing

+ Better Noise Performance

Chapter 9Ex.1

Ex.2

ECE697BB/Oliaei

82

OUTPUT IMPEDANCE ENHANCEMENT USING FEEDBACK

Rout=

A1g

m2r o

2r o

1

Disadvantage: Low swing or Large Supply Voltage

Regulated Cascode

Chapter 9

ECE697BB/Oliaei

83

DIFFERENTIAL GAIN BOOSTING

Low-Supply

High-Supply

Chapter 9

ECE697BB/Oliaei

84

OP-AMP USING DIFFERENTIAL GAIN BOOSTING

Enhanced Telescopic Cascode

Chapter 9

Enhanced Folded Cascode

ECE697BB/Oliaei

85

COMPARISON

Chapter 9

Performance Comparison of OP-AMP Topologies

ECE697BB/Oliaei

86

COMMON-MODE FEEDBACK

Chapter 9

Low-Gain Amplifier

-+- +

High-Gain Amplifier

•Output common-mode voltage in a low-gain diff-pair is well-defined.

•Output common-mode voltage in a low-gain diff-pair is ill-defined.

ECE697BB/Oliaei

87

COMMON-MODE FEEDBACK PRINCIPLE

Auxiliary amplifier sets the output common-mode.

CM

ref

oo

VV

VV

==

+ 22

1ref

CM

VV

=

ECE697BB/Oliaei

88

COMMON-MODE SENSING METHODS

Resistive

Buffered-Resistive

ECE697BB/Oliaei

89

FOLDED-CASCODE WITH COMMON-MODE CONTROL

(a)

(b)

ECE697BB/Oliaei

90

SIMPLIFIED CMFB

•M7and M8in Triode.

•Advantages:

•Simple, low power

•Disadvantages:

•Low Accuracy

•Reduced Output Swing due to M

7and M

8

•Increased Output Parasitic Capacitance

•CMFBwith improved output swing:

ECE697BB/Oliaei

91

IMPROVED CMFB

CM

ref

VV

=

Through Symmetry:

Complete Implementation

ECE697BB/Oliaei

92

TRANSIENT LARGE-SIGNAL: SLEWING

Sle

w r

ate

:

()LSS

out

CI

dt

tdV

SR

==

ECE697BB/Oliaei

93

SLEWING IN TELESCOPIC OP-AMP

()LSS

out

CI

dt

tdV

SR

2=

=

Fully-Differential:

ECE697BB/Oliaei

94

FOLDED-CASCODE SLEWING

()LSS

out

CI

dt

tdV

SR

2=

=

Fully-Differential: