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Analog Integrated Circuit Design

Nagendra Krishnapura

Address: Dept. of Electrical Engg., IIT Madras, Chennai, 600036, India.

Phone/Fax: +91-44-2257-4444/+91-44-2257-4402

e-mail: [email protected]

A video course under the NPTEL

Assignment problem set

Nagendra Krishnapura, Dept. of EE Indian Institute of Technology, Madras

Analog Integrated Circuit Design A video course under the NPTEL

Contents

1 Negative feedback systems 3

2 Opamps using controlled sources 5

3 Opamp circuits 7

4 Components and their models 10

5 Noise and mismatch 12

6 Miscellaneous 15

7 Opamp design at the transistor level 17

8 Oscillators 19

9 Bandgap reference 20

10 Low dropout regulator 21

11 Continuous-time filters 22

12 Switched-capacitor filters 24

13 Appreciating approximations 26

2



Topic 1

Negative feedback systems

ωu

s

e-sTd

Σ+-

vi vo

Figure 1.1: Problem 1

1. (a) Setup the differential equation for the system

above.

(b) Vi is 1V for a long time and changes to 0V at

t = 0. What is the equation for t > 0?

(c) Assume that the solution is of the form

Vp exp(σt). Obtain the equation from which

you will determine σ (You are not required to

solve it).

(d) Express the above equation as f(σ) = 0.

Sketch f(σ). Determine the extremum of f(σ)

in terms of Td. For what value of Td does the

extremum become equal to zero?

(e) Assume that the solution is of the form

Vp exp((σ + jω)t). Obtain the equations from

which you will determine σ and ω (You are not

required to solve them).

(f) Reduce the above to a single equation in ω.

2. Fig. 1.2(a) shows a nonlinearity f enclosed in a

negative feedback loop with a feedback fraction β.

VFig. 1.2(b) shows a nonlinearity f preceded by an

attenuation factor.

f()

β

ΣVi Vo

+

-

Ve f(Ve)

ΣVi

+

(a)

(b)Vnl

+

f()Vi Vo

1+f’(0)β

1

VoA

(c)


(a) In each case, denote the transfer characteristic

of the overall system by g, i.e. Vo = g(Vi) and

calculate the first three terms of the Taylor se-

ries of g about the operating point of the circuit

in terms of f and its derivatives. Assume that

f(0) = 0.

(b) Fig. 1.2(c) shows the linear small signal equiv-

alent circuit from Vi to Vo with an additional

input Vnl. For the systems in Fig. 1.2(a) and

(c) Fig. 1.2(b), compute the small signal equivalent

gain A and the additional input Vnl. What do

you infer from the results?

3. Fig. 1.3(a) shows the amplifier studied in class.

Fig. 1.3(b) shows the same system with the input

applied at a different place. Calculate the dc gain,

3



4 Nagendra Krishnapura ([email protected])

Σ+-

ωu dt

(k-1)R

R

Vo

Vf

VeVi

Σ+-

ωu dt

(k-1)R

R

Vo

Vf

Ve

Vi

(a)

(b)


the -3dB bandwidth, and the gain bandwidth prod-

uct of the system and compare them to the corre-

sponding quantities in Fig. 1.3(b). Also compare

the loop gains. Remark on conventional wisdom

such as “constant gain bandwidth product”, “closed

loop bandwidth = unity gain frequency/closed loop

dc gain”. What is the reason for the discrepancy?

Draw an equivalent block diagram of Fig. 1.3(b) such

that the classical form of feedback (sensed error in-

tegrated to drive the output) is clearly obvious (Hint:

compute the error voltage Ve).

4. The loop gain L(s) of a system withN extra poles is

given by

L(s) =ωu,loop

s

1∑N

m=0amsm

a0 = 1. What does the loop gain step re-

sponse (inverse laplace transform of L(s)/s) look

like after an initial transient period? Give your an-

swer in terms of the poles of the additional fac-

tor (Hint: Split L(s) into a sum of two parts, one of

which is ωu,loop/s)



Topic 2

Opamps using controlled sources

CcCo1 Gm2Ci1+

-

out

−

+

CL

Vi

Vo

Rc

GL

Gf

Gi

Go2Gm1 Go1


1. Gm1 = 20µS, Go1 = 0.25µS, Gm2 = 80µS, Go2 =

2µS, GL = Gf = Gi = 4µS, Ci1 = 10 fF, Co1 =

40 fF, Cc = 250 fF, CL = 1 pF, Rc = 12.5 kΩ.

Determine the poles and zeros of the loop gain—

Calculate them based on approximations discussed

in the class, and by calculating the Loop gain func-

tion symbolically and extracting the roots numeri-

cally. Comment on the accuracy of approximations.

Determine the closed loop transfer function and cal-

culate its poles and zeros. How do these relate to

poles and zeros of the loop gain function.

Plot the unit step response and the loop gain magni-

tude and phase response.

Change each (one at a time) of Cc, Rc, GL = Gf =

Gi to 0.5× and 2× their nominal values. Plot theunit step response and the loop gain magnitude and

phase response (overlaid on the same plot for each

case). Comment on the results.

CcCo1 Gm2vo1+

-

outGo2Gm1vd Go1

+

-

vo1vd

1

CcCo1 Gm2vo1

+

-

outGo2Gm1vd Go1

+

-

vo1vd

icic

current controlled current source

voltage buffer

(a)

(b)

CcCo1 Gm2vo1+

-

outGo2Gm1vd Go1

+

-

vo1vd

(c)


2. The circuits in Fig. 2.2(a, b) are modified

versions of the two stage miller compensated

opamp (Fig. 2.2(c)). Calculate their transfer func-

tions and compare them to that of the conventional

structure. What is the difference? Explain the re-

sults.

3. Design a three stage opamp (Fig. 2.3(a)) using the

opamp in Fig. 2.1 as the “inner” opamp (Fig. 2.3(b)).

ExcludeRc, Ci1,Gi,Gf , andGL from Fig. 2.1. Use

C3 = 1 pF. For the first stage of Fig. 2.3, use the

same values as in the first stage of Fig. 2.1. Deter-

mine the value of Cm1 to obtain a phase margin of

60. What is the unity gain frequency of the three

stage opamp?

5




−

+

A(s)

Cm1

Vo

+

-

Ve

Vi

Vf

Gm1 Ro1 C1 Gm2 Ro2 C2 Gm3 Ro3 C3

Cm2

Cm1

+

-

Vo

(a)

(b)

+

-

Ve

Vi

Vf

Gm1 Ro1 C1


Where are the poles and zeros? (Derive the expres-

sion assuming G1 = G2 = G3 = 0 and find the

roots exactly. Calculate the dc gain and unity gain

frequency separately). Comment on the location of

the zeros.

Connect a zero cancelling resistor in series withCm2

such that the corresponding zero moves to infinity.

What is the phase margin?

With the zero cancelling resistor in place, adjustCm1

such that the phase margin is 60. What is the new

unity gain frequency?

+

-

Vs

+

-

Vo

Gs GLgds CLCgdCgs gm


4. Fig. 2.4 shows the small signal equivalent circuit of a

common source amplifier. gm = 100µS, gds = 1µS,

GL = 2µS, Gs = 1µS, Cgs = 0.1 pF, Cgd =

0.05 pF, CL = 0.5 pF. Plot the magnitude and phase

response of the circuit (overlaid) for the following

cases: a) Cgd = 0, 0.05, 0.1, 0.2, 0.4, 0.8, 1.6 pF,b) CL = 0, 0.05, 0.1, 0.2, 0.4, 0.8, 1.6 pF, c)GL = 0, 1, 2, 4, 8, 16µS. (In each case all other

components have their nominal values). Comment

on the results.

5. Calculate the poles and zeros for each case in the

above problem. How do they compare to the approx-

imate expressions?



Topic 3

Opamp circuits

−

+

−

+Vi

Vi

R

(k-1)R

R

kR

(a) (b)

VoVo


1. Fig. 3.1(a) and Fig. 3.1(b) shows amplifiers which

realize gains of k and −k respectively with ideal

opamps. Compare the following parameters of the

two circuits. Model the opamp as an integrator ωu/s.

(a) Input impedance

(b) Bandwidth

(c) Differential (V+(s) − V−(s)) and common

mode ((V+(s) + V−(s))/2) input voltages of

the opamps

Assuming that the sign of the gain is unimportant

in your application, what would make you choose

one over the other? Is there any reason to choose

Fig. 3.1(b) at all?

2. Fig. 3.2 shows the four types of controlled sources

using an opamp. Model the opamp as an integra-

tor ωu/s. For each of these, calculate the trans-

fer ratio (output/input), input impedance, and output

impedance at (a) dc, and (b) an arbitrary frequency

ω. For (b), set Rout = 0 when calculating the input

impedance and Rin = ∞ while calculating the out-put impedance. What happens to these three quanti-

ties at high frequencies in each case?

−

+Vi

Vo

−

+

Ii

RinRout

Rin

Vo

(k-1)R

R

−

+Vi RinRout

R

+−

vopa

vopa

Io

load

Rout

−

+RinRout

R

+−

vopa

vopa

Io

load

Ii

(k-1)R

(a)

(c)

(b)

(d)

R

Figure 3.2: Problem 2. (a) VCVS, (b) CCVS, (c) VCCS,

(d) CCCS

3. Due to some parasitic effects, an opamp has a trans-

fer function with an extra pole p2 (ωu/s(1 + s/p2)

instead of ωu/s). This is used to realize an am-

plifier with a closed loop dc gain k. Instead of

the step response, the criterion here is the band-

width. Find the conditions to maximize the band-

width without the closed loop gain increasing above

k for any frequency (This condition is known as max-

imal flatness, and the mathematical condition is to

have dn/dωn|H(jω)|2 = 0, n = 1, 2, . . . for as large

an n as possible). To avoid mess, assume a general

form of the second order transfer function, evaluate

the damping factor for maximal flatness, and substi-

tute the values from the transfer function of the am-

plifier. How does it compare to a critically damped

system?

4. Fig. 3.3 shows a transimpedance amplifier driven by

a photodiode. The photodiode can be modelled as

7




−

+

Rf

Is

Vo

Ao=103

fu=100MHz

p2=400MHz

1pF

Cf


a current source in parallel with a capacitor. The

opamp has Ao = 103, ωu/2π = 100MHz and

p2/2π = 400MHz (Make a model of the opamp us-

ing controlled sources and passive elements. A pa-

rameterized macromodel of the opamp is very useful

for future circuit designs).

(Don’t include Cf for this part) What is the largest

transimpedance Rf you can have without peaking in

the frequency response Vo/Is? Show the ac magni-

tude response and the transient response to a current

step of 1/Rf Amperes with a 100 ps risetime?

Increase Rf by 20× and show the ac magnitude re-sponse step response (current step of 1/Rf Amperes.

Compare this to the earlier case and comment on the

results.

Calculate |Vo/Is| including Cf . Find the condition

for maximal flatness. Calculate Cf for the increased

value of Rf and show the magnitude response and

the step response. What does the loop gain look like

for this circuit?

Calculate the expression for the “gain-bandwidth

product” with Cf (gain = Rf ).

(For analytical calculations of maximally flat magni-

tude response, it’ll be simpler to use an ideal integra-

tor model for the opamp, and then adjust the values

to account for the second pole).

5. Simulate the open loop frequency response of the

opamp OPA656. If you try to measure it as given

−

+

−

+

Clarge

Llarge

Vi(jω)

Vo(jω)

Vi(jω)

Vo1(jω)

(a) (b)

Figure 3.4: Problem 5: Measuring an opamp’s frequency

response

in Fig. 3.4(a), the opamp may not be biased cor-

rectly. As you know, the opamp is biased correctly

only when there is dc negative feedback around the

opamp. A trick to maintain dc negative feedback,

but break the feedback loop for higher frequencies is

shown in Fig. 3.4(b). For frequencies where the volt-

age drop across the capacitor and the current through

the inductor are negligible, the input voltage appears

directly across the opamp and there is no feedback.

Since this is a simulator, use comfortably large val-

ues like Clarge = 1F and Llarge = 1 kH.

What are the dc gain, unity gain frequency, and

nondominant pole(s)? Estimate these from magni-

tude/phase plots.

−

+

−

+

−

+

Vtest(jω)

-L(jω)Vtest(jω)

-L(jω)Vtest(jω)Vtest(jω)

Clarge

Llarge

ViVo

Vi=0

Vi=0

R1

(a)

(b)

(c)

R2

R2

R1

R1

R2

Figure 3.5: Problem 6: Inverting amplifier

6. Simulate the frequency response and the loop gain of



Analog Integrated Circuit Design; Assignment problem set 9

an inverting amplifier (Fig. 3.5(a)) of gain 100. Loop

gain L(jω) can be determined by breaking the loop

as shown in Fig. 3.5(b). DC negative feedback has

to be maintained and the same trick as in the pre-

vious problem can be used (Fig. 3.5(c)). Do these

simulations for R1 = 100Ω and R1 = 10k Ω. Do

the closed loop bandwidths match the unity loop gain

frequencies? Are the latter in turn consistent with the

opamp’s unity gain frequency evaluated in the previ-

ous experiment? Explain the results clearly.

7. Design inverting and non-inverting amplifers with

gains −5 and +5 respectively using the opamp

OPA656 and ±5V supplies. Simulate these ampli-

fiers with 10MHz sinusoidal inputs of 400mV peak.

Compute the distortion components upto the fifth

harmonic and compare the distortion performance of

the two amplifiers.

Plot the differential and common mode inputs of the

opamp in the two cases and explain the results using

the results from the previous problem.

When taking the DFT for distortion analy-

sis, ensure that steady state is reached (wait

for a sufficiently long time before taking the

first point) and that you use an integer num-

ber of cycles to avoid spectral leakage (Refer to

http://www.ee.iitm.ac.in/∼nagendra/E6316/current/handouts.htmlor the relevant lecture from EE658 at

http://www.ee.iitm.ac.in/∼nagendra/videolectures/)

OPA656 model is available at

http://www.ee.iitm.ac.in/∼nagendra/cadinfo.html



Topic 4

Components and their models

V0-vx/2V0+vx/2

V0+vx/2 V0-vx/2

Vbias

200kΩ


1. (For this problem, The minimum usable dimension

is 0.3µm.) A MOSFET is used as a 200 kΩ re-

sistor (Fig. 4.1) V0 = 0.5V and vx is restricted to

0.25V. The nonlinear part of the current (Difference

between the exact expression and its linear approx-

imation) in the resistor should be at most 5%. Cal-

culate the gate bias Vbias and the dimensions of the

transistor. If a linear resistive material with a sheet

resistance of 10Ω/sq. is available, what would be

its dimensions? What is the motivation for using a

transistor instead of a resistive material?

2. Design a 2 pF capacitor using A square nMOS de-

vice (drain/source shorted). Plot its capacitance as

a function of voltage (0 to 1.8V). What is the usable

voltage range of this capacitor? (For this problem use

the process information given in the cadinfo page).

Repeat the above for a square pMOS device.

A square Metal1-Metal2 structure.

A square sandwiched structure with poly, M2, M4

tied together and M1, M3, M5 tied together.

For the last two structures, determine the bottom

plate parasitic capacitance.

3. (Repeat this for nMOS and pMOS and compare the

results) Bias a transistor with VGS = VDS = 1.0V

and determine W (with L = 0.18µm) to get a cur-

rent of 200µA. Simulate SIDthe noise spectral den-

sity of drain current from 100Hz to 100MHz.

Double the length and resize W to get 200µA, and

simulate SID. Repeat until L = 5.76µm. Over-

lay the spectral density plots (log y axis) and iden-

tify the 1/f noise corners. Plot the 1/f noise cor-

ners vs. L. Briefly explain the results. Plot ID vs.

VDS (0 to 1.8V) for VGS from 0 to 1.5V in steps of

0.25V and VBS = 0V. Overlay the plots forW/L =

3.6µm/0.36µm andW/L = 36µm/3.6µm. Com-

ment on the results.

4. Plot ID vs. VDS (0 to 1.8V) for VBS from -1V to

0V in steps of 0.25V and VGS = 1.5V. Overlay

the plots for W/L = 3.6µm/0.36µm and W/L =

36µm/3.6µm. Comment on the results.

5. Plot (log-log) ID vs. VGS (18mV to 1.8V) for

VDS = 1V and VBS = 0V. Overlay the

plots for W/L = 3.6µm/0.36µm and W/L =

36µm/3.6µm and temperatures of 0, 27, 100C.Comment on the results. Calculate the subthreshold

slope η. The current in a MOS transistor in the sub-

threshold region is proportional to exp(VGS/ηVt)

where Vt is the thermal voltage.

6. Plot (log-log) ID vs. VBS (-1.5V to -15mV) for

VDS = 1V and VGS = 1V. Overlay the

plots for W/L = 3.6µm/0.36µm and W/L =

10




36µm/3.6µm and temperatures of 0, 27, 100C.Comment on the results.



Topic 5

Noise and mismatch

−

+

Rf

Vo

Iin

Sv,opa

−

+

Rf/k

Vo

Iin

Sv,opa

−

+

R

R/k

−

+

Iin

Sv,opa

Rf

Vo

Rx

Sv,opa


1. Determine the output noise spectral density and input

referred (current) noise spectral density of the tran-

simpedance amplifiers in Fig. 5.1. The opamp has

an input referred voltage noise spectral density of

Sv,opaV2/Hz and is otherwise ideal.

2. Design a transimpedance amplifier with a gain of

10 kΩ and the highest possible bandwidth without

peaking using an OPA656 opamp. The photodiode

has a 5 pF capacitance. Simulate the frequency re-

sponse, step response (100µA step input), and input

referred and output noise spectral densities. How

does the simulated noise compare to analytical cal-

culations? What fraction of noise is contributed by

Rf? (The relative contribution of different compo-

nents can be printed out in the simulator)

C

R

Vpcos(ωt)

+

-

vo

+

-


3. The filter in Fig. 5.2 is driven by a sinusoid at ω =

1/RC. Calculate the output noise voltage, output

signal to noise ratio (ratio of mean squared signal to

mean squared noise voltages), and the power dissi-

pated in the circuit. If the impedances of all com-

ponents are scaled up by a factor α, what happens

to the transfer function of the circuit, output noise

voltage, output signal to noise ratio, and the power

dissipation?

Derive a relationship between the signal to noise ra-

tio, power dissipation, and the bandwidth of the cir-

cuit (in Hz). What tradeoffs does this relationship

represent?

4. Determine the rms signal, rms noise, signal to noise

ratio (as a ratio of mean squared quantities) at the

output of Fig. 5.3. Assume an low frequency input.

What is the amplifier’s transfer function? The opamp

can be either (i) class A (Fig. 5.3(b)): In this case

a constant current Ibias, equal to the highest possi-

ble output current) is drawn from the amplifier; or

12




−

+

+

-

Vi=(Vpp/2k)cos(ωt)

R/k

R

+Vs/2

-Vs/2

−

+

(a) (b)

(c)

C

-Vs/2

+Vs/2

Vo−

+-Vs/2

+Vs/2

ioutIbias

Ibias=max(iout)

−

+-Vs/2

+Vs/2


(ii) class B (Fig. 5.3(c)): In this case, currents out of

the opamp are drawn from the positive supply and

currents into the opamp are pushed into the negative

supply. In each case, calculate the power dissipation.

Relate the power dissipation to amplifier specifica-

tions: gain, bandwidth, and signal to noise ratio.

I0/n

W/n

L

W

L

Iout

+−

Vout


5. You are required to design a current mirror that can

operate with an output voltage Vout (Fig. 5.4). The

total current drawn from the supply must be Itot. De-

termineW/L and nwhich will maximize the ratio of

signal (load current) to noise (rms current in a band-

width fB)? Consider only the thermal noise spectral

density. Think about why this value of n is optimal

for signal to noise ratio.

6. Determine the output current in Fig. 5.5. Determine

the output noise current in terms of small signal pa-

rameters of M3 and M4. Which of the devices pri-

marily contribute to the noise? Determine the out-

put current error due to current factor and thresh-

old mismatches (∆β13,∆VT13 betweenM1 andM3,

W/4n

L

W/n

L

W

L

W

L

M2

M1 M3

M4

I0/nI0/n

Iout

gm4, gds4

gm3, gds3

Vdd


and ∆β24,∆VT24 between M2 and M4). Which of

the mismatches is more critical?

max. voltage=1.1V

1µA

100µA

Vdd=1.8V

M1 M2

(a)

max. voltage=1.1V

1µA

100µA

Vbiasp2

Vdd=1.8V

M2M1

M3 M4

(b)


7. Fig. 5.6 shows a simple current mirror and a cascode

current mirror delivering 100µA from a 10µA ref-

erence. The maximum voltage at the output can be

1.1V.

(a) Design the simple mirror with L = 2µm.

(b) Design the cascode current mirror for the same

output voltage constraint with L = 2µm for M1,2.

Choose M3,4 as you wish subject to the constraints

that the output impedance should be as high as pos-

sible at all frequencies and that the output thermal




noise spectral density should not increase by more

than 3 dB when compared to the simple current mir-

ror. Provide an arrangement to generate Vbiasp2.

Plot the output impedance and output current noise

spectral density in for the two mirrors (Terminate the

output with a 1.1V dc source). What is the relative

noise contribution from different devices? Plot the

dc output current as the output voltage is varied from

0 to 1.8V.

+−

+−

Vout Vout

+

-

VGS

ID-∆ID/2 ID+∆ID/2


8. Two transistors carrying a current ID are required to

have a current mismatch ≤ σIDand operate in satu-

ration with an output voltage Vout (Fig. 5.7). Com-

pute the transistor dimensions and its fT in terms of

the mismatch constants AV T and Aβ , ID, σIDand

Vout. Comment on the tradeoffs implied by this rela-

tionship.



Topic 6

Miscellaneous

1. The circuit in Fig. 6.1(b) is the miller equivalent

of Fig. 6.1(a). Determine the transfer functions of

Fig. 6.1(a) and Fig. 6.1(b)? Are they the same?

Determine the transfer function of Fig. 6.1(c). Re-

place Fig. 6.1(c) by its miller equivalent Fig. 6.1(d)

and determine its transfer function. Are the results

the same? If not, what are the differences and why?

Carry out this exercise by first omitting Cgs and CL,

and then including them in the analysis.

Vdd

Vi

RL

Vo

I0

(a)

Vdd

Vi

Vo

I0

(b)

Vdd

RL

I0

(c)

I0VG

Vo

Vi

Rs


2. Determine the spectral density of output noise volt-

age and input referred noise voltage of the stages in

Fig. 6.2.

15




gm, gds

C

-A

C(1+A) C(1+1/A)

C

+

-

Vi

+

-

Vo

+

-

Vi

+

-

Vo

-A

+

-

Vi

-

Vo

+

gm, gds

+

-

Vi

-

Vo

+

Rs

Rs Rs

Rs

Ci

Co

Cgs

CL




Topic 7

Opamp design at the transistor level

Vcm+vcm

Vdd

gds0

M1 M2

M3 M4

vo

Vcm+vcm

Vdd

gds0

M1 M2

M3 M4

vo

(a) (b)

I0I0 I0/2


1. The common mode gain of a differential amplifier is

measured by applying a small signal common mode

input vcm as shown in Fig. 7.1. Fig. 7.1(a) has a cur-

rent mirror load and Fig. 7.1(b) has a current source

load which is independently biased. What is the

common mode gain of these two configurations? Ex-

press the answer in terms of the small signal param-

eters of: M0 (gm0, gds0), M1,2 (gm0, gds1 = ∞),M3,4 (gm3, gds3)

+- vo vo

I0I0

I0/2 I0/2 I0/2

+

-

(a) (b)

Vcm+vi/2 Vcm-vi/2 Vcm+vi/2 Vcm-vi/2


2. Determine the small signal dc gains of the two am-

plifiers in Fig. 7.2. The transistors can be modeled

using gm and gds . Explain the results.

Vcm+vi/2 Vcm-vi/2

Vdd

vx

R1 R2


3. Calculate the small signal tail node voltage vx in

Fig. 7.3. vi is a small signal increment. The tran-

sistors can be modeled using gm and gds .

4.

+

−

voutVcm ± vi/2Vcm

vi = Vip cos(2πfint)

φ1

φ2

8 pF

1/fs0 t

φ1

φ2

8 pF

8 pF

8 pF

φ1

φ1

φ2

φ2

φ2

Figure 7.4: Problem 5: Sample and hold circuit

5. Sample and hold: Design the sample and hold cir-

cuit in Fig. 7.4 using the fully differential folded cas-

17




code opamp designed above. Use ideal switches with

1 kΩ on resistance. Use fs = 4MHz and fin =

1/4, 9/4MHz (sinusoidal input with 1.6Vppd1amplitude) and plot the output waveforms. Provide a

plot that shows the settling behavior of the opamp.

Vcm

vip

vin

Vcm

vip, vin

differential step common mode step

10 kΩ

10 kΩ

10 kΩ

10 kΩ

10 kΩ

10 kΩ

8 pF

8 pF

Vcm

Vcm = 0.9 V

vin

vip

Figure 7.5: Problem 6: Inverting amplifier

6. Inverting amplifier: Design the inverting amplifier

in Fig. 7.5 using the fully differential two stage am-

plifier designed above. Show the output waveforms

for a 1V differential step and a 0.5V common mode

step.

1Vppd: volts, peak-peak differential



Topic 8

Oscillators

Vdd

L LRdiff

I0

Rs Rs

vopvom

ix

(a)

Vdd

L L

I0

Rs Rs

vopvom

(b)

C C


1. Calculate the current flowing in each transistor in

Fig. 8.1(a) in the quiescent condition. Calculate the

small signal differential resistance Rout looking into

the drains of the two transistors.

In Fig. 8.1(b), calculate (vop − vom)/ix. What is

the condition for this to be infinity? What is the fre-

quency at which this happens?

Vdd

C1

C2

I0

Zin


2. Calculate the input impedance Zin in Fig. 8.2. Is

there anything special about it? Model the transistor

using only its gm.

Vdd

C1

C2

L

ix

vx

I0Rs


3. Calculate the small signal impedance vx/ix. What is

the condition for this to be infinity? What is the fre-

quency at which this happens? Model the transistor

using only its gm.

N inverters(N: odd)


4. In Fig. 8.4, assume that all nodes are at the self bias

voltage of the inverter. Model the small signal gain

of each inverter as A0/(1 + s/p1) and calculate the

condition for instability (i.e. when the loop gain be-

comes −1). Hint: Among the roots of −1, pick the

one which satisfies the above for the lowest value of

A0.

19



Topic 9

Bandgap reference

Bias a 1x sized diode connected PNP1 at 5µA as shown

in Fig. 9.1(a) and sweep the temperature from 0 to 100C.

Determine dVBE/dT at 27C.

Design the bandgap shown in Fig. 9.1(c). Choose R1 for

a quiescent current of 5µA and R2 to get zero tempera-

ture coefficient at Vbg . Choose R3 = R2. What is the role

of R3? Simulate the bandgap reference with the model

of a single stage opamp assuming that the single stage

opamp is made like the first stage of the previous prob-

lem. (Fig. 9.1(b)-model the gm, and the pole zero dou-

blet). Choose Cc for ringing ≤ 10%. Test the bandgap

reference by sweeping the temperature from 0 to 100C

and plot Vbg . Test the transient response by applying a

1 uA pulse to the output of the opamp. Adjust the values

ofR1,R2,R3 (= R2) if necessary to get zero TC at 27C.

Modify the circuit as in Fig. 9.1(d). How should Vx, Vy ,

and Vbg change? What is the purpose of this modifica-

tion? Resimulate with the opamp model as before and

test the temperature sensitivity, transient response and the

loop gain.

Substitute the differential pair opamp designed in the pre-

vious assignment and simulate the temperature sensitivity

of Vbg and the transient response to a current step at the

output.

1Use the model ideal pnp in ideal diode.lib

Vdd

5µA

Vbe

+

-

R1

R3R2

Cc

−

+

Vdd

R1

R3R2Cc

−

+

Vdd

1x 8x

1x 8x

model of thesingle stage opamp

Vbg

Vbg

1GΩ+

-

+−

1.0

gm1

C1

C2

R1

model of the single stage opamp

adjust R1,C1,2 and gm1 to model the pole-zero doublet

and the transconductance of the single stage opamp

single stage opamp

Vx

Vy

Vx Vy

W/L W/L

W/L W/L

1µA pulse for

transient test

1µA pulse for

transient test

(a)

(b)

(c)

(d)

Vz Vw

connect the opamp inputs to

Vx and Vy OR Vz and Vw depending on the

input common mode range

Vz or Vx

Vw or Vy

Figure 9.1: Bandgap reference

20



Topic 10

Low dropout regulator

Bandgap

reference

1.2V −

+

Vdd

20µA

Vout

Load

IL

M1

−

+Bandgap

reference

1.2V

R2

R1

Vout

(a)

Load

IL

(b)

VddIsup

CL

Zout

Figure 10.1: Low dropout regulator

A voltage regulator is nothing but a noninverting amplifier

whose input is the bandgap voltage from a reference. In

Fig. 10.1(a), the output voltage is (R2/R1)Vbg . By mak-

ing R2 variable, one can get a variable voltage output.

• The output impedance should be very low: This isaccomplished by realizing a very high loop gain over

as wide a bandwidth as possible.

• The efficiency ((VoutIL)/(VddIsup)) should be very

high: For this, the current Isup−IL consumed by the

circuit should be minimized (This makes it hard to

satisfy the previous condition). The “dropout” Vdd −Vout should be minimized.

• Usually only a positive IL needs to be driven. The

output voltage is constant over time. These are de-

partures from conventional amplifiers.

Fig. 10.1(b) shows a “pass transistor” M1 enclosed in a

feedback loop. For simplicity, a unity gain case is shown.

M1 should have a high enough W/L to remain in sat-

uration with the desired dropout and the highest output

current. Miller compensation around M1 is usually not

used because it severely compromises power supply re-

jection (Incremental voltage gain from Vdd to the output

voltage).

Use the model in Fig. 9.1(b) for the single stage opamp.

Use a 50µA quiescent current in M1. Adjust the

width (with minimum length) of M1 for a dropout of

300mVwith a 50mA current. You can use a 1.2V voltage

source in place of the bandgap reference. Compensate the

loop using a load capacitor CL for a phase margin of 45

at IL = 0 and IL = 50mA and choose the higher one. Do

the following (except the last one) for two cases (IL = 0

and IL = 50mA—you can use a current source for the

load):

1. Vary Vdd from 1.4V to 1.8V and plot Vout

2. Plot Zout from 1 kHz to 10MHz

3. Plot the transfer function from Vdd to Vout from

1 kHz to 10MHz

4. Plot the small signal step response for a 10µA step

in the output current

5. Plot the large signal step response (IL switching

from zero to 50mA and 50mA to zero)

21



Topic 11

Continuous-time filters

1. (a) Compute the transfer functions Vo/Vi in terms

of the parameters (Q, ωp, b0, b1, b2) for the cir-

cuits in Fig. 11.1(a, b).

(b) Turn these circuits into parameterized subcir-

cuits “bilinear” and “biquad” in a circuit sim-

ulator1 with the required parameters. You can

then use these subcircuits to realize ideal cas-

cade realizations of any transfer function.

0dB

-1dB

-40dB

1M

Hz

2M

Hz

0dB

-1dB

-40dB

1 r

ad

/s

2 r

ad

/s

(a) (b)


2. You are required to realize a filter that meets

the specifications shown in Fig. 11.2(a). You

are given (Table 11.1) the poles and zeros of 4

types (Excluding Bessel) of filters which satisfy the

prototype specifications in Fig. 11.2(b).

(a) Tabulate the order, the resonance frequencies,

the quality factors of the poles, and the loca-

tion of transmission zeros (if present) of the dif-

ferent types of filters that satisfy the specs. in

Fig. 11.2(a).

1In circuit simulators, to realize a current controlled voltage source,

you also usually need to have a 0V voltage source through which the

desired current is flowing.

(b) Using the parameterized subcircuits for the bi-

linear and the biquadratic filters, simulate the

four filters (using the cascade structure) in a cir-

cuit simulator. Use the rules of cascading dis-

cussed in the lectures. Clearly state the order of

cascade and the pole zero pairing.

For the Bessel filter, simulate the frequency

response of the prototype (last column of Ta-

ble 11.1). If this filter were scaled such that it

had an attenuation As = 40 dB at 2MHz (the

stopband edge), what would be its attenuation

at the passband edge (1 MHz)?2 Does it meet

the specs in Fig. 11.2(a)?

Now simulate the scaled Bessel filter.

Plot their magnitude and phase responses3, and

the group delay.

(c) For each filter, determine the maximum trans-

fer function magnitude from the input to each

of the stage (first or second order) outputs. If

each output were limited to 1V, what is the

maximum input voltage that could be applied

to each without having distortion?

(d) For each of the 5 filters list the maximum

quality factor of the biquad stages used, the

maximum resonant frequency, and the maxi-

2You don’t need to rescale the filter and simulate. You should be able

to answer this by looking at the prototype response.3Plot the magnitude responses of the 5 filters in the same plot; same

for the phase response and the group delay. Plot the magnitude re-

sponse (in dB) twice—once showing the whole picture and once zoomed

in on the passband. Use sensible scales so that the details of the response

can be seen. e.g. with notches, the response goes down to −∞ dB and

the default scale may be totally unsuitable.

22




R=QC=1/ωp L=1/ωp

IC IR IL

+-

+-

+-

Vi

Vi

tra

nsco

nd

ucta

nce

=1

S

b2IC

b1IR

b0IL

+

-

Vo

+

-

R=1C=1/ωp

IC IR

+-

+-

Vi

Vi

tra

nsco

nd

ucta

nce

=1

S

b1IC

b0IR

+

-

Vo+

-

(a) (b)

"bilinear" "biquad"


mum group delay variation in the passband (<

1MHz). This gives you a comparison of differ-

ent types of filters that are designed to meet a

given specification (Fig. 11.2).

Table 11.1: Prototype zeros and poles

Butterworth Chebyshev Inverse Chebyshev Elliptic Bessel

poles poles zeros poles zeros poles poles

−1.1031 ± j0.2194 −0.0895 ± j0.9901 ±j3.0671 −0.2811 ± j1.1013 ±j3.5251 −0.3643 ± j0.4786 −0.3868 ± j1.0991

−0.9351 ± j0.6248 −0.2342 ± j0.6119 ±j1.8956 −0.9461 ± j0.8751 ±j1.6095 −0.1053 ± j0.9937 −0.6127 ± j0.8548

−0.6248 ± j0.9351 −0.2895 −1.4202 −0.7547 ± j0.6319

−0.2194 ± j1.1031 −0.8453 ± j0.4179

−0.8964 ± j0.2080

−0.9129



Topic 12

Switched-capacitor filters

1. A continous time first order filter has a transfer func-

tion

Hc(s) =2

1 + s/ωp

ωp = 2π × 20 krad/s. TransformHc(s) into discrete

time transfer functionsHd(z) using bilinear transfor-

mation. The sampling frequency fs = 1MHz.

Plot the magnitude and phase responses of Hc and

Hd with the real frequency (Hz) from 0 to 1MHz

along the x axis. Are the magnitude and phase re-

sponses the same for all the cases? Comment on the

results.

Repeat for ωp = 2π × 200 krad/s.

2. Design the above filter (Hc(s) orHd(z)) as

(a) a continuous time opamp-RC filter

(b) bilinear transformed switched capacitor fil-

ter (for this, assume that both the input Vi and

its inverted form −Vi are available)

(c) switched capacitor version of a) with the resis-

tor replaced by a switched capacitor

(d) Noninverting delayed switched capacitor inte-

grator whose magnitude response is equal to

that of the bilinear transformed filter at dc and

the 3 dB frequency (i.e., the pole of the SC in-

tegrator should be adjusted such that its -3dB

frequency is the same as that of the LDI trans-

formed filter).

Do it for both ωp = 2π × 20 krad/sand ωp = 2π ×200 krad/s. In each case, give the schematic and the

component values.

3. Simulate each of the filters designed in problem 3

in a circuit simulator. Plot the magnitude and phase

responses.

4. A second order filter has a transfer function has the

form

H(s) =N(s)

1 + (s/Qpωp) + (s/ωp)2

(a) What is N(s) for lowpass, bandpass, highpass,

and band stop filters? (In each case, assume that

the gain in the center of the passband is unity)

(b) Transform each of these into a discrete time fil-

ter using bilinear transformation. Assume that

Qp = 4 and ωp = fs/10, where fs is the sam-

pling frequency.

(c) Sketch the pole zero plots of the continumous

time filters and their discrete time counterparts.

5. Compute the transfer function V1/Vi in the Fleischer

Laker biquad. Fig. 12.1. The output is defined at the

end of φ1 and the input Vi changes on the rising edge

of φ2.

6. Transform a second order CT (continuous time)

bandpass filter into a DT(discrete time) bandpass fil-

ter using bilinear transformation. The gain at center

frequency and the quality factor of the CT prototype

are both 10. The resonant frequency fp (in Hz) is

20% of the sampling frequency fs (in Hz).

7. Compute the values of the capacitors in the

Fleischer-Laker biquad to realize the above filter.

Assume B = D = 1 and A = C. Also, usually,

24




−

+

E

C

G

H

D

−

+

A

I

J

B

F

Vi

V2

V1

φ1 φ1

φ2φ2

φ1 φ1

φ2φ2

φ1 φ1

φ2φ2

φ2 φ1

φ2φ1

φ2 φ1

φ2φ1

φ2 φ1

φ2φ1

φ1 φ1

φ2φ2

φ1 φ1φ2 φ2 φ2 φ2

n-1

n n+

1

φ1

Vi[n]Vi[n-1] Vi[n+1] Vi[n+2]

n+

2

V1[n]V1[n-1] V1[n+1] V1[n+2]

V2[n]V2[n-1] V2[n+1] V2[n+2]

(input)


you can set one ofG,H, I, J to zero. Try each of the

following cases

(a) V1 as output; F circuit (E = 0)

(b) V1 as output; E circuit (F = 0)

(c) V2 as output; F circuit (E = 0)

(d) V2 as output; E circuit (F = 0)

What is the spread in capacitor values (The ratio of

the largest to the smallest capacitor) in each case?

8. Simulate the magnitude and phase responses of

the first case above in a circuit simulator. See

the handout below on guidelines to simulat-

ing switched capacitor filters in a circuit simulator:

http://www.ee.iitm.ac.in/∼nagendra/E4215/2004/handouts/scfsim.pdf



Topic 13

Appreciating approximations

Approximations are key to understanding anything com-

plicated. Exact expressions, even when possible, may be

too complicated to give any insight to the problem. Ap-

proximating is not the same as being sloppy. On the con-

trary, a greater understanding of the problem is required

to judiciously use approximations than plug in the whole

formula (e.g. see the quadratic eq. example below).

Evaluate the conditions for 1% and 10% accuracy for the

quantities mentioned using the approximations below.

1. You are required to calculate√

1 + x and you ap-

proximate it by 1 + x/2.

2. You are required to solve the quadratic equation

ax2+bx+c and you approximate the roots by−b/a,

−c/b. This works for widely separated real roots.

How widely do they have to be separated (ratio)?

3. You have a two stage amplifier in feedback loop with

loop gain L(s) = A0,loop/(1 + s/p1)(1 + s/p2),

p2 > p1, p1 = ωu,loop/A0,loop and you approximate

it by moving the lower frequency pole to the origin—

i.e. use the transfer function L(s) ≈ (ωu,loop/s)(1+

s/p2) instead. You have to calculate (a) natural fre-

quency ωn, (b) damping factor ζ. Compare the ex-

pressions for the two quantities. Calculate A0,loop to

get the above errors (Assume p2 = 2ωu,loop).

The above are rather simple examples to show how much

you can get away with, if you use judicious approxima-

tions. See the book below for an extensive treatment of

approximation techniques.

Sanjoy Mahajan, Street-Fighting Mathematics: The Art of

Educated Guessing and Opportunistic Problem Solving,

The MIT Press, 2010.

26



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