analog integrated circuit design ee401an/ee5590an · prerequisites: ece 4220 - analog integrated...
TRANSCRIPT
Advanced Analog Integrated Circuit Design
Lecture 1: Introduction
Instructor: Yang (Cindy) Yi
1
Outline
• Course Introduction
• Required Materials
• Course Topics
• Grading
• Introduction to Analog Design
• Brief Self Introduction
2
Course Introduction
Instructor: Dr. Cindy-Yang Yi
Office: 441 Whittemore Hall
Phone: 540-231-7561 (e-mail preferred)
E-Mail: [email protected]
Office Hours: TBD
Meetings will also be available by appointment (e-mail).
GTA: Mr. Chenyuan Zhao [email protected]
Course Website: http://www.yangyi.ece.vt.edu/Teaching/Adv_analog.html and
https://canvas.vt.edu/
Means of Communication
Your VT email will be the official means of communication for this course.
3
Announcements in Canvas
Course Introduction
Prerequisites
Prerequisites: ECE 4220 - Analog Integrated Circuit Design. The material
covered in the Advanced Topics course is of a nature which requires varied
analytical and engineering skills which cannot be associated with any specific
course. A general maturity of the enrolled graduate students in the course is
expected.
Course Objective
• Design, analyze, and optimize analog and mixed signal integrated circuits
(Op Amp and Comparator, A/D and D/A, Voltage References, Integrated
Filter, Phase-locked Loops);
• Simulate and analyze the performance metrics (such as: speed, area,
power and signal integrity) of transistors, interconnects, and circuits;
• Study advanced topics in IC area including neuromorphic electronic circuit
design for brain-inspired computing system, and energy efficient Three
Dimensional (3D) IC design and automation;
• Familiarize CAD tools in the levels of schematic, layout, extraction and
circuit simulation through labs and projects.
4
Required Materials
CMOS: Circuit Design, Layout, and Simulation –
Third Edition by J. Baker, Wiley, 2010.
Design of Analog CMOS Integrated Circuits,
by B. Razavi, McGraw-Hill, 2001
Analog Integrated Circuit Design (2nd edition) by
T. Carusone, D. Johns and K. Martin, Wiley,
2011
Paper and Lecture Notes
Cadence Virtuoso Custom IC Design Tools
5
Course Topics
• CMOS Technology and Design (Review)
• Physical Structure and Fabrication Process of Integrated
Circuits
• Op Amp and Comparator Design
• Data converters : A/D and D/A
• Voltage References
• Integrated Filter Design
• Phase-locked Loops
• High Speed Circuit Timing Analysis and Design Optimization
• Neuromorphic Electronic Circuit Design for Brain-inspired
Computing System.
• Energy Efficient Three Dimensional (3D) IC Design and
Automation
6
Do & Don’t for This Course
• No laptops or Internet appliances can be used during
lectures or exams.
• No late work submission is accepted.
• Regularly being tardy for lectures, reaching late for
lectures, leaving in the middle of lectures, or earlier
from lectures is unacceptable.
• Phones and Class Interruptions: You are not permitted
to use a phone for any purpose during class, and you
must set your phone to be silent before class begins.
• Cheating or plagiarism will result in an automatic “F”
grade in the course (so do your homework and
projects).
7
8
Grading:
Points will be allocated for several different parts of the course.
A letter grade will be assigned based upon the total points
accumulated. The points allocated for different parts of the
course are as listed below:
Exams 30%
Final Project 30%
Homework and Lab Assignments 25%
Pop Up Quizzes 10%
Class Participation 5%
-100%-
Bonus Questions 5 points
Grading policies:
Late homework and lab assignments will not be accepted and
will be assigned a grade of zero.
Examinations:• There will be two examinations. All examinations will be closed
book, closed notes. You are allowed to bring a “cheat sheet”: one A4-sized sheet, one single side.
• NO makeup examinations will be given! If you miss one examination for a reason that has been approved in advance, your total exam score will be the max value of (90% of the highest scores, average of two scores). Missed exams without prior approval will be scored as zeroes.
Homework:• Students may discuss general approaches to solving homework
problems among themselves. The actual solutions that are turned in for grading are expected to be the original work of the individual student. See the section on the Honor Code in this syllabus.
• Homework will be submitted during classes unless specified otherwise. All information that is turned in for grading should be neat, clearly organized, and legible. Work that can not be easily read (in the opinion of instructor or GTA) will receive no credit.
• You are required to STAPLE your assignments
9
10
Pop Up Quizzes:
• Short, unannounced, in-class quizzes will be given.
• The quizzes will be on material covered recently in lecture or
reading assignments. Quizzes will be open book and notes.
• Make-up quizzes will only be given to the students who send me
emails about their class absence notice ahead of the quiz time.
Lab Assignments, Paper Reading and Final Project:
• Lab Assignments focus on using EDA tools in the following levels
– schematic, layout, extraction and circuit simulation through labs.
• Paper Reading/Presentation and Final Project are completed in
groups of up to four students.
• Paper Reading/Presentation and Final Project topics might be
suggested by the student or assigned by the instructor. All will be
presented in class.
Bonus Questions Participation:
• Short, unannounced, in-class questions will be given.
Introduction to Analog Design
• Why should we need to study analog design?▫ Natural signals are analog
▫ Analog circuits are required to amplify and condition the signal for
further processing
▫ Performance of analog circuits often determine whether the chip
works or not
• Examples Sensors
RF transceivers
Microprocessor circuits (PLL, high-speed I/O, OTA)
11
Example: Analog Circuits in Wireless Network
IDFT
P
to
S
CLOCK
DAC
DAC
Low
Pass
Low
Pass
33 MHz
text
cos( )IFt
sin( )IFt
Band
Pass
cos( )RFt
Band
Pass
Channel (Fiber Link/Wireless Connection)
Non-Linear
Power Amplifier
Band
Pass
Band
Pass
cos( )IFt
sin( )IFt
Low
Pass
Low
Pass
CLOCK
ADC
ADC
33 MHzS
to
PDFT
Low Noise
Amplifier
cos( )RFt
12
What Things Would an Analog Engineer
Design?
13
Video: Introduction to
Analog Design
Why Analog? Question: Is analog design more difficult than digital design?
Answer: ? Digital Design ▫ Large noise margin
▫ Trade-off between power and speed (and area) only
• Analog needs multi-dimensional trade-offs between ▫ Power, speed (frequency), gain, precision (drifts),
power supply voltage
• Analog circuits are more sensitive to “Noise and cross-talk”
• Modeling and simulation pose biggest challenge.
14
An Analog designer is a Smart guy who uses Experience
and Intuition to use simulators.
Reference Maxim Note HFDN-27.0 (Rev. 0, 09/03)
Tx +
-
+
-
Rcvpath +
-
+
-
Clean, open, logical 1 & 0 at launch from transmitter
Smeared edges at end of long interconnect.
Logical 1 & 0 can be hard to distinguish at end of long interconnects; (this is often called a “closed eye”)
Fast, sharp, edges at transmitter launch
15
High Speed Circuit Timing Analysis and
Design Optimization
Analog Designers are in Good Demand
16
Analog Designers are in Good Demand
17
Synthesis and Analysis Schematic Entry & Simulation
Layout DesignEvaluation and Testing
18
Analysis vs Synthesis
Circuit
AnalysisProperties
19
Analysis vs. Synthesis
PropertiesSynthesis
Circuit 1
Circuit 2
Circuit 3
20
21
Design Process
for Analog
Integrated
Circuits
22
Cadence Virtuoso
• Cadence's market share exceeds 80 percent in this area, according to market research firm Gartner Dataquest Inc.
• "We're expanding the Virtuoso [product] name to cover the whole platform for full custom, including simulation, capture, integration and silicon analysis," said Estrada.
- EETimeshttp://www.eetasia.com/ART_8800317637_480100_NP_b5ed79b5.HTM?jumpto=view_welcomead_1408937170685
23
Cadence Virtuoso• Design, abstract and visualize the many interdependencies of an analog,
RF, or mixed-signal design to understand and determine their effects on circuit performance.
• Virtuoso Schematic Editor▫ Provides a complete design and constraint composition environment.
• Virtuoso Analog Design Environment▫ Provides a comprehensive array of capabilities for electrical and
statistical analysis, verification, and optimization.
• Virtuoso Layout Suite for Electrically Aware Design▫ Cadence® Virtuoso® Layout Suite enhances design team productivity
and circuit performance for custom ICs.
• Virtuoso Visualization and Analysis▫ A waveform display and analysis tool that efficiently and thoroughly
analyzes the performance.
24
Video: Introduction to Virtuoso
Brief Introduction of the Instructor
• Ph.D. of ECE at Texas A&M University
• Research Intern, IBM
• Research Intern, Freescale Semiconductor Inc.
• Senior R&D Engineer, Intel Corporation
• Member of Technical Staff, Texas Instruments Inc.
• Assistant Professor, University of Kansas
Website:http://www.yangyi.ece.vt.edu/
25
26
• Invited Talks at Industrial Companies:▫ IBM/IBM Research (TJ Watson, Austin)▫ Intel▫ Samsung▫ Qualcomm▫ Global Foundries▫ AMD▫ Freescale▫ Texas Instruments▫ Agilent▫ Nvidia▫ Synopsys
Brief Introduction of the Instructor
• Research Projects▫ Neuromorphic Electronic Circuits Design
and Automation for Brain-Inspired Computing System
▫ High Speed and Low-Power Circuit Design▫ Integrated Circuit Modeling , Simulation,
Design▫ Advanced CMOS Device Construction and
Process Integration
27
Brief Introduction of the Instructor
http://www.yangyi.ece.vt.edu/
http://www.mics.ece.vt.edu/
Brief Introduction of Our Teaching Assistant
• Mr. Chenyuan Zhao
• Email: [email protected]
• Office: 477 Whittemore Hall
28
How about you?
• Your name, major
• When you plan to graduate?
• What kind of job you plan to
apply after graduation?
• Why you take the course?
• What is your background in
electronic circuits (courses
& projects)?
• What do you want to learn
from this course?
29
30
Before next class
• Next topic:
“Mommy and Daddy, what is CMOS Technology?”
• Reading assignment:
CMOS: Circuit Design, Layout, and Simulation
Chapter 1-6
Design of Analog CMOS Integrated Circuits
Chapter 1-2