analog devices welcomes hittite microwave corporationnov 01, 2016 · for price delivery and to...
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Analog Devices Welcomes Hittite Microwave Corporation
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HMC833* Product Page Quick LinksLast Content Update: 11/01/2016
Comparable PartsView a parametric search of comparable parts
Evaluation Kits• HMC833LP6GE Evaluation Board
DocumentationApplication Notes• Frequency Hopping with Hittite PLLVCOs Application
Note• PLL & PLLVCO Serial Programming Interface Mode
Selection Application Note• Power-Up & Brown-Out Design Considerations for RF
PLL+VCO Products Application Note• Wideband RF PLL+VCO and Clock Generation Products
FAQsData Sheet• HMC833 Data Sheet
Tools and Simulations• ADIsimPLL™
Reference MaterialsQuality Documentation• HMC Legacy PCN: LP6CE and LP6GE QFN - Alternate
assembly source• Package/Assembly Qualification Test Report: LP6, LP6C,
LP6G (QTR: 2014-00368)• Semiconductor Qualification Test Report: BiCMOS-A
(QTR: 2013-00235)Technical Articles• Low Cost PLL with Integrated VCO Enables Compact LO
Solutions
Design Resources• HMC833 Material Declaration• PCN-PDN Information• Quality And Reliability• Symbols and Footprints
DiscussionsView all HMC833 EngineerZone Discussions
Sample and BuyVisit the product page to see pricing options
Technical SupportSubmit a technical question or find your regional support number
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HMC833LP6GEv03.714
FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Functional Diagram
Features• RFBandwidth:25-6000MHz
• MaximumPhaseDetectorRate100MHz
• UltraLowPhaseNoise-110dBc/HzinBandTyp.
• FigureofMerit(FOM)-227dBc/Hz
•
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HMC833LP6GEv03.714
FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
General DescriptionTheHMC833LP6GEisalownoise,wideband,Fractional-NPhase-Locked-Loop(PLL)thatfeaturesanintegratedVoltageControlledOscillator(VCO)withafundamentalfrequencyof1500MHz-3000MHz,andanintegratedVCOOutputDivider(divideby1/2/4/6.../60/62)anddoubler,thattogetherallowtheHMC833LP6GEtogeneratefrequenciesfrom25MHzto6000MHz.TheintegratedPhaseDetector(PD)anddelta-sigmamodulator,capableofoperatingatupto100MHz,permitwiderloop-bandwidthswithexcellentspectralperformance.
TheHMC833LP6GEfeaturesindustryleadingphasenoiseandspuriousperformance,acrossallfrequencies,thatenable it tominimizeblockereffects,andimprovereceiversensitivityandtransmitterspectralpurity.Thesuperiornoisefloor(<-170dBc/Hz)makestheHMC833LP6GEanidealsourceforavarietyofapplications-suchas;LOforRFmixers,aclocksourceforhigh-frequencydata-converters,oratunablereferencesourceforultra-lowspuriousapplications.
AdditionalfeaturesoftheHMC833LP6GEincludeRFoutputpowercontrolfrom0to9dB(3dBsteps),outputMutefunction,andadelta-sigmamodulatorExactFrequencyModewhichenablesuserstogenerateoutputfrequencieswith0Hzfrequencyerror.
Parameter Condition Min. Typ. Max. Units
RF Output Characteristics
OutputFrequency 25 6000 MHz
VCOFrequencyatPLLInput 1500 3000 MHz
RFOutputFrequencyatfVCO 1500 3000 MHz
Output Power
RFOutputPoweratffundamental=2000MHz
AcrossAllFrequenciesseeFigure9BroadbandMatchedInternally
[1]1.5 3 4.5 dBm
OutputPowerControlRange 3 9 dB
OutputPowerControlStep 0.75 3 dB
RFOutputPoweratfdoubler=3000MHz
AcrossAllFrequenciesseeFigure9BroadbandMatchedInternally
[1]-3.5 -2.5 -1 dBm
RFOutputPoweratfdoubler=6000MHz
AcrossAllFrequenciesseeFigure9BroadbandMatchedInternally
[1]-11 -7 -5 dBm
Harmonics for Fundamental Mode
foModeat2GHz 2nd/3rd/4th -20/-29/-45 dBc
fo/2Modeat2GHz/2=1GHz 2nd/3rd/4th -23/-15/-35 dBc
fo/30Modeat3GHz/30=100MHz 2nd/3rd/4th -25/-10/-33 dBc
fo/62Modeat1550MHz/62=25MHz 2nd/3rd/4th -17/-8/-21 dBc
Harmonics in Doubler Mode
2foModeat4GHz ½/3rd/4th/5th -7/-23/-15/-40 -4/-15/-7/-28 dBc
VCO Output Divider
VCORFDividerRange 1,2,4,6,8,...,62 1 62
Electrical SpecificationsVPPCP, VDDLS, VCC1, VCC2 = 5 V; RVDD, AVDD, DVDD3V, VCCPD, VCCHF, VCCPS = 3.3 V Min and Max Specified across Temp -40 °C to 85 °C
[1]Measuredsingle-ended.Additional3dBpossiblewithdifferentialoutputs.
[2]Measuredwith100Ωexternaltermination.See“ReferenceInputStage”sectionformoredetails.
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THMC833LP6GE
v03.714
FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Parameter Condition Min. Typ. Max. Units
PLL RF Divider Characteristics
19-BitN-DividerRange(Integer) Max=219-1 16 524,287
19-BitN-DividerRange(Fractional)Fractionalnominaldivideratiovaries(-3/+4)dynamically
max20 524,283
REF Input Characteristics
MaxRefInputFrequency 350 MHz
RefInputVoltage ACCoupled[2] 1 2 3.3 Vp-p
RefInputCapacitance 5 pF
14-BitR-DividerRange 1 16,383
Phase Detector (PD) [3]
PDFrequencyFractionalModeB [4] DC 100 MHz
PDFrequencyFractionalModeA(andRegis-ter6[17:16]=11)
DC 80 MHz
PDFrequencyIntegerMode DC 125 MHz
Charge Pump
OutputCurrent 0.02 2.54 mA
ChargePumpGainStepSize 20 µA
PD/ChargePumpSSBPhaseNoise 50MHzRef,InputReferred
1kHz -143 dBc/Hz
10kHz Add1dBforFractional -150 dBc/Hz
100kHz Add3dBforFractional -153 dBc/Hz
Logic Inputs
Vsw 40 50 60 %DVDD
Logic Outputs
VOHOutputHighVoltage DVDD V
VOLOutputLowVoltage 0 V
OutputImpedance 100 200 Ω
MaximumLoadCurrent 1.5 mA
Power Supply Voltages
3.3VSuppliesAVDD,VCCHF,VCCPS,VCCPD,RVDD,DVDD
3.0 3.3 3.5 V
5VSupplies VPPCP,VDDLS,VCC1,VCC2 4.8 5 5.2 V
Power Supply Currents
+5VAnalogChargePump VPPCP,VDDCP 8 mA
+5VVCOCoreandVCOBufferfo/1ModeVCC2 105 mA
fo/NModeVCC2 80 mA
+5VVCODividerandRF/PLLBufferfo/1ModeVCC1 25 mA
fo/NModeVCC1 80 100 mA
Electrical Specifications (Continued)
[3]Slewrateofgreaterorequalto0.5ns/Visrecommended,see“ReferenceInputStage”sectionformoredetails.Frequencyisguaranteedacrossprocessvoltageandtemperaturefrom-40°Cto85°C.[4]ThismaximumphasedetectorfrequencycanonlybeachievediftheminimumNvalueisrespected.eg.InthecaseoffractionalBmode,themaximumPFDrate=fvco/20or100MHz,whicheverisless.
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HMC833LP6GEv03.714
FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Electrical Specifications (Continued)Parameter Condition Min. Typ. Max. Units
+3.3VAVDD,VCCHF,VCCPS,VCCPD,RVDD,DVDD3V
52 mA
PowerDown-CrystalOffReg01h=0,
CrystalNotClocked10 µA
PowerDown-CrystalOn,100MHzReg01h=0,
CrystalClocked100MHz5 mA
Power on Reset
TypicalResetVoltageonDVDD 700 mV
MinDVDDVoltageforNoReset 1.5 V
PoweronResetDelay 250 µs
VCO Open Loop Phase Noise at fo @ 2 GHz
10kHzOffset -86 dBc/Hz
100kHzOffset -116 dBc/Hz
1MHzOffset -141 dBc/Hz
10MHzOffset -162 dBc/Hz
100MHzOffset -171 dBc/Hz
VCO Open Loop Phase Noise at fo @ 2 GHz/2 = 1 GHz
10kHzOffset -92 dBc/Hz
100kHzOffset -122 dBc/Hz
1MHzOffset -147 dBc/Hz
10MHzOffset -165 dBc/Hz
100MHzOffset -165 dBc/Hz
VCO Open Loop Phase Noise at fo @3 GHz/30 = 100 MHz
10kHzOffset -112 dBc/Hz
100kHzOffset -142 dBc/Hz
1MHzOffset -165 dBc/Hz
10MHzOffset -168 dBc/Hz
100MHzOffset -171 dBc/Hz
VCO Open Loop Phase Noise at 2fo @ 4 GHz
10kHzOffset -80 dBc/Hz
100kHzOffset -110 dBc/Hz
1MHzOffset -135 dBc/Hz
10MHzOffset -155 dBc/Hz
100MHzOffset -162 dBc/Hz
VCO Open Loop Phase Noise at 2fo @ 6 GHz
10kHzOffset -75 dBc/Hz
100kHzOffset -105 dBc/Hz
1MHzOffset -131 dBc/Hz
10MHzOffset -152 dBc/Hz
100MHzOffset -162 dBc/Hz
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THMC833LP6GE
v03.714
FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Parameter Condition Min. Typ. Max. Units
Figure of Merit
FloorIntegerMode Normalizedto1Hz -230 dBc/Hz
FloorFractionalMode Normalizedto1Hz -227 dBc/Hz
Flicker(BothModes) Normalizedto1Hz -268 dBc/Hz
VCO Characteristics
VCOTuningSensitivityat2800MHz Measuredat2.5V 13.3 MHz/V
VCOTuningSensitivityat2400MHz Measuredat2.5V 13.8 MHz/V
VCOTuningSensitivityat2000MHz Measuredat2.5V 13.6 MHz/V
VCOTuningSensitivityat1600MHz Measuredat2.5V 12.1 MHz/V
VCOSupplyPushing Measuredat2.5V 2 MHz/V
Electrical Specifications (Continued)
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HMC833LP6GEv03.714
FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Figure 1. Typical Closed Loop Integer Phase Noise[“LoopFilterConfigurationTable”]
Figure 2. Typical Closed Loop Fractional Phase Noise[“LoopFilterConfigurationTable”]
Figure 3. Free Running Phase NoiseFigure 4. Free Running VCO Phase Noise vs. Temperature
Figure 5. Typical VCO Sensitivity at Fo
-220
-200
-180
-160
-140
-120
-100
-80
1 10 100 1000 10000 100000
fout 3800 MHz,Lopp BW 74KHz,rms jitter 108fsecfout 3800MHz,Loop Filter 90KHz,rms jitter 87fsecfout 5600MHz,Loop BW 74KHz,rms jitter 188fsec
fout 1600MHz,Loop BW 74KHz,rms jitter 127fsecfout 1600MHz,Loop BW 90KHz, rms jitter 97fsec
fout 5600MHz,Loop BW 90KHz,rms jitter 118fsec
OFFSET(KHz)
PH
AS
E N
OIS
E(d
Bc/
Hz)
-220
-200
-180
-160
-140
-120
-100
-80
1 10 100 1000 10000 100000
fout 3805 MHz,Loop BW 74KHz,rms jitter 123fsecfout 3805MHz,Loop BW 90KHz,rms jitter 104fsecfout 5605MHz,Loop BW 74KHz,rms jitter 202fsecfout 5605MHz,Loop BW 90KHz,rms jitter 128fsecfout 1605MHz, Loop BW 74KHz,rms jitter 130fsecfout 1605MHz, Loop BW 90KHz, rms jitter 123fsec
OFFSET (kHz)P
HA
SE
NO
ISE
(dB
c)
-180
-160
-140
-120
-100
-80
-60
-40
103
104
105
106
107
108
5536 MHz4732 MHz3885 MHz3058 MHz
PH
AS
E N
OIS
E (
dB
c/H
z)
OFFSET (Hz)
-180
-170
-160
-150
-140
-130
-120
-110
-100
10 100 1000 10000
27C-40C85C
PH
AS
E N
OIS
E (d
Bc/
Hz)
FREQUENCY (MHz)
100 MHz Offset
1 MHz Offset
100 kHz Offset
0
1
2
3
4
5
TU
NE
VO
LT
AG
E A
FT
ER
CA
LIB
RA
TIO
N (
V)
VCO FREQUENCY(MHz)
fmin fmax
1500 30000
10
20
30
40
50
60
0 1 2 3 4 5
2817 MHz at 2.5V, Tuning Cap 152418 MHz at 2.5V, Tuning Cap 151996 MHz at 2.5V, Tuning Cap 151575 MHz at 2.5V, Tuning Cap 15
TUNING VOLTAGE (V)
kV
CO
(M
Hz/V
)
Typical Performance Characteristics
Figure 6. Typical Tuning Voltage After Calibration at Fo
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THMC833LP6GE
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FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Figure 7. Integrated RMS Jitter[1]
[1]RMSJitterdataismeasuredinfractionalmodewith100kHzLoopbandwidthusing50MHzreferencefrequencyfrom1kHzto20MHzintegrationbandwidth.
[2]TheoutputpowerfromFrequency25MHzto3000MHzisusingfundamentalConfigurationwithGainSetting01,outputpowerfromFrequency3000MHzto6000MHzisusingdoublerConfigurationwithGainSetting11
[3]Measuredfroma50Ωsourcewitha100Ωexternalresistortermination.See“ReferenceInputStage”sectionformoredetails.FullFOMperformanceuptomaximum3.3Vppinputvoltage.
Figure 8. Figure of Merit
Figure 9. Typical Output Power vs. Temperature [2]
Figure 10. Output Power vs Gain Control Setting (VCO_Reg02h[8]=1. See VCO_Reg02h)
Figure 11. Reference Input Sensitivity, Square Wave, 50 Ω[3]
Figure 12. Reference Input Sensitivity Sinusoidal Wave, 50 Ω[3]
50
100
150
200
250
300
10 100 1000 10000
-40C27C85C
JIT
TE
R (
fs)
OUTPUT FREQUENCY (MHz)
-240
-230
-220
-210
-200
102
103
104
105
106
NO
RM
AL
IZE
D P
HA
SE
NO
ISE
(d
Bc/H
z)
FREQUENCY OFFSET (Hz)
FOM FloorFOM 1/f Noise
Typ FOM vs Offset
-12
-10
-8
-6
-4
-2
0
2
0 1000 2000 3000 4000 5000 6000
27 C-40 C85 C
OU
TP
UT
PO
WE
R (
dB
m)
OUTPUT FREQUENCY (MHz)
-234
-232
-230
-228
-226
-224
-222
-220
-15 -12 -9 -6 -3 0 3
14 MHz Square Wave25 MHz Square Wave50 MHz Square Wave100 MHz Square Wave
FO
M
REFERENCE POWER (dBm)
-235
-230
-225
-220
-215
-210
-205
-200
-20 -15 -10 -5 0 5
14 MHz sin25 MHz sin50 MHz sin100 MHz sin
REFERENCE POWER (dBm)
FO
M (
dBc/
Hz)
-10
-5
0
5
10
0 1000 2000 3000 4000 5000 6000
Gain Setting 11Gain Setting 10Gain Setting 01Gain Setting 00
OU
TPU
T P
OW
ER
(dB
m)
OUTPUT FREQUENCY (MHz)
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HMC833LP6GEv03.714
FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Figure 13. Integer Boundary Spur at 5900.8 MHz[4]
Figure 14. Integer Boundary Spur at 3900.4 MHz [5]
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
1 10 100 1000 10000 100000
PH
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dB
c/H
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OFFSET (kHz)
[4]FractionalModeB,50MHzPDfrequency,74kHzLoopFilterBW[5]FractionalModeinModeB,IntegerBoundaryat3800MHz[7]ExactFrequencyMode,REFin=100MHz,PD=50MHz,OutputDivider1Selected,LoopFilterbandwidth=100kHz,ChannelSpacing=100kHz[8]ExactFrequencyMode,ChannelSpacing=100kHz,FractionalModeBRFout=2591MHz,REFin=100MHz,PDfrequency=50MHz,Output
Divider1selected,LoopFilterbandwidth=120kHz,[9]FractionalModeBRFout=2591MHz,REFin=100MHz,PDfrequency=50MHz,OutputDivider1selected,LoopFilterbandwidth=120kHz.
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
1 10 100 1000 10000 100000
PH
AS
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OIS
E (
dB
c/H
z)
OFFSET (kHz)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
1 10 100 1000 10000 100000
PH
AS
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OIS
E (
dB
c/H
z)
OFFSET (kHz)
Figure 15. Fractional-N Exact Frequency Mode ON Performance at 2113.5 MHz[7]
Figure 16. Fractional-N Exact Frequency Mode ON Performance at 2591 MHz[8]
Figure 17. Fractional-N Exact Frequency Mode OFF Performance at 2591 MHz[9]
-180
-160
-140
-120
-100
-80
-60
1000 10000 100000 1000000 10000000 100000000
PH
AS
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OIS
E (
dB
c/H
z)
OFFSET (kHz)
-180
-160
-140
-120
-100
-80
-60
1 10 100 1000 10000 100000
PH
AS
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OIS
E (d
Bc/
Hz)
OFFSET (kHz)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
0.1 1 10 100 1000 10000 100000
PH
AS
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OIS
E (
dB
c/H
z)
OFFSET (kHz)
Figure 18. Worst Spur, Fixed 50 MHz Reference, Output Freq. = 2000.1 MHz[10]
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THMC833LP6GE
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FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
LoopFilterBW(kHz)
C1(pF)
C2(nF)
C3(pF)
C4(pF)
R2(kΩ)
R3(kΩ)
R4(kΩ)
LoopFilterDesign
74 150 27 220 220 0.82 1 1
90 270 3.9 56 56 1.2 1 1
200 56 1.8 N/A N/A 2.2 0 0
Loop Filter Configuration Table
Figure 19. RF Output Return Loss Figure 20. Worst Spur, Tunable Reference, Output Frequency = 2000.1 MHz [10]
[10]CapabilityofHMC830LP6GEtogeneratelowfrequencies(aslowas25MHz),enablestheHMC830LP6GEtobeusedasatunablereference
sourceintotheHMC833LP6GE,whichmaximizesspurperformanceoftheHMC833LP6GE.Pleasesee“HMC833LP6GEApplication
Information”formoreinformation.[11]Thegraphisgeneratedbyobserving,andplotting,themagnitudeofonlytheworstspur(largestmagnitude),atanyoffset,ateachoutput
frequency,whileusingafixed50MHzreferenceandatunablereferencetunedto47.5MHz.See“HMC833LP6GEApplicationInformation”formoredetails.
[12]PhasenoiseperformanceoftheHMC833LP6GEwhenusedasatunablereferencesource.HMC833LP6GEisoperatingat6GHz/30,6GHz/54forthe100MHz,55.55MHzcurvesrespectivelyLoopFilter56pF//(2.2kohm+1.8nF)IntegerMode100MHzWenzeloscillatorwithRdiv=250MHzcomparisonfrequency.
Figure 21. Low Frequency Performance [11]
-170
-160
-150
-140
-130
-120
0.1 1 10 100 1000 10000 100000
Carrier Frequency = 25 MHzCarrier Frequency = 55.55 MHzCarrier Frequency = 100 MHz
PH
AS
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OIS
E (
dB
c/H
z)
OFFSET (kHz)
Figure 22. Low Frequency Performance [12]
-120
-110
-100
-90
-80
-70
-60
-50
2GHz +1kHz 2GHz +10kHz 2GHz +100kHz 2GHz +1000kHz 2GHz +10000kHz
Fixed 50 MHz ReferenceTunable Reference
WO
RS
T S
PU
R (
dB
c)
OUTPUT FREQUENCY
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
0.1 1 10 100 1000 10000 100000
PH
AS
E N
OIS
E (
dB
c/H
z)
OFFSET (kHz)
-35
-30
-25
-20
-15
-10
-5
0
25 100 1000 10000
RE
TU
RN
LO
SS
(dB
)
FREQUENCY (MHz)
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HMC833LP6GEv03.714
FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Pin DescriptionsPinNumber Function Description
1 AVDD DCPowerSupplyforanalogcircuitry.
2,5,6,8,9,11-14,18-22,24,26,29,34,37,38
N/CThepinsarenotconnectedinternally;however,alldatashownhereinwasmeasuredwiththesepinsconnectedtoRF/DCgroundexternally.
3 VPPCP PowerSupplyforchargepumpanalogsection
4 CP ChargePumpOutput
7 VDDLS PowerSupplyforthechargepumpdigitalsection
10 RVDD ReferenceSupply
15 XREFP ReferenceOscillatorInput
16 DVDD3V DCPowerSupplyforDigital(CMOS)Circuitry
17 CEN ChipEnable.Connecttologichighfornormaloperation.
23 VTUNE VCOVaractor.TuningPortInput.
25 VCC2 VCOAnalogSupply2
27 VCC1 VCOAnalogSupply1
28 RF_OUT RFOutput
30 SEN PLLSerialPortEnable(CMOS)LogicInput
31 SDI PLLSerialPortData(CMOS)LogicInput
32 SCK PLLSerialPortClock(CMOS)LogicInput
33 LD_SDO LockDetect,orSerialData,orGeneralPurpose(CMOS)LogicOutput(GPO)
35 VCCHF DCPowerSupplyforAnalogCircuitry
36 VCCPS DCPowerSupplyforAnalogPrescaler
39 VCCPD DCPowerSupplyforPhaseDetector
40 BIAS
Externalbypassdecouplingforprecisionbiascircuits.Note:1.920V±20mVreferencevoltage(BIAS)isgeneratedinternallyandcannot
driveanexternalload.Mustbemeasuredwith10GΩmetersuchasAgilent34410A,normal10MΩDVMwillreaderroneously.
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FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Outline Drawing
NOTES:
1.PACKAGEBODYMATERIAL:LOWSTRESSINJECTIONMOLDEDPLASTICSILICAANDSILICONIMPREGNATED.
2.LEADANDGROUNDPADDLEMATERIAL:COPPERALLOY.
3.LEADANDGROUNDPADDLEPLATING:100%MATTETIN.
4.DIMENSIONSAREININCHES[MILLIMETERS].
5.LEADSPACINGTOLERANCEISNON-CUMULATIVE.
6.PADBURRLENGTHSHALLBE0.15mmMAX.PADBURRHEIGHTSHALLBE0.25mmMAX.
7.PACKAGEWARPSHALLNOTEXCEED0.05mm.
8.ALLGROUNDLEADSANDGROUNDPADDLEMUSTBESOLDEREDTOPCBRFGROUND.
9.REFERTOHITTITEAPPLICATIONNOTEFORSUGGESTEDPCBLANDPATTERN.
Absolute Maximum RatingsAVDD,RVDD,DVDD3V,VCCPD,VCCHF,VCCPS
-0.3Vto+3.6V
VPPCP,VDDLS,VCC1,VCC2 -0.3Vto+5.5V
OperatingTemperature -40°Cto+85°C
StorageTemperature -65°Cto150°C
MaximumJunctionTemperature 150°C
ThermalResistance(RTH)(junctiontogroundpaddle)
9°C/W
ReflowSoldering
PeakTemperature 260°C
TimeatPeakTemperature 40sec
ESDSensitivity(HBM) Class1B
StressesabovethoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thisisastressratingonly;functionaloperationofthedeviceat theseoranyotherconditionsabove thoseindicatedintheoperationalsectionofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditions for extended periods may affect devicereliability.
Parameter Condition Min. Typ. Max. Units.
Temperature
JunctionTemperature 125 °C
AmbientTemperature -40 85 °C
Supply Voltage
AVDD,RVDD,DVDD3V,VCCPD,VCCHF,VCCPS 3.0 3.3 3.5 V
VPPCP 4.8 5.0 5.2 V
Recommended Operating Conditions
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FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
PartNumber PackageBodyMaterial LeadFinish MSLRating PackageMarking[1]
HMC833LP6GE RoHS-compliantLowStressInjectionMoldedPlastic 100%matteSn MSL1H833XXXX
[1]4-DigitlotnumberXXXX
Package Information
Evaluation PCB Schematic
Thecircuitboardused in theapplicationshoulduseRFcircuitdesign techniques.Signal linesshouldhave50Ohmimpedancewhilethepackagegroundleadsandexposedpaddleshouldbeconnecteddirectlytothegroundplanesimilar to thatshown.Asufficientnumberofviaholesshouldbeusedtoconnect the topandbottomgroundplanes.TheevaluationcircuitboardshownisavailablefromHittiteuponrequest.
To view this EvaluationPCBSchematic please visit www.hittite.com and choose HMC833LP6GE from the “Search by Part Number” pull down menu to view the product splash page.
Evaluation PCB
Item Contents PartNumber
EvaluationKit
HMC833LP6GEEvaluationPCBUSBInterfaceBoard6’USBAMaletoUSBBFemaleCableCDROM(ContainsUserManual,EvaluationPCBSchematic,EvaluationSoftware,HittitePLLDesignSoftware)
EKIT01-HMC833LP6GE
Evaluation Order Information
http://hittite.com/content/documents/eval_pcb_schematic/hmc833lp6ge_eval_pcb_schematic.pdfhttp://www.hittite.com
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FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
HMC833LP6GE Application InformationLargebandwidth(25MHzto6000MHz),industryleadingphasenoiseandspuriousperformance,excellentnoisefloor(
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FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Output gain setting for Optimal Power FlatnessTheoutputoftheHMC833LP6GEismatchedto50Ωacrossalloutputfrequenciesfrom25MHzto6000MHz.Asa result of thewideband50Ωmatch, theoutput power of theHMC833LP6GEdecreaseswith increasingoutputfrequency,asshowninFigure9.Ifrequired,itispossibletoadjusttheoutputstagegainsettingoftheHMC833LP6GE(“VCO_Reg02hBiases”[7:6])atvariousoperatingfrequenciesinordertoachieveamoreconstantoutputpowerlevelacrossthefrequencyoperatingrangeoftheHMC833LP6GE.AnexampleisshowninFigure26.
Figure 26.
-20
-15
-10
-5
0
5
0 1000 2000 3000 4000 5000 6000
OU
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UT
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R (
dB
m)
OUTPUT FREQUENCY (MHz)
Gain = 0 dB
Gain = 9 dBGain = 6 dB
Divider outputstage gain = 3 dB(VCO_Reg02h[8] = 1)
Reducing the output power variation of HMC833LP6GE across frequency by adjusting output stage gain
control. IfahigheroutputpowerthanthatshowninFigure26isrequired,itispossibletofollowtheHMC833LP6GEoutputstagewithasimpleamplifiersuchasHMC311SC70E inorder toachieveaconstantandhighoutputpower levelacrosstheentireoperatingrangeoftheHMC833LP6GE.
http://hittite.com/content/documents/data_sheet/hmc311sc70.pdf
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FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
1.0 Theory of OperationHMC833LP6GEistargetedforultralowphasenoiseapplicationsandhasbeendesignedwithverylownoisereferencepath,phasedetectorandchargepump.
TheHMC833LP6GEconsistsofthefollowingfunctionalblocks:
1.ReferencePathInputBuffersand’R’Divider2.VCOPathInputBufferandMulti-Modulus’N’Divider3.Δ∑FractionalModulator4.PhaseDetector5.ChargePump6.SerialPortwithReadWriteCapability7.GeneralPurposeOutput(GPO)Port8.PowerOnResetCircuit9.VCOSubsystem10.Built-InSelfTestFeatures
1.1 VCO SubsystemTheHMC833LP6GEcontainsaVCOsubsystemthatcanbeconfiguredtooperatein:• Fundamentalfrequency(fo)mode(1500MHzto3000MHz).• DividebyN(fo/N),whereN=1,2,4,6,8...58,60,62mode(25MHzto1500MHz).• Doubler(2fo)mode(3000MHzto6000MHz).AllmodesareVCOregisterprogrammableasshowninFigure27.OneloopfilterdesigncanbeusedfortheentirefrequencyofoperationoftheHMC833LP6GE.
Figure 27. PLL and VCO Subsystems
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FRACTIONAL-N PLL WITH INTEGRATED VCO25 - 6000 MHz
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
1.2 VCO Calibration
1.2.1 VCO Auto-Calibration (AutoCal)HMC833LP6GEusesasteptunedtypeVCO.AsimplifiedsteptunedVCOisshowninFigure28.AsteptunedVCOisaVCOwithadigitallyselectablecapacitorbankallowingthenominalcenterfrequencyoftheVCOtobeadjustedor‘stepped’byswitchingin/outVCOtankcapacitors.AmoredetailedviewofatypicalVCOsubsystemconfigurationisshowninFigure29.AsteptunedVCOallowstheusertocentertheVCOontherequiredoutputfrequencywhilekeepingthevaractortuningvoltageoptimizednearthemid-voltagetuningpointoftheHMC833LP6GE’schargepump.ThisenablesthePLLchargepumptotunetheVCOoverthefullrangeofoperationwithbothalowtuningvoltageandalowtuningsensitivity(kvco).
The VCO switches are normally controlled automatically by the HMC833LP6GE using theAuto-Calibration feature. TheAuto-Calibration feature is implemented in the internal statemachine. ItmanagestheselectionoftheVCOsub-band(capacitorselection)whenanewfrequencyisprogrammed.TheVCOswitchesmayalsobecontrolleddirectlyvia registerReg05h for testingor forotherspecialpurposeoperation.OthercontrolbitsspecifictotheVCOarealsosentviaReg05h.
Figure 28. Simplified Step Tuned VCO
Figure 29. HMC833LP6GE PLL and VCO SubsystemsTouseastep tunedVCOinaclosed loop, theVCOmustbecalibratedsuch that theHMC833LP6GEknowswhichswitchpositionontheVCOisoptimumforthedesiredoutputfrequency.TheHMC833LP6GEsupportsAuto-Calibration (AutoCal)of thestep tunedVCO.TheAutoCalfixes theVCOtuningvoltageat theoptimummid-pointof thechargepumpoutput, thenmeasures the free runningVCO frequencywhilesearching for thesettingwhich results in the free runningoutput frequency that isclosest to thedesired phase locked frequency. This procedure results in a phase locked oscillator that locks over
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
averynarrowvoltage rangeon thevaractor.A typical tuningcurve forastep tunedVCO isshown inFigure30.Notehowthetuningvoltagestaysinanarrowrangeoverawiderangeofoutputfrequencies.
0
1
2
3
4
5
920 960 1000 1040 1080 1120 1160
CALIBRATION FREQUENCY (MHz)
TU
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VO
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AF
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R C
ALI
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(V
)
50MHz PFD, 500kHz Tuning Steps, +25C256 Count Calibration ,195kHz Resolution31usec Total Cal Time
01531
Figure 30. A Typical 5-Bit 32 Switch VCO Tuning Voltage After CalibrationThecalibrationisnormallyrunautomaticallyonceforeverychangeoffrequency.ThisensuresoptimumselectionofVCOswitchsettingsvs.timeandtemperature.TheuserdoesnotnormallyhavetobeconcernedaboutwhichswitchsettingisusedforagivenfrequencyasthisishandledbytheAutoCalroutine.TheaccuracyrequiredinthecalibrationaffectstheamountoftimerequiredtotunetheVCO.ThecalibrationroutinesearchesforthebeststepsettingthatlockstheVCOatthecurrentprogrammedfrequency,andensuresthattheVCOwillstaylockedandperformwelloverit’sfulltemperaturerangewithoutadditionalcalibration,regardlessofthetemperaturethattheVCOwascalibratedat.
Auto-CalibrationcanalsobedisabledallowingmanualVCOtuning.Refertosection1.2.2foradescriptionofmanualtuning
1.2.1.1 AutoCal Use of Reg05hAutoCal transfers switch control data to the VCO subsystem via Reg 05h. The address of the VCOsubsysteminReg05hisnotalteredbytheAutoCalroutine.TheaddressandIDoftheVCOsubsysteminReg05hmustbesettothecorrectvaluebeforeAutoCalisexecuted.Formoreinformationseesection1.19.
1.2.1.2 Auto-reLock on Lock Detect FailureIt is possible by settingReg 07h[13] to have the VCO subsystem automatically re-run the calibrationroutineandre-lockitselfifLockDetectindicatesanunlockedconditionforanyreason.Withthisoptionthesystemwillattempttore-Lockonlyonce.Auto-reLockisrecommended.
1.2.2 Manual VCO Calibration for Fast Frequency HoppingIfitisdesirabletoswitchfrequenciesveryquicklyitispossibletoeliminatetheAutoCaltimebycalibratingtheVCOinadvanceandstoringtheswitchnumbervsfrequencyinformationinthehost.ThiscanbedonebyinitiallylockingthePLLwithIntegratedVCOoneachdesiredfrequencyusingAutoCal,thenreading,andstoringtheVCOswitchsettingsselected.TheVCOswitchsettingsareavailableinReg10h[7:0]aftereveryAutoCaloperation.ThehostmustthenprogramtheVCOswitchsettingsdirectlywhenchangingfrequencies.ManualwritestotheVCOswitchesareexecutedimmediatelyasarewritestotheintegerandfractionalregisterswhenAutoCalisdisabled.HencefrequencychangeswithmanualcontrolandAutoCaldisabled,requiresaminimumoftwoserialporttransferstothePLL,oncetosettheVCOswitches,andoncetosetthePLLfrequency.
IfAutoCalisdisabledReg0Ah[11]=1,theVCOwillupdateitsregisterswiththevaluewrittenviaReg05himmediately.TheVCOinternaltransferrequires16VSCKclockcyclesafterthecompletionofawriteto
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Reg05h.VSCKandtheAutoCalcontrollerclockareequaltotheinputreferencedividedby0,4,16or32ascontrolledbyReg0Ah[14:13].
1.2.2.1 Registers required for Frequency Changes in Fractional ModeAlargechangeoffrequency,infractionalmode(Reg06h[11]=1),mayrequireMainSerialPortwritesto:
1. theintegerregisterintg,Reg03h (only required if the integer part changes)
2.theVCOSPIregister,Reg05h
• requiredformanualcontrolofVCOifReg0Ah[11]=1 (AutoCal disabled)
• requiredtochangetheRFDividervalueifneeded(“VCO_Reg02hBiases”)
• requiredtoturnon/offthedoublermodeifneeded(VCO_Reg03h[0])
3.thefractionalregister,Reg04h.ThefractionalregisterwritetriggersAutoCalifReg0Ah[11]=0,andisloadedintothemodulatorautomaticallyafterAutoCalruns.IfAutoCalisdisabled,Reg0Ah[11]=1,thefractionalfrequencychangeisloadedintothemodulatorimmediatelywhentheregisteriswrittenwithnoadjustmenttotheVCO.
Smallstepsinfrequencyinfractionalmode,withAutoCalenabled(Reg0Ah[11]=0),usuallyonlyrequireasinglewritetothefractionalregister.Worstcase,5MainSerialPorttransferstotheHMC833LP6GEcouldberequiredtochangefrequenciesinfractionalmode.Ifthefrequencystepissmallandtheintegerpartofthefrequencydoesnotchange,thentheintegerregisterisnotchanged.Inallcases,infractionalmode,itisnecessarytowritetothefractionalregisterReg04hforfrequencychanges.
1.2.2.2 Registers Required for Frequency Changes in Integer ModeAchangeoffrequency,inintegermode(Reg06h[11]=0),requiresMainSerialPortwritesto:
1.VCOSPIregister,Reg05h
• requiredformanualcontrolofVCOifReg0Ah[11]=1 (AutoCal disabled)
• requiredtochangetheRFDividervalueifneeded(“VCO_Reg02hBiases”)
• requiredtoturnon/offthedoublermodeifneeded(VCO_Reg03h[0])
2.theintegerregisterReg03h.
• Inintegermode,anintegerregisterwritetriggersAutoCalifReg0Ah[11]=0,andisloadedintotheprescalerautomaticallyafterAutoCalruns.IfAutoCalisdisabled,Reg0Ah[11]=1,theintegerfrequency change is loaded into theprescaler immediatelywhenwrittenwith noadjustmenttotheVCO.NormallychangestotheintegerregistercauselargestepsintheVCOfrequency,hencetheVCOswitchsettingsmustbeadjusted.AutoCalenabledistherecommendedmethodforintegermodefrequencychanges.IfAutoCalisdisabled(Reg0Ah[11]=1),aprioriknowledgeof the correctVCOswitch settingand the correspondingadjustment to theVCO is requiredbeforeexecutingtheintegerfrequencychange.
1.2.3 VCO AutoCal on Frequency ChangeAssuming Reg 0Ah[11]=0, the VCO calibration starts automatically whenever a frequency change isrequested.IfitisdesiredtoreruntheAutoCalroutineforanyreason,atthesamefrequency,simplyrewritethefrequencychangewiththesamevalueandtheAutoCalroutinewillexecuteagainwithoutchangingfinalfrequency.
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
1.2.4 VCO AutoCal Time & AccuracyTheVCOfrequencyiscountedforTmmt,theperiodofasingleAutoCalmeasurementcycle.
Tmmt = Txtal · R · 2n (EQ1)
n issetbyReg0Ah[2:0]andresultsinmeasurementperiodswhicharemultiplesofthePDperiod,TxtalR.
R isthereferencepathdivisionratiocurrentlyinuse,Reg02h
Txtal istheperiodoftheexternalreference(crystal)oscillator.
TheVCOAutoCalcounterwill,onaverage,expectNcounts,roundeddown(floor)tothenearestinteger,everyPDcycle.
N istheratioofthetargetVCOfrequency,fvco,tothefrequencyofthePD,fpd,whereNcanbeanyrationalnumbersupportedbytheNdivider.
Nissetbytheinteger(Nint = Reg03h)andfractional(Nfrac = Reg04h)registercontents
N = Nint + Nfrac / 224 (EQ2)
TheAutoCalstatemachineandthedatatransferstotheinternalVCOsubsystemSPI(VSPI)runattherateoftheFSMclock,TFSM,wheretheFSMclockfrequencycannotbegreaterthan50MHz.
TFSM = Txtal · 2m (EQ3)
m is0,2,4or5asdeterminedby Reg0Ah[14:13]
TheexpectednumberofVCOcounts,V,isgivenby
V = floor (N · 2n) (EQ4)
ThenominalVCOfrequencymeasured,fvcom,isgivenby
fvcom = V · fxtal / (2n · R) (EQ5)
wheretheworstcasemeasurementerror,ferr,is:
ferr ≈ ±fpd / 2n + 1 (EQ6)
Figure 31. VCO CalibrationA 5-bit step tuned VCO, for example, nominally requires 5measurements for calibration, worst case6measurements, andhence7VSPIdata transfersof 20 clock cycleseach.Themeasurementhasaprogrammablenumberofwait states, k, of 100FSMcyclesdefinedbyReg0Ah[7:6] = k.Hence totalcalibrationtime,worstcase,isgivenby:
Tcal = k128TFSM + 6TPD 2n + 7 · 20TFSM (EQ7)
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
orequivalently
Tcal = Txtal (6R · 2n + (140+128k) · 2m)
where k = Reg0Ah[7:6] decimal(EQ8)
For guaranteed hold of lock, across temperature extremes, the resolution should be better than1/8ththefrequencystepcausedbyaVCOsub-bandswitchchange.Betterresolutionsettingswillshownoimprovement.
1.2.4.1 VCO AutoCal ExampleTheVCOsubsystemmustsatisfythemaximumfpdlimitedbythetwofollowingconditions:
a.N≥16(fint),N≥20.0(ffrac),whereN=fVCO/fpd
b.fpd≤100MHz
SupposetheVCOsubsystemoutputfrequencyistooperateat2.01GHz.Ourexamplecrystalfrequencyisfxtal= 50 MHz, R=1, and m=0 (Figure31),henceTFSM=20ns(50MHz).Note,whenusingAutoCal,themaximumAutoCalFiniteStateMachine(FSM)clockcannotexceed60MHz(seeReg0Ah[14:13]).TheFSMclockdoesnotaffecttheaccuracyofthemeasurement,itonlyaffectsthetimetoproducetheresult.Thissameclockisusedtoclockthe16bitVCOserialport.
Iftimetochangefrequenciesisnotaconcern,thenonemaysetthecalibrationtimeformaximumaccuracy,andthereforenotbeconcernedwithmeasurementresolution.
Usinganinputcrystalof50MHz(R=1andfpd=50MHz)thetimesandaccuraciesforcalibrationusing(EQ6)and(EQ8)areshowninTable1.Whereminimaltuningtimeis1/8thoftheVCObandspacing.
Across all VCOs, ameasurement resolution better than 800 kHzwill produce correct results. Settingm=0,n=5,provides781kHzofresolutionandadds8.6µsofAutoCaltimetoanormalfrequencyhop.OncetheAutoCalsetsthefinalswitchvalue,8.64µsafterthefrequencychangecommand,thefractionalregisterwillbeloaded,andtheloopwilllockwithanormaltransientpredictedbytheloopdynamics.HencewecanseeinthisexamplethatAutoCaltypicallyaddsabout8.6µstothenormaltimetoachievefrequ-encylock.Hence,AutoCalshouldbeusedforallbutthemostextremefrequencyhoppingrequirements.
Table 1. AutoCal Example with Fxtal = 50 MHz, R = 1, m = 0
ControlValueReg0Ah[2:0]
n 2nTmmt(µs)
Tcal(µs)
FerrMax
0 0 1 0.02 4.92 ±25MHz
1 1 2 0.04 5.04 ±12.5MHz
2 2 4 0.08 5.28 ±6.25MHz
3 3 8 0.16 5.76 ±3.125MHz
4 5 32 0.64 8.64 ±781kHz
5 6 64 1.28 12.48 ±390kHz
6 7 128 2.56 20.16 ±195kHz
7 8 256 5.12 35.52 ±98kHz
1.2.5 VCO Output Mute FunctionTheoutputmutefunctionenablestheHMC833LP6GEtodisabletheVCOoutputwhilemaintainingthePLLandVCOsubsystemsfullyfunctional.Themutefunctionprovidesover40dBofisolationthroughouttheoperatingrangeoftheHMC833LP6GE.TomutetheoutputoftheHMC833LP6GE,thefollowingregisterwritesarenecessary:
1. Initially,andonlyonce,typicallyafterpower-up,pre-configuretheVCOsubsystembywritingVCO_Reg01h[8:0]=3h(accomplishedbywriting toReg05h=188h).Thiswriteeffectivelyenables themasterenable,andPLLbufferenable,anddisablesthemanualmodeRFbuffer,divide-by1,andRF
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
divideroftheVCOsubsystem,asshowninFigure27.AlthoughthiswritedisablesthemanualmodeenablesoftheVCOsubsystem,ithasnoaffectonthePLLorVCOsubsystembecausetypicallyandbydefaulttheVCOsubsystemisoperatinginautomode.
2. ThentomutethePLLoutputsimplywriteVCO_Reg03h[2]=1(accomplishbywritingtoPLLReg05h=2218hindoublermode,andReg05h=2A98hinfundamentalmodeoftheVCO),whicheffectivelyplacestheVCOsubsysteminmanualmode.Manualmodeenableshavebeenpre-configuredinstep1tomutethePLLoutput.
3. IfitisrequiredtotunetheHMC833LP6GEwhiletheoutputismutedafinalwrite,Reg05h=0h,isrequired.
ToenabletheHMC833LP6GEoutputaftermuting:1. WriteVCO_Reg03h[2]=0(accomplishbywritingtoPLLReg05h=2018hindoublermode,orReg
05h=2898hinfundamentalmode).2. AfinalwritetoReg05h=0hisrequired.
PleaserefertoFigure27formoreinformation.AlsonotethattheVCOsubsystemregistersarenotdirectlyaccessible. They are written to the VCO subsystem via PLL Reg 05h. More information about VCOsubsystemSPIinsection1.19.
1.3 VCO Built in Test with AutoCalThefrequencylimitsoftheVCOcanbemeasuredusingtheBISTfeaturesoftheAutoCalmachine.
ThisisdonebysettingReg0Ah[10]=1whichfreezestheVCOswitchesinoneposition.VCOswitchesmaythenbewrittenmanually,withthevaractorbiasedatthenominalmid-railvoltageusedforAutoCal.ForexampletomeasuretheVCOmaximumfrequencyuseswitch0,writtentotheVCOsubsystemviaReg05h=[0000000000000VCOID].WhereVCOID=‘000’b.
IfAutoCalisenabled,(Reg0Ah[11]=0),andanewfrequencyiswritten,AutoCalwillrun,butwithswitchesfrozen.TheVCOfrequencyerrorrelativetothecommandfrequencywillbemeasuredandresultswrittentoReg11h[19:0]whereReg11h[19]isthesignbit.TheresultwillbewrittenintermsofVCOcounterror(EQ4).ForexampleiftheexpectedVCOis2GHz,referenceis50MHz,andnis6,weexpecttomeasure2560counts.Ifwemeasureadifferenceof-5countsinReg11h,thenitmeansweactuallymeasured2555counts.HencetheactualfrequencyoftheVCOis5/2560low,or1.99609375GHz,±1Count~±781kHz.
1.4 Spurious Performance
1.4.1 Integer Operation and Reference SpuriousTheVCOalwaysoperatesatanintegermultipleofthePDfrequencyinanintegersynthesizer.Ingeneral,spurioussignalsoriginatingfromanintegersynthesizercanonlyoccuratmultiplesofthePDfrequency.These unwanted outputs closest to the carrier are often simply referred to as reference sidebands.Unwantedreferenceharmonicscanalsoexistfarfromthecarrierduetocircuitisolation.
Spursunrelatedtothereferencefrequencymustoriginatefromoutsidesources.ExternalspurioussourcescanmodulatetheVCOindirectlythroughpowersupplies,ground,oroutputports,orbypasstheloopfilterduetopoorisolationofthefilter.ItcanalsosimplyaddtotheoutputofthePLL.
Referencespuriouslevelsaretypicallybelow-100dBcwithawelldesignedboardlayout.Aregulatorwithlownoiseandhighpower supply rejection, suchas theHMC1060LP3E, is recommended tominimizeexternalspurioussources.
Referencespuriouslevelsofbelow-100dBcrequiresuperbboardisolationofpowersupplies,isolationoftheVCOfromthedigitalswitchingofthesynthesizerandisolationoftheVCOloadfromthesynthesizer.Typicalboardlayout,regulatordesign,evalboardsandapplicationinformationareavailableforverylowspuriousoperation.Operationwithlowerlevelsofisolationintheapplicationcircuitboard,fromthoserec-ommendedbyHittite,canresultinhigherspuriouslevels.
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Application Support: Phone: 978-250-3343 or [email protected]
IftheapplicationenvironmentcontainsotherinterferingfrequenciesunrelatedtothePDfrequency,andiftheapplicationisolationfromtheboardlayoutandregulationareinsufficient,theunwantedinterferingfrequencieswillmixwith thedesiredsynthesizeroutputandcauseadditionalspuriousemissions.Theleveloftheseemissionsisdependantuponisolationandsupplyregulationorrejection(PSRR).
1.4.2 Fractional Operation and SpuriousUnlikeanintegerPLL,spurioussignalsinafractionalPLLcanoccurduetothefactthattheVCOoperatesatfrequenciesunrelatedtothePDfrequency.HenceintermodulationoftheVCOandthePDharmonicscancausespurioussidebands.SpuriousemissionsarelargestwhentheVCOoperatesveryclosetoanintegermultipleofthePD.WhentheVCOoperatesexactlyataharmonicofthePDthen,noin-closemixingproductsarepresent.
AsshowninFigure32,interferenceisalwayspresentatmultiplesofthePDfrequency,fpd,andtheVCOfrequency,fvco.Thedifference,Δ,betweentheVCOfrequencyandthenearestharmonicofthereference,will createwhat are referred to as integer boundary spurs.Dependingupon themodeof operationofthesynthesizer,higherorder, lowerpowerspursmayalsooccuratmultiplesof integer fractions(sub-harmonics)ofthePDfrequency.Thatis,fractionalVCOfrequencieswhicharenearnfpd+fpdd/m,wheren,dandmareallintegersandd4spursaresmallorunmeasurable.
Theworstcase,infractionalmode,iswhend=0,andtheVCOfrequencyisoffsetfromnfpdbylessthantheloopbandwidth.Thisisthe“in-bandintegerboundary”case.
Figure 32. Fractional Spurious ExampleCharacterizationofthelevelsandordersoftheseproductsisnotunlikeamixerspurchart.Exactlevelsoftheproductsaredependentuponisolationofthevarioussynthesizerparts.Hittitecanofferguidanceaboutexpected levelsofspuriouswithHMC833LP6GEevaluationboards.Regulatorswithhighpowersupplyrejectionratios(PSRR)arerecommended,especiallyinnoisyapplications.
1.4.2.1 Charge Pump and Phase Detector Spurious ConsiderationsCharge pump and phase detector linearity are of paramount importancewhen operating in fractionalmode.Anynon-linearitydegradesphasenoiseandspuriousperformance.
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Application Support: Phone: 978-250-3343 or [email protected]
Wedefinezerophaseerrorwhen the referencesignaland thedividerVCOsignalarriveat thePhaseDetectorat thesame time. Phasedetector linearitydegradeswhen thephaseerror isverysmallandwhentherandomphaseerrorscausethephasedetectortoswitchbackanforthbetweenreferenceleadandVCOlead.
Theseswitchingnon-linearitiesinfractionalmodeareeliminatedbyoperatingthephasedetectorwithanaveragephaseoffsetsuchthateitherthereferenceorVCOalwaysleads.
AprogrammablechargepumpoffsetcurrentsourceisusedtoaddDCcurrenttotheloopfilterandcreatethedesiredphaseoffset.PositivecurrentcausestheVCOtolead,negativecurrentcausesthereferencetolead.
TheoffsetchargepumpiscontrolledviaReg09h.Thephaseoffsetisscaledfrom0degrees,thatisthereferenceandtheVCOpatharriveinphase,to360degrees,wheretheyarriveafullcyclelate.Theoffsetcanalsobethoughtofinabsolutetimedifferencebetweenthearrivals.
Therecommendedoperatingpointforthechargepumpinfractionalmodeisonewherethetimeoffsetatthephasedetectoris~2.5ns+4TVCO,whereTVCOistheRFperiodatthefractionalprescalerinput.TherequiredCPoffsetcurrentshouldneverexceed25%oftheprogrammedCPcurrent.
The specific level of chargepumpoffset currentReg09h[20:14] is determinedby this timeoffset, thecomparisonfrequencyandthechargepumpcurrent:
( ) ( )( )92.5 10 4 sec ,0.25Required CP Offset min VCO comparison CP CPT F I I− • + • • • • =where:
TVCO: is the RF period at the fractional prescaler inputICP: is the full scale current setting of the switching charge pump Reg09h[6:0] Reg09h[13:7]
(EQ9)
OperationwithchargepumpoffsetinfluencestherequiredconfigurationoftheLockDetectfunction.RefertothedescriptionofLockDetectfunctioninsection1.11.Notethatthiscalculationcanbeperformedforthecenterfrequencyof theVCO,anddoesnotneedrefinementforsmalldifferences<25%incenterfrequencies.
AnotherfactorinthespectralperformanceinFractionalModeisthechoiceoftheDelta-SigmaModulatormode.ModeAcanofferbetterin-bandspectralperformance(insidetheloopbandwidth)whileModeBoffersbetteroutofbandperformance.SeeReg06h[3:2] forDSMmodeselection.Finally,all fractionalsynthesizerscreatefractionalspursatsomelevel.Hittiteoffersthelowestlevelfractionalspuriousintheindustryinanintegratedsolution.
1.4.2.2 Spurious Related to Channel Step Size (Channel Spurs)ManyfractionalPLLsalsocreatespuriousemissionsatoffsetswhicharemultiplesofthechannelstepsize.WerefertotheseasChannelSpurs.Itiscommonintheindustrytosetthechannelstepsizebyuseoftheso-calledmodulus.Forexample,channelstepsizeof100kHzrequiresasmallmodulusrelatedtothestepsize,andoftenresultsin100kHzChannelSpurs.
The HMC833LP6GE uses a large fixedmodulus unrelated to the channel step size. As a result, theHMC833LP6GEhasextremelyloworunmeasurableChannelSpurs.InadditionExactFrequencyMode(1.12.2.2)allowsexactchannelstepsizewithnoChannelSpurs.
ThelackofChannelSpursmeansthattheHMC833LP6GEhaslargeregionsofoperationbetweenIntegerBoundarieswithlittleornospursofanykind.LargespuriousfreezonesenabletheHMC833LP6GEtobeusedwithatunablereference,toeffectivelymovethespurfreezonesandhenceachievespur-freeoperationatallfrequencies.TheresultingPLLisvirtuallyspur-freeatallfrequencies.
Formoreinformationsee1.4.2.3.
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Application Support: Phone: 978-250-3343 or [email protected]
1.4.2.3 Spurious Reduction with Tunable ReferenceSection 1.4.2 discussed fractional mode Integer Boundary spurious caused by VCO operation nearreferenceharmonics. It ispossible,withHittite fractionalsynthesizers, tovirtuallyeliminate the integerboundaryspuriousatagivenVCOfrequencybychangingthefrequencyofthereference.Thereferencefrequencyisnormallygeneratedbyacrystaloscillatorandisnottunable.However,anyofHittite’swidebandPLLswithIntegratedVCOs,includingHMC833LP6GE,canbeusedasahigh-qualitytunablereferencesource,asshowninFigure33.
Figure 33. TunablereferencesourceWiththesetupshowninFigure33,theHMC833LP6GEiscapableofoperatingacrossallofitsfrequencyrangewithoutsacrificingphasenoise,whilevirtuallyeliminatingspuriousemissions.Optimumoperationrequiresappropriateconfigurationofthetwosynthesizerstoachievethisperformance.Hittiteapps-supportcanassistwiththerequiredalgorithmsforultra-lowspurioustunablereferenceapplications.
An HMC833LP6GE tunable reference PLL typically uses a high frequency crystal reference for bestperformance.PhasenoisefromtheMC830LP6GEtunablereferenceoutputat100kHzoffsetvariestypicallyfrom-145dBcat100MHzoutputto-157dBcat25MHzoutput.ThisperformanceofHMC833LP6GEasatunablereferenceisequivalenttothephasenoiseofhighperformancecrystaloscillators.
Figure 34. Phase noise performance of the HMC833LP6GE
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curves respectively.)Worst case spurious levels (largest spurs at any offset) of conventional fixed reference vs. a tunablereferencecanbecomparedbymultipleindividualphasenoisemeasurementsandsummarizedonasingleplotvs.carrierfrequency.
Forexample,Figure35showsthespectrumofacarrieroperatingat2000.1MHzwitha50MHzfixedreference.Thiscaseis100kHzawayfromanIntegerBoundary(50MHzx40).Worstcasespuriouscanbeobservedat100kHzoffsetandabout-52dBcinmagnitude.
Figure36showsthesameHMC833LP6GEPLLVCOoperatingatthesame2000.1MHzcarrierfrequency,usingatunablereferenceat47.5MHzgeneratedbyHMC830LP6GE.Worstcasespuriousinthiscasecanbeobservedat5MHzoffsetandabout-100dBcinmagnitude.
The resultsofFigure35andFigure36show that the tunable referencesourceachieves50dBbetterspuriousperformance,whilemaintainingessentiallythesamephasenoiseperformance.
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Application Support: Phone: 978-250-3343 or [email protected]
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Figure 35. HMC833LP6GE Worst spur at any offset, fixed 50 MHz reference, output frequency = 2000.1
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Figure 36. HMC833LP6GE worst spur at any offset, tunable reference (HMC830LP6GE), output
frequency = 2000.1 MHz
Manyspuriousmeasurements,suchastheonesinFigure35andFigure36canbesummarizedintoasingleplotofworstcasespuriousatanyoffsetvs.carrierfrequencyasshowninFigure37.Alogfrequencydisplayrelativetothe2000MHzfixedreferenceIntegerBoundarywasusedtoemphasizetheimportanceoftheloopbandwidthonspuriousperformanceofthefixedreferencecase.Thistechniqueclearlyshowsthelogarithmicroll-offoftheworstcasespuriouswhenoperatingneartheIntegerBoundary.InthiscasetheloopfilterbandwidthoftheHMC833LP6GEwas100kHz.
Figure 37.
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Largest observed spurious, at any offset, using a fixed 50 MHz reference source and a tunable reference source.
Forexampleworstcasespuriousoperatingat2000.1MHz(point(A)) inFigure35withafixed50MHzreference)isrepresentedbyasinglepointinFigure37(point(A))onthebluecurve.Similarly,worstcasespuriousfromFigure36withvariablereference,operatingat2000.1MHzisrepresentedbyasinglepointinFigure37(point(B))onthegreencurve.
The plot in Figure 37 is generated by tuning the carrier frequency away from Integer Boundary andrecordingtheworstcasespurious,atanyoffset,ateachoperatingfrequency.Figure37showsthattheworstcasespurious for the50MHzfixedreferencecase, isnearlyconstantbetween-51dBcand-55dBcwhenoperatingwithacarrierfrequencylessthan100kHzfromtheIntegerBoundary(bluecurve).Italsoshowsthattheworstcasespuriousrollsoffatabout25dB/decaderelativeto1loopbandwidth.Forexample,atanoperatingfrequencyof2001MHz(equivalentto10loopbandwidthsoffset)worstcasespuriousis-80dBc.Similarly,atanoperatingfrequencyof2010MHz(equivalentto100loopbandwidths)worstcasespuriousis-100dBc.
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Application Support: Phone: 978-250-3343 or [email protected]
Incontrast, thegreencurveofFigure37shows that theworstcasespuriousover thesameoperatingfrequency range,whenusinganHMC830LP6GEtunable reference, isbelow-100dBcatalloperatingfrequencies!
IngeneralallfractionalPLLshavespuriouswhenoperatingnearIntegerBoundaries.HighperformancetunablereferencemakesitpossibletooperateHMC833LP6GE,virtuallyspur-freeatallfrequencies,withlittleornodegradationinphasenoise.
1.5 Integrated Phase Noise & JitterThestandarddeviationofVCOsignaljittermaybeestimatedwithasimpleapproximationifitisassumedthatthelockedVCOhasaconstantphasenoise,o|2(fo),atoffsetslessthantheloop3dBbandwidthanda20dBperdecaderoll-offatgreateroffsets.ThesimplelockedVCOphasenoiseapproximationisshownontheleftofFigure38.
Figure 38. PLL with Integrated VCO Phase Noise & JitterWiththissimplificationthetotalintegratedVCOphasenoise,o|2,inrads2inthelinearformisgivenby
o|2=o|2(fo) Bπ (EQ10)
whereo|2(fo) isthesinglesidebandphasenoiseinrads2/Hzinsidetheloopbandwidth,andBisthe3dB
cornerfrequencyoftheclosedloopPLL
Theintegratedphasenoiseatthephasefrequencydetector,o|2pd
isjustscaledbyN2
/N2=o|2pd o|2 (EQ11)
ThermsphasejitteroftheVCOinrads,o|,isjustthesquarerootofthephasenoiseintegral.
Sincethesimpleintegralof(EQ10)isjustaproductofconstants,wecaneasilydotheintegralinthelogdomain.ForexampleiftheVCOphasenoiseinsidetheloopis-100dBc/Hzat10kHzoffsetandtheloopbandwidthis100kHz,andthedivisionratiois100,thentheintegratedphasenoiseatthephasefrequencydetector,indB,isgivenby:
o|2=10log(o|2(fo)Bπ/N2)=-100+50+5-40=-85dBcpddB
orequivalently,o|=10-85/20=53.6e-6rads=3.2e-3degrees.
Whilethephasenoisereducesbyafactorof20logNafterdivisiontothereference,duetotheincreasedperiodofthePDreferencesignal,thejitterisconstant.
Thermsjitterfromthephasenoiseisthengivenby
Tjpn = Tpdo|pd/2π (EQ12)
InthisexampleifthePDreferencewas50MHz,Tpd=20ns,andhenceTjpn=179femto-sec.
Itshouldbenotedthatthislastexpressionisbaseduponaclosedformintegraloftheentirespectrumoftheoscillatorphasenoise.ThisintegralstartsatDC.Itiscommonforrealsystemtoevaluatejitterovershorterintervalsoftime,hencetheintegraloftenstartsatsomefinitefrequencyoffsetandwillproducea
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
jitterthatislessthanthatgivenbythefullexpression.Finallyrealoscillatorshavenoisefloorsthatalsocontributetojitter.Thephasenoiseofawhitenoisefloorisasimpleintegralofnoisefloordensitytimesbandwidthof interest to thesystem.Thisadditionalnoisepowershouldbeadded to theexpressionof(EQ16)togiveamoreaccuratejitternumber.Dependinguponthebandwidthofthesysteminquestionthisnoisefloorcontributionmaybeanimportantfactor.
1.6 Reference Input Stage
Figure 39. Reference Path Input StageThe referencebuffer provides thepath fromanexternal reference source (generally crystal based) totheRdivider,andeventuallytothephasedetector.ThebufferhastwomodesofoperationcontrolledbyReg08h[21].HighGain(Reg08h[21]=0),recommendedbelow200MHz,andHighfrequency(Reg08h[21]=1),for200to350MHzoperation.ThebufferisinternallyDCbiased,with100Ωinternaltermination.For50Ωmatch,anexternal100Ωresistortogroundshouldbeadded,followedbyanACcouplingcapacitor(impedance<1Ω),thentotheXREFPpinofthepart.
Atlowfrequencies,arelativelysquarereferenceisrecommendedtokeeptheinputslewratehigh.Athigherfrequencies,asquareorsinusoidcanbeused.Thefollowingtableshowstherecommendedoperatingregionsfordifferentreferencefrequencies. Ifoperatingoutsidetheseregionsthepartwillnormallystilloperate,butwithdegradedreferencepathphasenoiseperformance.
Minimumpulsewidthatthereferencebufferinputis2.5ns.ForbestspurperformancewhenR=1,thepulsewidthshouldbe(2.5ns+8TPS),whereTPSistheperiodoftheVCOattheprescalerinput.WhenR>1minimumpulsewidthis2.5ns.
Table 2. Reference Sensitivity TableSquareInput SinusoidalInput
ReferenceInputFrequency
(MHz)
Slew>0.5V/ns RecommendedSwing(Vpp) RecommendedPowerRange(dBm)
Recommended Min Max Recommended Min Max
<10 YES 0.6 2.5 x x x
10 YES 0.6 2.5 x x x
25 YES 0.6 2.5 ok 8 15
50 YES 0.6 2.5 YES 6 15
100 YES 0.6 2.5 YES 5 15
150 ok 0.9 2.5 YES 4 12
200 ok 1.2 2.5 YES 3 8
Input referredphasenoiseof thePLLwhenoperatingat50MHz isbetween -150and -156dBc/Hzat
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Application Support: Phone: 978-250-3343 or [email protected]
10kHzoffsetdependinguponthemodeofoperation.Theinputreferencesignalshouldbe10dBbetterthanthisfloortoavoiddegradationofthePLLnoisecontribution.ItshouldbenotedthatsuchlowlevelsareonlynecessaryifthePLListhedominantnoisecontributorandtheselevelsarerequiredforthesystemgoals.
1.7 Reference Path ’R’ DividerThereferencepath“R”dividerisbasedona14-bitcounterandcandivideinputsignalsbyvaluesfrom1to16,383andiscontrolledbyrdiv (Reg02h).
Minimumpulsewidthatthereferencebufferinputis2.5ns.ForbestspurperformancewhenR=1,thepulsewidthshouldbe(2.5ns+8Tps),whereTpsistheperiodoftheVCOattheprescalerinput.WhenR>1minimumpulsewidthis2.5ns.
1.8 RF Path ’N’ DividerThemainRFpathdivideriscapableofaveragedivideratiosbetween219-5(524,283)and20infractionalmode,and219-1(524,287)to16inintegermode.TheVCOfrequencyrangedividedbytheminimumNdividervaluewillplacepracticalrestrictionsonthemaximumusablePDfrequency.ForexampleaVCOoperatingat1.5GHzinfractionalmodewithaminimumNdividervalueof20willhaveamaximumPDfrequencyof75MHz.
1.9 Charge Pump & Phase DetectorThePhasedetector(PD)hastwoinputs,onefromthereferencepathdividerandonefromtheRFpathdivider.When in lock these two inputsareat thesameaverage frequencyandarefixedataconstantaveragephaseoffsetwithrespecttoeachother.WerefertothefrequencyofoperationofthePDasfpd.Most formulae related to step size, delta-sigmamodulation, timersetc., are functionsof theoperatingfrequencyofthePD,fpd.fpdisalsoreferredtoasthecomparisonfrequencyofthePD.
ThePDcomparesthephaseoftheRFpathsignalwiththatofthereferencepathsignalandcontrolsthechargepumpoutputcurrentasa linear functionof thephasedifferencebetween the twosignals.Theoutputcurrentvarieslinearlyoverafull±2πradians(±360°)ofinputphasedifference.
1.10 Phase Detector FunctionsPhasedetectorregisterReg0Bhallowsmanualaccesstocontrolspecialphasedetectorfeatures.
PD_up_en(Reg0Bh[5]), if 0, masksthePDupoutput,whichpreventsthechargepumpfrompumpingup.̀
PD_dn_en(Reg0Bh[6]), if 0,masksthePDdownoutput,whichpreventsthechargepumpfrompumpingdown.
Clearing bothPD_up_en andPD_dn_en effectively tri-states the charge pumpwhile leaving all otherfunctionsoperatinginternally.
PDForceUPReg0Bh[9] = 1andPDForceDN Reg0Bh[10] = 1allowsthechargepumptobeforcedupordownrespectively.ThiswillforcetheVCOtotheendstothetuningrangewhichcanbeusefulintestoftheVCO.
1.11 Phase Detector Window Based Lock DetectLock Detect Enable Reg07h[3]=1isaglobalenableforalllockdetectfunctions.
The window based Lock Detect circuit effectivelymeasures the difference between the arrival of thereferenceandthedividedVCOsignalsat thePD.Thearrival timedifferencemustconsistentlybelessthantheLockDetectwindowlength,todeclarelock.Eithersignalmayarrivefirst,onlythedifferenceinarrivaltimesiscounted.
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Application Support: Phone: 978-250-3343 or [email protected]
1.11.1 Analog Window Lock DetectThelockdetectwindowmaybegeneratedbyeitherananalogoneshotcircuitoradigitaloneshotbaseduponaninternaltimer.SettingReg07h[6]=0willresultinafixed,analog,nominal10nswindow,asshowninFigure40.TheanalogwindowcannotbeusedifthePDrateisabove50MHz,oriftheoffsetistoolarge.
Figure 40. Normal Lock Detect Window - Integer Mode, Zero OffsetForexamplea25MHzPDratewitha1mAchargepumpsetting(Reg09h[6:0]=Reg09h[13:7]= 32h)and400µAoffsetdowncurrent(Reg09h[20:14]=50h Reg09h[22]= 1),wouldhaveanoffsetofabout400/1000=40%ofthePDperiodorabout16ns.InsuchanextremecasethedividedVCOwouldarrive16nsafterthePDreference,andwouldalwaysarriveoutsideofthe10nslockdetectwindow.Insuchacasethelockdetectcircuitwouldalwaysreadunlocked,eventhoughtheVCOmightbelocked.Whenusingthe10nsanaloglockdetectwindow,witha40nsPDperiod,theoffsetmustalwaysbelessthan25%ofthechargepumpsetting,20%toallowfortolerances.Hencea1mAchargepumpsettingcannotusemorethan200µAoffsetwitha25MHzPDandananalogLockdetectwindow.Chargepumpcurrent,chargepumpoffset,phasedetectorrateandlockdetectwindowarerelated.
1.11.2 Digital Window Lock DetectSettingReg07h[6]=1willresultinavariablelengthlockdetectwindowbaseduponaninternaldigitaltimer.ThetimerperiodissetbythenumberofcyclesoftheinternalLDclockasprogrammedbyReg07h[9:7].TheLDclockfrequencyisadjustablebyReg07h[11:10].TheLDclocksignalcanbeviewedviatheGPOtestpins.Refer1.16fordetails.
1.11.3 Declaration of Lockwincnt_maxinReg07h[2:0]definesthenumberofconsecutivecountsofthedividedVCOthatmustlandinsidethelockdetectwindowtodeclarelock.Ifforexamplewesetwincnt_max=2048,thentheVCOarrivalwouldhavetooccur insidethewindow2048times inarowtobedeclared locked,whichwouldresultinaLockDetectFlaghigh.Asingleoccurrenceoutsideofthewindowwillresultinanoutoflock,i.e.LockDetectFlaglow.Oncelow,theLockDetectFlagwillstaylowuntilthewincnt_max=2048conditionismetagain.
TheLockDetectFlagstatus isalwaysreadable inReg12h[1], if locked=1.LockDetectstatus isalsooutputtotheLD_SDOpinifReg0Fh[4:0]=1.Again,iflocked,LD_SDOwillbehigh.Setting Reg0Fh[6]=0 willdisplaytheLockDetectFlagonLD_SDOexceptwhenaserialportreadisrequested,inwhichcasethepinrevertstemporarilytotheSerialDataOutpin,andreturnstotheLockDetectFlagafterthereadiscompleted.Referto1.11.5forTimingoftheLockDetectinformation.
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
1.11.4 Phase Offset & Fractional LinearityWhenoperatinginfractionalmodethelinearityofthechargepumpandphasedetectoraremuchmorecritical than in integermode.Thephasedetector linearity isdegradedwhenoperatingwithzerophaseoffset.HenceinfractionalmodeitisnecessarytooffsetthephaseofthePDreferenceandtheVCOatthephasedetector.Insuchacase,forexamplewithanoffsetdelay,asshowninFigure41,theVCOarrivalwillalwaysoccurafterthereference.Thelockdetectcircuitwindowmayneedtobeadjustedtoallowforthedelaybeingused.fordetailsseesection“DigitalLockDetectwithDigitalWindowExample”.
Figure 41. Lock Detect Window - Fractional Mode with Offset
1.11.5 Digital Lock Detect with Digital Window ExampleTypicalDigitalLockdetectwindowwidthsareshowninTable3.LockDetectwindowstypicallyvary±10%vsvoltageand±25%overtemperature(-40°Cto+85°C).
Table 3. Typical Digital Lock Detect WindowLD Timer Speed
Reg07[11:10]Digital Lock Detect Window
Nominal Value ±25% (ns)
Fastest00 6.5 8 11 17 29 53 100 195
01 7 8.9 12.8 21 36 68 130 255
10 1.7 9.2 13.3 22 38 72 138 272
Slowest11 7.6 10.2 15.4 26 47 88 172 338
LDTimerDivideSettingReg07[9:7]
0 1 2 3 4 5 6 7
LDTimerDivideValue
0.5 1 2 4 8 16 32 64
Asanexample,ifweoperateinfractionalmodeat2GHzwitha50MHzPD,chargepumpcurrentgainof2mAandadownleakageof400uA.ThenouraverageoffsetatthePDwillbe0.4mA/2mA=0.2ofthePDperiodorabout4ns(0.2x1/50MHz).However,thefractionalmodulationoftheVCOdividerwillresultintimeexcursionsoftheVCOdivideroutputof+/-4Tvcofromthisaveragevalue(2nsinthisexample).Hence,wheninlock,thedividedVCOwillarriveatthePD4+/-2nsafterthedividedreference.TheLockDetectwindowalwaysstartsonthearrivalofthefirstsignalatthePD,inthiscasethereference.TheLockDetectwindowmustbelongerthan4ns+2ns(6ns)andshorterthantheperiodofthePD,inthisexample,20ns.AperfectLockDetectwindowwouldbemidwaybetweenthesetwovalues,or13ns.
There is a always a good solution for the LockDetectwindow for a given operating point. The user
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
shouldunderstandhoweverthatonesolutiondoesnotfitalloperatingpoints.IfchargepumpoffsetorPDfrequencyarechangedsignificantlythenthelockdetectwindowmayneedtobeadjusted.
Figure 42. Lock Detect Window Example with 50 MHz PD and 3.9 ns VCO Offset
1.11.6 Cycle Slip Prevention (CSP)When changing VCO frequency and the VCO is not yet locked to the reference, the instantaneousfrequenciesofthetwoPDinputsaredifferent,andthephasedifferenceofthetwoinputsatthePDvariesrapidlyoverarangemuchgreaterthan±2πradians.SincethegainofthePDvarieslinearlywithphaseupto±2π,thegainofaconventionalPDwillcyclefromhighgain,whenthephasedifferenceapproachesamultipleof2π,tolowgain,whenthephasedifferenceisslightlylargerthanamultipleof0radians.TheoutputcurrentfromthechargepumpwillcyclefrommaximumtominimumeventhoughtheVCOhasnotyetreacheditsfinalfrequency.
Thechargeontheloopfiltersmallcapmayactuallydischargeslightlyduringthelowgainportionofthecycle.ThiscanmaketheVCOfrequencyactuallyreversetemporarilyduringlocking.Thisphenomenaisknownascycleslipping.Cycleslippingcausesthepull-inrateduringthelockingphasetovarycyclically.CycleSlipping increases the time to lock toavaluegreater than thatpredictedbynormalsmallsignalLaplaceanalysis.
ThesynthesizerPDfeaturesanabilitytoreducecycleslippingduringacquisition.TheCycleSlipPreven-tion(CSP)featureincreasesthePDgainduringlargephaseerrors.ThespecificphaseerrorthattriggersthemomentaryincreaseinPDgainissetviaReg0Bh[8:7]
1.11.7 Charge Pump GainAsimplifieddiagramofthechargepumpisshowninFigure43.ChargepumpUpandDowngainsaresetbyCP DN GainandCP UP Gainrespectively(Reg09h[6:0] and Reg09h[13:7]).ThecurrentgainofthepumpinAmps/radianisequaltothegainsettingofthisregisterdividedby2π.
ForexampleifbothCP DN GainandCP UP Gainaresetto‘50d’theoutputcurrentofeachpumpwillbe1mAandthephasefrequencydetectorgainkp=1mA/2πradians,or159µA/rad.Seesection1.4formoreinformation.
1.11.8 Charge Pump Phase Offset - Fractional ModeInintegermode,thephasedetectoroperateswithzerooffset.ThedividedreferencesignalandthedividedVCOsignalarriveatthephasedetectorinputsatthesametime.Infractionalmodeofoperation,chargepumplinearityandultimately,phasenoise,ismuchbetteriftheVCOandreferenceinputsareoperatedwithaphaseoffset.AphaseoffsetisimplementedbyaddingaconstantDCoffsetcurrentattheoutputofthechargepump.
DC offset may be added to the UP or DN switching pumps using Reg 09h[21] or Reg 09h[22]. The
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
magnitudeoftheoffsetiscontrolledbyReg09h[20:14],andcanrangefrom0to635µAinstepsof5µA.Downoffsetishighlyrecommendedinfractionalmodeofoperation.Integermodeofoperationworksbestwithzerooffset.
Asanexample,aPDcomparisonoffPD=50MHz(20nsperiod)withthemainpumpgainsetat2mA,andadown(DN)offsetof-385µAwouldrepresentaphaseoffsetofabout(-385/2000)*360=-69degrees.ThisisequivalenttothedividedVCOarriving3.8nsafterthereferenceatthePDinput.Itiscriticalthatphaseoffsetbeusedinfractionalmode.Normally,downoffsetslargerthan3nsaretypical.
If the charge pump gain is changed, for example to compensate for changes in VCO sensitivity, it isrecommendedtochangethechargepumpoffsetproportionallytomaintainaconstantphaseoffset.
Figure 43. Charge Pump Gain & Offset Control
1.12 Frequency TuningHMC833LP6GEVCOsubsystemalwaysoperates in fundamental frequencyofoperation(1500MHzto3000MHz).TheHMC833LP6GEgeneratesfrequenciesbelowitsfundamentalfrequency(25MHzto1500MHz)by tuning to theappropriate fundamental frequencyandselecting theappropriateOutputDividersetting(divideby2/4/6.../60/62)in“VCO_Reg02hBiases”[5:0].ConverselytheHMC833LP6GEgeneratesfrequenciesgreaterthanitsfundamentalfrequency(3000MHzto6000MHz)bytuningtotheappropriatefundamentalfrequencyandenablingthedoublermode(VCO_Reg03h[0]=0).
TheHMC833LP6GEautomaticallycontrols frequency tuning in the fundamentalbandofoperation, formoreinformationsee“1.2.1VCOAuto-Calibration(AutoCal)”.
To tune to frequenciesbelow the fundamental frequency range (3000MHz)itisrequiredtotunetheHMC833LP6GEtotheappropriatefundamentalfrequency,andthenenablethedoublermodeofoperation(VCO_Reg03h[0]=0).
1.12.1 Integer ModeTheHMC833LP6GEiscapableofoperatinginintegermode.ForIntegermodesetthefollowingregisters
a.DisabletheFractionalModulator,Reg06h[11]=0
b.BypasstheModulatorcircuit,Reg06h[7]=1
InintegermodetheVCOstepsizeisfixedtothatofthePDfrequency,fpd.Integermodetypicallyhas3dBlowerphasenoisethanfractionalmodeforagivenPDoperatingfrequency.Integermode,however,oftenrequiresalowerPDfrequencytomeetstepsizerequirements.Thefractionalmodeadvantageisthat
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
higherPDfrequenciescanbeused,hencelowerphasenoisecanoftenberealizedinfractionalmode.ChargePumpoffsetshouldbedisabledinintegermode.
1.12.1.1 Integer Frequency TuningInintegermodethedigitalΔ∑modulatorisshutoffandtheN(Reg03h)dividermaybeprogrammedtoanyintegervalueintherange16to219-1.ToruninintegermodeconfigureReg06hasdescribed,thenprogramtheintegerportionofthefrequencyasexplainedby(EQ13),ignoringthefractionalpart.
a.DisabletheFractionalModulator,Reg06h[11]=0b.Bypassthedelta-sigmamodulatorReg06h[7]=1c. To tune to frequencies (3000MHz),enablethedoublermodeofoperation(VCO_Reg03h[0]=1).
WritingtoVCOsubsystemregisters(“VCO_Reg02hBiases”[5:0]andVCO_Reg03h[0]inthiscase)isaccomplishedindirectlythroughPLLregister5(Reg05h).MoreinformationoncommunicatingwiththeVCOsubsystemthroughPLLReg05hisavailablein“1.19VCOSerialPortInterface(SPI)”section.
1.12.2 Fractional ModeTheHMC833LP6GEisplacedinfractionalmodebysettingthefollowingregisters:
a.EnabletheFractionalModulator,Reg06h[11]=1
b.Connectthedeltasigmamodulatorincircuit,Reg06h[7]=0
1.12.2.1 Fractional Frequency TuningThisisagenericexample,withthegoalofexplaininghowtoprogramtheoutputfrequency.Actualvariablesaredependantuponthereferenceinuse.
TheHMC833LP6GEinfractionalmodecanachievefrequenciesatfractionalmultiplesofthereference.ThefrequencyoftheHMC833LP6GE, fvco,isgivenby
fvco=(Nint+Nfrac)=fint+ffracfxtal
R(EQ13)
fout=fvco/ k (EQ14)
Where:
fout istheoutputfrequencyafteranypotentialdividersordoublers.
k is0.5fordoubler,1forfundamental,ork=1,2,4,6,…58,60,62accordingtotheVCOSubsystemtype
Nint istheintegerdivisionratio,Reg03h,anintegernumberbetween20and 524,284
Nfrac isthefractionalpart,from0.0to0.99999...,Nfrac=Reg04h/224
R isthereferencepathdivisionratio,Reg02h
fxtal isthefrequencyofthereferenceoscillatorinput
fpd isthePDoperatingfrequency,fxtal/R
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Asanexample:
fout 1402.5MHz
k 2
fvco 2,805MHz
fxtal =50MHz
R =1
fpd =50MHz
Nint =56
Nfrac =0.1
Reg04h =round(0.1x224)=round(1677721.6)=1677722
fVCO=(56+)=2805 MHz +1.192 Hz error1677722
22450e6
1(EQ15)
fout= =1402.5 MHz +0.596 Hz errorfVCO
2(EQ16)
Inthisexampletheoutputfrequencyof1402.5MHzisachievedbyprogrammingthe19-bitbinaryvalueof56d=38hinto intg_reginReg03h,andthe24-bitbinaryvalueof1677722d=19999Ahinto frac_regin Reg04h.The0.596Hzquantizationerrorcanbeeliminatedusingtheexactfrequencymodeifrequired.Inthisexampletheoutputfundamentalisdividedby2.Specificcontroloftheoutputdividerisrequired.Seesection3.0anddescriptionformoredetails.
1.12.2.2 Exact Frequency TuningDue toquantizationeffects, theabsolute frequencyprecisionofa fractionalPLL isnormally limitedbythenumberofbitsinthefractionalmodulator.Forexample,a24bitfractionalmodulatorhasfrequencyresolutionsetbythephasedetector(PD)comparisonratedividedby224.Thevalue224inthedenominatorissometimesreferredtoasthemodulus.HittitePLLsuseafixedmoduluswhichisabinarynumber.InsometypesoffractionalPLLsthemodulusisvariable,whichallowsexactfrequencystepstobeachievedwithdecimalstepsizes.Unfortunatelysmallstepsusingsmallmodulusvaluesresultsinlargespuriousoutputsatmultiplesof themodulusperiod(channelstepsize).ForthisreasonHittitePLLsusea largefixedmodulus.Normally,thestepsizeissetbythesizeofthefixedmodulus.Inthecaseofa50MHzPDrate,amodulusof224wouldresultina2.98Hzstepresolution,or0.0596ppm.Insomeapplicationsitisnecessarytohaveexactfrequencysteps,andevenanerrorof3Hzcannotbetolerated.
Fractional PLLs are able to generate exact frequencies (with zero frequency error) if N can beexactly represented in binary (eg. N = 50.0,50.5,50.25,50.75 etc.). Unfortunately, some commonfrequencies cannot be exactly represented. For example,Nfrac = 0.1 = 1/10must be approximated asround((0.1x224)/224)≈0.100000024.AtfPD=50MHzthistranslatesto1.2Hzerror.Hittite’sexactfrequencymodeaddressesthisissue,andcaneliminatequantizationerrorbyprogrammingthechannelstepsizetoFPD/10inReg0Chto10(inthisexample).Moregenerally,thisfeaturecanbeusedwheneverthedesiredfrequency,fVCO,canbeexactlyrepresentedonastepplanwherethereareanintegernumberofsteps(
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For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or [email protected]
Where:
gcdstandsforGreatestCommonDivisor
fN=maximumintegerboundaryfrequency<fVCO1
fPD =frequencyofthePhaseDetector
andfVCOk arethechannelstepfrequencieswhere0<k<224-1,AsshowninFigure44.
Figure 44. Exact Frequency TuningSomefractionalPLLsareabletoachievethisbyadjusting(shortening)thelengthofthePhaseAccumulator(thedenominatororthemodulusoftheDelta-Sigmamodulator)sothattheDelta-Sigmamodulatorphaseaccumulator repeatsatanexactperiod related to the interval frequency (fVCOk - fVCO(k-1)) inFigure44.Consequently,theshortenedaccumulatorresultsinmorefrequentrepeatingpatternsandasaresultoftenleads tospuriousemissionsatmultiplesof the repeatingpatternperiod,oratharmonic frequenciesoffVCOk-fVCO(k-1).Forexample,insomeapplications,theseintervalsmightrepresentthespacingbetweenradiochannels,andthespuriouswouldoccuratmultiplesofthechannelspacing.
TheHittitemethodontheotherhandisabletogenerateexactfrequenciesbetweenadjacentinteger-Nboundarieswhilestillusing the full24bitphaseaccumulatormodulus, thusachievingexact frequencystepswithahighphasedetectorcomparisonrate,whichallowsHittitePLLstomaintainexcellentphasenoiseandspuriousperformanceintheExactFrequencyMode.
1.12.2.3.3 Using Hittite Exact Frequency ModeIftheconstraintin(EQ17)issatisfied,HMC833LP6GEisabletogeneratesignalswithzerofrequencyerroratthedesiredVCOfrequency.ExactFrequencyModemaybere-configuredforeachtargetfrequency,orbeset-upforafixedfgcdwhichappliestoallchannels.