analog data aquisition- ananthnag & balakrishna

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A Project Report on HIGH RESOLUTION ANALOG DATA ACQUISITION IN NUCLEAR POWER PLANT USING 16-BIT AI BOARD Submitted in partial fulfillment of the requirements for the award of the degree of BACHELOR OF TECHNOLOGY IN ELECTRONICS AND COMMUNICATION ENGINEERING J.N.T.UNIVERSITY By BEZGAM ANANTHNAG 07K81A0411 D. BALAKRISHNAREDDY 07K81A0416 Under the esteemed guidance of Mrs. CH. SRI SUBBA LAKSHMI Mrs. ANDAL RAMCHANDAR .T INTERNAL GUIDE EXTERNAL GUIDE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING ST. MARTINS ENGINEERING COLLEGE Affiliated to Jawaharlal Nehru Technological University Hyderabad Dhullapally, secunderabad 500014

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Analog Data Aquisition

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Page 1: Analog Data Aquisition- AnanthNag & BalaKrishna

A Project Report on

HIGH RESOLUTION ANALOG DATA ACQUISITION IN NUCLEAR

POWER PLANT USING 16-BIT AI BOARD

Submitted in partial fulfillment of the requirements for the award of the degree of

BACHELOR OF TECHNOLOGY

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

J.N.T.UNIVERSITY

By

BEZGAM ANANTHNAG 07K81A0411

D. BALAKRISHNAREDDY 07K81A0416

Under the esteemed guidance of

Mrs. CH. SRI SUBBA LAKSHMI Mrs. ANDAL RAMCHANDAR .T

INTERNAL GUIDE EXTERNAL GUIDE

DEPARTMENT OF

ELECTRONICS AND COMMUNICATION ENGINEERING

ST. MARTINS ENGINEERING COLLEGE

Affiliated to Jawaharlal Nehru Technological University – Hyderabad

Dhullapally, secunderabad – 500014

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ACKNOWLEDGEMENT

We are grateful to Dr.H.L.Suryanarayana Head of the Department of Electronics &

Communication Engineering, and our internal guide Mrs.Ch.Sri Subba Lakshmi,

St.MARTINS ENGINEERING COLLEGE, Dhullapally for their valuable suggestions, which

helped us during the project.

We would like to express our profound gratitude to Sri P.Vishwanath GM, Control and

Automation Division, ECIL, for permitting us to carry out the project work.

We are grateful to Mrs.Andal Ramchander.T, Senior Manager, for giving us an

opportunity, guiding us and also providing all facilities to us.

Last but not the least we are grateful to each and everyone one of them who helped us

directly or indirectly at various stages of our project.

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ABSTRACT

In the present world scenario there is a rapid modernization of lifestyle especially in the

scientific aspect. This is leading to more industrialization with higher demand of quantity and

quality. To meet such kind of a situation the industries need high-speed processes along with

high precision of accuracy in operation. Thus arises, the need of automation, which requires

sophisticated control systems that can function efficiently under the time constraint. And one

among the very important parts of such an automated system is a high-speed data acquisition

system. This kind of a system that has to function under the time constraint, and interact with &

process the real world entities is named as a ‘Real Time Data Acquisition System’.

This real time data acquisition system consists of a computer which acts as controller;

input/output modules that help in converting data into the controller understandable format and

the driver software that acts as an interface between the computer and the input/output modules.

The advancements in the field of science and technology when go hand in hand with man's

creativity lead to some interesting achievements.

Nuclear power plants and Thermal power plants are the Powerhouses for any country for

power generation. Even a small plant has thousands of parameters, which are to be stored and

retrieved by data acquisition systems. Data Acquisition Systems used in Power Plants determines

the changing status and behavior of process of power generation, foreseeing impacts, and

managing what can be controlled for the maximum benefit to the plant by total power generation

as per the plant capability with minimum risks and human interaction.

The EC I/O System is a part of the COIS system, that deals with the acquisition of data.

This project mainly deals with how the Analog data from the field is acquired and

interfaced to a computer system and Designing of Analog Input Board.

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CONTENTS

CHAPTER 1:

1. INTRODUCTION 1

1.1. INDUSTRIAL AUTOMATION 1

1.2. DATA ACQUISITION 2

1.3. REAL TIME SYSTEM 4

1.4. FUNCTIONS OF REAL TIME DAQ SYSTEMS 5

1.4.1. SENSING THE REAL WORLD PHENOMENON 5

1.4.2. SIGNAL CONDITIONING 6

1.4.3. AMPLIFICATION 6

1.4.4. ISOLATION 6

1.4.5. MULTIPLEXING 6

1.4.6. FITERING 7

1.4.7. EXCITATION 7

1.4.8. LINEARIZATION 7

1.5. DESIGN CONSIDERATIONS FOR A DAQ SYSTEM 8

1.5.1. SAMPLING RATE 8

1.5.2. RESOLUTION 8

1.5.3. RANGE 9

1.6. DATA LOGGING 10

CHAPTER 2:

2. CHANNEL TEMPERATURE MONITORING 12

2.1. OVERVIEW 12

2.2. DESCRIPTION OF CTM SYSTEM 13

2.3. MAIN FUNCTIONS OF CTM LOGGER SYSTEM 13

2.4. GENERAL TERMS AND THEIR DEFINITIONS 14

2.4.1. CTM ZONE 14

2.4.2. ZONE MEAN TEMPERATURE 15

2.4.3. CHANNEL TEMPERATURE DEVIATION 15

2.4.4. ZONE MEAN TEMPERATRE DEVIATION 15

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CHAPTER 3:

3. ECIL’S I/O SYSTEM 16

3.1. FEATURES OF I/O SYSTEM 16

3.2. FUNCTIONAL DIAGRAM OF ECIL’S I/O SYSTEM 17

3.3. I/O SYSTEM CONFIGURATION 18

3.3.1. I/O CONTROLLER 18

3.3.2. I/O BIN 19

3.3.3. LOGIC MOTHER BOARD 20

3.3.4. POWER SUPPLY UNITS 21

3.3.5. LOGIC POWER SUPPLY 21

3.3.6. ANALOG POWER SUPPLY 22

3.3.7. FIELD POWER SUPPLY 22

CHAPTER 4:

4. DESIGN OF 16-BIT AI BOARD 23

4.1. LISTING OUT THE REQUIREMENTS 23

4.2. NEED FOR A NEW DESIGN 24

4.3. FEASIBILITY STUDIES 24

4.3.1. TECHNOLOGY AND SYSTEM FEASIBILITY 25

4.3.2. ECONOMIC FEASIBILITY 25

4.3.3. SCHEDULE FEASIBILITY 25

4.4. DESIGN 25

4.4.1. DESIGN OF INPUT SECTION 26

4.4.2. DESIGN OF OUTPUT SECTION 28

4.4.3. DESIGN OF CONTROL SECTION 29

4.4.4. DESIGN OF DIAGNOSTICS SECTION 30

4.4.5. OVERALL AI BOARD BLOCK DIAGRAM 31

4.5. SELECTION OF COMPONENTS 32

4.5.1. ANALOG MULTIPLEXER 32

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4.5.2. SAMPLE AND HOLD AMPLIFIER 34

4.5.3. ANALOG TO DIGITAL CONVERTER 36

4.5.4. PROGRAMMABLE ARRAY LOGIC 40

CHAPTER 5:

5. OPERATION OF 16-BIT AI BOARD 42

5.1. ANALOG INPUT BOARD 42

5.2. ADDRESS DECODING 44

5.3. SLOT SELECTION 45

5.4. CONTROL SIGNAL BUFFERING 45

5.5. SAMPLE AND HOLD AMPLIFIER 45

5.6. ADC CIRCUIT 45

5.7. SHA CONVERSION CONTROL LOGIC 46

5.8. DIAGNOSTICS 46

CHAPTER 6:

6. CONCLUSIONS 47

REFERENCES 48

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LIST OF FIGURES

S.No. Figure No. TITLE OF THE FIGURE PAGE No.

1. 1.1 Industrial Automation – Illustration 1

2. 1.2 Block diagram of a typical data acquisition system 3

3. 1.3 Real Time Computer System in action 4

4. 1.5 Block diagram of a DAQ System 8

5. 1.6.1 Block diagram of a data logger 10

6. 1.6.2 Data Logging Applications 11

7. 2.1 The core of a nuclear reactor 12

8. 2.2 Signal flow in CTM 13

9. 2.3 Channel matrix of a 306-channel nuclear reactor 14

10. 3.2 Functional diagram of ECIL’S I/O system 17

11. 3.3.2 I/O Bin 20

12. 3.3.3 Logic Mother Board 21

13. 4.4 Basic segmentation of AI Board Design 26

14. 4.4.1 Signal flow in input section 28

15. 4.4.2 Tri-state buffers 28

16. 4.4.3 Block diagram of output section 29

17. 4.4.4 Block diagram of diagnostics section 30

18. 4.4.5 Block diagram of the AI board 31

19. 4.5.3 Functional Block Diagram of Analog to Digital Converter 39

20. 4.5.4 Functional Block Diagram of Programmable Array Logic 41

21. 5.1.1 Operation of AI Board 43

22. 5.1.2 Manufactured PCB (AI Board) 44

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LIST OF TABLES

S.No. Table No. TITLE OF THE TABLE Page No.

1. 4.5.1 Selection of Analog Multiplexer 32

2. 4.5.2 Selection of Sample and Hold Amplifier 34

3. 4.5.3 Selection of Analog to Digital Converter 38

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1. INTRODUCTION

1.1. INDUSTRIAL AUTOMATION

Automation (auto = self dictated in ancient Greek) or industrial automation or

numerical control is the use of control systems such as computers to control industrial

machinery and processes, replacing human operators. In the scope of industrialization, it is

a step beyond mechanization. Whereas mechanization provided human operators with

machinery to assist them with the physical requirements of work, automation greatly

reduces the need for human sensory and mental requirements as well.

There are still many jobs which are in no immediate danger of automation. No

device has been invented which can match the human eye for accuracy and precision in

many tasks, nor the human ear. Even the admittedly handicapped human is able to identify

and distinguish among far more scents than any automated device. Human pattern

recognition, language recognition, and language production ability is well beyond anything

currently envisioned by automation engineers.

Fig1.1: Industrial Automation - Illustration

Specialized hardened computers referred to as programmable logic controllers, are

frequently used to synchronize the flow of inputs from (physical) sensors and events with

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the flow of outputs to actuators and events. This leads to precisely controlled actions that

permit a tight control of almost any industrial process.

Human-machine interface (HMI) or computer-human interface (CHI), formerly known

as man-machine interfaces, are usually employed to communicate with PLCs and other

computers such as entering and monitoring temperatures or pressures for further automated

control or emergency response. Service personnel who monitor and control these interfaces

are often referred o as stationary engineers.

Another form of automation involving computers is test automation, where computer-

controlled automated test equipment is programmed to simulate human testers in manually

testing an application. This is often accomplished by using test automation tools to

generate special scripts (written as computer programs) that direct the automated test

equipment in exactly what to do in order to accomplish the tests.

1.2. DATA ACQUISITION

Data acquisition is a term used to describe the process of "sampling" a signal (capturing a

sequence of numbers for a digital machine to work with) from a real-world system. In

many cases, the signal captured represents the physical quantity of electric voltage, for two

reasons:

Most signals of another type can be readily transformed into voltage, through the

use of transducers such as microphones, thermistors, light-sensitive diodes,

piezoelectric material, etc.

There exist many inexpensive devices that perform periodic time sampling of

voltage and are compatible with digital computers.

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Fig1.2: Block diagram of a typical data acquisition system.

The figure above shows the block diagram of a typical DAQ. The figure depicts the

following two important features of such a system. Signals that are input to a sensor are

conditioned, converted into bits that a computer can read, and analyzed to extract

meaningful information and data from a computer is converted into an analog or a digital

signal and output to an actuator. Often, the second step is replaced by a computer-human

interaction device such as a data logger, or an alarm system, in which case the systems is

purely a monitoring system.

In order to configure a data acquisition system it is important to know some information

about the signal to be captured. The most important characteristic is the bandwidth of the

signal. The bandwidth of a signal refers to the difference between the highest frequency at

which the signal can change, and the lowest. Since many signals may not change at all for

some length of time (zero frequency is sometimes known as "DC"), bandwidth often refers

simply to the maximum signal frequency component. Frequency, an oft-used term in

digital signal processing, may be thought of as the rate at which a signal changes values.

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The maximum signal frequency occurs when a signal changes from its lowest possible

value to its highest possible value or vice versa in the smallest amount of time. In

mathematical terms, one divided by this minimum time interval is the maximum signal

frequency. Thus, frequency is expressed in units called Hertz (Hz), where 1 Hz is 1/1sec.

Once the bandwidth of the signal is known, it is possible to determine the minimum rate

at which the signal can be sampled (the maximum time interval between adjacent time

samples) and still be truly representative of the continuous analog time signal. There are

two important resources to be conserved in a DAQ. They are processor time between

samples for actual digital signal processing work, and processor memory storage for

samples.

1.3. REAL TIME SYSTEM

Real-time means that both hardware and software must be capable of interacting with

physical "events" external to the computer itself, and this interaction must be sufficiently

fast as to capture and preserve the essential information associated with the event. In some

cases, the computer must also be able to make a fast calculation of some response data that

can be applied as feedback to control subsequent events.

Naturally, this definition of real-time means that the requirements of the computer

system depend highly on the speed of some external processes. A system that logs data in a

solar-energy building can be said to be real-time, but the timing requirements are far more

liberal than those for a system controlling the flight of a spacecraft or airplane.

Fig1.3: Real Time Computer System in action

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The concept of interrupts is vital to real-time computing. Both hardware and software

must support the handling of interrupts from (in most cases) multiple sources. An external

event triggers an electrical signal, and a transition from logical false to true of this signal

causes the computer to take some action within a predefined maximum time for the level of

interrupt in question. The faster reaction a specific type of event needs, the higher is the

interrupt level it is assigned to. In this way it can be assured that for instance reading data

from a nuclear reaction takes priority over something like keyboard input.

1.4. FUNCTIONS OF A REAL TIME DAQ SYSTEMS

1.4.1. SENSING THE REAL WORLD PHENOMENON:

The job of a Data Acquisition System is to acquire samples of a real world phenomenon,

condition it and give it as an input to a computer which takes an appropriate action. Hence,

the first stage of such a system is sensing the real world phenomenon such as temperature,

pressure, etc.

A transducer is a device which converts one form of energy into another form of energy.

Temperature to voltage transducers such as thermocouples, RTDs, thermistors, and IC

sensors convert temperature into a voltage or resistance.

These sensors require an accurate excitation current or voltage source to sense the

change in resistance. The thermistors have a relatively high resistance and can typically be

measured with a voltage source and one reference resistor. However, RTDs and strain

gauges are low resistance and low sensitivity devices that need additional circuitry to

enhance their sensitivity and account for lead resistance. RTDs are often used in a 4-wire

configuration; one pair of wires carries the excitation current and the other pair senses the

RTD voltage. This 4-wire configuration avoids errors due to lead resistance because

current does not flow in the leads connected to the measurement system.

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1.4.2. SIGNAL CONDITIONING:

Sensor signals are often incompatible with the data acquisition hardware. To overcome

this incompatibility, the signal must be conditioned. For example, an input signal may

need to be conditioned by amplifying it or by removing unwanted frequency components.

Output signals may need conditioning as well.

1.4.3. AMPLIFICATION:

The most common type of conditioning is amplification. Low-level thermocouple signals,

for example, should be amplified to increase the resolution and reduce noise. For the

highest possible accuracy, the signal should be amplified so that the maximum voltage

range of the conditioned signal equals the maximum input range of the ADC.

1.4.4. ISOLATION:

Another common application for signal conditioning is to isolate the transducer signals

from the computer for safety purposes. It may contain high-voltage transients that could

damage the computer. Isolation is also needed to make sure that the readings from the

plug-in DAQ board are not affected by differences in ground potentials or common mode

voltages. When the DAQ board input and the signal being acquired are each referenced to

ground, problems occur if there is a potential difference between the two grounds. This

difference can lead to what is known as a ground loop, which may cause inaccurate

representation of the acquired signal, or if too large, may damage the measurement system.

Using isolated signal conditioning modules eliminates the ground loop and ensures that the

signals are accurately acquired.

1.4.5. MULTIPLEXING:

A common technique for measuring several signals with a single ADC is multiplexing. A

multiplexer selects and routes one channel to the ADC for digitizing, then switches to

another channel and repeats. Because the same ADC is sampling many channels, the

effective rate of each individual channel is reduced in proportion to the number of channels

sampled. As an example, a PCI-MIO-16E-1 sampling at 1.25 MS/s on 10 channels will

effectively sample each individual channel at 125 kS/s per channel. You can often use

external analog multiplexers to increase the numbers of channels a board can measure. For

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example, SCXI uses multiplexing modules to expand the number of input channels up to

3,072 with a single board.

1.4.6. FILTERING:

Filtering removes unwanted signals from the signal that you are trying to measure. A noise

filter is used on DC-class signals such as temperature to attenuate higher frequency signals

that can reduce the accuracy of your measurement. Many of the SCXI modules have 4 Hz

and 10 kHz low pass filters to eliminate noise before the signals are digitized by the DAQ

board. AC-class signals such as vibration often require a different type of filter known as

an anti-aliasing filter. Like the noise filter, the anti-aliasing filter is also a low pass filter;

however, it also has a very steep cutoff rate, so that it almost completely removes all

frequencies components that are higher than the input bandwidth of the board. If the

signals are not removed, they erroneously appear as signals within the input bandwidth of

the board.

1.4.7. EXCITATION:

Signal conditioning also generates excitation for some transducers. Strain gauges,

thermistors, and RTDs, for example, require external voltage or current excitation. Signal

conditioning modules for these transducers usually provide these signals. RTD

measurements are usually made with a current source that converts the variation in

resistance to a measurable voltage. Strain gauges are resistance devices in a Wheatstone

bridge configuration, which often require bridge completion circuitry and excitation

sources.

1.4.8. LINEARIZATION:

Another common signal conditioning function is linearization. Many transducers, such as

thermocouples, have a nonlinear response to changes in the phenomenon being measured.

NI-DAQ and National Instruments application software include linearization routines for

thermocouples, strain gauges, and RTDs.

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1.5. DESIGN CONSIDERATIONS FOR A DAQ SYSTEM

Data acquisition is the process of gathering information in an automated fashion from

analog and digital measurement sources such as sensors and devices under test. Data

acquisition uses a combination of PC-based measurement hardware and software to

provide a flexible, user-defined measurement system. In general, the overall block

diagram is as given below.

Fig1.5: Block diagram of a DAQ System

The key considerations in the design are:

1.5.1. SAMPLING RATE:

The speed at which a data acquisition system collects data is called sampling rate. The

speed is normally expressed in samples per second. When acquiring data from several

input channels, the analog multiplexer connects each signal to the ADC at a constant rate.

This method, known as continuous scanning, is significantly less expensive than having a

separate amplifier and ADC for each input channel. Because the multiplexer switches

between channels, a time skew is generated between each channel sample. This method is

appropriate for applications where the time relationship between sampled points is

unimportant. For those applications where the time relationship between inputs is

important (such as phase analysis of AC signals), you will need to simultaneously sample.

DAQ products capable of simultaneous sampling use sample-and-hold circuitry for each

input channel. An analog multiplexer connects one of the input signals to the ADC for

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processing. You can simulate simultaneous sampling hardware without paying for

additional sample-and-hold circuitry. Interval scanning creates the effect of simultaneous

sampling for low-frequency signals, such as temperature and pressure, while maintaining

the cost benefits of continuous scanning. This method scans the input channels at one

interval and uses a second interval to determine the time before repeating the scan. The

input channels are scanned within microseconds, creating the effect of simultaneously

sampling the input channels.

1.5.2. RESOLUTION

Resolution is the smallest change in the signal increment, which can be detected by a data

acquisition system. Resolution can be expressed in bits, in proportions, or in percent of full

scale. The number of bits that the ADC uses to represent the analog signal is the resolution.

The higher the resolution, the higher the number of divisions the voltage range is broken

into, and therefore, the smaller the detectable voltage changes. A 3-bit converter divides

the analog range into 23, or 8 divisions. Each division is represented by a binary code

between 000 and 111. Clearly, the digital representation is not a good representation of the

original analog signal because information has been lost in the conversion. By increasing

the resolution to 16 bits, however, the number of codes from the ADC increases from 8 to

65,536 and you can therefore obtain an extremely accurate digital representation of the

analog signal if the rest of the analog input circuitry is designed properly.

1.5.3. RANGE

Range refers to the minimum and maximum voltage levels that the ADC can span. The

multifunction DAQ boards offer selectable ranges so that the board is configurable to

handle a variety of different voltage levels. With this flexibility, you can match the signal

range to that of the ADC to take best advantage of the resolution available to accurately

measure the signal. The range, resolution, and gain available on a DAQ board determine

the smallest detectable change in voltage. This change in voltage represents 1 LSB of the

digital value, and is often called the code width. The ideal code width is found by dividing

the voltage range by the gain times two raised to the order of bits in the resolution.

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1.6. DATA LOGGING

Data logging and recording is a very common measurement application. In its most basic

form, data logging is the measurement and recording of physical or electrical parameters

over a period of time. The data can be temperature, strain, displacement, flow, pressure,

voltage, current, resistance, power, or any of a wide range of other parameters.

Fig1.6.1: Block diagram of a data logger

Real-world data logging applications are typically more involved than just acquiring

and recording signals, typically involving some combination of online analysis, offline

analysis, display, report generation, and data sharing. Moreover, many data logging

applications are beginning to require the acquisition and storage of other types of data,

such as recording sound and video in conjunction with the other parameters measured

during an automobile crash test.

Data logging is used in a broad spectrum of applications. Chemists record data such as

temperature, pH, and pressure when performing experiments in a lab. Design engineers log

performance parameters such as vibration, temperature, and battery level to evaluate

product designs. Civil engineers record strain and load on bridges over time to evaluate the

safety. Geologists use data logging to determine mineral formations when drilling for oil.

Breweries log the conditions of their storage and brewing facilities to maintain quality.

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Fig1.6.2: Data Logging Applications

The list of applications for data logging goes on and on, but all of these applications

have similar common requirements. The purpose of this paper is to provide a general

background on data logging, discuss the various functional requirements that are common

to most logging applications, and examine some of the modern hardware and software

options available to scientists and engineers for implementing powerful PC-based data

logging systems.

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2. CHANNEL TEMPERATURE MONITORING

2.1. OVERVIEW

The CTM logger system is a PC based data acquisition system. It is one of the applications

of real time data acquisition systems. It monitors the temperature at the outlet of 306

coolant channels of the reactors.

Controlled fission is a critical phenomenon in nuclear reactors. In the absence of proper

channel monitoring systems, chain reactions may occur which can lead to disasters of

mammoth proportions. Hence the temperature at each fuel rod is monitored continually and

it the sample at any instant crosses the threshold, a cautioning system such as an alarm

comes to life. The figure below shows an instructional model of the core of a nuclear

reactor.

Fig2.1: The core of a nuclear reactor

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2.2. DESCRIPTION OF CTM SYSTEM

Each coolant channel has two RTDs installed on it, one of them is connected to CTM

Installation - I and other to CTM Installation - II. The RTDs are platinum-200 ohm RTDs.

These RTDs are connected to a resistive network in which temperature sensing element is

connected in series with 10ohm potentiometer and a fixed resistor and series of circuit is

excited by a stable 36V DC power supply. Analog voltage signal ranging from 4-8v is

tapped from potentiometer wiper arm. These signals are given as input to the CTM logger

system. The two installations of CTM logger scan these analog voltage signals and process

them to compute channel temperature as per given voltage verses temperature relationship

and other parameters.

Fig2.2: Signal flow in CTM

The two loggers are networked through a dual LAN. In case of failure of both the LAN

each of the CTM loggers shall function normally except for computation of those

parameters which require data from installation.

2.3. MAIN FUNCTIONS OF CTM LOGGER SYSTEM

Scan the input signals at specified rate.

Display the channel temperature and other calculated parameters, like zone mean-

temperature, zone-mean temperature deviation etc.

Generate alarms on various parameters as per the alarm settings.

Trending and archiving of data for history.

Generate on -demand and routine printouts and plots for selected parameters.

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Allow the user to interact through some standard input devices, e.g., keyboard,

mouse etc. For display, prints, storage, retrieval of history data etc.

The figure below shows the channel matrix for the 306 channels of the nuclear reactor.

Each block represents a channel. Such a display could be used to show temperature

deviations from normal values, channel outlet temperatures, channel voltages, and their

corresponding digital values (ADC outputs) etc.

Fig2.3: Channel Matrix of a 306-channel nuclear reactor

2.4. GENERAL TERMS AND THEIR DEFINITIONS

2.4.1. CTM ZONE:

The entire CTM matrix of 306 coolant channels are grouped into 8 Zones and they are

named as A1, B1, C1, D1, A2, B2, C2 and D2.Zones A1, B1, C1 and D1 each consists of

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31 channels. Zones A2 and C2 each consists of 48 channels whereas, zones B2 and D2

each consists of 43 channels.

2.4.2. ZONE MEAN TEMPERATURE (ZMT):

Zone mean temperature is defined as the arithmetic mean of the temperature of all the

channels of a particular zone.

2.4.3. CHANNEL TEMPERATURE DEVIATION (CTD):

The Channel temperature deviation of a particular channel is defined as the deviation of its

channel temperature from its respective zone mean temperature. It is positive when channel

temperature is more than the ZMT.

2.4.4. ZONE MEAN TEMPERATURE DEVIATION (ZMTD):

There are in total 8 zones, out of which A1, B1, C1, D1 are the four outer zones and

remaining are the inner zones. The ZMTD is defined as the difference between the

particular ZMT and the average of the four zone mean temperatures (inner or outer to

which that particular zone belongs to).

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3. ECIL’S I/O SYSTEM

The EC I/O SYSTEM manufactured by the Control & Automation Division of Electronics

Corporation of India Limited, Hyderabad, India is an intelligent data transfer system useful

to interface analog and digital field signals of a process or an industry to a computer system

for data acquisition, monitoring and alarm generation purpose.

The ECI/O SYSTEM can handle a wide range of analog input signals covering

thermocouple signals, mV signals, RTDs, strain gauges, 4-20mA, 0-5 V, 1-5 V, 0-10 V,-10

to + 10 V signals etc. It handles a variety of digital input signals comprising of potential

free contacts, 24V, 48 V, or 110 V DC or binary signals and 220 V or 240 V, 50 Hz AC

signals. It provides 0-5 V, 1-5 V, 1-10 V or 4-20mA analog output signals and 24 V/ 48 V/

110 V DC, 2A or 120 V/ 240 V, 2 A AC digital outputs.

The I/O system can be connected to any standard computer system using a suitable

interface. Interfaces to the ISA bus are readily available to connect the I/O system to a

CPU operating on ISA bus, or the PCI bus, the standard bus architectures of a computer.

The interface comprises of an ISA I/O Interface Board and an I/O Bus interface board

along with a pair of 50 core flat cable assemblies connecting these two boards. It is

possible to use the I/O system with dual redundant CPUs with the help of arbitration logic

provided on the I/O bus interface boards.

3.1. FEATURES OF I/O SYSTEM

Ruggedness

Reliable

Indigenously developed

Redundancy

Modularity

Availability

Custom built

Configurability

Expandability

Testability

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3.2 Functional diagram of ECIL’S I/O system:

Fig3.2: Functional diagram of ECIL‟S I/O system

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3.3 I/O SYSTEM CONFIGURATION

The I/O system is built around the following basic building blocks:

I/O Controller

I/O Bin

Power Supply Units

3.3.1 I/O CONTROLLER:

The I/O controller is the actual governing block of the I/O system. It decides the types of

signals (analog or digital) and the instants at which they should be acquired, or given out

through their corresponding boards. It then issues the necessary control signals to enable

the required board and thus performs data transfer. It also controls the speed at which data

is transferred.

It consists of:

Pentium PC: This processor is a high performance 32 bit-processing engine with a

multiprocessing architecture used for different applications. The PC is an Intel Pentium

CPU, 32 bit processor and houses serial and parallel I/O ports, an onboard SRAM and a

BIOS EPROM, IDE interfaces supporting up to four devices. The motherboard supports

standard PS/2 104-keys keyboard and mouse. This PC comes with a 10/100 Base-T

Ethernet adapter. The processor is connected to a host computer, to which other such I/O

systems are also connected through 12 port D-link Ethernet 10/100 Mbps switches.

Specifications:

Bus Compatibility : ISA / Compact PCI Bus

Data Bus : 16 / 32-bit Data Bus

Address Bus : 16 / 24 / 32-bit Address Bus

CPU : Intel PENTIUM

SRAM : 32MB

Serial Port : Two UART serial ports RS232/RS485

Parallel Port : One parallel port

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Ethernet Interface : 10/100 Base-T Ethernet

Power requirement : +5 V, 10 A DC ±12 V, 100mA, DC

Temperature : Operating temperature is 00 to 40

0 C

Storage temperature is 00

to 550 C

3.3.2 I/O BIN:

The I/O bin is a 19” mountable rack which houses the following boards:

Logic Mother Board

Analog Input Boards

Analog output boards

Digital input boards.

Digital output boards

The I/O bus interface board connects the I/O Controller with the I/O bus through the

ISA I/O interface board. The I/O devices, which operate on 24V/48VDC, 120/240V AC

are suitably interfaced with the I/O boards on the I/O bus. The bin is capable of driving 16

boards of any combination of I/O boards and I/O bus interface board. The I/O bus

motherboard communicates with the I/O Controller through the I/O bus interface board,

using a 50 core flat cable and the ISA I/O Interface board of the I/O controller. The

maximum number of analog/digital I/O boards per bin is 16. This means that a

combination of the ISA-I/O and I/O bus interface boards cater to one I/O bin and more than

one such combination of interface boards, i.e., more than one I/O bin can be connected to

the I/O controller.

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Fig 3.3.2: I/O Bin

3.3.3 LOGIC MOTHER BOARD:

The logic motherboard (LMB) is an 18 slot analog and digital mother board which serves

as the common bus for both the analog and digital I/O boards. The first two slots are

reserved for two I/O bus interface boards and the next sixteen slots can be used for any

type of I/O board. The I/O bus interface board is required for the LMB to interface the I/O

controller. In case two I/O controllers are accessing the same I/O bin for a redundant

controller system, two I/O bus interface boards are required. The I/O bus interface board is

connected to the I/O controller by means of a pair of 50 core flat cables and an interface

board on the I/O controller. The LMB can accommodate 16 I/O boards of different types,

i.e., the Analog Input, the Analog Output, the Digital Input and the Digital Output boards.

The 16 slots meant for the I/O boards can be addressed from “0000” to “1111” with a 4-bit

slot address meant for each slot, which is set by means of a 4-pin jumper block (SA1-SA4

of which SA4 is MSB and SA1 is LSB) on the rear side of the motherboard. A jumper

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inserted sets up logic „0‟ and an open jumper pin sets up logic „1‟ in the slot address. Since

these sixteen I/O slots can be addressed by means of hardware jumper selection on the

backplane of the motherboard, it is called a logic motherboard. The I/O boards are powered

through this motherboard.

Fig3.3.3: Logic Mother Board

3.3.4 POWER SUPPLY UNITS:

The power supplies required for the I/O systems are:

1. The logic power supply 5V DC,

2. The analog power supply 5V, ±15V DC,

3. The field power supply 24V OR 48V DC.

3.3.5 LOGIC POWER SUPPLY:

This is a plug-in module type switch mode multi-output power supply used for providing

logic power to the I/O Controller and the digital I/O boards. It is a 5V at 25A, at 1A

power supply. Optional hot standby feature is available on 19” rack mountable bin.

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3.3.6 ANALOG POWER SUPPLY:

This is a linear regulated multi-output power supply used for providing power to the DACs

of the analog output boards and for the ADCs of the analog input boards. It is a 5V at 25A,

and + 15V at 5A DC rated power supply. This power supply is designed for parallel

operation with another similar power supply to provide redundancy.

3.3.7 FIELD POWER SUPPLY:

This is a plug-in module type switch mode power supply used for providing interrogation

power to the digital inputs and field power to the digital outputs. It is a 24V or 48V at 20A

rated power supply.

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4. DESIGN OF 16-BIT ANALOG INPUT BOARD

Though the main job of AI board in a CTM system is A to D conversion of the field signal

and feeding it to the computer, there are several components that need to be properly

chosen as per the requirements. Even before the design process is started, the need for a

new board has to be analyzed and feasibility studies have to be performed. The following

are the steps, in sequence, of designing an AI board:

Listing out the requirements

Study the need for a new design

Feasibility studies

Design feasibility

Feasibility in terms of availability of components

Manufacturing feasibility

Design Analysis

Selection of components

PCB layout

PCB manufacturing

4.1. LISTING OUT THE REQUIREMENTS

The AI board is designed so as to meet the requirements that are specified by the client

(Operator of a nuclear power plant)

A sample specifications sheet such as the one in design here is shown below.

Compatibility : Compatible with I/O bus of I/O system.

Number of channels : 32 single ended

Input range : 0 --10V / 0 – 5 V DC

Resolution : 0.15mV

Accuracy at 250C : 10 LSBs

Conversion time (max) : 50 micro seconds

Operating temperature : 0-500C

Storage temperature : 0-700C

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Size : 233.4mm x 160mm Double Euro format

Through put rate : 20 K samples.

Power Requirements : 5V DC at 1A and -15 V DC at 1A.

Interface : Two 64 pin Euro connectors.

P1 - for connecting the motherboard

P2 – for connecting the field signals

4.2. NEED FOR A NEW DESIGN

Upon receiving a specification sheet from a client, the first move by the manufacturer is to

dig into existing designs so as to see if any such design matches the requirements. If a

verified and operable design exists, the manufacturer refrains from making a new design. If

such a design is not exiting, which is most likely, the manufacturer will assign his

engineers the work for making a new design in coherence with the specifications. For

instance, if a similar board exists with all the required features, but does not meet the

physical dimensions criterion, new design is imperative. Hence, the first step in the design

process is to study the need for a new design.

4.3. FEASIBILITY STUDIES

A feasibility study is an evaluation of a proposal designed to determine the difficulty in

carrying out a designated task. Generally, a feasibility study precedes technical

development and project implementation. In other words, a feasibility study is an

evaluation or analysis of the potential impact of a proposed project.

The most common feasibility studies done prior to taking up an industrial project are:

4.3.1 Technology and system feasibility

The assessment is based on an outline design of system requirements in terms of Input,

Processes, Output, Fields, Programs, and Procedures. This is done in order to estimate

whether the new system will perform adequately or not. Technological feasibility is carried

out to determine whether the company has the capability, in terms of software, hardware,

personnel and expertise, to handle the completion of the project

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4.3.2 Economic feasibility

Economic analysis is the most frequently used method for evaluating the effectiveness of a

new board. If remuneration outweighs costs, then the decision is made to design and

implement the system. An entrepreneur must accurately weigh the cost versus benefits

before taking an action.

Cost Based Study: It is important to identify cost and benefit factors, which can be

categorized as follows: 1. Development costs; and 2. Operating costs. This is an analysis of

the costs to be incurred in the system and the benefits derivable out of the system.

4.3.3 Schedule feasibility

A project will fail if it takes too long to be completed before it is useful. Typically this

means estimating how long the system will take to develop, and if it can be completed in a

given time period. Schedule feasibility is a measure of how reasonable the project

timetable is.

After a thorough feasibility study is done, if the design is deemed viable, we proceed

with the project.

4.4. DESIGN

The design of the analog input board is primarily divided into 3 major sections:

1. Input section

2. Control section

3. Output section

The function of the AI board is to convert the analog signals into digital ones which are

suitable for interpretation by the computer. In an abstract manner, the input section is

responsible for analog to digital conversion, the output section for latching the digital

outputs to the I/O bus, and the control section for managing the flow of signals through the

board. The analog inputs to the board that is to be designed are:

Temperature inputs (x 306)

Alarm reference signals (x 2)

36V supply reference signal (x 1)

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In all, there are 309 inputs to the Analog Input board. If we design an AI board that can

handle at most 32 channels by suitably multiplexing between the channels, then we will

need ten such AI boards.

For each AI board, we can have two connectors, one say, P2 from field and the other

say, P1 to the processor. In P2 slot if we have 64 pins, 32 analog data sources can be

accommodated. Then will raise the question of slot selection or card selection. The logic

mother board has a total 16 slots for the input side. Among these, 10 are occupied by the

AI cards as just said. Hence, an address selection mechanism is present on the bin which

enables us to fix the addresses of the various slots on the bin as a four bit binary number in

any order.

FIG 4.4: Basic segmentation of AI board design

4.4.1. DESIGN OF INPUT SECTION:

The input section covers the following features:

Accepts analog signals as input

Select one input from 32 inputs.

Convert Analog signal to digital output.

Within each AI board, there should again be a mechanism by which the processor can

request for data from one channel at once. Hence a multiplexer is needed. For this, if we

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use 16-bit multiplexers, which are the most cost-effective ones, we will need two such

multiplexer ICs. Also, at no instant should analog data from two channels be overlapped or

selected simultaneously, for this reason we need to select a multiplexer to provide “break

before make switching”. It means that before a new channel is selected the previous one is

deselected to prevent simultaneous selection.

The analog value from one of the selected channels from the multiplexer is to be

converted to a corresponding digital value which is understandable to the processor. But

since the samples are taken from the analog signal at regular intervals of time, we need a

Sample and Hold Circuit to hold to a particular signal level for each interval. It must also

be noted that such an SHA circuit used must also be compatible to the ADC circuit that is

cascaded to it.

Temperature monitoring in nuclear power plants is very critical. Hence the temperature

measurement is ought to be done with high amount of precision and low tolerance. Hence,

it is advisable to convert the analog signal into high resolution, say 16-bit, digital data.

Hence we require a 16-bit Analog to Digital Converter. It is easy to find an SHA which is

compatible to our ADC from the standard data book of the component manufacturer.

The CTM data logger shall compute, display and print temperature with a resolution of

0.1ºC and this corresponds to 1mv at the input of DAQ board.

But this resolution cannot be achieved by a 12 bit board which was used in previous

CTM systems. The resolution of such a 12 bit board in the range of 0-10V is calculated

below

This doesn‟t meet our present requirement of 1mV.

Hence an upgrade was inevitable, and the result was a 16 bit board whose resolution is

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Fig 4.4.1: Signal flow in input section

4.4.2. DESIGN OF OUTPUT SECTION:

The output section covers the following features:

Storage of digital data using appropriate buffers and latches.

Compatibility to I/O bus

Transfer of data to CPU for further processing.

The ADC converts analog samples of one channel after another, therefore, the output of

ADC keeps changing periodically, in order to ensure proper transfer of these digital values

into the bus, we need latches to store the data temporarily. If a D flip-flop is used for this

purpose, the data at the D input at the end of each clock is sampled to the I/O bus.

In the absence of data from the ADC, the bus should not hold definite digital values;

therefore the buses can be tri-stated. In the absence of data from ADC, the tri-state buffers

are disabled and the bus is in a high-impedance state.

A tri-state buffer is a useful device that allows us to control when current passes through

the device, and when it doesn't.

Fig 4.4.2: Tri-state buffers

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A tri-state buffer has two inputs: a data input x and a control input c. The control input

acts like a valve. When the control input is active, the output is the input. That is, it

behaves just like a normal buffer. The "valve" is open.

When the control input is not active, the output is "Z". The "valve" is open, and no

electrical current flows through. Thus, even if x is 0 or 1, that value does not flow through.

Fig 4.4.3: Block diagram of output section

4.4.3. DESIGN OF CONTROL SECTION:

Control Section controls the process of transferring of data from input to output section by

sequential accepting and generating the required control signals, thus governing the data

acquisition mechanism.

The control section covers the following features

Receives signals from the I/O controller through the I/O bus and generates signals

internally to regulate signal flow.

Provides required control signals for functioning of various stages.

Controls the working of both input and output sections thus governing the data

acquisition mechanism.

There is a need for controlling the timing between the SHA and ADC. By the time the

output of SHA is ready to be converted to Digital form, the ADC circuit must be ready.

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Hence, the ADC should be enabled one cycle before the SHA. For this purpose, we can

make use of a delaying circuit.

Programmable Array Logic:

Programmable Array Logic (PAL) is used to describe a family of programmable logic

device semiconductors used to implement logic functions in digital circuits. PAL devices

consisted of a small PROM (programmable read-only memory) core and additional output

logic used to implement particular desired logic functions with few components.

Before PALs were introduced, designers of digital logic circuits would use small-scale

integration (SSI) components, such as those in the 7400 series TTL family; the 7400 family

included a variety of logic building blocks, such as gates, multiplexers and de-multiplexers,

flip-flops and others. One PAL device would typically replace dozens of such "discrete"

logic packages, so PALs are used extensively today. PALs were used advantageously in

many products such as minicomputers.

4.4.4. DESIGN OF DIAGNOSTICS SECTION

Fig 4.4.4: Block Diagram of Diagnostics Section

Field parameter monitoring is extremely critical in power plants; hence unchecked failure

of AI board is unwanted. Hence, we can provide for an onboard test signal generator which

can generate 10% and 90% of the maximum signal (i.e., 10V). Channels 32 and 16 can be

dedicated for these signals. When this generated test signal is fed to the multiplexer and

one of these two channels is selected, the obtained digital value can be compared with the

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standard value for this signal. If they do not match bit by bit, a fault indicating LED must

be made to glow.

4.4.5. SKETCHING THE OVERALL AI BOARD BLOCK DIAGRAM:

By the above analysis, we have broadly identified the component blocks that are required

in the design. A proper interconnection of such blocks gives the block diagram of the AI

board which can be sketched as follows.

In all, the AI board, once selected by address selection mechanism, converts the analog

field sample values into 16-bit digital values for each channel and gives them to the

computer through the I/O bus. A diagnostic test is done periodically to ensure that no fault

is left uncorrected.

The overall block diagram of the AI board is the result of the integration of the block

diagrams of input section, output section, control and timing section, and diagnostics

section. This is shown in the figure below. Now that we know the components required

with their intended functions, we can take up selection of components. This is seen next.

Fig 4.4.5: Block diagram of the AI board

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4.5. SELECTION OF COMPONENTS

4.5.1. ANALOG MULTIPLEXER:

A multiplexer or MUX is a device that selects one of many data-sources and outputs that

source into a single channel. In electronics, multiplexers function as multiple-input, single-

output switches. A multiplexer has multiple inputs and a selector that connects a specific

input to the single output.

In digital signal processing (DSP), the multiplexer takes several separate digital data

streams and combines them together into one data stream of a higher data rate. This allows

multiple data streams to be carried from one place to another over one physical link, which

saves cost.

Table 4.5.1: Selection of Analog Multiplexer

Multiplexer

Type

Channels

Single / Diff

Interfacing Other

Characteristics

MUX-16

16

(Single Ended)

Parallel Digital I/P‟s are designed

to operate from both TTL

and CMOS levels

ADG406

16

(Single Ended)

Parallel

Fast switching times

ADG506A

16

(Single Ended)

Parallel

TTL and 5V CMOS logic,

compatible digital I/P‟s

10.8V to 16.5V single or

dual supply range

High switching speeds

ADG726

16

(Differential)

32

(Single Ended)

Parallel

30 ns switching time

1.8V to 5.5V single supply

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The main selection criteria are high switching speed, and break-before-make-

switching, single-ended input, and input protection, i.e., in case of signal presence during

component failure, the component is protected by internal circuitry. Here, we can use two

16-bit multiplexers in place of a single 32-bit multiplexer. Hence, ADG506A is the most

suitable for our design.

The ADG506A is a monolithic analog multiplexer with 16 channels. This switches one

of the inputs to the common output depending on the state of 4 binary addresses and

enables input. The device can comfortably operate anywhere in the 10.8 V to 16.5V range

(single or dual supply).

Specifications:

Analog over voltage protection : 70V p-p

No channel interaction during over voltage

Break before make switching

Analog signal range : +15v

Standby power : 7.5mW

True second source

Functional Block Diagram:

Fig 4.5.1: Functional Block Diagram of Analog Multiplexer

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Description:

The ADG506A is a monolithic analog multiplexer with 16 channels. The ADG506A

switches one of 16 inputs to a common output, depending on the state of four binary

addresses and an enable input. The device has TTL and 5 V CMOS logic compatible

digital inputs. The ADG506A is designed on an enhanced LC2MOS process, which gives

an increased signal capability of VSS to VDD and enables operation over a wide range of

supply voltages. The device can operate comfortably anywhere in the 10.8 V to 16.5 V

single or dual supply range. This multiplexer also feature high switching speeds.

Special Features:

1. Single/Dual Supply Specifications with a Wide Tolerance: The devices are specified in

the 10.8 V to 16.5 V range for both single and dual supplies.

2. Extended Signal Range: The enhanced LC2MOS processing results in a high breakdown

and an increased analog signal range of VSS to VDD.

3. Break-Before-Make Switching: Switches are guaranteed break-before-make so input

signals are protected against momentary shorting.

4. Low Leakage: Leakage currents in the range of 20pA make these multiplexers suitable

for high precision circuits.

4.5.2. SAMPLE AND HOLD AMPLIFIER:

To reduce errors arising from the digitizing a fast varying or noisy signal a sample/hold

amplifier is used. The common output analog signal from the multiplexer is passed to the

sample and holds amplifier. The SHA can be configured for gains 1 or 2 by means of

jumpers. Offset adjustment is performed by a trimming potentiometer.

Table 4.5.2: Selection of Sample and Hold Amplifier

SHA Type Acquisition

Time

Input

Voltage

Other

Characteristics

AD781 700ns ±15V Low power dissipation

High Speed

AD1154 3.5µs ±10V Low cost

Low Non-linearity

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Out of these suitable ICs, AD1154 meets our requirements. The SHA follows the amplifier

output until the (A/D converter is about to digitize an input) HOLD* input is at high level.

An active low control signal from the control logic causes the SHA to hold signal steady at

the present value and therefore, it ceases to follows the input during the conversion period.

The SHA used in the analog input board is AD1154.

Specifications:

Low Nonlinearity: + 7.6ppm max (1/2 LSB @16 bit Accuracy)

Fast acquisition time to + 0.00076 %:3.5µs

Low droop rate: 0.02µV/µs

Aperture Jitter: 150 ps

+ 10 V Input Range

Hold mode feed through Rejection of -106dB

14 pin Metal dip

Gain of +1V/V

Low Cost

Functional Block Diagram:

Fig 4.5.2: Functional Block Diagram of Sample And Hold Amplifier

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Special Features:

The fast acquisition time (3.5micro seconds) and low aperture jitter make it the

right choice for high speed, high accuracy data acquisition.

Its low droop rate (0.02 uV/uSec) allows it to be used in slower systems without

noticeable performance degradation.

The AD1154 is ideal for systems requiring wide dynamic range.

Low price reduces overall system cost.

Unity gain buffer architecture allows ease of use.

4.5.3. ANALOG TO DIGITAL CONVERTER:

Analog-to-digital (A/D) converters are used to transform analog information, such as audio

signals or measurements of physical variables (for example, temperature, force, or shaft

rotation) into a form suitable for digital handling, which might involve any of these

operations:

Processing by a computer or by logic circuits, including arithmetical operations,

comparison, sorting, ordering, and code conversion,

Storage until ready for further handling,

Display in numerical or graphical form, and

Transmission.

If a wide-range analog signal can be converted, with adequate frequency, to an

appropriate number of two-level digits, or bits, the digital representation of the signal can

be transmitted through a noisy medium without relative degradation of the fine structure of

the original signal.

Types of Analog-to-Digital Converters:

Successive Approximation Converter: A successive approximation converter

provides a fast conversion of a momentary value of the input signal. It works by first

comparing the input with a voltage which is half the input range. If the input is over

this level it compares it with three-quarters of the range, and so on. Twelve such steps

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gives 12-bit resolution. While these comparisons are taking place the signal is frozen in

a sample and hold circuit. After A-D conversion the resulting bytes are placed into

either a pipeline or buffer store. A pipeline store enables the A-D converter to do

another conversion while the previous data is transferred to the computer. Buffered A-

D converters place the data into a queue held in buffer memory. The computer can read

the converted value immediately, or can allow values to accumulate in the buffer and

read them when it is convenient. This frees the computer from having to deal with the

samples in real time, allowing them to be processed in convenient batches without

losing any data.

Dual Slope Integrating Converter: This converter reduces noise but is slower than

the successive approximation type. It lets the input signal charge a capacitor for a fixed

period and then measures the time for the capacitor to fully discharge at a fixed rate.

This time is a measure of the integrated input voltage, which reduces the effects of

noise.

Charge Balancing Converter: The input signal again charges a capacitor for a fixed

time, but in this converter the capacitor is simultaneously discharged in units of charge

packets: if the capacitor is charged to more than the packet size it will release a packet,

if not a packet cannot be released. This creates a pulse train. The input voltage is

determined by counting the pulses coming out of the capacitor. Noise is reduced by

integrating the input signal over the capacitor charging time.

Flash Converter: A flash converter is the fastest type of converter we use. Like the

successive approximation converter it works by comparing the input signal to a

reference voltage, but a flash converter has as many comparators as there are steps in

the comparison. An 8-bit converter, therefore, has 2 to the power 8, or 256,

comparators.

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Table 4.5.3: Selection of Analog to Digital Converter

ADC

Resolution

Linearity

Error

(%FSR)

Interfacing

Type

Characteristics

ADC76 16-bit ±0.003 Serial

and

Parallel

All digital I/O are TTL

compatible

Operation temperature ranges

from 00 – 70

0 C

ADC700 16-bit ±0.003 Serial

and

Parallel

Output buffer latch for

improved interface timing

flexibility.

Faster conversion time (17μs)

AD1376 16-bit ±0.003 Serial and

Parallel Low power dissipation

Fastest conversion time

(14μs)

Of all the above mentioned ADCs, AD1376 meets our requirements with fastest

conversion time of 14μs. AD1376 is a 16-bit successive approximation type Analog to

Digital converter is used in this board, which converts the input Analog signal in to straight

Binary digital form. The ADC can be configured for various uni-polar or bipolar 0-5V, 0-

10V, 0-20V & +/-2.5V, +/-5V, +/-10V by means of the jumpers. Digital output data is

provided in parallel and serial form with corresponding Clock and Status outputs. Typical

applications include medical and analytic instrumentation, precision measurement for

industrial robotics, automatic test equipment (ATE), and multi-channel data acquisition

systems, servo control systems etc.

Features:

Complete 16 bit converter with reference and clock

+ 0.003% Maximum nonlinearity

No missing codes to 14 bit s over temperature

Fast conversion -14µs

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Short cycle capability

Parallel and serial outputs

Low power:645mW typical

Industry standard pin out

Special Features:

The AD1376 provide 16-bit resolution with a maximum linearity error of ±0.003%

at +25 degrees centigrade.

AD1376 conversion time is 14 microseconds short cycled to 14 bits, and 16

microseconds to 16 bits.

Two binary codes are available on the digital output. They are CSB

(Complementary Straight Binary) for uni-polar voltage ranges and COB

(Complementary Offset Binary) for bipolar input ranges. Complementary Two's

Complement (CTC) coding may be obtained by inverting Pin 1 (MSB).

The AD1376 include internal reference and clock, and external clock rate adjust

pin, and serial and parallel digital outputs.

Functional Block Diagram:

Fig 4.5.3 Functional Block Diagram of Analog to Digital Converter

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4.5.4. PROGRAMMABLE ARRAY LOGIC:

This device implements the familiar Boolean logic transfer function, the sum of products.

The PAL device is a programmable AND array driving a fixed OR array. The AND array

is programmed to create custom product terms, while the OR array sums selected terms at

the output.

The product terms are connected to the fixed OR array. The OR sums of the product

reads the output Macro cells. Each Macro cell can be programmed as registered or

combinatorial, and active high or active low. Two fuses controlling two multiplexers in

each macro cell determine the output configuration.

The PAL CE is a CMOS Flash Erasable second generation programmable array logic

device. It is implemented with a familiar sum of products (AND-OR) logic structure and

the programmable macro cell. It is a 24 pin DIP. The device provides up to 22 inputs and

10 outputs. The PAL CE can be electrically erased and re-programmed.

Features:

Advanced second generation architecture

Low power

CMOS Flash technology for electrical erasability and re-programmability

User-programmable macro cell

High reliability

DIP, LCC and PLCC available

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Functional Block Diagram:

Fig 4.5.4: Functional Block Diagram of Programmable Array Logic

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5. OPERATION OF 16-BIT ANALOG INPUT BOARD

5.1. ANALOG INPUT BOARD

The Analog Input board consists of two sections. The input section interfaces the analog

field signals, converting it into digital signals and the output section interfaces the

converted 16-Bit data i.e. the output of the ADC to the I/O bus for the I/O controller to

read.

The input section apart from interfacing the analog signals selects one channel out of 32

channels by multiplexing. The I/O controller does the channel addressing. The signal that

is present on the selected channel is then fed to a SAMPLE AND HOLD AMPLIFIER

(SHA) circuit. In this stage the signal is sampled continuously.

The output of this SHA is given to the ANALOG TO DIGITAL CONVERTER (ADC).

The I/O controller now issues a command for starting conversion STC to the ADC and

simultaneously a HOLD signal is issued to the SHA. Now the signal is transferred to the

output of the SHA, which is input to the ADC. After the conversion is completed the ADC

issues an HIGH END OF CONVERSION signal, which means the signal is converted into

its 16-bit equivalent value. This 16-Bit data is latched and then fed to the output section of

the AI board.

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Fig 5.1.1: Operation of AI Board

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Fig 5.1.2: Manufactured PCB (AI Board)

5.2. ADDRESS DECODING

The address set up on the mother board by means of SA1 to SA4 jumper block for the

particular slot in which the AI board is placed (A0 to A3), is fed as reference input to the

PAL which acts as a 4-bit address comparator. The address is compared with IOA1 to

IOA4 address input, (B0 to B3), generated by the controlling processor. If the inputs

match, the comparator generates logic 1, (A=B) signal and the board is selected for

subsequent I/O operations. Otherwise it generates logic 0, (A! =B) and the card cannot be

used.

Active high output from the comparator is fed to the enable input of the control, the

channel address, and the data tri-state buffers. The enabled board gets access to the

address, control and data lines of the I/O bus, whereas other boards on the bus are isolated

through high impedance state.

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5.3. SLOT SELECTON

Any I/O slot/card can be selected by sending the slot address of the card. Any slot/card can

be selected by sending the slot address of that card on the slot address port. For example, to

select a card in slot number 5 in a bin with base address 0x340, the slot address is packed

into a byte and sent on the port 0x340.

5.4. CONTROL SIGNAL BUFFERING

All the control signals that originate in the processor subsystem are transmitted to the AI

board through the I/O bus whereas the other boards on the bus are isolated through high

impedance state. The control signals are supplied to the input of the control buffer. If the

buffer is disabled with high input, it goes into high impedance mode i.e., tri state. All the

active low control signals are individually pulled up to logic supply ensuring negation

during high impedance state.

5.5. SAMPLE AND HOLD AMPLIFIER

To reduce errors arising from digitizing a fast varying or noisy signal a sample/hold

amplifier (SHA) is used. The common output analog signal from the multiplexers is passed

to the sample and hold amplifier. The SHA can be configured for gains 1 or 2 by means of

jumpers. Null adjustment is performed by a trimming potentiometer. The SHA follows the

multiplexer output until the HOLD* input is at high level (i.e., when the A/D converter is

about to digitize an input). An active low control signal from the control logic causes the

SHA to hold the signal steady at the present value and therefore, it ceases to follow the

input during the conversion period.

5.6. A/D CONVERSION CIRCUIT

A 16 bit successive approximation A/D converter, AD1376 is used in this board, which

converts the input analog signal into straight binary digital form. The ADC can be

configured for various unipolar or bipolar signals such as 0–5V, 0-10V, 10V, 5V by

means of jumpers. (At present boards of 0-5V and 0-10V are available).

The unipolar offset, bipolar offset and the gain of the ADC can be adjusted by means of

the trimming potentiometers. The tri-state binary outputs of the ADC are applied to the

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inputs of the 12-bit latch. The latch is enabled by the STS output of the ADC. The latches

hold the latest 12 bit conversion data

5.7. SAMPLE/HOLD, CONVERSION CONTROL LOGIC

At power ON, the S/H amplifier is in sample mode. The STC* control signal is fed

to the timing and logic circuit. A low level on this puts the SHA in "HOLD" mode. At the

same time the STC* control signal enables the ADC. Once the ADC is triggered, the ADC

STS (Status) output is kept at high logic level during the conversion period. This continues

all along during the conversion period. When conversion ceases, the input of SHA is back

in sample mode. The final converted data is available on the read data bus through the data

bus buffer. Thus the analog signal from the field is converted into the digital form for the

I/O controller for subsequent use.

5.8. DIAGNOSTICS

A precision voltage source is employed for generating on board precision reference

voltages. The desired voltage ratio is obtained by means of a potential divider network

comprising precision resistors and trimming potentiometers. The two reference levels are

configured near 0 and the span of the input range, with the help of the resistors and

potentiometers and applied to channels 16 and 32 of the multiplexers. These two channels

can be used as external field inputs or for calibration purposes by suitable jumper selection.

At present the reference levels that are available are for 16th

channel - 75% or 90% of full

scale and 32nd

channel - 25% or 10% of full scale. The I/O controller reads these two

values and if they are found to be within the specified accuracy limits the AI board is

treated as healthy.

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6. CONCLUSIONS

In this project, an effort has been made to implement the acquisition of analog data in a real

time industrial application. The hardware involved in acquiring the data and its interface

with I/O controller has been analyzed. Sample Analog Acquisition applications for a

nuclear power station have been taken up to explain the acquisition, storing, reporting, and

monitoring functions.

An upgrade of the components present on the Analog Input Board for 16-bit resolution

has been made and tested successfully.

The objective of this project has been the integration of computers and electronic

devices for the effective and reliable operation of nuclear power plants.

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REFERENCES

http://www.analog.com/

http:// www.ecil.co.in/

http://www.datasheetcatalog.com/

http://www.wikipedia.org/

http://www.amd.com/in/

http:// www.electronics-manufacturers.com/