an soc testable sigma-delta adc with dft...

An SoC Testable Sigma-delta ADC with DfT feature

Chee-Kian Ong, Kwang-Ting (Tim) Cheng, Li-C WangElectrical & Computer Engineering

Univ. of California, Santa Barbara, U.S.

2

Outline

SoC BIST motivationΣ∆ Analog-to-Digital ConverterGeneral ADC testing methodsProposed Σ∆ ADC test techniqueConclusion

3

SoC

SoC Application

RFTransceiver

Blocks

AD/DABlocks

DigitalProcessing

Blocks

Ana

logLimited

Access

Dig

ital

4

Outline


5

Why SoC BIST?Testing SoC analog blocks with traditional methods:

Accessibility to SoC internal blocks are limited.Multiple ATEs for memory, digital and analog production testing?

With BIST:Remove complicate test environment setting –especially analog; consistent test results.Provide all digital/single-ATE test solution for SoC or their analog sub-blocks.SoC BIST enable single ATE production.To achieve test cost reduction.

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Some Basic Analog Blocks in SoC

ADCacquire signal from real world for processing; e.g. voice command.

DACgenerate real world signal for application, visual display.

FiltersEnsure signal within certain bandwidth are captured.

High-speed Serial LinksFuture Trend for data transfer.

7

Outline


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Is Σ∆ ADC a Popular Choice?ADC is generally required to digitize real world info for processing – a necessity block in SoCΣ∆ ADC has relatively low analog engineering

Relax anti-aliasing low-pass filterLittle/simple components matchingRelatively few components architectureMore predictable performance

Digital filtering (Σ∆ ADC requisite) becomes cheaperTransistor size scaling down – area reduction

Can be implemented in low-cost CMOS processHigh resolution base/narrow band application.Relatively high power.

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Σ∆ Modulation

+ A/D∫

D/A

LPFx

1

1

1 −

−

− zz

( ) errqzxzy 11 1 −− −+=x̂

FFT

FFT

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

1.00E+01

0.00 0.00 0.00 0.01 0.10 1.00 10.00

qerr(1-z-1)

x

qerr

i

( )oizo += −1

i o

errqio +=

o

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2nd-Order Σ∆ modulation

+ A/D∫

qerr

x

D/A

1

1

1 −

−

− zz

( ) errqzxzy 212 1 −− −+=+ ∫1

1

1 −

−

− zz

-2 LPF

x̂

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

1.00E+01

0.00 0.00 0.00 0.01 0.10 1.00 10.00

x

qerr(1-z-1)2

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Outline


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Traditional ADC Testing

n-bit ADCUnder Test

Ramp StimulusStatic Testing

Converted Ramp

HistogramAnalysis

# of

occ

urre

nce

codes2n1,2,3

n-bit ADCUnder Test

SinewaveStimulus

Dynamic TestingConverted Sinewave

HistogramAnalysis

# of

occ

urre

nce FFT/

codes2n1,2,3

Pow

er

Freq

13

Outline

SoC BIST motivationΣ∆ Analog-to-Digital ConverterGeneral ADC testing methodsNew Σ∆ ADC test techniqueConclusion

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Motivation for new testing technique for Σ∆ ADC

Most techniques generates test stimulus without quantifying its quality.Some characterize circuits based on insufficient model parameters.In general, mixed-signal BIST architectures has an inherent dead-lock situation, where stimulus generator and signal analyzer are inter-dependent during the self characterization of the BIST architecture.

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Testing Σ∆ ADC using Digital StimulusC.K.Ong VTS’02

Numerical 2nd-orderDelta-sigmaModulator

2nd-orderDelta-sigmaModulatorUnder-Test

1/G

MUT

Digital logic/ Digital ATE on-chip processor

FP num 0110101101v-v+v+v+v-v-v+ 0110101101

Bit-streamQuantization

Noise

pow

er

freq. (Log scale)

pow

er

freq. (Log scale)po

wer

freq. (Log scale)

12 dB

pow

er

freq. (Log scale)

FP Stimulus

Freq

uenc

ySp

ectr

um

Digital bit-stream Stimulus

ReducedAmplitude

Software Generated

NumericalQuantization

Noise

MUTQuantization

Noise

G=4

The SNR of MUT is calculated Using Fourier Transformation

FFT

FFT

FFT

FFT

MUTOUTPUT

z -1 z -1+ +

-2-1

x

1 -1

y

Second-order Delta-sigma Modulator

1/4

Di

1 1

DFT Circ uit

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DfT Σ∆ modulator

Additional passive component matched with internal component

Identical switching devices; no-surprises

3dB (0.5 ENOB) measurement accuracy

is mainly due to the use of internal

reference voltages

z -1 z -1+ +

-2-1

x

1 -1

y

Second-order Delta-sigma Modulator

1/4

Di

1 1

DFT Circuit

SNR = 6N + 1.76 dBwhere N = Effective Number of Bits (NOB)

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Overhead for DfT Σ∆ ADCAdditional Gain Stage required:

Identical to those in the Σ∆ architecture feedback loopPassive components (1-2 cap/res) to implement the gain stage requiredPassive components matching identical to those in the feedback loopNoise need to be considered for the additional passive componentduring design.Area overhead is ~ ¼ of the feedback cap in the Σ∆ integrator for Switched-Capacitor networksDigital stimulus requiredRouted from digital blocks; assuming test mode available in digital blocksGenerated on-chip using on-chip processor or digital Σ∆ oscillator (G. Roberts)

Analysis may be performed by on-chip processor/DSP OR external digital ATE

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Outline


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ConclusionDfT is integrated into the Σ∆ ADC architecture

Spec can be integrated into design specDesigner is given clear direction of what needs to be done

Test stimulus is digitalEasily generated on chipNo worry on bandwidth-limited test channel (on/off chip)Support future SoC platformEnable full BIST with support from on-chip digital processor.

Dynamic Test TypeEnable SNR, THD, etc measurementTest time is similar to conventional test methodShorter than conventional INL,DNL test

an soc testable sigma-delta adc with dft...

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