an improved planar module automatic layout method for ... · fig. 1. planar package to reduce...

CES TRANSACTIONS ON ELECTRICAL MACHINES AND SYSTEMS, VOL. 1, NO. 3, DECEMBER 2017 411

Abstract—The layout of power modules is one of the key points

in power module design, especially for silicon carbide module, which may parallel more devices compared with silicon counterpart. In this paper, along with the design example, a improved layout design method for planar power modules is presented. Some practical considerations and implementations are also introduced in the optimization of module layout design.

Index Terms—Multi-chip module, packaging.

I. INTRODUCTION S shown in [1, 2], the parasitic parameters of a power module may have detrimental influences on switching

losses and dynamic behaviors. This phenomenon is exaggerated when the power density increases, because a higher switching rating leads to faster variations. In order to ensure high efficiency and high performance of a high-density power module, efforts are required for power module layout designs [3].

Recently, to further reduce parasitic parameters of wirebond modules, many advanced power semiconductor packaging were invented [4] (shown in Fig.1). In these packages, top sides of dies are soldered or sintered directly to direct bonded copper (DBC), copper strip or terminals. However, literatures rarely demonstrate any method to optimize the layout of these planar packages. The parasitic parameters of these package could be reduced less than half compared with conventional wirebond packages. The thermal resistance can also be cut to half compared with wirebond packages.

As the next generation power devices, silicon carbide (SiC) chips have many advantages over conventional silicon devices. However, limited by manufacture capability, the current for each die is commonly limited up to 50A [5]. Many dies need to be paralleled for renewable energy, automotive application and

This work is supported by The National key research and development program of China (2016YFB0100600), the Key Program of Bureau of Frontier Sciences and Education, Chinese Academy of Sciences (QYZDBSSW-JSC044), and the National Natural Science Foundation of China (No. 51507166).

Puqi Ning is with the Institute of Electrical Engineering, Chinese Academy of Sciences , Beijing, 100190 China and Collaborative Innovation Center of Electric Vehicles in Beijing (e-mail: npq@ mail.iee.ac.cn).

Lei Li is with the Institute of Electrical Engineering, Chinese Academy of Sciences , Beijing, 100190 China (e-mail: lilei@ mail.iee.ac.cn).

Xuhui Wen is with the Institute of Electrical Engineering, Chinese Academy of Sciences , Beijing, 100190 China (e-mail: wxh@ mail.iee.ac.cn).

Han Cao is with the Institute of Electrical Engineering, Chinese Academy of Sciences , Beijing, 100190 China (e-mail: chan@ mail.iee.ac.cn).

other medium power applications (at least 300 A required). It means that a three phase-leg module needs to contain at least 36 SiC switches and 36 SiC diodes. It is very difficult to layout a power module with human design knowledge and experiences.

IR PowerPack Virginia Tech HVEP

Fraunhofer planar Toyota LS600

Fig. 1. Planar package to reduce parasitics.

During the conventional design iterations, devices and power terminals, which are the basic components in layout design, first are geometrically placed by considering the electrical connections. The second step is the routing process, in which the dies and pads are connected with copper traces and wire bonds. Then the parasitic parameters in the designed layout can be obtained from finite element analysis simulation tools or theoretical equation-based calculations [3–6]. According to a survey of the relevant literature, there is still no figure of merit that can be used to find the best layout design for minimum power loss. The fitness of a layout can only be determined based on manual based evaluation of the parasitic parameters.

There are many manual layout design procedures presented in the literatures [3-5]. The main issues for these methods are the design speed and the limited choice of candidates. Manual design is always an experience-based process that lacks consistency. Hence, automatic layout design is highly preferred during the iteration process. Reference [6] provides a semi-automatic layout design method, but experience based pre-design is required. References [7] introduced an automatic layout design method, but the positions of the dies are fixed. Because human experience was still the main determination point in the positioning process, the layout design space is not thoroughly optimized.

In [8] and [9], an automatic design methods by using genetic algorithms (GA) were invented and introduced by the same author of this paper. With this automatic methods, layout

An Improved Planar Module Automatic Layout Method for Large Number of Dies

Puqi Ning, Member, IEEE, Xuhui Wen, Member, IEEE, Lei Li and Han Cao

A

412 CES TRANSACTIONS ON ELECTRICAL MACHINES AND SYSTEMS, VOL. 1, NO. 3, DECEMBER 2017

design spaces can be better searched and optimized without any human interruption.

However, for a silicon carbide planar module, the design procedure may become very slow when the number of dies increase over 10. The main issue is the complex layout interpretation steps (sp method in [8]) and the inductance calculation steps (partial element equivalent circuit in [8]).

crossover operation of position part

Mutation operation of position part

Fig. 2. Automatic layout design procedure and brief DNA operation in reference [8].

In this paper, based on previous work, the automatic design procedure is improved and becomes faster and more reliable. Furthermore, by adding analytical equations which can describe thermal behavior of the packaging materials, the optimized planar module can better consider multi-physics factors and thus be suitable for operations.

II. PLANAR MODULE LAYOUT INTERPRETATIONS In the layout iterations, the representations of devices are the

most important key to solve a layout problem effectively. In [8], the sequence pair (SP) method, which is particularly suitable for stochastic algorithms such as GA, has been proposed as the representation of a solution for this problem. However, the SP method becomes slower and much more complicated when the number of components increases over 10. In [9], typical elements were listed and interpreted for a planar modules, as shown in Fig.3. The DBC is not divided in small regions. Instead, a virtual grid plain is used. Devices is set in the center of grid, without considering the dimension in the out loop. In the evaluation step, the virtual grid will be converted to real DBC layout with a growing method. With this improvement, the positioning procedure speed was increased.

However, the DNA interpretation in [9] is still not simple enough for SiC planar module with a large number of dies. To speed up the positioning procedure, only 3 types are left, as

switches, diodes and power terminals. The detailed connections for gate pads and emitter pads on switches are no longer described in the outer loop DNA string. Instead, these details will be considered in the evaluation step.

Fig. 3. Basic elements interpretation for planar package.

Since the shapes of devices and terminal are rectangle or square, a matrix representing a grid layout region can be used to interpret device positions. Their positions can be then converted to one dimension vector and expressed as integral numbers. The length of position DNA is i+j+k, including i power terminals, j switches and k diodes.

The orientations of elements are also critical to parasitic parameter reduction and the balance between paralleled devices. It is because the pads on dies may be asymmetrically distributed while the power terminal connections are restricted by mechanical limits or manufacture limits. The basic element orientations for planar package are depicted in Fig.4.

When considering edge limits for a planar package, the orientations of power terminals are always faces out of the edges. Thus, the orientations in x-y plane can be reduced from 4 to 1. The facing up and facing down elements can be combined with different z axis orientation (1 digit binary). The transfer area can be formed in the copper growing step when required (in Section III). With these simplification, the orientation string of planar module is reduced to i+3j+k, including i power terminals, j switches and k diodes, as shown in Fig. 5.

Switch

1 2

3 4

1 (switch) 2 (switch)

3 (diode) 4 (diode)

5 (terminal) 6 (terminal)

7 (terminal) 8 (transfer area)

NING et al: AN IMPROVED PLANAR MODULE AUTOMATIC LAYOUT METHOD FOR LARGE NUMBER OF DIES 413

Fig. 4. Basic orientations in planar module.

Fig. 5. DNA string for positions and orientations of a planar module.

With the same simplification, the orientation string can be extended to wirebond module layout design. An orientation DNA in a wirebond module can be expressed by i+2j+k, for i power terminals, j switches and k diodes.

As an example, the phase-leg module presented in Fig.6 can be represented with 9 elements, including 5 power terminals, 2 power switches and 2 power diodes. In the design, the positions of these elements are limited to a 4×4 grid layout plane with the position of p0 to p15, as shown in Fig. 7. In this example, the

position DNA string is [9,1,10,0,11,4,7,5,6] and the orientation DNA string is [0,1,0,1,0,1,0,0,0,0,1,0,1].

In this phase-leg module, there are 5 terminals. They are, positive pin, neutral pin, negative pin, up gate pin and bottom gate pin. This 5 terminals are label from T0 to T5.

Fig. 6. Phase-leg module with 9 elements.

In orientation DNA, terminal part are defined as [0,1,0,1,0],

it actually means [face up (z axis), face down (z axis), face up (z axis), face down (z axis), face up (z axis)]. For device part, the first IGBT DNA is [100], which means face up (z axis) and gate pad to top (y axis). The second IGBT DNA is [001], which means face down (z axis) and gate pad to bottom (y axis). The first diode DNA is 0 (face up in z axis), and the second diode DNA is 1 (face down in z axis). The full interpreted layout is depicted in Fig.7.

DNA: position[9,1,10,0,11,4,7,5,6] ,orientation [0,1,0,1,0,1,0,0,0,0,1,0,1]

Fig. 7. Planar package layout representation example.

Terminal

1 2

3 4


III. LAYOUT DESIGN PROCEDURE The genetic algorithm was used in the optimization iterations.

Genetic algorithms (GAs) are based on natural genetics and are a particular class of evolutionary algorithms that use techniques inspired by the mechanisms of evolutionary biology such as inheritance, mutation, selection, and crossover [14]. The GA approach is categorized as a global search heuristic, and as such, GA is a search technique used in computing to find exact or approximate solutions to optimization and search problems. The GA is a stochastic search method that deals with the individuals composed of candidate solutions (populations), each of which is generally encoded in a problem-independent representation. During the genetic process, new candidate solutions are evaluated by their fitness and are reproduced using the genetic operators such as crossover and mutation [15].

As shown in Fig.8, the proposed layout design includes two loops both utilizing genetic algorithm (GA). The outer loop is the element placement loop, in which the components are placed in grid layout plane by following the electrical netlist. The inner loop arranges the orientations of elements by following the packaging limits and rules. At the end of each inner loop, the best candidate with the largest fitness will be transferred to the outer loop. After several iterations, the best layout design can be found to meet certain criterion.

Fig. 8. Two loop genetic algorithm.

In the outer loop, all the elements are placed in a grid layout plane with a certain matrix size. The matrix size should be at least larger than the total element number. For the first generation, element sequences are generated randomly without overlapping. Then, the DNA strings will evolve with crossover operation and mutation operation to form a new generation. The algorithm terminates when a maximum number of generations is reached or when the optimization criteria is fit.

Special operations are required and designed for the crossover and mutation. The position DNA is first converted to their full position matrix (converted in one dimension DNA string). A crossover points is then appointed. The digits before the crossover point of the first parent are preserved in the same sequence. The sequence of rest digits after the crossover point will copy their sequence in the second parents (one example is shown in Fig.9). Finally the matrix sequence of the child is converted back to a position DNA.

In this example, the DBC plane is a 2×4 grids and there are five elements. Father DNA and mother DNA are randomly chosen and can be interpreted as [0,1,4,3;0,2,0,5] and [5,0,0,4;3,1,2,0] in grid plane. With line connections, the

parents are [0143020205] and [50043120]. The crossover point is selected as 5. The first 5 elements ([0,1,4,3,0]) of father layout is reserved, and the rest elements in father layout are recorded as [2,0,5]. Their sequence in mother layout is [5,2,0], and it is added to the first 5 elements in father layout. The child is recorded as [0, 1, 4, 3, 0, 5, 2, 0]. With interpretation, the child DNA is used as [1, 6, 3, 2, 5] in the following iteration.

Fig. 9. Crossover operations for outer loop.

Fig.10 shows a mutation operation example, which is similar

to crossover operation. The selected two elements can be either a power terminal, a switch, a diodes, or a space.

Fig. 10. Mutation operations for outer loop.

In the inner loop, the element orientations are stochastically

selected. Then evolution is conducted with the most common binary crossover and binary mutation operations. In this procedure, gaps exist between elements and copper areas grow to final layout (as shown in Fig. 11).

Fig. 11. DBC substrate copper growing.

Boundary element method based parasitic parameter calculation is used for fitness evaluation in [6]. It is the main cause for low speed. To increase the optimization speed, the current conducting lengths are used to represent parasitic resistance and the surrounded areas are used to represent the inductance of commutation path. These value can be simply

If connected

If not connected

Copper growing

Copper growing


calculated with the positions of the elements in a very fast speed.

In this paper, the calculations were further simplified. The resistance was calculated by multiple the length between two 3-D point and a certain coefficient. From the definition, the cross sectional area decreases and the length increases in the conductor, the resistance increases. Since the cross sectional area will not change much in planar package, the length is the main factor to influence the resistance.

The length of two 3-D point A(x1, y1, z3) and B(x2, y2, z2) can be obtained as (1).

( ) ( ) ( )221

221

221 zzyyxx −+−+− (1)

In the inductance calculation part, the target 3-D layout pattern was first divided into n triangles. These triangles include the center point and two corner points of the 3-D layout pattern. The commutation-path inductance was obtained by multiple the sum up the individual area of each triangle and a certain coefficient.

If the corner point of a 3-D triangle is A(x1, y1, z3), B(x2, y2, z2), C(x3, y3, z3), the area of the triangle can be calculated from (2). The corner points can be obtained from position DNAs.

2

1313

12122

1313

12122

1313

1212

21

yyxxyyxx

xxzzxxzz

zzyyzzyy

−−−−

−−−−

+−−−−

+

(2)

The best routing results will be passed to outer loop in the end of inner loop iterations. In this paper, the fitness evaluation also considers the parasitic resistance, parasitic inductance and the footprint, as shown in (3).

F= Ainductance Lresistance

Afootprint (3)

With the best fitness, the layout can provide low parasitics, as well as small footprint. This definition can be further extended to evaluate thermal and mechanical performance by adding proper parameters.

For example, the conventional compact modeling for heat conduction in solids was done by applying finite-difference

approximation to the governing equations of heat transfer. Assuming the material has isotropic thermal conductivity, the equation is expressed in (4). Cv is the volumetric specific heat of the material, T is the control cell temperature, and q is the volumetric heat generation.

( ) •

=∇−+ qTkdtdTCv

2 (4)

( )•

=∇+∇−⋅∇+ qTuCTkdtdTC vv

(5)

By combining and energy conservation equation of heat transfer in a control volume of air flow and Stroke’s theorem equation, (5) can be derived as a compact convection cell model [7]. In (5), u is the velocity of outflow of the fluid at the surface of the control volume and it can represent the net outflow of heat from the control volume due to the convection. Comparing (5) to (4), the conduction term is no longer written using a Laplacian operator because heat transfer in air flow cell is no longer isotropic.

In [8], a method for using a time domain circuit code to solve partial differential equations was described. The partial differential equation is finite differenced in space and written in state variable form. The spatial derivatives can be finite differenced on a uniform spatial mesh x1,..., xj-1, xj, xj+1,..., xk, where Δx = xj+1- xj. The 1st-order and 2nd-order differential items can be substituted with equation (4) and (5). Equation (6) and (7) shows the discretization result. With these equations, the thermal management part can be simplified as Fig.12, and can be used in the layout optimization.

Fig. 12. The discretized cell model for solid.

zyxqz

TTTk

yTTT

kx

TTTk

tTzyxC kjikjikjikjikjikjikjikjikji

v ∆∆∆=∆

+−−

∆

+−−

∆

+−−∆∆∆

•−+−+−+

21,,,,1,,

2,1,,,,1,

2,,1,,,,1 222 (6)

zyxqTTAuCz

TTTk

yTTT

kx

TTTk

tTzyxC SSyyv

kjikjikjikjikjikjikjikjikjiv ∆∆∆=−∆+

∆

+−−

∆

+−−

∆

+−−∆∆∆

•−+−+−+ )(

222122

1,,,,1,,2

,1,,,,1,2

,,1,,,,1 (7)

IV. EXAMPLES OF AUTOMATIC LAYOUT DESIGN

In order to better explain the proposed method, one design example is demonstrated in Fig. 13. The example focuses on a three-phase wirebond module, which has 12 power switches, 6 diodes and 11 terminals. The project also requires a easy connection of all the phase terminal and then can be convert to a one phase module. The phase terminals need to be in one side

of module, and the positive and negative terminal should be in another side.

The design iteration terminates after 45 outer loops and each with 100 inner loops. Two of the initial designs are shown in Fig.14. The fitness is 932 and 824 respectively.


Fig. 13. Automatic layout design example.

Fig. 14. Initial layout designs

The solution with largest fitness (573) is shown in Fig. 15. The interpreted planar power module is in Fig.16.

Fig. 15. Optimized layout example

With the same example, this automatic optimization method was compared with the presented novel method and previous methods in [8] and [9]. They were all conducted on the same software platform Matlab. The calculation time is listed Table 1. With this improved design procedure, it is 15 times faster than previous method in [8] and 1.8 times faster than method in [9].

This design result was also verified by FEM software Ansoft Q3D. Compared with other candidates, its performance was agreed well with presented method. . More detailed simulations and verifications for complex cases will be investigated in the future.

Fig. 16. Interpreted planer power module

Fig. 17. Compared with wirebond module layout.

Literature [9] presents a wirebond layout optimization (shown in Fig.17). Compared with it, the size of planar power module is reduced to 47%, the average parasitic resistance reduced to 27%, and the average parasitic inductance reduced to 63%.

TABLE I AUTOMATIC OPTIMIZATION PROCEDURE COMPARISON

Optimization method Calculation time (minute) Method in this paper 45.6 Method in [8] 693.1 Method in [9] 83.5

V. SUMMARY AND CONCLUSION This paper presents an improved automatic layout design

method for planar power modules. With the novel element interpretation method, related special genetic operation method, and fast evaluation method, the automatic layout design is improved and the design speed is almost doubled. The presented method is useful for planar modules with large number of dies.

Some practical considerations are introduced and implemented in the optimization. Along with design examples, the performance of proposed method is demonstrated. It could be a major step to improve the overall performance of future power module.

REFERENCES [1] Chen, X. Yang, J.Liu, Z. Wang, “Practical Design Considerations for

IPEM-based PFC Converter Employing CoolMOS Q and SiC Diode,” in Proc. IEEE APEC 2006, pp.6-12.

[2] H. A. Mustain, A. B. Lostetter, W. D. Brown, “Evaluation of gold and aluminum wire bond performance for high temperature (500 /spl deg/C) silicon carbide (SiC) power modules,” in Proc. Electronic Components and Technology Conference, 2005, pp, 1623–1628, vol. 2.

[3] J. D. van Wyk, F. C. Lee, Z. X. Liang, R. G. Chen, S. Wang, B. Lu, “Integrating Active, Passive and EMI-Filter Functions in Power Electronics Systems: A Case Study of Some Technologies,” in IEEE Trans. on Power electronics, vol. 20, no. 3, pp. 523–536, May. 2005.


[4] Z. Liang, B. Lu, J. van Wyk, and F. C. Lee, “Integrated CoolMOS FET/SiC-Diode Module for High Performance Power Switching,” in IEEE Trans. on Power Electron., vol. 20, no. 3, pp.679-686, MAY 2005.

[5] C. Martin, J. Guichon, and J. Schanen, “Gate Circuit Layout Optimization of Power Module Regarding Transient Current Imbalance,” in IEEE Trans. on Power Electron., vol. 21, no. 5, pp. 1176–1184, Sep. 2006.

[6] N. Hingora, X. Liu, B. McPherson, Y. Feng, and H. A. Mantooth, "Power-CAD: A Novel Methodology for Design, Analysis And Optimization of Power Electronic Module Layouts," in Proc. IEEE ECCE 2010, pp. 2692-2699.

[7] Jonah Zhou Chen, Ying Feng Pang, Dushan Boroyevich, Elaine P. Scott, Karen A. Thole, “ Electrical and Thermal Layout Design Considerations for Integrated Power Electronics Modules,” in Proc. IEEE IAS 2002, pp. 242–246, vol.1.

[8] P. Ning, F. Wang, and K. D. T. Ngo, "Automatic layout design for power module," in IEEE Trans. on Power Electronics, vol 28, issue 1, pp. 481-487, Jan. 2013.

[9] P. Ning, and Xuhui Wen, "A Fast Universal Power Module Layout Method", in Proc. IEEE ECCE2015, pp.4132-4237.

Puqi Ning received his Ph.D. degree from electrical engineering of Virginia Tech, Blacksburg, US in 2010. He is full professor in Institute of Electrical Engineering, Chinese Academy of Sciences. Dr. Ning has been involved in high temperature packaging and high density converter design for more than 10 years.

Lei Li is a Ph.D. student in Institute of Electrical Engineering, Chinese Academy of Sciences. He has been involved in power device modeling and high density converter design for 3 years.

Xuhui Wen was born in Chengdu, China. She received her B.S, M.S and PhD degree in electrical engineering from Tsinghua University in 1984, 1989, 1993 respectively. She is full professor in Institute of Electrical Engineering, Chinese Academy of Sciences. Dr. Wen has been involved in high power density electrical drive and generation especially

for electric vehicle application for more than 20 years. .

Han Cao is a Master student in Institute of Electrical Engineering, Chinese Academy of Sciences. He has been working on power device modeling and high density converter design for 1 year.

an improved planar module automatic layout method for ... · fig. 1. planar package to reduce...

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